An Optimized Cost/Performance PDS Design Using OptimizePI

An Optimized Cost/Performance PDS Design Using OptimizePI

Paul ChuInventec/CAE5/20/2008

Paul ChuInventec/CAE5/20/2008

Page 2

AgendaAgendaAgendaAgenda Introduction What Is The Benefit of OptimizePI The Design Flow and Design Experience Verification Conclusion

Introduction What Is The Benefit of OptimizePI The Design Flow and Design Experience Verification Conclusion

IntroductionIntroductionIntroductionIntroduction

With increasing frequency and decreasing noise margin, the power rail integrity is becoming more and more important. The reason is that the voltage variation depends on the Z(f) and I(f).

The self-impedance represents the resonance profile at the observed node. The general method to mitigate the high impedance of power/ground rail is to use the de-capacitor.

The designer must manually replace/remove de-capacitors to check if both self-impedance and transfer-impedance are improved on traditional simulators. Also, it is a time-consuming job to observe all interesting nodes when each time the cap was changed .

If the cost of the design is concerned, the overall capacitor cost needs to be calculated when each time the cap was changed.

With increasing frequency and decreasing noise margin, the power rail integrity is becoming more and more important. The reason is that the voltage variation depends on the Z(f) and I(f).

The self-impedance represents the resonance profile at the observed node. The general method to mitigate the high impedance of power/ground rail is to use the de-capacitor.

The designer must manually replace/remove de-capacitors to check if both self-impedance and transfer-impedance are improved on traditional simulators. Also, it is a time-consuming job to observe all interesting nodes when each time the cap was changed .

If the cost of the design is concerned, the overall capacitor cost needs to be calculated when each time the cap was changed.

Page 4

What Is The Benefit of OptimizePIWhat Is The Benefit of OptimizePIWhat Is The Benefit of OptimizePIWhat Is The Benefit of OptimizePI The powerful translator for Allegro-to-OptimizePI. The de-capacitors can be automatically replaced and selected without

impact on the layout modification. The performance vs. cost chart is informative for the designer to avoid

the over-design. The PDS design can be improved by selecting the specific solutions

from numerous design schemes. The available room for the routing can be increased, and the spacing

can be utilized for the robust system design.

The powerful translator for Allegro-to-OptimizePI. The de-capacitors can be automatically replaced and selected without

impact on the layout modification. The performance vs. cost chart is informative for the designer to avoid

the over-design. The PDS design can be improved by selecting the specific solutions

from numerous design schemes. The available room for the routing can be increased, and the spacing

can be utilized for the robust system design.

The Design Flow and Design The Design Flow and Design ExperienceExperience File TranslationFile Translation

The Design Flow and Design The Design Flow and Design ExperienceExperience File TranslationFile Translation Determine which power-tree to be analyzed before the simulation. For the file translation, the insignificant nets can be deselected, and

the simulation time can be reduced.

Determine which power-tree to be analyzed before the simulation. For the file translation, the insignificant nets can be deselected, and

the simulation time can be reduced.

CT_P5V_LX P5V P5V_USB10

Q1

P5V_VGA1

R1

L1

L2 (Bead)

VGA1_CON_P9

J1

IC_B

VRM

P5V_VGA2

R2 J2

U2

IC_A

U1

The Design Flow and Design The Design Flow and Design ExperienceExperience User InterfaceUser Interface

The Design Flow and Design The Design Flow and Design ExperienceExperience User InterfaceUser Interface The simulation can be completed by the workflow listed below. The simulation can be completed by the workflow listed below.

The Design Flow and Design The Design Flow and Design ExperienceExperience Capacitor LibraryCapacitor Library

The Design Flow and Design The Design Flow and Design ExperienceExperience Capacitor LibraryCapacitor Library The capacitor

library can be maintained with XML format and it can be reused for any other power rails.

There are two capacitor libraries in the Capacitor Library Manager. For the External Library, the count of capacitors is free.

The capacitor library can be maintained with XML format and it can be reused for any other power rails.

There are two capacitor libraries in the Capacitor Library Manager. For the External Library, the count of capacitors is free.

The Design Flow and Design The Design Flow and Design ExperienceExperience Stackup Definition and Net SelectionStackup Definition and Net Selection

The Design Flow and Design The Design Flow and Design ExperienceExperience Stackup Definition and Net SelectionStackup Definition and Net Selection If the PCB cross-section and material information

were defined in the layout tool, the design data can be transferred to SPD file for OptimizePI.

All following power planes/islands in the specific power tree must be selected in the Net Manager.

If the PCB cross-section and material information were defined in the layout tool, the design data can be transferred to SPD file for OptimizePI.

All following power planes/islands in the specific power tree must be selected in the Net Manager.

The Design Flow and Design The Design Flow and Design ExperienceExperience Circuit Model DefinitionsCircuit Model Definitions

The Design Flow and Design The Design Flow and Design ExperienceExperience Circuit Model DefinitionsCircuit Model Definitions Models of VRM, bead, and fuse can be defined in the “Define Circuit

Models” for the power plane/island connection. The model can be edited with RLC SPICE format.

Please note that capacitor models listed here are just for reference. The simulator would grab capacitor models from the Project Capacitor Library.

Models of VRM, bead, and fuse can be defined in the “Define Circuit Models” for the power plane/island connection. The model can be edited with RLC SPICE format.

Please note that capacitor models listed here are just for reference. The simulator would grab capacitor models from the Project Capacitor Library.

The Design Flow and Design The Design Flow and Design ExperienceExperience VRM Model SetupVRM Model Setup

The Design Flow and Design The Design Flow and Design ExperienceExperience VRM Model SetupVRM Model Setup VRM model can be assigned by using the created model in the

“Define Circuit Models”. VRM model can be assigned by using the created model in the

“Define Circuit Models”.

The Design Flow and Design The Design Flow and Design ExperienceExperience Decoupling Capacitor AssignmentDecoupling Capacitor Assignment

The Design Flow and Design The Design Flow and Design ExperienceExperience Decoupling Capacitor AssignmentDecoupling Capacitor Assignment Capacitor models can be automatically assigned if the layout model

name matches the “Part No.” listed in the “Project Library”. If the capacitor is a non-installed type, the capacitor must be deselected.

Capacitor models can be automatically assigned if the layout model name matches the “Part No.” listed in the “Project Library”.

If the capacitor is a non-installed type, the capacitor must be deselected.

The Design Flow and Design The Design Flow and Design ExperienceExperience Impedance Observation Setup Impedance Observation Setup

The Design Flow and Design The Design Flow and Design ExperienceExperience Impedance Observation Setup Impedance Observation Setup The reference impedance and current excitation can be defined for each

impedance observation point, and these definitions would affect the optimized result.

The reference impedance and current excitation can be defined for each impedance observation point, and these definitions would affect the optimized result.

The Design Flow and Design The Design Flow and Design ExperienceExperience Other Circuits SetupOther Circuits Setup

The Design Flow and Design The Design Flow and Design ExperienceExperience Other Circuits SetupOther Circuits Setup For the transistor, the circuit must be manually created by “Circuit/Linkage

manager”, and a DC resistor model can be assigned for the transistor circuit.

For the transistor, the circuit must be manually created by “Circuit/Linkage manager”, and a DC resistor model can be assigned for the transistor circuit.

The Design Flow and Design The Design Flow and Design ExperienceExperience Frequency Range SetupFrequency Range Setup

The Design Flow and Design The Design Flow and Design ExperienceExperience Frequency Range SetupFrequency Range Setup

The frequency range needs to be specified by referring to the bandwidth of current excitation.

The “Starting Time” and “Ending Time” also need to be specified if the time-domain verification is needed.

Entire simulation setup can be completed by the following workflow.

The frequency range needs to be specified by referring to the bandwidth of current excitation.

The “Starting Time” and “Ending Time” also need to be specified if the time-domain verification is needed.

Entire simulation setup can be completed by the following workflow.

The Design Flow and Design The Design Flow and Design ExperienceExperience Power Nets Selection for the OptimizationPower Nets Selection for the Optimization

The Design Flow and Design The Design Flow and Design ExperienceExperience Power Nets Selection for the OptimizationPower Nets Selection for the Optimization To select the power net with the impedance observation point is the first

step of the capacitor optimization. To select the power net with the impedance observation point is the first

step of the capacitor optimization.

The Design Flow and Design The Design Flow and Design ExperienceExperience Capacitor’s Candidate SelectionCapacitor’s Candidate Selection

The Design Flow and Design The Design Flow and Design ExperienceExperience Capacitor’s Candidate SelectionCapacitor’s Candidate Selection The check mark must be deselected if that capacitor cannot be

replacement. The condition of the replaceable capacitor is able to be filtered by using the

capacitor’s size.

The check mark must be deselected if that capacitor cannot be replacement.

The condition of the replaceable capacitor is able to be filtered by using the capacitor’s size.

The Design Flow and Design The Design Flow and Design ExperienceExperience Cost Constraint and Optimization FrequencyCost Constraint and Optimization Frequency

The Design Flow and Design The Design Flow and Design ExperienceExperience Cost Constraint and Optimization FrequencyCost Constraint and Optimization Frequency If the optimization result is not good as expected, to adjust cost constraint

may be able to improve the optimization result. The optimization frequency range must be the same or smaller than the

defined simulation frequency range.

If the optimization result is not good as expected, to adjust cost constraint may be able to improve the optimization result.

The optimization frequency range must be the same or smaller than the defined simulation frequency range.

The Design Flow and Design The Design Flow and Design ExperienceExperience Optimization Settings of Impedance ObservationOptimization Settings of Impedance Observation

The Design Flow and Design The Design Flow and Design ExperienceExperience Optimization Settings of Impedance ObservationOptimization Settings of Impedance Observation The “Weighting” can help the simulator to determine how we concern on

each impedance observation point. The weight setup is able to refer to the information of the power consumption.

The “Weighting” can help the simulator to determine how we concern on each impedance observation point. The weight setup is able to refer to the information of the power consumption.

The Design Flow and Design The Design Flow and Design ExperienceExperience Optimization Result ReviewOptimization Result Review

The Design Flow and Design The Design Flow and Design ExperienceExperience Optimization Result ReviewOptimization Result Review A Performance vs. Cost chart is able to provide user numerous

solutions/scheme for the capacitor replacement. The impedance plot can be used to compare the self-impedance of

original design with the self-impedance of each scheme.

A Performance vs. Cost chart is able to provide user numerous solutions/scheme for the capacitor replacement.

The impedance plot can be used to compare the self-impedance of original design with the self-impedance of each scheme.

The Design Flow and Design The Design Flow and Design ExperienceExperience Time Domain VerificationTime Domain Verification

The Design Flow and Design The Design Flow and Design ExperienceExperience Time Domain VerificationTime Domain Verification For the impedance plot, if it is difficult to know which scheme is the

appropriate solution for the design consideration, the time domain verification can help the user make the decision.

For the impedance plot, if it is difficult to know which scheme is the appropriate solution for the design consideration, the time domain verification can help the user make the decision.

The Design Flow and Design The Design Flow and Design ExperienceExperience Placement ReportPlacement Report

The Design Flow and Design The Design Flow and Design ExperienceExperience Placement ReportPlacement Report An Excel format report can be

generated, and the capacitor replacement table of each scheme is listed.

The table can be translated for user’s format, and the updated list can be used for manufacture.

An Excel format report can be generated, and the capacitor replacement table of each scheme is listed.

The table can be translated for user’s format, and the updated list can be used for manufacture.

VerificationVerification Power Noise Measurement (3.3V Rail)Power Noise Measurement (3.3V Rail)VerificationVerification Power Noise Measurement (3.3V Rail)Power Noise Measurement (3.3V Rail) It is recommended to create an updated BOM for the chosen scheme,

and the manufacture is able to install those capacitors by SMT process. The verification of 3.3V power rail is based on the manually re-work.

Therefore the measurement result includes the adverse parasitic of solder.

Original Design: Vp-p= 4.8 mV Chosen Scheme: Vp-p= 3.6 mV

It is recommended to create an updated BOM for the chosen scheme, and the manufacture is able to install those capacitors by SMT process.

The verification of 3.3V power rail is based on the manually re-work. Therefore the measurement result includes the adverse parasitic of solder.

Original Design: Vp-p= 4.8 mV Chosen Scheme: Vp-p= 3.6 mV

4.8mV 3.6mV

ConclusionConclusionConclusionConclusion It is very easy to use OptimizePI for the PDS analysis and the

simulation can be completed by the listed workflow. OptimizePI can automatically replace/remove capacitors, and it

would save lots of engineering time. Both frequency and time domain responses can be observed for the

PDS analysis. OptimizePI is able to avoid costly over-design. OptimizePI helps engineers find a better solution for the robust PDS

design.

It is very easy to use OptimizePI for the PDS analysis and the simulation can be completed by the listed workflow.

OptimizePI can automatically replace/remove capacitors, and it would save lots of engineering time.

Both frequency and time domain responses can be observed for the PDS analysis.

OptimizePI is able to avoid costly over-design. OptimizePI helps engineers find a better solution for the robust PDS

design.