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Using the ClockLock &ClockBoost Features in

APEX Devices

May 1999, ver. 1.0 Application Note 115

Introduction APEXTM 20K devices have the ClockLockTM and ClockBoostTM features, which use PLLs to increase performance and provide clock-frequency synthesis. The ClockLock feature minimizes clock delay and clock skew within the device, reducing clock-to-output and setup times while maintaining zero hold times. The ClockBoost feature allows designers to run the internal logic of the device at a faster or slower rate than the input clock frequency. This technique simplifies board design because the clock path on the board does not have to distribute a high-speed signal. Through the use of time-domain multiplexing, the ClockBoost feature allows the designer to improve device area efficiency by sharing resources within the device.

APEX 20KE devices include PLLs with an enhanced ClockLock feature set, such as advanced ClockBoost capability for m/(n × k) multiplication, low voltage differential signaling (LVDS) support, external clock outputs and feedback ability, and ClockShiftTM circuitry for more complex clock-frequency synthesis applications. These enhanced features permit system-level clock management and skew control in APEX 20KE devices.

The ClockLock and ClockBoost features provide significant improvements in system performance, bandwidth, and System-on-a-Programmable-ChipTM integration. This application note explains the APEX 20K and APEX 20KE ClockLock and ClockBoost features. It also describes common applications for these features.

Clock Delay & Skew

The delay from a clock pin to a register, especially for large devices, can be significant enough to degrade both on- and off-chip performance. The equation for the pin-to-pin clock-to-output delay (tCO) is shown in Figure 1.

The clock delay (tCLOCK) and clock skew (tSKEW) parameters account for a significant portion of the total clock-to-output delay in larger devices. By reducing clock delay and clock skew, the ClockLock and ClockBoost circuitry improves clock-to-output times for the device.

Altera Corporation 1

A-AN-115-01

AN 115: Using the ClockLock & ClockBoost Features in APEX Devices

2 Altera Corporation

Figure 1. APEX 20K & APEX 20KE Hold, Setup & Clock-to-Output Times

Clock skew—the difference between clock delays to different registers— also increases the setup time indirectly. To ensure a zero hold time (tH), a data delay must be added to account for the longest clock delay to any register. This delay must be large enough to ensure a zero hold time under fast process, voltage, and temperature conditions. However, the added data delay also increases the register’s setup time under slow process, voltage, and temperature conditions. When a ClockLock signal feeds a register, the data delay element to the register is bypassed, resulting in a decreased setup time. Because the clock skew and delay is reduced, the register maintains a zero hold time.

As programmable devices become larger, clock delay and skew can become a problem. Also, clock skew can affect a board design. To address these issues, designers can use either phase-locked loops (PLLs) or delay-locked loops (DLLs). Although both can be used to reduce the skew within system clocks, PLLs are more flexible than DLLs for frequency synthesis of system clocks. Additionally, DLLs are not capable of performing m/n scaling. PLLs are ideal for clock multiplication and division applications because they can perform m/n scaling.

ClockLock & ClockBoost Features

The ClockLock and ClockBoost circuitry locks onto the rising edge of the incoming clock. The circuit output drives the clock port of registers. Both negative- and positive-edge-triggered registers can use the ClockLock and/or ClockBoost output in an APEX 20K device.

D Q

D Q

data1

clock

data2

tH = tREG_H + tCLOCK + tSKEW – tDATA

tSU = tREG_SU + tDATA – tCLOCK – tSKEW

tCO = tCLOCK + tSKEW + tREG_CO + tOUTPUT

DataDelay

DataDelay

ClockDelay

Skew

OutputDelay

OutputDelay


Table 1 shows the features for APEX 20K and APEX 20KE devices.

Notes:(1) APEX 20K devices that support ClockLock and ClockBoost features are denoted by an “X” suffix in the ordering

code (e.g., EP20K400FC672-1X).(2) m, n, and k are integers ranging from 1 to 16.

APEX 20K Devices

The APEX 20K PLL offers enhanced ClockLock synchronization circuitry, with an extended output frequency range from 25 MHz to 133 MHz. APEX 20K devices also support enhanced ClockBoost multiplication circuitry, offering 1×, 2×, and 4× clock multiplication. Figure 2 shows the ClockLock and ClockBoost circuitry block diagram.

Table 1. APEX 20K & APEX 20KE ClockLock Features Note (1)

Device Number of PLLs

ClockBoostFeature

Number of External

Clock Outputs

Number of Feedback

Inputs

ClockShift T1/E1 Conversion

LVDS Clock

LVDS Data

EP20K100 1 1×, 2×, 4× – – – – – –

EP20K200 1 1×, 2×, 4× – – – – – –

EP20K400 1 1×, 2×, 4× – – – – – –

EP20K100E 2 m/(n × k) (2) 1 1 v v v –

EP20K160E 2 m/(n × k) (2) 1 1 v v v –

EP20K200E 2 m/(n × k) (2) 1 1 v v v –

EP20K300E 4 m/(n × k) (2) 2 2 v v v vEP20K400E 4 m/(n × k) (2) 2 2 v v v vEP20K600E 4 m/(n × k) (2) 2 2 v v v vEP20K1000E 4 m/(n × k) (2) 2 2 v v v v




Figure 2. ClockLock & ClockBoost Circuitry in APEX 20K Devices

You can use a single output clock of 1×, 2×, or 4× or dual output clocks in any combination of 1×, 2×, and/or 4× for ClockLock circuitry and ClockBoost multiplication circuitry. Table 2 shows the clock combinations supported by the ClockLock and ClockBoost circuitry. These outputs can drive any logic element (LE), I/O element (IOE), or embedded system block (ESB) in the device. The output of the ClockLock and ClockBoost circuits is not available at any of the device pins in APEX 20K devices.

1 The QuartusTM software enables the ClockLock and ClockBoost features in APEX 20K devices; external devices are not required. Designers can use the Quartus software to program these features within APEX devices.

The dedicated clock pin (GCLK1) supplies the clock to the PLL. While the dedicated clock pin is driving the ClockLock or ClockBoost circuitry, it cannot drive any other signals in the device.

÷ 1, 2, or 4

PhaseComparator

Voltage-ControlledOscillator

ClockBoost

ClockLock

PrimaryClock

LockedClock

Table 2. Multiplication Factor Combinations

Clock 0 Clock 1

1× 2×1× 4×2× 4×



Table 3 shows the timing parameters for the APEX 20K ClockLock and ClockBoost features.

Notes:(1) This information is preliminary.(2) All input clock specifications must be met. The PLL may not lock onto an incoming clock if the clock specifications

are not met, creating an erroneous clock within the device.(3) During device configuration, the ClockLock and ClockBoost circuitry is configured first. If the incoming clock is

supplied during configuration, the ClockLock and ClockBoost circuitry locks during configuration, because the lock time is less than the configuration time.

(4) The jitter specification is measured under long-term observation.(5) If the input clock stability is 50 ps, TJITTER is 200 ps.

Table 3. APEX 20K ClockLock & ClockBoost Parameters Notes (1), (2)

Symbol Parameter Minimum Maximum Unit

fOUT Output frequency 25 133 MHz

fCLK1 Input clock frequency (ClockBoost clock multiplication factor equals 1)

25 133 MHz


20 66 MHz


15 33 MHz

tOUTDUTY Duty cycle for ClockLock/ClockBoost-generated clock

40 60 %

tR Input rise time 5 ns

tF Input fall time 5 ns

tLOCK Time required for ClockLock/ClockBoost to acquire lock (3)

10 µs

tSKEW Skew delay between related ClockLock/ClockBoost-generated clocks

500 ps

tJITTER Jitter on ClockLock/ClockBoost-generated clock (4) 250 (5) ps

tINCLKSTB Input clock stability (measured between adjacent clocks)

100 (5) ps



Table 4 lists the APEX 20K ClockLock pins and their function.

Note:(1) LVCMOS: low-voltage complementary metal-oxide semiconductor, LVTTL: low-voltage transistor-to-transistor

logic, PCI: peripheral component interconnect.

APEX 20KE Devices

APEX 20KE devices incorporate multiple ClockLock circuits with advanced features. These features include ClockLock and ClockBoost circuitry with m/(n × k) scaling, LVDS support, ClockShift circuitry, external clock outputs and feedback inputs, and T1/E1 clock domain conversion. Figure 3 shows the ClockLock and ClockBoost circuitry in APEX 20KE devices.

Figure 3. ClockLock & ClockBoost Circuitry in APEX 20KE Devices

Table 4. APEX 20K Device ClockLock Pins

Pin Name Pin Type Description I/O Standard Supported (1)

GCLK1 Input Dedicated pin that drives the ClockLock and ClockBoost circuitry.

2.5-V I/O, LVCMOS, LVTTL, 3.3-V PCI

LOCK Output Optional pin that shows the status of the ClockLock and ClockBoost circuitry. When the ClockLock and ClockBoost circuitry is locked to the incoming clock and generates an internal clock, LOCK is driven high. LOCK remains high as long as the clock input remains within specification.

÷ m

÷ n ÷ k

PhaseComparator Voltage-Controlled

Oscillator

PrimaryClock

LockedClock

LockedClock

ClockShiftCircuitry

ClockLock


EP20K200E, EP20K160E, and EP20K100E devices contain two enhanced general-purpose PLLs with ClockLock, ClockBoost, and ClockShift features, as shown in Figure 4.

Figure 4. PLL & Global Clock Diagram for EP20K200E, EP20K160E & EP20K100E Devices

÷ k

÷ k

PLL 1GCLK1

PLL 3GCLK3

4 DedicatedClocks

CLKLK_FB1

CLKLK_OUT1

APEX 20KE Device

GCLK2

GCLK0



EP20K300E and larger devices contain four enhanced, general-purpose PLL circuits. Two PLLs are designed for either general-purpose or LVDS use. The remaining two PLLs are designed for general-purpose use, as shown in Figure 5.

Figure 5. PLL & Global Clock Diagram for EP20K1000E, EP20K600E, EP20K400E & EP20K300E Devices

Notes:(1) These PLL connections are only used in LVDS mode.(2) PLL 2 or PLL 3 cannot be configured for general purpose and LVDS use simultaneously.(3) CMOS/LVDS interface clock.(4) LVDS/CMOS interface clock.

÷ k ÷ k

÷ k ÷ k

PLL 1

PLL 3

PLL 0

PLL 2

4 DedicatedClocks

CLKLK_FB1

CLKLK_OUT1

CLKLK_FB0

CLKLK_OUT0

GCLK2

GCLK0

GCLK3

CLK_LVDS2CLK_LVDS3

CLKLVDS_OUT3

GCLK1

APEX 20KE Device

(1)(1) (1)(1)

(1)

(3) (4)

(1)

(1)

(2) (2)1× 1×



Table 5 lists the APEX 20KE ClockLock pins and their function.

Notes:(1) AGP: advanced graphics port, CTT: center-tap terminated, GTL+: Gunning transceiver logic, HSTL: high speed

transceiver logic, SSTL: stub-series terminated logic.(2) This pin is available in EP20K1000E, EP20K600E, EP20K400E, and EP20K300E devices only.

Advanced ClockBoost m/(n × k) Multiplication & Division

Each APEX 20KE PLL includes circuitry that provides clock synthesis using m/(n × k) scaling factors. When a PLL is locked, the locked output clock aligns to the rising edge of the input clock. The closed loop equation for Figure 5 gives an output frequency fOUT = (m/(n × k)) fIN. This equation allows the multiplication or division of clocks by a programmable number. Variables m, n, and k are integers ranging from 1 to 16 over specified frequency ranges. The n factor is used for pre-scale division of the input before it is multiplied by m; the k factor is used for post-scale division.

The m/(n × k) multiplication gives a wide range of user-defined multiplication and division ratios that are not possible with DLLs. For example, if a frequency scaling factor of 3.75 is needed for a given input clock, then scale factors of m = 15, n = 2, and k = 2 can be used. This advanced ClockBoost scaling can be performed with a single PLL, making it unnecessary to cascade PLL outputs.

Table 5. APEX 20KE Device ClockLock Pins

Pin Name Pin Type Description I/O Standard Supported (1)

GCLK Input Dedicated pins that drive the PLL clock inputs. 1.8-V I/O, 2.5-V I/O, AGP, CTT, HSTL, LVCMOS, LVDS, LVTTL, GTL+, 3.3-V PCI, SSTL-2, SSTL-3

LOCK Output Optional pin that shows the status of the ClockLock and ClockBoost circuitry. When the ClockLock and ClockBoost circuitry is locked to the incoming clock and generates an internal clock, LOCK is driven high. LOCK remains high as long as the clock input remains within specification.

CLKLK_FB Input Dedicated pins that allow for external feedback to the PLLs.

CLKLK_OUT Output Dedicated clock output that allows the PLL output to be driven off-chip.

CLK_LVDS (2) Input Dedicated pin that drives PLL clock input in LVDS mode for LVDS/CMOS data conversion.

LVDS

CLKLVDS_OUT (2)

Output Dedicated LVDS clock output that allows PLL to drive the LVDS 1× clock off-chip in LVDS mode. LVDS output data is synchronized to this clock.



Separate n and k division factors ensure that each PLL’s voltage-controlled oscillator (VCO) operates in its specified frequency range. Clock inputs that exceed the maximum output frequency of 200 MHz when multiplied should be divided by n (pre-scaled) before multiplication. For example, use a m/n scale factor of 7/5 together with a 125-MHz clock to obtain a 175-MHz clock output. A value of n = 5 should be used because it will divide, or pre-scale, the input clock before the multiplication by m = 7; the multiplied rate of 125 × 7 without first dividing by 5 first exceeds the VCO maximum frequency range. The reverse is true when using low-frequency inputs. The multiplication should be performed first to ensure that the VCO operates at its minimum frequency and then division should be performed with the k post-scale factor. For example, multiply an input clock of 5 MHz by a value of m, or m/n, to obtain a frequency ≥ 20 MHz. This value can then be divided to a desired frequency that is less than 20 MHz by using the k value. The Quartus software helps to choose the appropriate scaling factors.

Duty cycle correction for outputs with 50/50 duty cycle is also available. Setting k to an even number will give approximately 50/50 duty cycle, and can be chosen along with m for odd numbered clock multiplication. For example, by setting m = 6 and k = 2, a 3× clock can be generated with 50/50 duty cycle.

When the PLL is configured for the LVDS interface, the scaling factor ability changes. In LVDS mode, fOUT = (w) fIN where w = 4, 7, or 8. Tables 6 through 8 show the ClockLock and ClockBoost parameters and scaling factor parameter specifications and conditions.

Table 6. APEX 20KE ClockLock & ClockBoost Parameters

Symbol Parameter Minimum Maximum Unit

fOUT Output frequency 1.25 200 MHz

fIN Input clock frequency (general-purpose PLL)

1.5 160 MHz

fINLVDS Input clock frequency (PLL in LVDS mode)

30 80 MHz

Table 7. Rate Multiplication for General-Purpose PLLs in APEX 20KE Devices Note (1)

Scale Factor Parameter Minimum Maximum Unit fINm, n, k Multiplication factors 1 16 Integer 1.5 to 20 MHz (2), (3)

1 8 Integer 30 to 160 MHz (2), (3)



Notes to tables:(1) Scale factor values and fIN must meet these conditions simultaneously:

1.5 MHz ≤ (fIN/n) ≤ 160 MHz20 MHz ≤ (fIN × (m/n)) ≤ 200 MHz

(2) These parameters are preliminary. For the most up-to-date information, contact Altera Applications.(3) The PLL VCO frequency range is 20 MHz ≤ fOUT ≤ 200 MHz.(4) The PLL VCO frequency range when used for LVDS is 200 MHz ≤ fOUT ≤ 622 MHz.

For APEX 20KE devices at low frequencies (< 16 MHz), the input jitter tolerance is 2% of the period. Avoid high-frequency multiplication for low-frequency inputs with high jitter. Otherwise, the high jitter of the low-frequency input is reflected in the high frequency output and can be substantial. For example, you could use a 1.5-MHz input frequency to generate a 24-MHz output frequency by setting m = 16. In this case, the input jitter is allowed to be 13 ns, or 2% of the period, and the PLL will still lock. However, a 250 ps output jitter for the 24-MHz clock output cannot be expected if there is a 13-ns input jitter. In this multiplication application, results are improved with less input jitter.

T1/E1 Clock Conversion

Two of the general-purpose PLLs include special circuitry to support T1/E1 conversion. The T1 telecommunications standard uses a 1.544-MHz clock, and the E1 telecommunications standard uses a 2.048-MHz clock. Two of the general-purpose LVDS PLLs in EP20K1000E, EP20K600E, EP20K400E, and EP20K300E devices can convert a T1 clock to an E1 clock, and vice versa. T1/E1 conversion is only available when these PLLs are used for general-purpose use. One of the PLLs in EP20K200E, EP20K160E, and EP20K100E devices can convert a T1 clock to an E1 clock, and vice versa.

Table 8. Rate Multiplication for PLLs used for LVDS in APEX 20KE Devices Note (4)

Scale Factor Parameter Value Unit fINw Multiplication factors 7, 8 Integer 30 to 80 MHz (2)

4 Integer 50 to 80 MHz (2)



Configuration for LVDS Interface

In EP20K300E and larger devices, two of the ClockLock PLLs can be configured for use in LVDS I/O interfaces. When using LVDS, the I/O clock can be multiplied to support high-speed data transfer rates and to convert between LVDS and CMOS data. These PLLs interface with the APEX 20KE LVDS input and output blocks. The clock input can be multiplied by 4, 7, or 8 to capture or convert to LVDS data. The PLL can also be bypassed for lower-speed LVDS inputs.

External Clock Outputs

In EP20K300E and larger devices, low-jitter external clocks, CLKLK_OUT0 and CLKLK_OUT1, are available for external clock sources. In EP20K200E, EP20K160E, and EP20K100E devices, one external clock, CLKLK_OUT1, is available for an external clock source. The CLKLK_OUT0 signal originates from the general-purpose PLL 0. The CLKLK_OUT1 signal originates from general-purpose PLL 1. Other devices on the board can use these outputs as clock sources. The PLL incorporates multiplication circuitry which can be used with an external clock.

If you are using CLKLK_OUT with or without feedback along with an internal global signal from the same PLL, a delay occurs between an internal global signal and CLKLK_OUT. When using the CLKLK_FB pin, the PLL adjusts CLKLK_OUT to align with GCLK. When you are not using feedback, the Quartus software allows you to choose which signal—CLKLK_OUT or the global signal—is aligned to GCLK. In either case, if both signals need to be aligned to GCLK, two PLLs should be used.

When using LVDS, the CLKLVDS_OUT pin is available to drive the PLL LVDS 1× clock off-chip. The LVDS output data is synchronized with low skew margin to the LVDS output clock.

External Feedback Inputs

In addition to the clock output capability, feedback inputs can be used to align the feedback clock with the input clock. By aligning these clocks, you can actively remove clock delay and skew between devices. You cannot use the phase shift capability of the ClockShift circuitry if a CLKLK_OUT signal is used with an external feedback input.

When using the CLKLK_FB pin, the CLKLK_OUT frequency should not be divided on the board and fed back to the APEX 20KE device. The CLKLK_FB pin is intended for clock skew adjustment, not frequency adjustment.



Lock Signals

The APEX 20KE ClockLock circuitry supports individual LOCK signals. The LOCK signal drives high when the ClockLock circuit has locked onto the input clock. Lock remains high as long as the clock input remains within specification. It will go low if the input is out of specification for three consecutive clock cycles. A LOCK pin is optional for each PLL used in the APEX 20KE devices; when not used, they are I/O pins.

ClockShift Circuitry

APEX 20KE PLLs have ClockShift circuitry that provides programmable clock delay and phase shift. Programmable clock delay allows for step delays in increments of 0.5 ns for a total of –2 ns lagging or +2 ns leading output clock edges with respect to the input. The time delay setting (N) has 15% tolerance within the device, e.g., N ± (N × 15%), where N = 0.5, 1.0, 1.5, or 2.0. The clock phase can be adjusted by 90˚ steps for phase shifting of 90˚, 180˚, or 270˚. The phase-adjusted and non-adjusted versions of the same clock can be distributed on two different clock lines. The Quartus software automatically configures the ClockShift circuitry for the user-specified angle shift and/or delay shift. In LVDS mode, the PLL ClockShift circuitry is not available.

The APEX 20K and APEX 20KE ClockLock circuits are designed to align to the rising edges of the clock input. The ClockShift circuitry also adjusts the clock with respect to rising edges. The falling edges of clock signals are determined by the duty cycle specification and are not adjustable. By setting k to an even number (i.e., dividing by an even number), the output clock cycle will be approximately 50%.

Board Layout Each PLL requires its own VCC and GND pins. APEX 20K devices have one pair of VCC and GND pins for the ClockLock and ClockBoost circuitry. APEX 20KE devices require a VCC and GND pair for each PLL and each clock output pin. Table 9 shows the power pins required for APEX 20K and APEX 20KE devices.



Power supply noise, such as ground bounce and VCC sag, directly affects clock jitter. To avoid excessive jitter, use proper power supply decoupling. To ensure noise resistance, isolate the power and ground supply to the ClockLock and ClockBoost circuitry and clock outputs from the power and ground to the rest of the device. Use dedicated printed circuit board (PCB) traces to power the ClockLock circuits and the clock outputs, separate from the VCCINT/GNDINT and VCCIO/GNDIO planes. Each of the VCC_CKLK/GND_CKLK and VCC_CKOUT/GND_CKOUT pairs should be fed with wide, dedicated PCB traces coming from the power supply to avoid coupling between PLLs. Each of the VCC_CKLK/GND_CKLK and VCC_CKOUT/GND_CKOUT pairs should be decoupled with a 0.2-µF power-supply decoupling capacitor located as close as possible to the APEX 20K device. Place a 100-µF capacitor immediately adjacent to the location where the power-supply lines for the ClockLock and ClockBoost circuits come into the PCB. See Figure 6.

Table 9. Power Pin Requirements for APEX 20K & APEX 20KE ClockLock & ClockBoost Features

Device Pin Name Description

EP20K100EP20K200EP20K400

VCC_CKLK

GND_CKLK

Power and ground pins for the ClockLock and ClockBoost circuitry. To ensure noise resistance, the power and ground supply to the ClockLock and ClockBoost circuitry should be isolated from the power and ground to the rest of the device.

EP20K100EEP20K160EEP20K200E

VCC_CKLK[1..0]

GND_CKLK[1..0]

VCC_CKOUT

GND_CKOUT

Power and ground pins for the ClockLock and ClockBoost circuitry and clock outputs. To ensure noise resistance, the power and ground supply to the ClockLock and ClockBoost circuitry and clock outputs should be isolated from the power and ground to the rest of the device.

EP20K300EEP20K400EEP20K600EEP20K1000E

VCC_CKLK[3..0]

GND_CKLK[3..0]

VCC_CKOUT[1..0]

GND_CKOUT[1..0]

Power and ground pins for the ClockLock and ClockBoost circuitry and clock outputs. To ensure noise resistance, the power and ground supply to the ClockLock and ClockBoost circuitry and clock outputs should be isolated from the power and ground to the rest of the device.



Figure 6. Power Supply Decoupling

Note:(1) The VCC_CKOUT and GND_CKOUT pins are only available on APEX 20KE devices.

Applications Various applications can use the features of the APEX 20K and APEX 20KE PLL circuits. This section describes some of the possible applications.

Clock Multiplication & Division

The ClockBoost feature allows the designer to reduce the effects of high-speed signals by using a low-speed clock on the board. The ClockBoost feature is used to increase the on-chip speed. Reducing transmission line effects allows the designer to simplify board layout. In APEX 20K devices, the board clock can be multiplied by 2 or 4 within the device. More complex ratios are possible with APEX 20KE devices. See Tables 7 and 8 on pages 10 and 11 for more information.

Clock multiplication and division are useful for communications applications. The ClockBoost feature can be used when transfer rates must be multiplied or divided. The multiplication and division of clocks is also needed to maintain bit rates when converting between parallel data streams and serial data streams.

0.2 µF

0.2 µF

VCC GND

VCC_CKLK

GND_CKLK

VCC_CKOUT (1)

GND_CKOUT (1)

APEX 20KE Device

100 µF



In microprocessor-based systems, a system clock may run at a lower rate than other system components. For example, an embedded processor or its peripheral circuits may run at a faster rate than the system I/O bus clock. Embedded applications also require faster internal rates for operations such as synchronization and counting. The ClockBoost feature can be used to multiply a slower system bus clock for an embedded application in an APEX 20K device. The multiplication and division capabilities of an APEX 20K device give designers the ability to develop System-on-a-Programmable-Chip designs. Figure 7 shows clock synthesis in an embedded application.

Figure 7. Embedded Application Using Clock Synthesis

The ClockBoost feature can be used to create variable-size pulse widths. By using a multiplied frequency and a counter, you can create pulse widths of various sizes depending on the multiplied frequency driving the counter. These pulses can be used to interface with external SRAM or DRAM. For example, write enable (WE), row address strobe (RAS), and column address strobe (CAS) signals can be generated for an SDRAM interface, meeting appropriate address and data setup times. See Figure 8.

MicroprocessorSystem

Clock8 MHz

Logic

Logic

Logic

Logic

PLL2×

PLL4×

PLL8×

PLL16×

16 MHz

32 MHz

64 MHz

128 MHz



Figure 8. Using Multiplication to Generate Pulses

Removing Board Delay

APEX 20KE device feedback pins allow the designer to reduce the clock skew between several devices on a board. The PLL actively aligns the feedback input to the GCLK input clock. The PLL dynamically adjusts the output during operation to account for delay changes that occur due to temperature or voltage. While designing the board, you should match the return delay containing the feedback input with the delay to each device involved. Similar delays ensure that the aligned feedback input edge is also aligned at the destination devices, eliminating delay. Figure 9 illustrates how board delay is reduced using an APEX 20KE device.

CLK

CLK × 2

ADDR

DATA

WE

A0 A1 A2

D1

CLK

CLK × 4

Pulse



Figure 9. Reducing Board Delay Using an APEX 20KE Device Note (1)

Note:(1) For board design, the route delay from CLKLK_OUT1 to each device and the return

route delay to FB1 should be equal.

Minimize the delays between the CLKLK_OUT and CLKLK_FB signals in APEX 20KE devices. Because the feedback path closes the loop, a long delay of board fly time can add poles and phase lag to the PLL loop, resulting in an unstable output. Be sure the PLL clock-out time plus board fly time is less than the period of CLKLK_FB.

LVDS

In EP20K300E and larger devices, two of the general-purpose PLLs can be configured for use in LVDS interfaces. These PLLs interface with the APEX 20KE LVDS differential input and output blocks. You can multiply the clock input by 4, 7, or 8 for LVDS/CMOS data conversion using dedicated, built-in parallel-to-serial and serial-to-parallel converters.

APEX 20KE Device

GCLK1

CLKLK_FB1

CLKLK_OUT1

Device

Device

Device



When the APEX 20KE device is configured to use LVDS, it uses PLL 2 to multiply the CLK_LVDS2 input. Serial-to-parallel conversion circuitry uses the multiplied clock to convert the high-speed serial LVDS data to lower speed parallel CMOS data. The multiplication factor used should match the multiplexer/de-multiplexer ratio desired. For example, if a conversion of 1-to-8 is required for a 622-Mbps LVDS channel, the multiplication factor needed is 8 with a clock input of 77.75 MHz. If needed, the serial-to-parallel converter and PLL can be bypassed for low-speed LVDS data inputs. Figure 10 shows the built-in LVDS input interface with the LVDS serial input at 622 Mbps and the multiplexer/de-multiplexer ratio at 1-to-8.

Figure 10. APEX 20KE LVDS PLL/Input Interface

When the APEX 20KE device is configured to use LVDS, it uses PLL 3 to multiply the CLK_LVDS3 input. Parallel-to-serial conversion circuitry uses the multiplied clock to convert the lower speed parallel CMOS data to higher speed serial LVDS output data. The multiplication factor should match the multiplexer/de-multiplexer ratio desired. For example, if a conversion of 7-to-1 is needed for a 462-Mbps LVDS output, the multiplication factor of 7 is needed with an input clock of 66 MHz. If needed, the parallel-to-serial converter and PLL can be bypassed for a low-speed LVDS serial output. Figure 11 shows the built-in LVDS output interface that converts internal parallel data into LVDS serial data with a 7-to-1 ratio at 462 Mbps.

I/O Serial-to-Parallel

Converter

data[7..0]

Dedicated Clock

622 MHz (8×)

77.75 MHz (1×)

Serial Data 622 Mbps

CLK_LVDS277.75 MHz Clock

PLL 2

APEX 20KE LVDS

+

–

+

–



Figure 11. APEX 20KE LVDS PLL/Output Interface

Note:(1) In LVDS mode, PLL 3 is fed by CLK_LVDS3 or one of the three remaining internal global clocks.

T1 & E1 Clock Domain Conversion

In APEX 20KE devices, the ClockBoost circuitry can be used to convert a T1 clock frequency (1.544 MHz) to an E1 clock frequency (2.048 MHz), and vice versa. The ClockLock circuit has a special mode to perform T1/E1 conversions; this multiplication is not done just by setting k, m, and n to appropriate values.

As with any type of clock domain data transfer, use the appropriate asynchronous design techniques to transfer data from one clock domain to the other. For example, the DCFIFO first-in first-out (FIFO) function can be used to buffer the data transfer. Figure 12 shows a DCFIFO that interfaces between clock domains. For example, a DCFIFO is fed with input data clocked by the PLL input T1 clock. The output of the DCFIFO should be clocked with the converted E1 clock from the PLL output. Output data is synchronized to the PLL output E1 clock. This same practice is used for synchronization across other clock domains.

Built-in I/OParallel-to-Serial

Converter

data[6..0]

Internal Global Clock66 MHz (1×)

66-MHz CLK_LVDS3462 MHz (7×)

PLL 3

Internal GlobalClocks (1)

Serial Data 462 MbpsAPEX 20KE LVDS Interface

+

–

+

–

CLKLVDS_OUT3+

–



Figure 12. Using DCFIFO to Interface Between Clock Domains

Time-Domain Multiplexing

The ClockBoost feature allows the designers to implement time-domain multiplexed applications in which a given circuit is used more than once per clock cycle. Depending on whether the circuit is clocked by the 2× or 4× ClockBoost circuitry in the APEX 20K device, it can operate two or four times, respectively, per system cycle. With time-domain multiplexing, a given function can be implemented with fewer logic cells or ESBs.

For example, in a circuit using two 16 × 16 multipliers, each multiplier uses 447 LEs for a total of 894 LEs. Alternatively, you could implement the circuit as one multiplier that is used twice per clock cycle by using a clock that is 2× the system clock. The input of the multiplier is multiplexed so it can switch between two sets of inputs; the output is de-multiplexed so that it can drive out the two multiplication results. While some LEs are needed to accomplish the multiplexing, the cost is outweighed by the LEs saved from using one multiplier. Figure 13 shows a schematic of the time-domain multiplexed circuit.

rdreq

wrreq wrreq

T1_data

E1_sync_data

E1_clk

T1_clk

RDCLK

RDREQ (ACK)

WRCLK

DATA

Q

DCFIFO

WRREQ

PLL with T1/E1 ClockBoost Feature



Figure 13. Time-Domain Multiplexed Circuit

The same example can be applied to a circuit requiring four multipliers; the circuit would use a 4× clock and 4-to-1 multiplexers instead of the 2-to-1 multiplexers shown in Figure 13. A control line bus can be created using a one-hot counter or state machine to enable one output bus register per 4× clock cycle, permitting one multiplier to be used four times in a single system clock cycle. Table 10 shows the reduction in resource requirements.

Ddataa1[15..0]

Ddatab1[15..0]

D

D

D

dataa2[15..0]

Ddatab2[15..0]

ENA

ENA

16 × 16Multiplier

productb[31..0]

producta[31..0]

control signal

ClockLock

ClockBoost × 2clk

Table 10. Resources Required for 16 × 16 Multipliers

Design LEs Required

Two 16 × 16 multipliers 894

Two 16 × 16 multipliers, time-domain multiplexed with 2× ClockBoost

547

Four 16 × 16 multipliers 1,788

Four 16 × 16 multipliers, time-domain multiplexed with 4× ClockBoost

741



ClockShift Applications

Phase and time delay adjustments of PLL clock outputs have many interface applications. For example, adjusting the delay allows the designer to meet strict timing requirements more easily. By adjusting the lead or lag of the clock output, a known clock delay between various clocks can be used to improve the clock-to-output and setup times for APEX 20KE or external devices.

Some high-speed SDRAMs and other devices have access times that require fast setup times on the interface device for a given critical path. To meet this requirement, adjust the external clock output to the SDRAM so that it leads the input clock by a specified amount of time. By adjusting the clock edge, the SDRAM’s clock-to-output (tCO) will be sooner, meeting the fast setup time. Figure 14 shows the interface and timing between an APEX 20KE device and SDRAM. For example, you can have an APEX 20KE device reading from a high-speed SDRAM with a tCO of 5.5 ns. Assuming a 100-MHz system speed, 10-ns period, and 3-ns board propagation delay (tPD) between the SDRAM and APEX 20KE device, the combination of the tPD and tCO delays is 8.5 ns. This leaves only 1.5 ns for setup time into the APEX 20KE device. By adjusting the output clock to the SDRAM to lead an amount equal to tSU (for the APEX 20KE device) minus the tSU needed, the timing requirement can be met.



Figure 14. Using ClockShift to Meet SDRAM Timing

In addition to meeting setup times, an intentional clock delay can improve the device’s clock-to-output time, similar to how the clock-to-output time in the SDRAM interface was improved. Using a lagging clock for output devices makes the device’s clock-to-output time faster when compared to the system’s clock. An internal leading clock used on I/O registers also produces a faster clock-to-output time on output registers.

You can also use clock delay control instead of feedback to adjust clock delay to other devices based on their distance from the clock source. Designers manually adjust the external clock output of the APEX device to compensate for board delay.

You can also use phase adjustment to interface with an external device. An input clock can be phase shifted with two separate ClockLock and ClockBoost circuits and then output to the two external outputs. For example, these external outputs can be used together with the input for a 3-phase DC motor.

SDRAM

APEX 20KE DevicetCO tSUtPD

clk_infeedback

tPERIOD

tPERIOD

Required tSU

tCO + tPDclk_in

sdram_clk

tSU for APEX 20KE device

PLL withClockShift



In APEX 20KE devices, programmable phase shift is limited to one period of the VCO. Figure 15 shows the relationship between the scaling factors and the VCO. When the m scale factor is large, the period of the VCO is much smaller than the input period, i.e., tVCO is much lower than tCLKIN. If the k scale factor is large as well, the VCO period is much smaller than the output period, i.e., tVCO is much lower than tCLKOUT. The range of phase adjustments is limited by the VCO period; a small VCO period compared to the output clock period means the phase range will be especially small for clock output. Figure 15 shows example waveforms for how scaling factors affect the phase range. Choose n, m, and k so that the VCO period is long enough for the desired phase shift range.

Figure 15. Scaling Factor Relationship to Voltage-Controlled Oscillator

Software Support

The ClockLock and ClockBoost features in APEX 20K devices are enabled through the Quartus software. The software uses the CLKLOCK megafunction to utilize the ClockLock and ClockBoost features, which allows the user to specify the operating frequency for the input and the ClockBoost clock multiplication factor.

clkin clkout1n

1k

1m

VCO

clkin (n = 1)

fVCO (m = 9)

clkout (k = 7)

Phase shift limit = 1 VCO period

ClockShiftCircuitry



GCLK1 is the dedicated input that feeds both the ClockLock and ClockBoost circuitry. Any two combinations of output clocks can be utilized, such as 1× and 2×, 1× and 4×, or 2× and 4×. When two outputs are generated, the other clock pin (GCLK0) cannot be used. For designs that require two outputs from the ClockLock and ClockBoost circuits, the clock trace on the board should be connected to GCLK1 only. When two clock outputs are used, the input frequency parameter must be the same for both circuits. In this case, the input frequency parameter must meet the requirements specified for the highest multiplied output clock. For example, if both a 2× and 4× output is used, the input frequency must meet the 4× input frequency requirement of 15 MHz to 33 MHz.

Figure 16 shows a block diagram example of how to enable two ClockBoost circuit outputs in the Quartus software. The example shown is a schematic, but a similar approach applies for designs created in the Altera Hardware Description Language (AHDL), VHDL, and Verilog HDL.

Figure 16. Implementing Multiple ClockLock & ClockBoost Functions

The parameterized CLKLOCK function also allows APEX 20KE devices to control multiplication and shifting. You can use this function in the Quartus design entry editors (AHDL, VHDL, Verilog HDL, and Block Editor). The Quartus software includes a utility for generating the simulation files in VHDL or Verilog HDL for third-party tools.

D Q

D Q

CLOCKBOOST=4INPUT_FREQUENCY=33

CLKLOCK

CLOCKBOOST=2INPUT_FREQUENCY=33

CLKLOCK

gclk1

a

b

outa

outb



Conclusion The advanced APEX 20K ClockLock and ClockBoost features use PLLs to provide significant improvements in system performance and design versatility. The reduction in clock delay and the elimination of clock skew within the device improves design speed, and time-domain multiplexing improves area usage. The ClockBoost feature simplifies board design by running the internal logic of the device at a faster rate than the input clock frequency. The advanced APEX 20KE ClockLock and ClockBoost feature set is further enhanced with m/(n × k) multiplication, LVDS I/O interfaces, and phase adjustment for more complex clock synthesis applications.



®

Altera, APEX, APEX 20K, APEX 20KE, ClockBoost, ClockLock, ClockShift, EP20K100, EP20K100E,EP20K160E, EP20K200, EP20K200E, EP20K300E, EP20K400, EP20K400E, EP20K600E, EP20K1000E, Quartus,and System-on-a-Programmable-Chip are trademarks and/or service marks of Altera Corporation in theUnited States and other countries. Altera acknowledges the trademarks of other organizations for theirrespective products or services mentioned in this document. Altera products are protected under numerousU.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrantsperformance of its semiconductor products to current specifications in accordance with Altera’s standardwarranty, but reserves the right to make changes to any products and services at any time without notice.Altera assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing byAltera Corporation. Altera customers are advised to obtain the latest version of devicespecifications before relying on any published information and before placing orders forproducts or services.

Copyright 1999 Altera Corporation. All rights reserved.

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