voltage controlled oscillator (vco) -...
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27/03/2019
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Voltage controlled oscillator (VCO)
2
Oscillation frequency
TC22
0
21
21
2
0LC
1
)V(CCL
1
)]V(CLL[CC
CC
1
)]V(LC1[Lj)V(LC1
LjZ 2
2
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2
3
VCO gain /1
2
0
2
C
2
2
0
0
0 f)V(CL2)V(CCL4
)V(CL42/1Logf
f
f
30
2
0
Lf2
f)V(C
)V(CCL4LogLogf2 C2
0
4
VCO gain /2
Bi
0j
V/V1
C)V(C
V
)VV(
CV2/1V
)V/V1(
C
V
12/1)V(C
2/3Bi
0jBi
2/3Bi
0j
Bi
2/3
Bi
Bi
0jc
0jBi
2/3BiT
0jBi
V
)]VV(V/V1
CC[L8
CV
)]VV(C[L8
CVVk
2/3Bi
0jBi30
200V
)VV(
CVLf
V
C
C
f
V
fk
T
0LC)2(
1f
Poiché:
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5
Phase-locked loop (PLL) /1
• PLL is a system that allows synchronization of local oscillator in the receiver to received data: the phase-locked oscillator can be used or received signal regeneration
• The system performs evaluation of the phase of received signal, and then synchronization of VCO phase by means of a DC feedback loop
6
Phase-locked loop (PLL) /2
• The overall system comprises a Phase Detector, a low-pass filter with pulse response w(t), and a VCO
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Phase-locked loop (PLL) /3
• Under the hypothesis that the received signal vi(t) shows
instantaneous phase i(t), and that at initial time instant it
shows a phase difference vi(0) with respect to the signal at
VCO output:
vv(t) = Av(t) · sin(v t + vi(0))
vi(t) = Ai(t) · sin(i t)
• Kp is the phase detector gain, and Kv the VCO gain
8
Phase-locked loop (PLL) /4
• The system can be represented by means of the equivalent scheme below:
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Phase-locked loop (PLL) /5
ep(t) = Kp · [i(t) - v(t)] Ep(s) = Kp · [i(s) -v(s)]
ev(t) = ep(t) w(t) Ev(s) = Ep(s) ∙ W(s)
v(t) = 0 + Kv · ev(t)
10
Phase-locked loop (PLL) /6
• In order to understand the PLL dynamic behavior, we suppose
that at the initial time instant the system is in lock (i = 0, ev =
0).
• Moreover, we suppose a little deviation i(t) (i.e. a small-signal
model can be used) with respect to the value i0 at lock:
iTOT(t) = i0 + i(t)
vTOT(t) = v0 + v(t) = i0 + v(t)
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Phase-locked loop (PLL) /7
• From linear analysis, PLL transfer functions as a function of the loop gain T(s) are derived:
– T(s) = Kp · Kv · W(s) / s
– v(s) / i(s) = T(s) / [1 + T(s)] = H(s)
– (s) / i(s) = [i(s) - v(s)] / i(s) = 1 / [1 + T(s)]
• If Kp · Kv the VCO phase is locked to the received signal phase
12
Phase-locked loop (PLL) /8
• PLL operation can be comprised by evaluating the response to a
step input signal, starting from the lock condition. Both a phase
step and a frequency step are considered:
• In case of phase step i we get:
lim (t) = lim s·(s) = lim s · i/s · 1 / [1 + T(s)] = 0
t s 0 s 0
• In case of frequency step i we get:
lim (t) = lim s·(s) = lim s · i/s2 · 1 / [1 + T(s)] = i / [Kp·Kv·W(0)]
t s 0 s 0
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Phase-locked loop (PLL) /9
• The PLL behaves as a unitary feedback system with loop
gain T(s).
• Loop stability can be checked by tracing the root locus of
loop gain T(s), as a function of the filter transfer function
W(s)
T(s)i(s)] v(s)]
-
14
Phase-locked loop (PLL) /10
• If W(s) = 1 (no filter), T(s) shows a single pole in the origin, and
therefore no instability issues are found
• If W(s) = 1 / (1 + s R C) (R-C filter) T(s) shows a pole in the
origin and a second pole s = -1 / (R C): an oscillation behavior is
found in the time response, and the damping factor decreases
as the loop gain Kp· Kv increases:
CR
KK vpn
vp KKCR2
1
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Phase-locked loop (PLL) /11
• In order to induce oscillation damping, a zero is added in the
filter transfer function, so that the following root locus is found:
16
Phase-locked loop (PLL) /12
• Loop gain expression is:
C)RR(
KK
21
vpn
vp21
2vp
KKC)RR(2
CRKK1
C)RR(s1
CRs1
s
KK)s(T
21
2vp
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Phase-locked loop (PLL) /13
• A more efficient filter topology can be considered exploiting an
operational amplifier (active filter)
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Phase-locked loop (PLL) /14
• In this case we have T(s) = Kp· Kv / s ·(1 + s R2 C) / (s R1 C).
• In particular, W(s) shows a pole in the origin, and the system allows phase lock even in presence of a frequency step
CR
KK
1
vp
n
2
KKC)R/R( vp12
2
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Phase-locked loop (PLL) /15
• The following expression for H(s) is found:
• We’ll see below the effect of PLL in presence of white
phase noise
2nn
2
2nn
s2s
s2)s(H
20
Phase-locked loop (PLL) /16
• The Lock Range is a parameter which accounts for PLL
capability to recover instantaneously (i.e. within a single period)
the lock condition, in presence of phase noise
• The lock Time TL shows inverse proportionality versus the
natural radian frequency of poles n. The lock range L instead
shows direct proportionality versus n. Therefore, a more fast
synchronization is obtained with a grater n value (a greater loop
bandwidth)
• However, a greater loop bandwidth produces more phase noise at
the output
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Phase-locked loop (PLL) /17
• The Lock Range can be evaluated by supposing a stepwise input i:
it corresponds to an input phase error i =it, and at PD output (if
an analog multiplier is used) we find:
ep(t) = Kp · cos(i t)
• At filter output (W(j) = |W(j)| ∙ exp(W(j)) is filter response), the
signal ev(t) is:
ev(t) = Kp |W(ji)| · cos(i t + W(i))
• And maximum radian frequency variation at VCO output is:
MAX = Kp Kv |W(j i)|
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Phase-locked loop (PLL) /18
• The condition to obtain PLL lock within a period, as a function
of VCO tuning range and loop gain, is the following:
L = Kp Kv |W(j L)|
• If an active filter is consider, we have:
L = Kp Kv R2 / R1 = 2 n
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Noise sources in electronic devices /1
dff
IKi
B
AB
F2
kerFlic
F
BIq2i C2Shot
b2T kTBr4e
• The presence of such noise sources in a 2-port network can
be represented by means of a noisy equivalent model
24
Noise sources in electronic devices /2
• The power spectral density of current noise in a CE
amplifier shows the behavior depicted below, in which
three main regions can be seen:
– 1. 1/f behavior due to Flicker noise (up to some KHz)
– 2. Flat behavior due to white noise (Shot & Johnson)
– 3. f2 behavior due to transistor dominant pole
Ieq
f
1 2 3
fnc
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Phase noise in oscillators - 1
• Due to the presence o device noise sources, noise is added
to both amplitude and phase of the oscillators:
• Amplitude modulation can be cancelled by means of a
limiter, while phase noise cannot be eliminated
)]t(tsin[)]t(vV̂[)t(v 0out
dt
)t(d)t( 0
26
Phase noise in oscillators - 2
• Noise can be considered as a phasor that produces
modification of the output signal phasor: both the
amplitude (but it can be neglected) and the phase are
affected. For noise power (i.e. noise variance) we get:
• As it can be seen, power noise is inversely proportional to
signal-to-noise ratio
V̂
)t(n
)t(nV̂
)t(narctg)t( s
c
si
S2
N
S2
Bn)t(2
i
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Phase noise in oscillators - 3
• The signal spectrum shows 2 side-bands with different power,
together with the central frequency (i.e. the oscillation frequency f0)
• If we evaluate the spectral component at fm frequency of a signal
composed of 2 side-bands B1 (at -fm) e B2 (at fm), and f0
• It can be considered as the superposition of an amplitude modulation
and a low-index phase modulation
]t)cos[(B]t)cos[(B)tcos(A)t(v m02m010
28
Phase noise in oscillators - 4
• A symmetrical spectrum is produced by amplitude modulation
• If we suppose a cosine waveform with unitary amplitude and
phase modulation with maximum phase deviation << 90°:
]t)(cos[2
A)t]ωcos[(ω
2
At)cos(ωA
t)cos(ωt)]cos(ω[1Av(t)
m0m00
0m
)]t(sintcos[)t(v m0
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Phase noise in oscillators - 5
• By using trigonometric transformations, we get:
• In the following slide, we can see the overall signal
together with the 2 modulated signals
]t)(cos[2
)t]ωcos[(ω2
t)cos(ωv(t) m0m00
30
Phase noise in oscillators - 6
Overall
Amplitude modulation
Phase modulation
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Phase noise in oscillators - 7
• The Figure of Merit used to account for phase noise
performance is Single Sideband to Carrier Ratio SSCR(),
the ratio between noise in a single sideband = 21Hz
placed at distance from 0, and the overall power:
• Now, a link will be found between physical noise sources
in electronic devices and phase noise, under additive noise
hypothesis
tot
vv
P
)(Slog10)(SSCR
32
Phase noise in oscillators - 8
• Block A amplification is considered as real
• Noise is ‘filtered’ by a resonant network characterized with
its frequency stability coefficient SF:
• Noise N() of electronic devices produces transfer
function phase variation
F
0
S 2
2
F
02
)(N
S
)(S)(S
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Phase noise in oscillators - 9
• Phase noise spectrum can be evaluated from frequency
dependence on noise spectrum
• Around 0 Flicker noise is the main contribution and the
spectrum is:
• Only white noise is found for frequencies greater than the
noise corner frequency (fnc):
3
2
F
0 1
S)(S
2B
2
F
0 TkF
S)(S
34
Phase noise in oscillators - 10
• Noise is no more filtered by the resonant network: the SF
expression used to evaluate phase noise is not valid, and the
phase noise spectrum is white as the noise
• Finally, above the cut-off frequency of the amplifier block, noise
is filtered out by the amplifier transfer function (-20 dB/dec slope
if single-pole response)
S
TkF2)(S B
0
Flicker (-30dB/dec)
White (-20dB/dec)
No filtering
Amp. poles
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PLL Phase noise - 1
• Let’s suppose to start from lock condition and to inject white
noise with B bandwidth
• From PLL transfer functions we get:
• and finally the overall phase noise power spectrum is:
)s()s(H)s( iv
BS2
N)j(H)s(S)j(H)j(S
2i2v
36
PLL Phase noise - 2
• Output phase noise depends on PLL transfer function (and so
from chosen filter):
– No filter:
– RC filter:
– Active filter:
2vp
2
2
vp2
KK
KK)j(H
2n
222n
2
4n2
4)()j(H
2n
222n
2
2n
222n2
4)(
4)j(H
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PLL Phase noise - 3
• In particular, if an active filter is considered, for the output
phase noise power we get:
• Therefore, reduction of phase noise is obtained according to
the factor n/B ( = 0.5 is considered):
4
1
2BS2
N
d)j(HBS2
N
2
1)t(
n
22
v
B
B
S2
Nt n2
i )(
38
PLL Phase noise - 4
• PLL works as LPF for input phase noise, and as a HPF for VCO
phase noise: in both cases, n is the cut-off radian frequency
Kp W(s) Kv + 1/sOUT
ErrVCO
: N1/s
ErrQUARTZ
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4-quadrant Multiplier
• A 4-quadrant multiplier architecture is obtained by driving the Gilbert
cell by means of a differential current iX
• Also temperature compensation is obtained
T
YXF0
V2
vtanhii
40
4-quadrant Multiplier
• A multiplier is obtained under small-
signal hypothesis:
T
XEEFX
V2
vtanhIi
T
Y
T
XEEF0
V2
vtanh
V2
vtanhIi
(REE=0)
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4-quadrant Multiplier
• In case of small-signal inputs at the same radian frequency :
• The tone at radian frequency 2 is cancelled by means of a LPF, and
the output current is proportional the product of the 2 inputs:
T
Y
T
XEEF0
V2
tcosv̂
V2
tcosv̂Ii
2
t2cos1
V2
v̂v̂Ii
2T
YXEEF0
X
Filtered-out
42
4-quadrant Multiplier as Phase Detector• An analog multiplier and a LPF can be used as a phase detector, for instance in a
PLL:
• If the two inputs are at the same frequency but different phase:
• At the output we get:
• The PD gain Kp depends on amplitude of input signals
• In a PLL, when lock condition is found, /2 phase difference is got, as cos() = 0
)t(sinAv)t(sinAv
122
111
)t2cos()cos(2
AAv 1
21out
X
Filtered-out
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