space vs. speed: binary adders 11.3 space vs. speed
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Space vs. Speed: Binary Adders
11.3 Space vs. Speed
Binary Adders
• VHDL Adder
• Carry Lookahead Adder
4-Bit Adder
Full Adder
A B
0 C
S
0 0
1
0
Full Adder
A B
C
S
1 1
2
1
Full Adder
A B
C
S
2 2
3
2
Full Adder
A B
C S
3 3
4 3
C 1 1 1 0A 0 1 0 1B 0 1 1 1S 1 1 0 0
Adder in VHDL
a(3:0)
b(3:0) carry
sum(3:0)
adder
entity adder is port ( a: in STD_LOGIC_VECTOR (3 downto 0); b: in STD_LOGIC_VECTOR (3 downto 0); sum: out STD_LOGIC_VECTOR (3 downto 0); carry: out STD_LOGIC );end adder;
std_logic_arith.vhd
Ci
AiBi00 01 11 10
0
1
1
1 11
Ci+1
Ci+1 = Ai & Bi
# Ci & Bi
# Ci & Ai
std_logic_unsigned.vhd
a(3:0)
b(3:0) carry
sum(3:0)
adder
adder.vhd
Binary Multiplier
Half Adders are SufficientSince there is no Carry-inin addition to the two inputsto sum
2 bit by 2 bit
Binary Multiplier 4 bit by 3 bit
4 bit by 3 bityields
7 bit result
Binary Adders
• VHLD Adder
• Carry Lookahead Adder
Carry Lookahead Adder
C2 = G1 + P1(G0 + P0C0) = G1 + P1G0 + P1P0C0
C3 = G2 + P2(G1 + P1 (G0 + P0C0)) = G2 + P2(G1 + P1 G0 + P0C0) = G2 + P2G1 + P2P1G0 + P2PlP0C0
G0-3 = G3 + P3G2 + P3P2G1 + P3P2PlG0
P0-3 = P3P2PlP0
Ripple Carry Adder (4-bit)
• Typically, longest delay path through n-bit ripple carry adder is 2n + 2• Tends to be one of the largest delays in a typical computer design
Counts as 2 gate delays
2
1
2 4
1
3 4
00
0
4
4
0
0
2
4
56
6
4
4
0
0
2
6
78
8
66
4
4
0
0
2
8
910
10
6
8
68
4
46
8
68
10
10
• 10 Gate Delays• 16-bit Adder -- 34 Gate Delays• 64-bit Adder -- 130 Gate Delays
Carry Lookahead Adder
• Uses Propogate and Generate signals to “lookahead” for incoming carry signals• More complicated hardware configuration• Substantial decrease in gate delays
PFA: Partial Full Adders
Ripple Carry
CarryLookahead
• PropagateP = A xor BIf P = ‘1’ then the carry is “propagated”through. If P = ‘0’ then the carry is not“propagated” through.
• GenerateG = A and BIf G = ‘1’ a carry is “generated” regardlessof the carry bit.
Cin A B
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
Cout S
0 00 10 11 00 11 01 01 1
P G
0 01 01 00 10 01 01 00 1
For final carry determination, the Propagate signal is ANDed with the Carry Outand the Generate signal is ORed to the resulting signal.
G P Cin
Cout
Always Generate a Carry forA = 1, B = 0
Cin A B
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
Cout S
0 00 10 11 00 11 01 01 1
P G
0 01 01 00 10 01 01 00 1
Cin A B
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
Cout S
0 00 10 11 00 11 01 01 1
P G
0 01 01 00 10 01 01 00 1
Propagate the Carry in
Cout
Cout
24
1
2
34
Cout
24
1
2
34
2
23
14
2
12
123
3
4
2
12
3
4
PFA For Bit # 1
24
1
4
2
6
26
1
4
2
6
Bit #1Bit #2
Bit #3Bit #4
1
4
Significant Delay Reduction
• 4 - bit Ripple: 10 DelaysCLA: 6 Delays 1 CLA level: 1*4 + 2 = 6
• 16 - bitRipple: 34 DelaysCLA: 10 Delays 2 CLA levels: 2*4 + 2 = 10
• 64 - bitRipple: 130 DelaysCLA: 14 Delays 3 CLA levels: 3*4 + 2 = 14
But at the expense of a significant increase in the number of gatesused by the circuit
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