sequential circuits design
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Hardware Design with VHDL Sequential Circuit Design II ECE 443
ECE UNM 1 (9/25/12)
Sequential Circuit Design: Practice
Topics Poor design practice
More counters
Register as fast temporary storage
Pipelining
Synchronous design is the most important for designing large, complex systems
In the past, some non-synchronous design practices were used to save chips/area
Misuse of asynchronous reset Misuse of gated clock
Misuse of derived clock
Misuse of asynchronous reset
Rule: you should neveruse reset to clear register during normal operation
Heres an example of a poorly designedmod-10 counter which clears the regis-
ter immediately after the counter reaches "1010"
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Poor Sequential Circuit Design Practice
libraryieee;useieee.std_logic_1164.all;
useieee.numeric_std.all;
entitymod10_counteris
port(
clk, reset:instd_logic;
q:outstd_logic_vector(3downto0)
);
endmod10_counter;
architecturepoor_async_archofmod10_counteris
signalr_reg: unsigned(3downto0);
signalr_next: unsigned(3downto0);
signalasync_clr: std_logic;
begin
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Poor Sequential Circuit Design Practice
-- registerprocess(clk, async_clr)
begin
if(async_clr = 1)then
r_reg 0);
elsif(clkeventandclk = 1)then
r_reg
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Poor Sequential Circuit Design Practice
Problem Transition from "1001" to "0000" goes through "1010" state (see timing diag.)
Any glitches in combo logic drivingaync_clrcan reset the counter
Can NOT apply timing analysis we did in last chapter to determine max. clk. freq.
Asynchronous reset should only be used for power-on initialization
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Poor Sequential Circuit Design Practice
Remedy: load "0000" synchronously -- looked at this in last chapterarchitecturetwo_seg_archofmod10_counteris
signalr_reg: unsigned(3downto0);
signalr_next: unsigned(3downto0);
begin
-- register
process(clk, reset)
begin
if(reset = 1)then r_reg 0);
elsif(clkeventandclk = 1)then
r_reg
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-- next-state logic r_next 0)whenr_reg = 9else
r_reg + 1;
-- output logic
q
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Poor Sequential Circuit Design Practice
The clock tree is a specially designed structure (b/c it needs to drive potentially thou-sands of FFs in the design) and should not be interfered with
Consider a counter with an enable signal
One may attempt to implement the enable by ANDing the clk with it
There are several problems
endoes not change with clk, potentially narrowing the actual clk pulse to the FF Ifenis not glitch-free, counter may count more often then it is supposed to
With the AND in the clock path, it interferes with construction and analysis of clock
distribution tree
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Poor Sequential Circuit Design Practice
A POOR approach to solving this problemlibraryieee;
useieee.std_logic_1164.all;
useieee.numeric_std.all;
entitybinary_counteris
port(
clk, reset:instd_logic;
en:instd_logic;
q:outstd_logic_vector(3downto0) );
endbinary_counter;
architecturegated_clk_archofbinary_counteris
signalr_reg: unsigned(3downto0);
signalr_next: unsigned(3downto0);
signalgated_clk: std_logic;
begin
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-- register
process(gated_clk, reset)
begin
if(reset = 1)then
r_reg 0);
elsif(gated_clkeventandgated_clk = 1)then
r_reg
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Poor Sequential Circuit Design Practice
A BETTER approacharchitecturetwo_seg_archofbinary_counteris
signalr_reg: unsigned(3downto0);
signalr_next: unsigned(3downto0);
begin
-- register
process(clk, reset)
begin
if(reset = 1)then r_reg 0);
elsif(clkeventandclk = 1)then
r_reg
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-- next-state logic
r_next
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The basic problem with the diagram on the left is that the system is no longersyn-
chronous
This complicates timing analysis, i.e., we can not use the simple method we looked at
earlier
We must treat this as a two clock system with different frequencies and phases
Consider a design that implements a "second and minutes counter"
Assume the input clk rate is 1 MHz clock
An example of a POORdesign that uses derived clocks is as follows
libraryieee;
useieee.std_logic_1164.cb;
Poor Correct
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useieee.numeric_std.all;
entitytimeris
port(
clk, reset:instd_logic;
sec,min:outstd_logic_vector(5downto0)
);
endtimer;
architecturemulti_clock_archoftimerissignalr_reg: unsigned(19downto0);
signalr_next: unsigned(19downto0);
signals_reg, m_reg: unsigned(5downto0);
signals_next, m_next: unsigned(5downto0);
signalsclk, mclk: std_logic;
begin
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-- register
process(clk, reset)
begin
if(reset = 1)then
r_reg 0);
elsif(clkeventandclk = 1)then
r_reg
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-- second divider
process(sclk, reset)
begin
if(reset = 1)then
s_reg 0);
elsif(sclkeventandsclk=1)then
s_reg
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-- minute divider
process(mclk, reset)
begin
if(reset = 1)then
m_reg 0);
elsif(mclkeventandmclk = 1)then
m_reg
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Proper Sequential Circuit Design Practice
A BETTER approach is to use asynchronous 1-clock pulse
architecturesingle_clock_archoftimeris
signalr_reg: unsigned(19downto0);
signalr_next: unsigned(19downto0);
signals_reg, m_reg: unsigned(5downto0);
signals_next, m_next: unsigned(5downto0);
signals_en, m_en: std_logic;
begin
-- registerprocess(clk, reset)
begin
if(reset = 1)then
r_reg 0);
s_reg 0);
m_reg 0);
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Proper Sequential Circuit Design Practice
elsif(clkeventandclk = 1)then
r_reg
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Proper Sequential Circuit Design Practice
-- next state logic/output logic for second divider
s_next 0)when
(s_reg = 59 and s_en = 1)else
s_reg + 1whens_en = 1else
s_reg;
m_en
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Proper Sequential Circuit Design Practice
Timing Diagram
Clk
500000
s_en
r_reg
59
m_en
1 m_reg
500000
59
0
58 s_reg00
r_reg499999
s_reg
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Power Concerns
Power is now a major design criteria
In CMOS technology
High clock rate implies high switching frequencies anddynamic poweris pro-
portionalto the switching frequency
Clock manipulation can reduce switching frequency but this should NOT be done at
RT level
The proper flow is
Design/synthesize/verify the regular synchronous subsystems
Use special circuit (PLL etc.) to obtain derived clocks
Use "power optimization" software tools to addgated clocksto some of the regis-ters
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Counters
A counter circulates its internal state through a set of patterns
Binary
Gray counter
Ring counter
Linear Feedback Shift Register (LFSR)
BCD counter
Binary counter
State follows binary counting sequence
Use an incrementer for the next-state logic
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Counters
Gray counter
State changes one-bit at a time
Use a Gray incrementer
libraryieee;
useieee.std_logic_1164.all;
useieee.numeric_std.all;
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Counters
entitygray_counter4is
port(
clk, reset:instd_logic;
q:outstd_logic_vector(3downto0)
);
endgray_counter4;
architecturearchofgray_counter4is
constantWIDTH: natural := 4;
signalg_reg: unsigned(WIDTH-1downto0);signalg_next, b, b1: unsigned(WIDTH-1downto0);
begin
-- register
process(clk, reset)
begin
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Counters
if(reset = 1)then
g_reg 0);
elsif(clkeventandclk = 1) cb
g_reg
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Counters
Ring counter
Circulates a single 1, e.g., in a 4-bit ring counter:
"1000", "0100", "0010", "0001"
There arenpatterns for n-bit register where the output appears as an n-phase signal
In the non self-correctingdesign, "0001" is inserted at initialization and thats it
H d D i ith VHDL S ti l Ci it D i II ECE 443
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Counters
libraryieee;
useieee.std_logic_1164.all;
entityring_counteris
port(
clk, reset:instd_logic;
q:outstd_logic_vector(3downto0)
);
endring_counter;
architecturereset_archofring_counteris
constantWIDTH: natural := 4;
signalr_reg: std_logic_vector(WIDTH-1downto0);
signalr_next: std_logic_vector(WIDTH-1downto0);
begin
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Counters
-- register
process(clk, reset)
begin
if(reset = 1)then
r_reg 1,others => 0);
elsif(clkeventandclk = 1)then
r_reg
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Counters
A self-correcting design ensures at a 1 is always circulating in the ring
This is accomplished by inspecting the 3 MSBs -- if "000", then the combo. logic
inserts a 1 into the low order bit
architectureself_correct_archofring_counteris
constantWIDTH: natural := 4;
signalr_reg, r_next:
std_logic_vector(WIDTH-1downto0);
signals_in: std_logic;
begin
-- register
process(clk, reset)
begin
if(reset = 1)then
-- no special input pattern is needed in this version
-- since the 1 is not circulated - its generated
r_reg 0);
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Counters
elsif(clkeventandclk = 1)then
r_reg
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Counters
Linear Feedback Shift Register (LFSR)
An LFSR is a shifter register that contains an XOR feedback network that deter-
mines the next serial input value
Only a subset of the register bits are used in the XORoperation
By carefully selecting the bits, an LFSR can be designed to circulate through all
2n-1 states for ann-bit register
Consider a 4-bit LFSR
Note that the state "0000" is excluded -- if it ever shows up, the LFSR becomes stuck
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Counters
The properties of an LFSR are derived from the theory offinite fields
The termlinearis used because the feedback expression is described using
AND and XOR operations, which define a linear system in algebra
In addition to the 2n-1 states properties, the following are also true
The feedback circuit to generate a maximal number of states exists for anyn
The output sequence is pseudorandom, i.e., it exhibits certain statistical properties
and appears random
The taps for the XOR gates aredefined using primitive polynomials
These examples show that very little
logic is needed in the feedback circuit -only between 1 and 3 XOR gates
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Counters
Applications of LFSRs
Pseudorandom: used in testing, data encryption/decryption
A counter with simple next-state logic
For example, a 128-bit LFSR using 3 XOR gates will circulate 2128-1 patterns --
which takes 1012years for a 100 GHz system
libraryieee;
useieee.std_logic_1164.all;
entitylfsr4isport(
clk, reset:instd_logic;
q:outstd_logic_vector(3downto0)
);
endlfsr4;
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g q g
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Counters
architectureno_zero_archoflfsr4is
signalr_reg, r_next: std_logic_vector(3downto0);
signalfb: std_logic;
constantSEED: std_logic_vector(3downto0):="0001";
begin
-- register
process(clk, reset)
begin
if(reset = 1)then
r_reg
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g q g
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Counters
-- next-state logic
fb
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Counters
Implemented by a binary counter with a special output circuit
libraryieee;
useieee.std_logic_1164.all;useieee.numeric_std.all;
entitypwmis
port(
clk, reset:instd_logic;
w:instd_logic_vector(3downto0);
pwm_pulse:outstd_logic
);
endpwm;
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Counters
architecturetwo_seg_archofpwmis
signalr_reg: unsigned(3downto0);
signalr_next: unsigned(3downto0);
signalbuf_reg: std_logic;
signalbuf_next: std_logic;
begin
-- register & output buffer
process(clk, reset)
begin
if(reset = 1)then
r_reg 0);
buf_reg
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Counters
-- next-state logic
r_next
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Register File
Register file
Registers arranged as a 1-D array
Each register is identified with an address
Normally has 1 write port (with write enable signal) and two or more read ports
For example, a 4-word register file with 1 write port and two read ports
Decoder used to route the write enable signal, MUXs used to create ports
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Register File
Write decoding circuit behaves as follows
Outputs "0000" ifwr_enis 0
Asserts one bit according tow_addrifwr_enis 1
A 2-D data type is needed here
libraryieee;useieee.std_logic_1164.all;
entityreg_fileis
port(
clk, reset:instd_logic;
wr_en:instd_logic;
w_addr:instd_logic_vector(1downto0);
w_data:instd_logic_vector(15downto0);
r_addr0, r_addr1:in std_logic_vector(1downto 0);
r_data0, r_data1:out
std_logic_vector(15downto0));
endreg_file;
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Register File
architectureno_loop_archofreg_fileis
constantW: natural := 2; -- # of bits in address
constantB: natural := 16; -- # of bits in data
typereg_file_typeis array(2**W-1downto0) of
std_logic_vector(B-1downto0);
signalarray_reg: reg_file_type;
signalarray_next: reg_file_type;
signalen: std_logic_vector(2**W-1downto0);
begin
-- register
process(clk, reset)
begin
if(reset = 1)then
array_reg(3) 0);
array_reg(2) 0);
array_reg(1) 0);
array_reg(0) 0);
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Register File
elsif(clkeventandclk = 1)then
array_reg(3)
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Register File
if(en(2) = 1)then
array_next(2)
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Register File
when"00" => en en en en
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Register File
withr_addr1select
r_data1
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FIFO Buffer
Circular queue implementation
Use two pointers and a "generic storage"
Write pointer: points to the empty slot beforethe head of the queue
Read pointer: points to the first element at the tail of the queue
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FIFO Buffer
FIFO controller
The read and write pointers are defined using 2 counters
Tricky part is distinguishing betweenfullandemptystatus because in both cases,
the pointers are equal
Design 1: Augmented binary counter
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FIFO Buffer
Augmented binary counter:
Increase the size of the counter by 1 bit
Use LSBs for as register address
Use MSB to distinguish full or empty
libraryieee;
useieee.std_logic_1164.all;
useieee.numeric_std.all;
Hardware Design with VHDL Sequential Circuit Design II ECE 443
FIFO B ff
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FIFO Buffer
entityfifo_sync_ctrl4is
port(
clk, reset:instd_logic;
wr, rd:instd_logic;
full, empty:outstd_logic;
w_addr, r_addr:outstd_logic_vector(1downto0) );
endfifo_sync_ctrl4;
-- merge this code with register file code to complete,
-- use component instantiation
architectureenlarged_bin_archoffifo_sync_ctrl4is
constantN: natural:=2;
signalw_ptr_reg, w_ptr_next: unsigned(Ndownto0);
signalr_ptr_reg, r_ptr_next: unsigned(Ndownto0);
signalfull_flag, empty_flag: std_logic;
begin
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FIFO B ff
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FIFO Buffer
-- register
process(clk, reset)
begin
if(reset = 1)then
w_ptr_reg 0);
r_ptr_reg 0);elsif(clkeventandclk = 1)then
w_ptr_reg
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FIFO Buffer
-- compare MSBs, when different and addresses are the
-- same, then FIFO is full
full_flag
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FIFO Buffer
-- FIFO is empty when MSBs are equal and address bits
-- are the same
empty_flag
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FIFO Buffer
architecturelookahead_bin_archoffifo_sync_ctrl4is
constantN: natural := 2;
signalw_ptr_reg, w_ptr_next: unsigned(N-1downto 0);
signalw_ptr_succ: unsigned(N-1downto0);
signal r_ptr_reg, r_ptr_next: unsigned(N-1downto 0);
signalr_ptr_succ: unsigned(N-1downto0);signalfull_reg, empty_reg: std_logic;
signalfull_next, empty_next: std_logic;
signalwr_op: std_logic_vector(1downto0);
begin
-- register
process(clk, reset)
begin
if(reset = 1)then
w_ptr_reg 0);
r_ptr_reg 0);
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FIFO Buffer
elsif(clkeventandclk = 1)then
w_ptr_reg
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FIFO Buffer
--nextvalues of the write and read pointers
w_ptr_succ
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FIFO Buffer
when"10" => -- write
if(full_reg /= 1)then-- not full
w_ptr_next
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-- write/read -- status not affected
when others=>
w_ptr_next
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p
Pipelines are used to increase system performance by overlapping operations
Systems performance can be measured using two metrics
Delay: required time to complete one task
Throughput: number of tasks completed per unit time
Pipelining increases throughputby overlapping operations
Basic idea is to divide the combinational logic into a set of stages, with buffers (regis-
ters or latches) inserted between each stage
Pipelined laundry
Sequential laundry
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Pipelines
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Non-pipelined: Delay: 60 min, Throughput 1/60 load per min
Pipelined: Delay: 60 min, Throughput of4loads is4/(40 +4*20) loads per min
where 40 is the time to load the first two stages
This yields 2/60, twice the throughput
In practice, stages are often notof equal length
Clock cycle time set by longest stage in a pipelined combinational circuit
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Pipelines
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Given a pipeline with stage delays ofT1,T2,T3andT4, clock cycle time is bounded
by the
Tmax= max(T1, T2, T3, T4)
AND the setup and clock-to-q delays of the pipeline registers
Tc= Tmax+ Tsetup+ Tcq
In non-pipelined version, delay to process one item is
Tcomb= T1+ T2+ T3+ T4
For the pipelined version, its actually longerTpipe= 4Tc= 4*Tmax+ 4*(Tsetup+ Tcq)
Thewinis actually w.r.t. the throughputmetric
TPcomb= 1/Tcomb
For pipelined version, it takes 3*Tctime to fill the pipeline and the time to processk
items is 3*Tc+kTcyielding TP =k/(3*Tc+kTc) which approaches 1/Tc
Hardware Design with VHDL Sequential Circuit Design II ECE 443
Pipelines
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Not all circuits are amenable to pipelines -- if the circuit meets the following criteria,
then it is a candidate for a pipelineData is always available for the pipelined circuits inputs
System throughputis an important performance characteristic
Combinational circuit can bedivided into stages with similar propagation delays
Propagation delay of a stage is much largerthan theTsetupandTcqof the regis-ter
Procedure to Add a Pipeline
Derive the block diagram of the original combinational circuit and arrange the cir-
cuit as a cascading chain
Identify the major components and estimate the relative propagation delays of these
components
Divide the chain into stages of similar propagation delays
Identify the signals that cross the boundary of the chain and insert registers
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Pipelines
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Consider a pipelined combinational multiplier
The two major components are theadderandbit-productgeneration circuit
Arrange this components in cascade as shown on the next slide, with the bit-productlabeled as BP
The bit-product circuit is simply an AND operation and therefore has a small delay
We combine it with the adder to define a stage
The horizontal lines in the combinational version on the next slide define the
stages
Hardware Design with VHDL Sequential Circuit Design II ECE 443
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Since no addition occursin the zeroth stage, we willmerge it with the first stage
Pipeline registers
Pipeline registers
Pipeline registers
Pipeline registers
Hardware Design with VHDL Sequential Circuit Design II ECE 443
Pipelines
Th t t f i li i t
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There are two types of pipeline registers
One type to accommodate the computation flow and to store the intermediate results(partial products pp1, ...pp4)
Second type to preserve the info needed in each stage, i.e.,a1,a2,a3,b1,b2, andb3
Since there are different multiplications occurring in each stage, the operands for any
given multiplication must move along with the partial products
NON-pipelined version
libraryieee;
useieee.std_logic_1164.all;
useieee.numeric_std.all;
entitymult5is
port(
clk, reset:instd_logic;
a, b:instd_logic_vector(4 downto 0);
y:outstd_logic_vector(9 downto 0));
end mult5;
Hardware Design with VHDL Sequential Circuit Design II ECE 443
Pipelines
hit t b h f lt5 i
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architecturecomb_archofmult5is
constantWIDTH: integer:=5;
signala0, a1, a2, a3:
std_logic_vector(WIDTH-1downto0);
signalb0, b1, b2, b3:
std_logic_vector(WIDTH-1downto0);signalbv0, bv1, bv2, bv3, bv4:
std_logic_vector(WIDTH-1downto0);
signalbp0, bp1, bp2, bp3, bp4:
unsigned(2*WIDTH-1downto0);
signalpp0, pp1, pp2, pp3, pp4:
unsigned(2*WIDTH-1downto0);
begin
-- stage 0 (signal names are for use later when we
-- show the pipelined version
bv0 b(0)); -- a * MSB of b
bp0
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pp0
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-- stage 3
bv3 b2(3));
bp3
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To implement the pipeline, we replace
pp2
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architecturefour_stage_pipe_archofmult5is
constantWIDTH: integer:=5;
signala1_reg, a2_reg, a3_reg:
std_logic_vector(WIDTH-1downto0);
signala0, a1_next, a2_next, a3_next:
std_logic_vector(WIDTH-1downto0);signalb1_reg, b2_reg, b3_reg:
std_logic_vector(WIDTH-1downto0);
signalb0, b1_next, b2_next, b3_next:
std_logic_vector(WIDTH-1downto0);
signalbv0, bv1, bv2, bv3, bv4:
std_logic_vector(WIDTH-1downto0);
signalbp0, bp1, bp2, bp3, bp4:
unsigned(2*WIDTH-1downto0);
signalpp1_reg, pp2_reg, pp3_reg, pp4_reg:
unsigned(2*WIDTH-1downto0);
signalpp0, pp1_next, pp2_next, pp3_next, pp4_next:
unsigned(2*WIDTH-1downto0);
Hardware Design with VHDL Sequential Circuit Design II ECE 443
Pipelines
begin
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begin
-- pipeline registers (buffers)
process(clk, reset)
begin
if(reset = 1)then
pp1_reg 0);
pp2_reg 0);
pp3_reg 0);
pp4_reg 0);
a1_reg 0);
a2_reg 0);
a3_reg 0);
b1_reg 0);
b2_reg 0); b3_reg 0);
Hardware Design with VHDL Sequential Circuit Design II ECE 443
Pipelines
elsif(clkeventandclk = 1)then
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( )
pp1_reg
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b0
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bv3 b2_reg(3)); bp3
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We can use a smaller(n+1)-bit adder to replace the2n-bit adder We can reduce the size of the partial-product register b/c the LSBs actually grow
fromn+1bits to2nbits
Therefore, the MSBs of the initial partial products are wasted (they are always
0)
For example, we can use a5-bit register for the initial partial product (pp0sig-
nal) and increase the size by 1 in each stage.
We can reduce the size of the registers that hold theb signal since only theith bit of
bis needed in theithstage
See text for VHDL code
You can also reduce the delay of then-bit combinational multiplier fromn-1adderstoceiling(log2n) using a tree-shaped network
This also works for the pipelined version by computing the bit-products in par-
allel and feeding them into tree-shaped network
Hardware Design with VHDL Sequential Circuit Design II ECE 443
Pipelines
Non-pipelined and pipelined version of tree adder network (see text for VHDL)
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