project report

A Survey on Flash Memory Testing and Fault Diagnosis

Priyanka Birari

830115679

pvbirari@rams.colostate.edu

• Introduction to Flash Memories• Flash memory fault models

- Disturbance faults

- Conventional memory faults• Flash memory test algorithms

- March-like test/diagnosis algorithms

- Diagonal test/diagnosis algorithm• Flash memory BIST• Flash memory BISD• Conclusion

INTRODUCTION

Flash memory testing is challenging,• Rapid scaling down of technology• Floating gate reliability issue.

APPROACHES TO TEST FLASH• Reasonable fault models• Efficient test algorithms• Built-in self-test (BIST)/Built-in self-diagnosis

(BISD)

Flash Memory Program and Erase

• Program(1 to 0): channel hot-electron (CHE) injection or Fowler-Nordheim (FN) electron tunneling

• Erase (0 to 1): FN electron tunneling• By the entire chip or large blocks (flash erasure)

PROGRAM – WRITE 0

ERASE – WRITE 1

FLASH DISTURBANCES• Program Disturbances

Word-Line Erase Disturbance

Word-line Program Disturbance

Bit-line Program Disturbance

Bit-line Erase Disturbance• Read disturbances• Over erase/program

disturbance

PROGRAM DISTURBANCES

READ DISTURBANCES

CONVENTIONAL MEMORY FAULT

• Address-Decoder Fault (AF)• Stuck-At Fault (SAF)• Transition Fault (TF)• Stuck-Open Fault (SOF)• Bridging Fault (BF)

ALGORITHM NOTATION

• r0 : read 0 from a memory location• r1 : read 1 from a memory location• w0 : write 0 to a memory location• w1 : write 1 to a memory location• ⇑ : increasing memory addressing• ⇓ : decreasing memory addressing• ⇕ : either increasing or decreasing

TEST ALGORITHMS

• March-C Algorithm

{ (w0); (r0,w1); (r1,w0); (r0); (r0,w1⇕ ⇑ ⇑ ⇕ ⇓); (r1,w0); (r0)}⇓ ⇕

- All faults not detected• March-Based Flash Test: March-FT

(f); (r1,w0,r0); (r0);(f); (r1,w0,r0); (r0)⇓ ⇕ ⇑ ⇕- Address decoder faults and coupling

faults not detected

MARCH ALGORITHMS

• Modified March-like Algorithm• Step1: f; {w1}; B{f,{rB'1}}⇑ ⇑• Step2:

f; {r0,w1}; {r1};f; {r0,w1}; {r1}⇑ ⇑ ⇓ ⇓- Source line interconnect faults (SLIF)

DIAGONAL ALGORTIHM• Diagonal Test

{(f); !D1(r1,w0,r0); D1(r1,w0,r0); !D1(r0);⇑ ⇑ ⇑(f); D1(r1,w0,r0); !D1(r1); D2(r1,w0,r0);⇓ ⇑ ⇓

⇑D1(r0)}

DIAGNOSITIC ALGORTIHM• Diagonal-FD

{(f); D1(w0; i,!D1(r1); j!D1(r1));⇑ ⇑ ⇑⇓D2(w0; i,D1(r1); j,D1(r1)); !D1(w0);⇑ ⇑ ⇑

⇑D1(w0; i,!D1(r0); j,!D1(r0));⇑ ⇑(f); D2(w0; i,D1(r0); j,D1(r0))}⇓ ⇑ ⇑

TYPES OF BIST

• Hardwired BIST- Custom Circuitry• Soft BIST- Exploits the processor• Programmable BIST- Mixture of hardwired BIST and soft BIST

BIST• Allows to perform self-testing• Reduce dependence on an external automated test equipment (ATE)

TPG State Diagram

BISD

BISD - includes a BIST module, extra circuitry to generate the fault signatures to support diagnostics.

BISD Architecture

• High Voltage (HI-V) Tests- TExecution(HI-V Erase) < TExecution(Erase)

• Internal Parallel Test- Test time is reduced by approximately 64%

CONCLUSION• Flash memory fault models and test algorithms

are proposed

− Both march-based and diagonal tests are effective

• Flash memory BIST/BISD is feasible- Use BIST to reduce the number of test pins- Use BISD to support diagnosis• Futurescope

− Diagnosis methodology for flash memories

− BISR

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THANK YOU!