presentation title goes here rick coulson intel sr. fellow

PRESENTATION TITLE GOES HERE Rick Coulson Intel Sr. Fellow

3D XPoint™ Technology Drives System Architecture

JANUARY 20, 2016, SAN JOSE, CA

The Journey to Low Latency Storage

The Latency Journey So Far New Media Enables the Next Step

A little about 3D XPoint™ Technology

System and SW Architecture Changes In Process Changes to Block Storage Stack to Minimize Latency Changes to Enable Persistent Memory

2

1957 IBM RAMAC 350 5 MBytes $57,000

$15200/Mbyte ~1.5 Random IOPs

Starting Point: The First HDD

*Other names and brands may be claimed as the property of others.

Why the Drive for Low Latency?

RAMAC 305 100 Hz best case “clock”

RAMAC 350 600ms

Core™ i7 ~3 Ghz clock

Source: Wikipedia *Other names and brands may be claimed as the property of others.

10K RPM ~6ms access

58 Years

~100x Access time reduction

~30,000,000x Clock speed increase

HDD

Processor

~10,000x Access time reduction

NAND SSD ~60us access

Continuing the Storage Device Latency Journey

5

Persistent Memory

3D XPoint™ memory (SCM)

Ultra fast SSD

Media Bottlenecks

Platform HW / SW bottlenecks

Drive for Lower Latency

Media Enabler: 3D XPoint™ Technology (Or any SCM)

Crosspoint Structure Selectors allow dense packing and

individual access to bits

Scalable Memory layers can be

stacked in a 3D manner

Breakthrough Material Advances

Compatible switch and memory cell materials

High Performance Cell and array architecture that can

switch states 1000x faster than NAND

What is 3D Xpoint™ Technology

Video here

3D XPoint™ Technology Instantiation

Intel® Optane™ SSD

DIMMs based on 3D XPoint™

Demonstration of 3D Xpoint™ SSD Prototype

0

20

40

60

80

100

120

NAND MLC NVMe SSD(4kB read)

3D Xpoint NVMe SSD(4kB read)

DIMM Memory(64B read)

The Need to Address System Architecture

Late

ncy

(use

cs)

Storage Enabler: NVMe Efficiency Exposes Low 3D XPoint™ Media Latencies

0

25

50

75

100

125

150

175

200

10,000 Latency (uS)

HDD +SAS/ SATA

SSD NAND +SAS/ SATA

SSD NAND

+NVMe™

Drive Latency

Controller Latency (ie. SAS HBA)

Software Latency

Source: Storage Technologies Group, Intel

SSD NAND technology offers ~500X reduction in media latency over HDD

NVMe™ eliminates 20 µs of controller latency

3D XPoint™ SSD delivers < 10 µs latency

SSD 3D

XPoint™ +NVMe™

PM 3D

Xpoint™

~7X

3D XPoint™ Persistent Memory

NVMe Delivers Superior Latency

0

10

20

30

40

50

60

70

80

90

100

0 100000 200000 300000 400000 500000 600000 700000 800000 900000

mic

rose

cond

s (u

s)

IOPS 2 WV LSI 4 WV LSI 6 WV LSI 2 WV AHCI

4 WV AHCI 1 FD 1 CPU 1 FD 2 CPU 1 FD 4 CPU

AHCI maxes out at ~150K IOPS

PCIe NVMe approaches theoretical max of 800K IOPS at 18us

Platform HW/SW Average Latency Excluding Media 4KB

Source: Storage Technologies Group, Intel

NVMe/PCIe Provides More Bandwidth

Bandwidth (GB/sec)

Source: Storage Technologies Group, Intel

0.55

3.2

6.4

SATA 4X PCIEG3/NVME 8X PCIEG3/NVME

PCIe/NVMe provides more than 10X the Bandwidth of SATA. Even More with Gen 4

Enabler: NVMe Over Fabrics

In most Datacenter usage models, a storage write does not “count” until replicated High replication overhead diminishes the performance differentiation of 3D XPoint™ technology NVMe over Fabrics is a developing standard for low overhead replication

Synchronous Completion for QD1?

Synchronous completion also costs less OS / CPU time

OS cost = Ta + Tb = 4.9 +

1.4 = 6.3 µs

Async (interrupt-driven)

Sync (polling)

OS cost = 4.4 µs

CPU

Storage Device

user kernel user

System call Return to user

2.9 µs

polling

4.4 µs

CPU

Storage Device

user kernel user kernel user (P2)

System call Return to user

4.1 µs

Tu = 2.7 µs Ta’ Ta’’ Tb=1.4

9.0 µs

Interrupt

Context Switch

Device command

Other Enablers

Storage Stack optimizations Reduced Paging Overhead HW RAID alternatives

16

0

5

10

15

20

25

30

NAND MLC NVMe SSD(4kB read)

3D Xpoint NVMe SSD(4kB read)

DIMM Memory(64B read)

Persistent Memory La

tenc

y (u

secs

)

Open NVM Programming Model

18

50+ Member Companies

SNIA Technical Working Group Initially defined 4 programming modes required by developers

Spec 1.0 developed, approved by SNIA voting members and published Interfaces for PM-aware file system accessing kernel PM

support

interfaces for application accessing a PM-aware file

system

Kernel support for block NVM extensions

Interfaces for legacy applications to access block

NVM extensions

NVM Library: pmem.io 64-bit Linux Initially

19

19

Intel DIMM

User Space

Kernel Space

Application

Load/Store Standard File API

pmem-Aware File System

MMU Mappings

Library

• Open Source • http://pmem.io

• libpmem • libpmemobj • libpmemblk • libpmemlog • libvmem • libvmmalloc

Transactional

New Instructions

20

Core

L1 L1 L2

L3

Core

L1 L1 L2

Core

L1 L1 L2

Core

L1 L1 L2

NVDIMM NVDIMM

NVDIMM NVDIMM

Memory Controller Memory Controller

MOV

CLFLUSH, CLFLUSHOPT, CLWB

PCOMMIT

Low Latency Ahead!

21

Persistent Memory

3D XPoint™ memory

Ultra fast SSD

NVMe SSD

<1 usec

<10 usec

Thank you

22