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NB1 NanoBoard Technical Reference Manual
Technical hardware reference manual for the NB1 NanoBoard FPGA implementation platform
TR0102 (v1.0) January 25, 2004
CAUTION
THIS EQUIPMENT INCLUDES EXPOSED ELECTRONIC COMPONENTS THAT ARE HIGHLY SENSITIVE TO DAMAGE FROM
STATIC ELECTRICITY. USERS ARE CAUTIONED TO ALWAYS FOLLOW STANDARD ANTISTATIC PROCEDURES WHEN
INSTALLING, HANDLING OR USING THIS EQUIPMENT.
THIS EQUIPMENT MUST ALWAYS BE POWERED DOWN WHEN MAKING ANY CONFIGURATION CHANGES, FOR EXAMPLE
WHEN REMOVING OR INSERTING ANY ACCESSORY DEVICES OR WHEN CONNECTING THESE DEVICES TO ANY OTHER
EQUIPMENT. FAILURE TO FOLLOW THESE INSTRUCTIONS MAY RESULT IN DAMAGE TO THE SUPPLIED EQUIPMENT OR
CONNECTED DEVICES. USER ASSUMES ALL RESPONSIBILITY FOR THE ELECTRICAL COMPATIBILITY OF ANY USER-PROVIDED DEVICES CONNECTED TO THIS EQUIPMENT.
THIS EQUIPMENT IS INTENDED FOR PROFESSIONAL USE IN A LABORATORY ENVIRONMENT ONLY AND CONTAINS
EXPOSED ELECTRONIC COMPONENTS AND CIRCUITS THAT ARE VULNERABLE TO MECHANICAL OR PHYSICAL
DAMAGE. USERS ARE CAUTIONED TO HANDLE THIS EQUIPMENT ACCORDINGLY.
DAMAGE TO THE SUPPLIED EQUIPMENT DUE TO MISHANDLING OR MISUSE, NOT LIMITED TO STATIC, MECHANICAL, PHYSICAL OR ELECTRICAL DAMAGE WILL VOID ANY WARRANTY OTHERWISE PROVIDED FOR THIS EQUIPMENT.
IN NO EVENT SHALL ALTIUM, ITS DIRECTORS, OFFICERS, EMPLOYEES OR AGENTS BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES (INCLUDING DAMAGES FOR LOSS OF PROFITS, LOSS OF
BUSINESS LOSS OF USE OR DATA, INTERRUPTION OF BUSINESS AND THE LIKE), EVEN IF ALTIUM HAS BEEN ADVISED
OF THE POSSIBILITY OF SUCH DAMAGES ARISING FORM ANY DEFECT OR ERROR IN THIS EQUIPMENT OR ITS
DOCUMENTATION.
WARNING THIS EQUIPMENT IS INTENDED FOR PROFESSIONAL USE IN A LABORATORY ENVIRONMENT ONLY. IT GENERATES AND
CAN RADIATE RADIO FREQUENCY ENERGY. IT HAS NOT BEEN TESTED FOR COMPLIANCE PURSUANT TO
REGULATIONS REGARDING RADIO FREQUENCY INTERFERENCE. OPERATION OF THIS EQUIPMENT MAY CAUSE
INTERFERENCE WITH COMMUNICATIONS OR OTHER EQUIPMENT. USERS ARE ADVISED TO BE AWARE OF THIS
POTENTIAL AND TO TAKE WHATEVER MEASURES NECESSARY TO PREVENT THIS INTERFERENCE.
Software, hardware, documentation and related materials:
Copyright © 2004 Altium Limited.
All rights reserved. You are permitted to print this manual provided that (1) the use of such is for personal use only and will not be copied or posted on any network computer or broadcast in any media, and (2) no modifications of the manual is made. Unauthorized duplication, in whole or part, of this document by any means, mechanical or electronic, including translation into another language, except for brief excerpts in published reviews, is prohibited without the express written permission of Altium Limited. Unauthorized duplication of this work may also be prohibited by local statute. Violators may be subject to both criminal and civil penalties, including fines and/or imprisonment. Altium, CAMtastic, CircuitStudio, Design Explorer, DXP, LiveDesign, NanoBoard, NanoTalk, Nexar, nVisage, P-CAD, Protel, Situs, TASKING, and Topological Autorouting and their respective logos are trademarks or registered trademarks of Altium Limited or its subsidiaries. All other registered or unregistered trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed.
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NanoBoard NB1 Technical Reference
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Table of Contents Introduction to the Altium NB1 NanoBoard 4
Overview of the Altium NB1 NanoBoard ................................................................................4 Key Features of the Altium NB1 NanoBoard..........................................................................6 Functional Overview of the Altium NB1 NanoBoard ..............................................................7
Setting up the NanoBoard 8 What’s in the box....................................................................................................................8 System requirements .............................................................................................................9
Altium design software .................................................................................................9 Important note on FPGA vendor tools .......................................................................10
Setting up the NanoBoard....................................................................................................11 Testing the PC to NanoBoard connection..................................................................13
Downloading a test project to the NanoBoard......................................................................16 A note on changing FPGA daughter boards ........................................................................19 Troubleshooting NanoBoard connection problems..............................................................19 Where to go to from here .....................................................................................................20
Operation of the Altium NB1 NanoBoard 21 NB1 NanoBoard board outline .............................................................................................22 NB1 NanoBoard Power Connectors ....................................................................................23 NanoBoard Resources.........................................................................................................23
5V Power Connectors (J6 and J7) .............................................................................23 NanoTalk Configuration Header.................................................................................24 NanoTalk Configuration LEDs....................................................................................25 Master and Slave I/O .................................................................................................26 System Clock .............................................................................................................27 FPGA Daughterboard Connectors (J8 and J9)..........................................................28 User Board Connectors..............................................................................................30 NEXUS JTAG Connector and Port ............................................................................31 Static RAM, 256 Kb x 8, Configurable........................................................................31 Serial SPI Flash RAM ................................................................................................32 Dual 18 way USER HEADER A and B.......................................................................33 RS232 Serial Port (J1) ...............................................................................................34 CAN Port (J2).............................................................................................................34 PS2 Keyboard Port (J4) .............................................................................................35 PS2 Mouse Port (J5)..................................................................................................35 VGA Port (J3).............................................................................................................35 Audio Codec (J10 In and J11 Out).............................................................................36 Four channel I2C 8-Bit ADC and 10-Bit DAC ............................................................36 LCD character display................................................................................................37
NanoBoard NB1 Technical Reference
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Keypad array, 4x4......................................................................................................38 Magnetic Audio Transducer .......................................................................................38 User Dip switch ..........................................................................................................39 User LED array ..........................................................................................................39 User Application TEST / RESET Button ....................................................................39
Advanced NanoTalk Configuration 40 Altium NanoTalk Features ...................................................................................................40 NanoTalk Operation.............................................................................................................40
Installing NanoTalk on the NB1 NanoBoard – ‘SYSTEM JTAG’ ...............................40 NanoBoard Default Clock Frequency – ‘CLOCK1…CLOCK3’ ..................................41 Standalone Configuration – ‘AUTO LOAD FPGA’ .....................................................41 Using the NanoBoard Status LEDs – ‘TEST0, TEST1’ .............................................42
Updating the NanoBoard firmware 44 Pre-update preparation ........................................................................................................44 Erasing the PROM...............................................................................................................45 Downloading the new firmware............................................................................................45 Testing the NanoBoard ........................................................................................................46
NanoBoard Test Procedures 48 NanoBoard Test Overview...................................................................................................48 Test Procedures...................................................................................................................48 On-Board Voltage Regulation Test ......................................................................................50 Programming the On-Board FPGA......................................................................................50 NanoBoard RAM Test..........................................................................................................51 Main Functional Test............................................................................................................53
Index 59
Appendix A – NanoBoard and Daughterboard Schematics 60
Revision History 60
NanoBoard NB1 Technical Reference
About This Manual This document describes the board level operations of the Altium NB1 NanoBoard. The NanoBoard is part of a development system that has been designed to allow Altium end users to design and prototype systems based on FPGA or CPLD (PLD) devices from multiple vendors.
The basic system components are the NanoBoard NB1 mother board, providing development infrastructure and application specific hardware, and a range of plug-in daughterboards that provide the target field programmable devices. Typically the target PLD devices will be FPGA or CPLD types. It provides a general purpose platform with a range of commonly used peripherals.
The NB1 is initially supplied with two daughterboards, the NBP1 Xilinx® Spartan™ XC2S300E-6PQ208C and the NBP2 Altera® Cyclone™ EP1C12Q240C7.
The manual includes schematic diagrams of all NanoBoard NB1 circuitry.
Notational Conventions This document uses the following conventions.
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FPGA or CPLD devices may be collectively referred to as PLD or FPGA
The NanoBoard may be referred to as the NB1.
Interactive instructions are shown in a bold typeface, for example: Continue View » Devices Program listings, program examples and filenames are shown in a mono-spaced typeface, for example: Firmware_NB1_6_V1_08.mcs
Reference to notations on printed circuit boards are referred to in single quotes, for example: ‘SYSTEM JTAG’
Information About Cautions This manual may contain cautions.
Caution statements look like this.
A caution statement describes a situation that could potentially damage your software, or hardware, or other equipment. The information in a caution is provided for your protection. Please read each caution carefully.
Related Documents Designing with nVisage software manual
Designing with Nexar software manual
Designing with Protel software manual
NanoBoard NB1 Technical Reference
Introduction to the Altium NB1 NanoBoard This chapter provides a description of the Altium NB1 NanoBoard along with the key features and a block diagram of the circuit board.
Overview of the Altium NB1 NanoBoard The emergence of low-cost FPGA and CPLD devices from multiple vendors has resulted in the need for a state of the art development system. The NB1 NanoBoard, in conjunction with Altium’s nVisage, Nexar or Protel PC-based development software allows hardware engineers and embedded systems developers to develop and evaluate complex programmable logic-based systems.
In addition to providing schematic and PCB tools, the DXP-based development system also allows complete FPGA designs to be created, designed and debugged. FPGA projects can be created with the schematic editor, using supplied schematic library components covering an extensive palette of IP functions, including a range of industry-standard microcontrollers.
All or parts of an application can be written in VHDL. A range of Tasking embedded-system C compilers, assemblers and debuggers are also included.
Every functional part of the NB1 NanoBoard was designed entirely with the DXP-based development system. The NanoBoard was designed to reveal the power of this development system.
The NB1 allows rapid testing of designs for a range of PLD products, consisting of a motherboard with a variety of commonly used peripherals and a range of plug-in FPGA or CPLD daughterboards.
The NanoBoard includes a unique communications protocol called NanoTalk, that provides connection between a host PC running the software and the NanoBoard. NanoTalk provides the ability to daisychain a number of NanoBoards, and communications access from the software to all resources on the NanoBoard, or daisychained sequence of NanoBoards.
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Two NB1 NanoBoards daisychained together
NanoBoard NB1 Technical Reference
Figure 1. PC connected to a NanoBoard.
Figure 2. PC with Daisychained NanoBoards and a User board.
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NanoBoard NB1 Technical Reference
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Key Features of the Altium NB1 NanoBoard The NB1 NanoBoard has the following features:
Altium NanoTalk parallel PC interface
NanoTalk daisychain, in and out
NanoBoard to NanoBoard user-defined communications, in and out
NanoTalk configuration header
NanoTalk configuration LEDs
Xilinx Spartan IIE 100K NanoTalk controller with JTAG accessible flash configuration PROM
Dual User Board JTAG Headers, 10 way
Dual 100 way FPGA daughterboard connectors
Programmable clock 6 to 200 MHz, programmable by Nexar or by a Daughterboard FPGA application
Fixed 20MHz reference clock
Dual 5V Power daisychain power connectors with power switch and LED indicator
RS232 Serial Port – DB9
CAN Port – DB9
VGA Port – DB15
PS2 Mini DIN Mouse Port
PS2 Mini DIN PC Keyboard Port
LCD character display, 16 x 2 chars, high contrast, LED backlight
Magnetic Audio transducer with PWM drive capability
8 way DIP switch
LED array, 8 LEDS
Serial SPI Flash ROM, up to 2 Mb
256 Kb x 8 FPGA configurable SRAM (128x16,128x8+128*8)
Dual 18 way (20 pin headers) expansion headers with power supply selection links
Four channel 8 Bit ADC, I2C
Four channel 10 Bit DAC, I2C
Screw Terminal Header for ADC and DAC
ADC/DAC/I2C 14 pin expansion header
Audio Codec, 8 bit mono with 2.5mm audio jacks
User application reset/test button
NanoBoard NB1 Technical Reference
Functional Overview of the Altium NB1 NanoBoard
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Figure 3. A block diagram of the NanoBoard configuration.
NanoBoard NB1 Technical Reference
Setting up the NanoBoard This section gives step-by-step instructions on connecting the NanoBoard to your PC, and testing the PC to NanoBoard connectivity. We suggest you read this section thoroughly before beginning the installation and setup process.
CAUTION: Utilize standard antistatic procedures when handling or using the NB1 and associated daughterboards and plug-ins. Always power the NB1 down when making changes to the configuration, for example when removing or inserting daughterboards, or adding or removing plug in devices to the NanoBoards expansion headers.
What’s in the box
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Figure 4 - NanoBoard package contents
A – NanoBoard reference manual B – NanoBoard and stand C – 4 x Mains power cords (US, EU, UK and Australia) D – NanoBoard power supply module E – Altera Cyclone EP1C12 plug in FPGA daughter board F – Xilinx Spartan IIE-XC2S300E plug in FPGA daughter board G – Power supply daisychain connector – for use with multiple NanoBoards
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H – NanoTalk loopback cable – used for testing NanoBoard J – NanoBoard daisychain cable – for connecting multiple NanoBoards K – User board connector – for connecting to JTAG link on user-designed boards L – 2 x User I/O connectors M – Parallel cable – for connecting the NanoBoard to your PC
If any components of the system are missing or appear damaged, please contact your nearest Altium representative.
System requirements Before installing the software, please ensure that your computer meets the minimum system requirements listed below. Recommended system To get the most from your Altium design software, we recommend a PC with the following specifications:
Windows XP (Professional or Home) or Windows 2000 Professional
2 GHz Pentium 4 processor or equivalent
1 GByte RAM
2 GByte hard disk space (Install + User Files)
Dual monitors with 1280x1024 screen resolution
32-bit color, 64 MB graphics card
Parallel port Minimum requirements The following computer specifications are the minimum needed to get adequate performance from your design software:
Windows XP (Professional or Home) or Windows 2000 Professional
1 GHz processor
512 MB RAM
2 GByte hard disk space (Install + User Files)
Main monitor 1280x1024 screen resolution
Strongly recommended: second monitor with minimum 1024x768 screen resolution
32-bit color, 32 MB graphics card
Parallel port
Altium design software To install your Altium design software you will need approximately 1GBytes of free disk space. To begin the install process simply insert the product CD into your computer’s CD ROM drive. The Installation Wizard will automatically start and guide you through the installation process. If the Installation Wizard does not start automatically, please run Setup.exe located in the \Setup directory of the program CD.
NanoBoard NB1 Technical Reference
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The first time you run the software you will be required to activate it. Use the Active License options in on the DXP License Management page that appears in the software to do this.
Once the installation of the software is complete, you should install the necessary FPGA vendor tools – if not already present – and then connect the NanoBoard to your PC before starting the design system.
Important note on FPGA vendor tools To place and route the FPGA design for the target FPGA device on the NanoBoard, FPGA vendor tools are used. The FPGA vendor tools ARE NOT supplied with the system and must be sourced independently.
Before you can download a design to the NanoBoard you must have the appropriate vendor tools installed on your computer.
The NanoBoard comes supplied with two FPGA devices housed on plug in daughter boards – an Altera Cyclone EP1C12and a Xilinx Spartan IIE-XC2S300E. Both of these devices are supported by the respective vendor’s freely-downloadable tools available on the web, as well as by the commercial versions of these tools.
In order to use both of the supplied FPGA daughter boards, you will need to install both the Altera and Xilinx tools.
More information on the vendor tools for the supplied FPGA devices can be found on the respective FPGA vendor’s web sites.
Altera Quartus II Web Addition from www.altera.com
Xilinx ISE WebPACK available from www.xilinx.com
Please note that Altium does not provide technical support for FPGA vendor tools. For information on installing these tools, please refer to the information provided by the FPGA vendors.
NanoBoard NB1 Technical Reference
Setting up the NanoBoard The NanoBoard is an integral part of Altium’s LiveDesign-enabled platform and allows FPGA designs to be implemented and tested without the need to manufacture a physical prototype. The NanoBoard is connected to your PC via the computer’s parallel port. The picture in shows an overview of the NanoBoard and the location of the main components addressed during installation.
Figure 5
Figure 5. The NanoBoard. 1 = NanoTalk Parallel connector. 2 = Power switch. 3 = Power supply sockets. 4 = FPGA daughter board connector.
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Please Note: Before using the NanoBoard, attach the backplate of the NanoBoard stand using the thumbscrews provided.
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NanoBoard NB1 Technical Reference
To set up the NanoBoard, refer to Figure 2 and complete the following steps:
1. Connect the supplied parallel cable to the parallel port of your PC. Connect the header plug of the parallel cable to the NanoTalk Parallel header socket [1] at the top right of the NanoBoard, ensuring that the red pin 1 marker on the cable is located on the side closest to the power switch, as shown below.
2. Select one of the FPGA daughter boards and gently orient it over the daughter board sockets [4] on the NanoBoard – the sockets are directional to ensure that the daughter board can only be inserted in the correct orientation. Once located, press the daughter board firmly onto the NanoBoard.
3. Connect the plug of the power supply module to either of the power connectors [3] on the top edge of the NanoBoard.
4. Connect the mains power cord to the power supply module and plug it in to a standard power socket.
5. Turn on the NanoBoard power switch [2]. The LED next to the power switch shows that power is available.
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NanoBoard NB1 Technical Reference
Testing the PC to NanoBoard connection Once you have connected the NanoBoard to your PC, you should check that the system software can connect to the NanoBoard. To do this, follow the steps below: 1. Start your Altium design system by selecting the DXP 2004 icon from the Windows Start menu.
2. The first time the system is run with a NanoBoard connected it will build a cache of supported programmable devices. A progress dialog will appear on screen during this process. Building the cache can take several minutes, depending on the speed of you computer. This only needs to be done once.
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NanoBoard NB1 Technical Reference
Once the system has started, you will be presented with the DXP 2004 Home page, which provides a jumping off point to many of the features offered by the system.
3. Click on the Device Management and Connections icon.
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NanoBoard NB1 Technical Reference
This will open the Devices view. Alternatively, you can select View » Devices from the menus.
4. Ensure that the Live checkbox is enabled and that the Connected indicator is green. This indicates that the system is connected and communicating with the NanoBoard.
5. If the Device does not show the NanoBoard status as connected or no FPGA icon is visible, refer to the section Troubleshooting NanoBoard connection problems later in this guide.
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NanoBoard NB1 Technical Reference
Downloading a test project to the NanoBoard To ensure that your design system and NanoBoard are functioning correctly installed, follow the steps below to compile and synthesize an example project and download it the NanoBoard. For this test we will use the FPGA_LedChaser_NanoBoard.PRJFPG example found in the Altium2004\Examples\FPGA Hardware\LED Chaser - Hardware directory.
1. From the menus select File » Open. 2. Navigate to the Altium2004\Examples\FPGA Hardware\LED Chaser - Hardware
directory. 3. In this directory, open the file FPGA_LedChaser_NanoBoard.PRJFPG. When the project has
loaded, the Projects panel on the left side of the workspace will display the files in this project.
4. If the Devices view is not active, select View » Devices from the menus to display it. The project open will automatically be assigned to the FPGA device on the active NanoBoard. The screenshot below shows this for the Spartan daughter board installed.
5. To process the project and download it to the NanoBoard, click the Program FPGA button in the Devices view.
The system will automatically compile the source project files, synthesize the design, call the vendor place and route tools to process the design for the target FPGA, and then download the
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NanoBoard NB1 Technical Reference
design to the NanoBoard. This can take several minutes depending on the speed of your computer and which FPGA daughter board is installed.
Please note: If the system fails during the Build processes, shown by a purple status indicator, this can be because the FPGA vendor tools are not correctly installed or have not been properly activated. Please refer to the information supplied with the FPGA vendor tools for information on installing and activating these tools.
Once the design has been downloaded all of the process indicators will be green and the Results Summary dialog will be shown. This indicates that the project has been successfully processed and downloaded to the NanoBoard. Close the Results Summary dialog.
Congratulations! You have just reconfigured your NanoBoard to operate as a light chaser! If you look at the NanoBoard you should see that the LED array to the right of the FPGA daughter board displays a moving pattern.
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NanoBoard NB1 Technical Reference
One additional thing to take note of is that the Devices view now shows icons representing some virtual instruments (IO modules) running on the NanoBoard.
In this project, the IO modules are used to control the operation of the LED chase sequence. The icons in the Devices view shows the system is communicating with these instruments running in the FPGA, allowing you to interact and control the instruments for development and debugging purposes. Explore the circuit schematics for more information on the operation of the IO modules. Double-click on an IO module icon in the Devices view to access the front panel for that device.
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NanoBoard NB1 Technical Reference
A note on changing FPGA daughter boards When changing FPGA daughter boards, please take care not to damage the dual connectors that attach the daughter board to the NanoBoard. The following procedure is recommended:
1. Ensure that the NanoBoard power is switched off.
2. Grip the two sides of the daughter between your thumb and fingers and gently pull the daughter board upwards. Gently rocking the daughter board from side to side can help loosen the connectors.
3. As the daughter board disengages, ensure that you keep the daughter board parallel to the NanoBoard and pull it straight up until both connectors are fully disengaged.
4. Install a new daughter board by gently locating it over the daughter board sockets on the
NanoBoard in the correct orientation. Once located, press the daughter board firmly onto the NanoBoard.
5. Switch the NanoBoard power on.
The system software interrogates the NanoBoard at regular intervals to determine the FPGA device installed. If you change daughter boards, the system should automatically detect the change and show the correct device in the Devices view. When the Devices view is active you can force the system to poll the NanoBoard by pressing the F5 key.
Troubleshooting NanoBoard connection problems If, after completing the NanoBoard setup and installation procedures, the Devices view shows that the system cannot connect to the NanoBoard or cannot detect the presence of an FPGA on the NanoBoard, go through the following steps to try to correct the problem:
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NanoBoard NB1 Technical Reference
1. Ensure that the NanoBoard is switched on and that the power LED next to the power switch is illuminated.
2. Ensure that the NanoBoard to PC cable is correctly plugged in to both the PC and the NanoBoard.
3. Check that you have correctly installed an FPGA daughter board on the NanoBoard. 4. With the Devices view active (View » Devices), ensure that the Live checkbox is checked.
5. With the Devices view active (View » Devices), select Tools » Synchronize NanoBoards from the menu.
6. With the Devices view active (View » Devices), select Tools » Synchronize Physical Devices from the menu.
If, after completing all the above steps, the system still cannot establish a connection with the NanoBoard and FPGA, then please contact your nearest Altium Sales & Support representative. Please note: The system requires the presence of a working, standard parallel port on your computer. The parallel port implementations on some computers do not strictly adhere to the standard, which may cause communications with the NanoBoard to fail. If possible, reinstall the system on a different computer to determine if this may be the problem.
Where to go to from here Once you have completed the steps outlined in this guide, your system is installed and ready for use. To help become familiar with your design system and its features, we suggest you read over the following learning guides that can be found in the online help system. This can be activated by selecting Help » Contents from the menus.
Getting Started with FPGA Design
Getting started with embedded software
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NanoBoard NB1 Technical Reference
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Operation of the Altium NB1 NanoBoard This chapter describes the NB1 NanoBoard, major components, and how they interact. It also provides information on the NanoBoards various interfaces in detail. NanoBoard schematics are provided in Appendix A, and should be referred to as the final reference.
The NB1 was designed using Altium’s Schematic and PCB editors, as a two layer printed circuit board. The internal routing capacity of the FPGA devices used in the NanoBoard and daughterboard has allowed PCB tracks to be optimally placed to minimize vias and is the main determinant in producing a two layer design for a relatively complex product. The component side of the PCB has been used for signal routing, while the reverse side contains mainly power and ground tracks. Power and ground distribution is facilitated using a star topology. All unused copper areas have been flood filled with ground.
Many of the NB1 signals, particularly those originating in FPGA devices, have series resistors to minimize ringing caused by reflection. The NB1 PCB provides a good example of techniques required for using low cost medium speed FPGA devices.
NanoBoard NB1 Technical Reference
NB1 NanoBoard board outline The NB1 NanoBoard is a 200.5 x 165mm (7.9” x 6.5”) two layer printed circuit board (PCB), powered by an external 5 Volt regulated supply. Fig 2.1 indicates the layout of the NB1 and its various features.
Figure 6. Physical layout of the NB1 NanoBoard.
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NanoBoard NB1 Technical Reference
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NB1 NanoBoard Power Connectors The NB1 NanoBoard is powered by a 5 volt regulated supply, available with the NB1. Typical current requirements for the NB1 without any current supplied to expansion devices is 100 to 500 mA. Two power connector jacks are provided (J6 and J7). These are connected in parallel so power can be supplied to a chain of NanoBoards using one of the jacks to power the daisychained NB1s. The NB1 has a power toggle switch with LED indicator. The switch only controls power to the NanoBoard, not to other NanoBoards in a daisychain configuration. If the total power consumption of a given NanoBoard configuration, i.e. daisychained and/or with connected expansion devices then a higher current capacity power supply may be required. Such a power source must provide a regulated 5 volt supply.
The NB1 has on board regulators that provide +3.3 volts, +1.8 volts for the Spartan IIE controller FPGA, and a second programmed source to provide an appropriate voltage for FPGA device(s) for the plug-in FPGA daughterboards. Each daughterboard module automatically programs the regulator to suit its own internal voltage requirements.
Both the 3.3 volt and 5 volt supply buses can be selected to power various expansion devices that can be connected to the NB1.
NanoBoard Resources The NB1 has a variety of resources individually wired to target daughterboard FPGA IO pins. These allow a wide variety of embedded examples to be executed on the NB1, in addition to providing a base for developing new applications. Nexar provides schematic library components that allow the NB1 resources to be easily incorporated in designs, these are available in the FPGA NanoBoard Port-Plugin integrated library. An image of each component is shown with the following descriptions.
The library components automatically establish connectivity between the resource and FPGA IO pins, allowing the same design to be built for different FPGA devices from different manufacturers. Nexar’s’ Configuration Manager enables a single project to be targeted at different FPGA devices. Library components can be placed into your FPGA design from the library: C:\Program Files\Altium2004\Library\Fpga\FPGA NanoBoard Port-Plugin.IntLib.
NanoTalk is instantiated in a Spartan IIE 100 FPGA, with a partner configuration flash PROM. Both these devices are JTAG accessible from Nexar.
5V Power Connectors (J6 and J7) The NB1 requires a regulated 5 volt supply as its primary power source. Two parallel-connected jacks are provided (J6 and J7). J6 is used to connect a power source, leaving J7 as an output that can be used to provide power to a daisychained NB1, i.e. the next NB1 in a daisychain.
NanoBoard NB1 Technical Reference
NanoTalk Configuration Header Header JP2 allows the insertion of links (jumpers) to configure the operational mode of the NB1 NanoTalk controller and to set the default clock rate.
When no links are inserted, the NB1 is in its default operational state, with a default clock frequency of 50 MHz. This (no links inserted) is the configuration that is appropriate when first using the NanoBoard.
Chapter 3 describes in detail how the configuration header is used for advanced debugging, however the ‘AUTO LOAD FPGA’ link can be inserted to cause the NanoBoard to automatically load the daughterboard FPGA with configuration data from NanoBoard SPI flash PROM on power up. A valid bit file for the target daughterboard must first be written to the SPI flash by Nexar before this function will operate successfully.
Details on programming the SPI flash PROM can be found in the application note Bootstrapping thDaughter Board FPGA.
e
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NanoBoard NB1 Technical Reference
NanoTalk Configuration LEDs The NanoTalk configuration LEDs (‘SL1..SL8’) indicate various circumstances, in conjunction with links that can be inserted in header JP2, the NanoTalk Configuration Header. Chapter 3 details the advanced usage of this resource; however with no links installed the LEDs are interpreted as follows SL1 – When the NanoBoard is powered up SL1 should illuminate, indicating that the Spartan IIE 100 NanoTalk controller has been successfully configured. SL2 – Illuminated when Hard JTAG signals are received from Nexar. This LED is driven by the Hard JTAG TCK signal. NanoTalk uses a JTAG protocol to communicate with all relevant JTAG hardware devices on the NanoBoard. So when SL2 illuminates Nexar is using the JTAG protocol to communicate with physical JTAG-equipped hardware devices. SL3 – Illuminated when Soft JTAG signals are received from Nexar. The LED is driven by the Soft JTAG TCK signal. NanoTalk uses the JTAG protocol to communicate with virtual (soft) devices instantiated in the daughterboard FPGA, providing resources to debug virtual hardware and embedded software. So when SL3 illuminates Nexar is using a JTAG protocol to communicate with your FPGA embedded design. SL4 – Illuminated when SPI signals are received from Nexar. Nexar uses the SPI protocol to communicate the SPI hardware devices on the NanoBoard. These include the SPI serial flash PROM and adjustable clock. SL5 – Indicates that a valid parallel cable is connected to the NanoBoard.
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NanoBoard NB1 Technical Reference
SL6, SL7 and SL8 – These LEDS provide a status value indicating success or failure in configuring a daughterboard FPGA from bit file data held in the NanoBoards SPI serial flash PROM resource. The daughterboard FPGA can be configured by Nexar, which occurs when a project is being developed or debugged, or automatically from NanoBoard serial flash PROM when the NanoBoard is powered up. The latter option allows the NanoBoard to run a stand-alone application, without being connected to Nexar via the parallel port. The ‘AUTO LOAD FPGA’ link can be inserted to cause the NanoBoard to automatically load the daughterboard FPGA from NanoBoard serial PROM on power up. Chapter 3 describes how these status LEDS are interpreted.
Master and Slave I/O The NanoBoard can be connected in a daisychain configuration, allowing multiple NanoBoard applications to be controller by Nexar. The Master and Slave I/O headers (HDR2 and HDR5 respectively) can be used to provide an application-defined communication resource between daughterboard applications on separate NanoBoards in a daisychain. Each header provides four daughterboard I/O signals. Since the signals Master and Slave I/O headers are connected to daughterboard FPGA I/O pins, they can also be used for any other application-defined purpose.
Caution: Signals on HDR2 (Master I/O) are also shared with the NanoBoard NB1 Audio Codec.
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System Clock The NB1 NanoBoard has an SPI-based system clock generator that provides a fixed 20MHz clock and a user-programmable clock providing frequencies from 6 to 200 MHz. Both clocks are available in the daughterboard FPGA, i.e. connected to target FPGA GCLK pins.
On power up the NanoTalk controller configures the adjustable clock to a frequency determined by links installed on the NanoTalk Configuration Header (JP2) ‘CLOCK0...CLOCK2’ locations. The default frequency, with no links installed, is 50 MHz.
The adjustable clock can be programmed from a PC with Nexar using the Instrument NanoBoard Controller. This allows frequency presets to common values, as well as any frequency possible with the ICS clock device.
The adjustable clock can also be programmed by the daughterboard FPGA application at run time, via the NanoTalk controller to daughterboard SPI interconnect.
The clock device is the ICS307-02. Datasheet available at www.icst.com.
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NanoBoard NB1 Technical Reference
FPGA Daughterboard Connectors (J8 and J9) J8 and J9 provide 200 pins that are used to mount an FPGA or CPLD daughterboard. The daughterboards allow the NB1 NanoBoard to be used with a variety of target PLDs, which can be FPGA or CPLD based, or a combination of devices. Daughterboards may be constructed with any configuration that matches the pin out requirements of J8 and J9.
The NB1 daughterboard connectors map all of the NanoBoards I/O resources directly to daughterboard FPGA or CPLD pins, as if the daughterboards FPGA or CPLD devices were mounted on the NanoBoard.
In addition to the user-available IO, the daughterboard connectors provide connections for functions required for the operation of NanoTalk, as follows: Hard JTAG signals – all daughterboard devices that are JTAG-equipped are connected to signals FPGA_TMS, FPGA_TCK, FPGA_TDI and FPGA_TDO. This allows the NanoBoard and Nexar to address the daughterboard hardware using the JTAG protocol. Soft JTAG signals – four FPGA I/O pins are reserved for JTAG signals that are utilized by the user FPGA application. Nexar uses JTAG IP to communicate directly with the FPGA fabric, allowing applications to be debugged live. These signals (NEXUS_TMS, NEXUS_TCK, NEXUS_TDI and NEXUS_TDO) are derived in the NanoBoards NanoTalk controller, implemented in a Spartan IIE 100K on the NanoBoard. FPGA configuration signals – The NanoBoard can be operated and configured using Nexar for development and debugging, however it is possible to create a standalone NanoBoard application. Under these circumstances the daughterboard FPGA is configured at power up by the NanoTalk controller, using data stored in the NanoBoards SPI serial flash memory resource (refer to the topic,
). Serial SPI Flash Daughterboard identification signals – FPGA devices from different manufacturers and families require differing auto configuration processes, so it is necessary for the NanoTalk controller to be able
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to identify the family. Four signals (FPGA_ID0 … FPGA_ID3) are hardwired on the daughterboard to provide the required identification to the NanoTalk controller. Daughterboard to NanoBoard SPI bus – SPI devices on the NB1 are accessible from both Nexar and the daughterboard. The NB1’s NanoTalk controller provides an SPI path from the daughterboard to each of the NB1 SPI devices, i.e. the SPI serial flash memory and the programmable clock. Daughterboard signals SPI_DIN, SPI_DOUT, SPI_CLK, SPI_SEL and SPI_MODE provide this connectivity. In operation the daughterboard application communicates with the NanoTalk controller to establish a path between the application and a specific NB1 SPI device then uses the SPI protocol associated with the selected device to communicate with it. Daughterboard auxiliary signals – future daughterboards are planned that require additional signals, for example to provide resources for configuring daughterboard devices that require special programming voltages. The four daughterboard auxiliary signals are FPGA_AUX0…FPGA_AUX3. J8 and J9 provide three power supplies to the daughterboard, as well as ground signals. The power supply voltages are 5V, 3.3 volts and a third programmable supply providing the internal voltage for the target FPGA. The voltage programming signals are defined by the daughterboard, i.e. the daughterboard determines the voltage supplied by a regulator on the NanoBoard (U11).
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NanoBoard NB1 Technical Reference
User Board Connectors The NB1 includes 2 User Board JTAG headers, User Board A (HDR6) and User Board B (HDR7). Use these headers to include a User-designed board in the hard and soft JTAG chains, for design download and debugging from within the software.
The presence of a User Board is determined by the signal level on pin 10 of the header, if this is low the NanoBoard controller will route both the Hard and Soft JTAG chains via the header. If the User board does not support the soft chain then route pin 5 (TDI_SOFT) to pin 6 (TDO_SOFT). BSDL data for devices not known to the system can be added in the folder C:\Program Files\Altium2004\Library\Bsdl\Generic. Refer to the text files in this folder for more details.
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NEXUS JTAG Connector and Port The Nexus, or soft devices chain is implemented in the FPGA design by the inclusion of the NEXUS_JTAG_CONNECTOR, which takes 4 pins on the target FPGA. The pin numbers will be displayed on the schematic next to the component symbol when it has been synthesized for the target device.
This is wired to the NEXUS_JTAG_PORT, the presence of which instructs the software to wire all components that include the parameter NEXUS_JTAG_DEVICE=True into a JTAG chain.
Static RAM, 256 Kb x 8, Configurable The NB1 provides two 128k x 8 static ram devices (RAM0-U15 and RAM1-U14), directly connected to I/O pins on the target FPGA of an installed daughterboard. The SRAM devices have a common Chip Select (CS) and address (RAM_ADDR0 - RAM_ADDR16) signals, but separate 8 bit data bus and RD/WR signals for each chip.
The memory resource can be application-configured as single 128k x 16 address space, a single 256k by 8 space, or two 128k x 8 spaces.
The NanoBoards LCD display is mapped into the same address space as RAM0. If the LCD is not used in an application the LCD_E (active high) signal must be held low. Similarly, if the SRAM is not used in application the memory CS (active low) signal must be held high, to eliminate bus contention. If both LCD and SRAM are used in the same application the LCD_E signal and the memory CS signal must be generated by the application’s memory mapping logic.
The 128k x 8 SRAM devices are IDT71V124SA15Y (access time = 15 nS).
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NanoBoard NB1 Technical Reference
Serial SPI Flash RAM The NanoBoard NB1 has a serial flash RAM resource, in two ST M25P40 low-cost 4-Mbit devices. The NanoBoard PCB provides footprints for both M25P40 and M25P80 devices (8-Mbit devices).
The SPI flash RAMs can be erased or programmed by Nexar, via the NanoBoard Controller instrument. The M25P40 and M25P80 devices support a serial data rate of 25MHz. Datasheets are available at www.st.com.
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Dual 18 way USER HEADER A and B A total of 36 daughterboard FPGA IO signals are terminated on NanoBoard 20 pin headers ‘USER HEADER A’ (HDR9) and ‘USER HEADER B’(HDR10), 18 signals per header. These headers also provide ground and either 3.3 volt or 5v power supplies, selectable using 4 pin supply select headers ‘JP5’ and ‘JP6’ respectively.
‘USER HEADER A’and ‘USER HEADER B’are provided to allow user defined hardware to be interfaced to the daughterboard FPGA. Since the USER HEADER I/O can be configured as either input or output, they are not provided as a NanoBoard component.
A range of devices with compatible 20 pin IDC header interfaces are available, e.g. www.burched.com.
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NanoBoard NB1 Technical Reference
RS232 Serial Port (J1) J1 (DB9F) provides a DTE RS232 port, with signals TXD, RXD, RTS and CTS. These signals are derived from the daughterboard FPGA. RS232 level translation is provided by a MAX232 device. www.maxim-ic.com.
CAN Port (J2) J2 (DB9M) provides a CAN protocol transceiver, interfaced to two daughterboard FPGA I/O pins. Header JP1 allows the user to insert a CAN load and configure the transceiver speed option.
The transceiver device is Microchip MCP2551, datasheet available at www.microchip.com.
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PS2 Keyboard Port (J4) J4 (MINIDIN) provides a standard PS2 port, nominally for use with a PC keyboard. The port is directly connected to daughterboard FPGA I/O pins.
PS2 Mouse Port (J5) J5 (MINIDIN) provides a standard PS2 port, nominally for use with a PC mouse. The port is directly connected to daughterboard FPGA I/O pins.
VGA Port (J3) J5 (DB15) provides a VGA-compatible RGB video monitor port. The port is configured with two bits per color, a total of six bits per pixel or 64 colors. The port is directly connected to six daughterboard FPGA I/O pins.
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NanoBoard NB1 Technical Reference
Audio Codec (J10 In and J11 Out) The NanoBoard provides an SPI-based 8bit audio codec, together with relevant analogue pre and post conditioning circuitry, terminated with stereo input and output jacks J10 and J11. It’s possible to connect high impedance stereo headphones to J11.
The gain of the audio input stage is adjustable with ‘VR2’ over a range from 0.1 to 10. The NanoBoard is shipped with the voltage gain set to 1.0. The built-in anti-aliasing and output filters are optimized for an audio sample rate of 22050 Hz.
Caution: Some NanoBoard NB1 Audio Codec SPI signals are shared with HDR2 (Master I/O).
The SPI audio codec is Maxim MAX1104. A datasheet is available from www.maxim-ic.com.
Four channel I2C 8-Bit ADC and 10-Bit DAC The NB1 is equipped with general purpose analogue to digital and digital to analogue converters, both interfaced using the I2C protocol. The analogue signals are available via a screw terminal strip TS1, providing four analogue inputs and four analogue outputs as well as a filtered 3.3V analogue supply and ground. The same analogue signals are also available via HDR8, which additionally provides I2C signals SDA and SCL and a 5 volt supply and power ground.
Digital to analogue conversion is provided by a Maxim MAX5841MEUB 8 bit DAC. The analogue to digital conversion is provided by a Maxim MAX1037EKA-T 8 bit ADC. The reference supply for the DAC is user-selectable via header JP4. The reference voltage can be the analogue 3.3 volt supply (link on JP4 pins 3 and 4), or a precision 2.0 volt reference provided by the
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ADC converter chip. The 2.0 volt reference is derived from the ADC AIN3 pin, which can be programmed either output the reference voltage or serve as the fourth ADC input.
The MAX1037 ADC converter provides four multiplexed analogue inputs, selectable by application software via the I2C connection.
Datasheets for the MAX5841MEUB and the MAX1037EKA-T are available from www.maxim-ic.com.
LCD character display The NB1 provides a 16 character by two line industry-standard LCD display, with a LED backlight (LCD1). The LCD is memory-mapped to the same address space as the 128k SRAM RAM0. Internal user-provided address mapping must be provided if the SRAM and LCD are used in the same application.
The LCD may be mapped into any four byte section of the RAM0 address space by gating the LCD_E (enable) signal. If the LCD is not used in an application the LCD_E (active high) signal must be held low. Similarly, if the SRAM is not used in application the memory CS (active low) signal must be held high, to eliminate bus contention. If both LCD and SRAM are used in the same application the LCD_E signal and the memory CS signal must be generated by the application’s memory mapping logic.
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NanoBoard NB1 Technical Reference
Keypad array, 4x4 User input can be entered using the keypad array, which consists of 16 miniature pushbuttons (SW1 ... SW16) arranged in a 4 x 4 matrix. The keypad is organized so that a row-column scanning process can read the status of each key.
The keypad has an escutcheon housing that features replaceable keypad overlays. The NB1 is provided with an overlay organized in a similar way to a mobile phone keypad, though key assignment is entirely defined by the user application.
Magnetic Audio Transducer The NB1 has a magnetic audio transducer (‘SPKR1’) driven by a daughterboard FPGA signal. The transducer may operate as a beeper when driven by audio frequency square-wave signals. Alternatively the transducer may be driven by a pulse-width-modulated signal to produce more complex sounds. The NB1 also has an audio codec for high quality 8 bit audio.
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User Dip switch The NB1 provides an 8 way dip switch S2, each switch connected to an individual daughterboard FPGA I/O signal. The dip switch is wired as an active low device, i.e. when the each switch is ON the signal produced is low.
User LED array The NB1 has eight red LEDs (‘LED0 ... LED7’), each driven by a separate daughterboard FPGA signal. The LED signals are active high, i.e. a high level on the LED signal illuminates the LED.
User Application TEST / RESET Button The NB1 has a button (SW17) labeled ‘TEST/RESET’ that is connected to daughterboard FPGA I/O signal. The button’s function is entirely determined by the user application, i.e. it has no intrinsic function unless defined by the user application.
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Advanced NanoTalk Configuration This chapter describes the features and operation of the NanoTalk interface in detail and provides a means of testing the NanoBoard for correct operation.
Altium NanoTalk Features The Altium NanoTalk protocol provides a communication path between a PC running Altium Nexar and one or more NanoBoards like the NB1. Altium NanoTalk is implemented in a Spartan IIE 100k FPGA device, U8. NanoTalk is field-upgradeable, by using Nexar to install configuration data in U5, a Xilinx XCF01SVO20C flash configuration device.
Altium Nexar uses NanoTalk to communicate with all appropriate resources (detailed in Chapter 2) on each NanoBoard in a daisychain.
In addition to providing communications with NanoBoard resources, NanoTalk also provides JTAG interfaces for communicating with user-supplied development boards. The NanoBoard NB1 implements two such ports, ‘USER BOARD A’ (HDR6) and ‘USER BOARD B’ (HDR7). These ports provide conventional hardware JTAG communications (Hard JTAG), and additionally Altium Nexus JTAG (Soft JTAG) communications if the user board(s) can support this feature. NanoTalk can be configured using the NanoTalk configuration header JP2. The NanoTalk controller is equipped with eight LEDs (‘SL1…SL8’) that can be used to indicate activity on various Hard JTAG and Soft JTAG data paths, depending upon links inserted in header JP2.
NanoTalk has been designed to be plug-and-play, in the sense that all NanoTalk communications paths automatically configure when daisychains or user board headers are connected. Altium Nexar scans the NanoTalk system and automatically maintains a map of all Hard JTAG and Soft JTAG devices.
NanoTalk Operation The NB1 uses the PC parallel port to connect the PC and the first NanoBoard in a daisychain. Future versions of the NanoBoard may utilize USB or other protocols to provide this link.
Additional NanoBoards are connected to the first using 10 way IDC ribbon cables from the ‘NanoTalk Slave’ (HDR4) on the first NanoBoard in a chain to ‘NanoTalk Master’ (HDR1) on the next NanoBoard in the daisychain. NanoTalk is run-time configurable with links installed on ‘JP2’. The default configuration is with no links installed.
Installing NanoTalk on the NB1 NanoBoard – ‘SYSTEM JTAG’ The NB1 NanoBoard is shipped with NanoTalk installed, but future revisions of NanoTalk can be installed at any time. To reconfigure NanoTalk JP2 link ‘SYSTEM JTAG’ must be installed. With this link installed Nexar has Hard JTAG access only to U8 and U5, all other resources are invisible to the software. In this mode it is possible to re-program U5 with configuration data loaded into U8 on power up. This is described in detail in the section Updating the NanoBoard firmware.
NanoBoard NB1 Technical Reference
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NanoBoard Default Clock Frequency – ‘CLOCK1…CLOCK3’ On power up the NanoTalk programs the NanoBoard system clock to a default frequency. With no links installed this is 50 MHz; however other default clocks are possible, as follows:
CLOCK0 CLOCK1 CLOCK2 Default NanoBoard Clock
INSERTED 10 MHz
INSERTED INSERTED 20 MHz
INSERTED 30 MHz
INSERTED INSERTED 40 MHz
50 MHz
INSERTED INSERTED INSERTED 60 MHz
INSERTED INSERTED 75 MHz
INSERTED 100 MHz
Standalone Configuration – ‘AUTO LOAD FPGA’ The NB1 NanoBoard can be configured by Altium Nexar during the development and debugging of an application. The NanoTalk controller can also automatically configure the daughterboard FPGA at power up, using configuration data stored in NanoBoard SPI flash memory (U6 and/or U7).
This occurs when valid configuration data for the target daughterboard FPGA is present in U6/U7 and JP2’s ‘AUTO LOAD FPGA’ link is installed.
Altium Nexar provides facilities to store a configuration bit file in U6/U7, when the target FPGA application has been developed and debugged. With no links installed in JP2’s ‘TEST0’ and ‘TEST1’ locations, LEDs ‘SL6’, ‘SL7’ and ‘SL8’ in combination indicate the status of the auto load process as follows:
SL8 SL7 SL6 Auto Load Status
OFF OFF OFF No errors
OFF OFF ON Configuration failed: SPI memory did not respond
OFF ON OFF Configuration failed: No FPGA detected
OFF ON ON Configuration failed: An unknown FPGA was detected
ON OFF OFF Configuration failed: FPGA did not respond to PROGRAM
ON OFF ON Configuration failed: FPGA did not acknowledge load
ON ON OFF Configuration failed: FPGA indicated a load error
ON ON ON Configuration successful
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Using the NanoBoard Status LEDs – ‘TEST0, TEST1’ When debugging applications it is useful to have a visual indication of communications occurring on the NanoBoard. LEDs SL1…SL8 are utilized to this using JP2’s ‘TEST0’ and ‘TEST1’ links.
With no links installed in ‘TEST0’ or ‘TEST1’ the behavior of SL1..SL8 is as described on the previous page. The following tables indicate the functions of SL1..SL8 with all possible combinations of ‘TEST0’ and ‘TEST1’ links.
No TEST Links Installed – General Status and Configuration Errors
LED Interpretation
SL1 Always on (Motherboard FPGA has been configured)
SL2 Hardware device chain activity (Driven by TCK)
SL3 Software device chain activity (Driven by TCK)
SL4 SPI Bus activity (Driven of CLK)
SL5 Parallel Port cable detect
SL6 Configuration status code
SL7 Configuration status code
SL8 Configuration status code
TEST0 installed – Alternate Status
LED Interpretation
SL1 Always off. (Allows LNK7 to double up as a simple logic probe)
SL2 Hardware device chain activity (Driven by TDO)
SL3 Software device chain activity (Driven by TDO)
SL4 SPI Bus activity (Driven by DOUT)
SL5 Parallel Port C_CTRL status.
SL6 User Board A or B cable detect.
SL7 NanoTalk Master or Slave cable detect.
SL8 NanoTalk MODE pin activity.
NanoBoard NB1 Technical Reference
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TEST1 installed – USER BOARD A and B Status
LED Interpretation
SL1 USER BOARD A Hard JTAG TDI Activity
SL2 USER BOARD A Hard JTAG TDO Activity
SL3 USER BOARD A Soft JTAG TDI Activity
SL4 USER BOARD A Soft JTAG TDO Activity
SL5 USER BOARD B Hard JTAG TDI Activity
SL6 USER BOARD B Hard JTAG TDO Activity
SL7 USER BOARD B Soft JTAG TDI Activity
SL8 USER BOARD B Soft JTAG TDO Activity
TEST0 and TEST1 installed This combination is reserved.
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Updating the NanoBoard firmware The NanoBoard firmware is the program that is loaded into the NanoBoard Controller when the board is powered-up. The NanoBoard uses a Xilinx Spartan IIE-100K device (XC2S100E) as the controller for the board. Referred to as the NanoBoard Controller, this device (U8 on the board) communicates with the host PC via NanoTalk, managing JTAG communications with the following:
•
•
•
•
•
•
•
FPGA Daughter Board
Master/Slave daisy-chain
User Board connectors (A and B)
Flash RAMs (U6 and U7)
The SPI Master clock.
The NanoBoard Controller also manages the following two areas of the board:
LEDs ‘SL1-SL8’
The following jumpers on JP2: ‘AUTO LOAD FPGA’ ‘CLOCK0’ ‘CLOCK1’ ‘CLOCK2’ ‘USER A – BYPASS SOFT’ ‘USER B – BYPASS SOFT’ ‘TEST 0’ ‘TEST 1’
The firmware that is loaded into the NanoBoard Controller is stored in a Xilinx Serial PROM device (XCF01S). This is U5 on the board.
On power-up, the firmware is automatically loaded into the NanoBoard Controller.
Pre-update preparation Before the new version of firmware can be downloaded to the Serial PROM, the NanoBoard must first be prepared as follows.
1. Turn off the NanoBoard.
2. Remove any FPGA Daughter Board that is currently plugged in. 3. Insert a jumper at JP2 ‘SYSTEM JTAG’ on the NanoBoard (to the bottom left of the parallel cable
connector). This is a fixed function jumper which, when inserted, switches control of the NanoBoard from the NanoBoard Controller (Spartan IIE-100K) to a simple hardware chain, which involves the NanoBoard Controller and the Xilinx Serial PROM. These will display in the Hard Devices chain in the Devices view, as shown in Figure 7.
4. Power-up the NanoBoard.
NanoBoard NB1 Technical Reference
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Erasing the PROM Within the Design Explorer application, open the Devices view, if not already open. Ensure that the Live check box is checked as this enables the auto-board-recognition system.
With the jumper inserted, the Xilinx Serial PROM device will appear in the Hard Devices chain, as shown in . Figure 7
Figure 7. Accessing the Serial PROM device.
The Xilinx Serial PROM is a Flash memory device. Before it can be programmed with the new firmware, it must first be cleared. To do this, right-click on its icon in the Hard Devices chain (Platform Flash) and choose Reset Hard Device from the pop-up menu.
The erasing process will proceed, with progress shown in the Design Explorer's Status bar. The process takes approximately 15 seconds to complete.
Downloading the new firmware The configuration for the Xilinx Serial PROM device is stored in a PROM file, using the Intel MCS-86 format. This is an ASCII hex file with extension .mcs.
To download the new configuration, right-click on the icon for the PROM in the Hard Devices chain of the Devices view and select Choose File and Download from the pop-up menu.
The Choose Programming File For Xilinx XCF00S XCF01SVO20C dialog appears. Use this dialog to navigate to the required programming file ( *.mcs) and click Open. By default, this file is located in the \Program Files\Altium2004\System folder.
A confirmation dialog will appear, asking whether you wish to verify the programming (of the PROM). At this stage, the new firmware has not been downloaded. Click Yes to proceed with the download and verification cycle.
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The download and verification will take approximately 30-40 seconds to complete. The progress is shown in the Design Explorer's Status bar. At the end of the cycle, an information dialog will appear with the result of the download.
If any errors occur during the download and verification cycle, a warning dialog will appear. If this happens, power-down the NanoBoard for a few seconds and then run the whole process again – including the erasure of the PROM device's memory.
Testing the NanoBoard Once the Xilinx Serial PROM device has been successfully programmed, the new firmware can be tested as follows.
1. Power-down the NanoBoard and plug-in an FPGA Daughter Board. 2. Remove the jumper from JP2 ‘SYSTEM JTAG’.
3. Power-up the NanoBoard. 4. Ensure that the Live check box (at the top left of the Devices view) is checked to enable the auto-
board-recognition system. 5. In the Devices view, press F5 (Refresh). This forces a scan of the hardware to detect which
devices are currently connected. The FPGA device on the Daughter Board should be automatically detected and appear in the Hard Devices chain.
6. Open an FPGA project that includes Nexus-enabled devices (e.g. Microprocessors, Counters, Logic Analyzers) and program the FPGA on the Daughter Board. This will test that the Soft Devices chain is functioning correctly.
NanoBoard NB1 Technical Reference
NanoBoard Controller chain
Soft Device chain
FPGA device on Daughter Board detected and displayed
in Hard Device chain
Figure 8. Target FPGA device detection and test of the Soft Devices chain.
7. With the chosen design running in the FPGA, double-click on the icon for the NanoBoard Controller (in the NanoBoard Controller chain of the Devices view). The Instrument Rack for the NanoBoard Controllers will appear. Use the Instrument Panel to change the system clock frequency. This will write the new clock frequency to the system clock, which, being an SPI device, will test that communication to SPI devices is working correctly.
As well as writing the new frequency to the clock, the value will also be stored in the NanoBoard Controller and will be read back to verify the change. The new frequency is persistent across design sessions with respect to the software, but not persistent across hardware sessions. Therefore, closing the application, relaunching and opening an FPGA project will result in the last clock frequency entered being used. However, cycling the power on the NanoBoard will result in the default clock frequency (50MHz) being used because the register used to store the chosen clock frequency in the NanoBoard Controller is cleared on power-down.
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NanoBoard Test Procedures This chapter describes test procedures for the NB1 NanoBoard, allowing the user to test the NB1 NanoBoard and verify correct operation.
NanoBoard Test Overview The NB1 NanoBoard and its associated FPGA daughterboards are reconfigurable devices, providing a platform that can be easily programmed to a large number of different applications. One such application utilizes the reconfigurable nature of the NB1 to provide acceptance self-testing, either in production or in the user environment. These test procedures are provided as an example in the Nexar examples folder.
Test Procedures Test procedures were developed to test the NB1 NanoBoard during its development phase to verify correct operation. The test procedures allow the NB1 to be tested without any additional hardware, with simple ribbon cables and with some additional electronic hardware. Thus there are several levels of test setups, depending on the additional test hardware available: On-Board Voltage Regulation Test This test should be performed before the DUT is connected to any external hardware. It checks for the integrity of the on-board voltage rails.
It requires:
•
•
Current limited power supply unit (PSU) with voltage and current meter
Digital Multi-Meter (DMM) On-Board FPGA Programming This can be performed with the DUT alone as it is shipped with no additional hardware. RAM Test This can be performed with the DUT alone as it is shipped with no additional hardware. The RAM test firmware also allows the NanoBoard running it to act as a tester for the CAN bus communications. Main Functional Test Some tests can be performed without additional hardware, while others require either loop-back cables, external hardware such as keyboard and monitor or custom test hardware such as the real time clock adapter PCB.
The following matrix shows what functional blocks can be tested with the different test setups.
NanoBoard NB1 Technical Reference
Test
Pag
e
Vol
tmet
er/A
mm
eter
Cab
le
Loop
back
plu
g
PS
2 K
eybo
ard
Mon
itor
2nd
Nan
oBoa
rd
3rd
Nan
oBoa
rd
RTC
PC
B
Power Supply and Rail Regulators 50 Power Toggle Switch 50 Power Indicator LED 50 PC Parallel Port Interface 50 Configuration Flash (U17) 50 User Flash (U5,U6) 56 JTAG Multiplexer (U4) 50 Clock Generator (U12) 56 SL LEDs 55 Mode Selector Header (JTAG Link) 56 Speaker 56 LCD Display 55 LCD Backlight 57 16 Key Keypad 56 TEST/REST Button 56 User LEDs (LED0..LED7]) 55 FPGA Daughterboard Connector 51 VGA port 57 A/D and D/A 57 Audio Codec (U21) 57 RS-232 Port 56,56
56 Slave I/O Port 56 PS2 Keyboard Port 56 PS2 Mouse Port 56 CAN-Bus Port 57 NanoTalk Master Port 53 NanoTalk Slave Port 53 Crystal Oscillator Frequency 57 Clock Generator 56 User Headers 56 External I2C Bus 57 Mode Selector Header (MODE_[1..8]) 56
Master I/O Port
TR0102 (v1.0) January 25, 2004 49
NanoBoard NB1 Technical Reference
50 TR0102 (v1.0) January 25, 2004
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On-Board Voltage Regulation Test This test must be performed before any other hardware is connected to the DUT. It is performed to make sure that no catastrophic faults in the power supply exist that could potentially damage external hardware. Parts Required:
Variable Laboratory Power Supply Unit (PSU) with integrated voltage and current meters and variable current limit. Cable with DC jack, wired centre positive to connect PSU to J6 on DUT
Digital Multi-Meter (DMM) Test Procedure:
Remove all cabling and any daughterboards from the DUT.
Set PSU output voltage to 5V±0.2V
Short out PSU output and set current limit to 1A Toggle On/Off switch S1 and verify the functionality of power LED (‘LED8’), otherwise disconnect PSU and reject DUT. Connect PSU output Jack to J6 on DUT, toggle On/Off switch S1 and verify the functionality of power LED ‘LED8’ and verify current is 100mA ±20mA in the ON position and <0.1mA in the OFF position, otherwise disconnect and reject DUT. Connect negative lead of multimeter to a GND pin on the DUT, for example ‘HDR14’ and verify the output voltage on the centre pin of U9 is 1.8±0.1V, otherwise disconnect PSU and reject DUT.
Verify the output voltage on the centre pin of U10 is 3.3±0.1V, otherwise disconnect PSU and reject DUT.
Verify the output voltage on the centre pin of U11 is 1.8±0.1V, otherwise disconnect PSU and reject DUT. Switch off ‘S1’ and install Altera Cyclone EP1C12Q240C7 daughterboard in socket. Verify the output voltage on the centre pin of U11 is 1.5±0.1V, otherwise disconnect PSU and reject DUT.
Programming the On-Board FPGA This will load the firmware into the NanoBoard’s on-board Xilinx Spartan XC2S100E FPGA. Refer to the section Updating the NanoBoard firmware in this manual for a more detailed description of this process. Parts Required:
PC running Nexar
NanoBoard Power Supply
NanoBoard PC NanoTalk Parallel Port Cable Test Procedure:
Connect NanoBoard power supply to J6, turn off S1
Connect NanoTalk Parallel Port Cable from PC parallel port to HDR3 on DUT
NanoBoard NB1 Technical Reference
•
TR0102 (v1.0) January 25, 2004 51
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Insert Jumper into JP2 ‘SYSTEM JTAG’ position
Start Nexar and load Workspace NB1 Testing.DsnWrk, if not already loaded. Select View » Devices and verify the Connected indicator status is green.
Right-Click on the Xilinx Platform Flash device and select Choose File and Download, then select the appropriate firmware MCS file. Confirm Yes when prompted for Verify Programming and verify correct programming of the device. Remove Jumper from JP2 ‘SYSTEM JTAG’ position.
Switch off S1, wait for ~1s, then switch ‘S1’ back on. Uncheck the Live checkbox ( )and recheck it again.
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Verify the green NanoBoard symbol is present in the JTAG chain.
NanoBoard RAM Test This test will verify the integrity of the 256k x 8 Static Ram. Since the code executes from the daughterboard FPGA’s internal RAM which is limited (8K for the Spartan device and 32K for the Cyclone), this test is a separate project. In addition to the RAM test, the firmware can also echo CAN bus signals for testing CAN bus communications with a second NanoBoard. Test Setup:
Open the project NanoBoardMemoryTester.PRJFPG
Switch off ‘S1’ to power down the DUT
Insert Xilinx SpartanXC2S300E daughterboard into daughterboard socket Switch on S1 and verify that the SpartanXC2S300E appears in the JTAG chain.
Select NanoboardMemoryTester / Memory Tester Spartan from the configuration options list,
then select Program FPGA ( ).
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Verify that the TSK51A_D processor appears in the JTAG chain. If the embedded software status indicator is not green (Up to Date) choose Compile first to compile the source. The indicator is now showing the green Up to Date message. Choose Download to download the firmware.
Test Procedure: Adjust ‘CONTRAST’ pot (VR1) until top row on LCD is just visible.
Right-click on the TSK51A_D processor icon and choose Continue
The 256kB of RAM are split into 4 banks of 64kB. The top four addresses in each bank are decoded to the LCD display which shares the data bus with RAM. The embedded software will perform a basic memory test on each bank and report the result. Each bank should result in an –OK message on the LCD display.
NanoBoard NB1 Technical Reference
•
52 TR0102 (v1.0) January 25, 2004
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The embedded software will then go into CAN bus echo mode which is used for the main test in conjunction with a second NanoBoard. Adjust ‘CONTRAST’ pot (VR1) for best contrast.
Connect two 10 way to 20 way User Board JTAG cables from ‘USER HEADER A’ ‘USER BOARD A’ and ‘USER HEADER B’ ‘USER BOARD B’. After a few seconds, two more NanoBoard Icons should appear in the JTAG chain:
• Remove both User Board JTAG cables.
NanoBoard NB1 Technical Reference
TR0102 (v1.0) January 25, 2004 53
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Main Functional Test This test tests as many on-board resources as practical. The sequencing of the tests is split into three parts:
1. Tests that can be performed without additional hardware.
2. Tests that can be performed with simple loop-back cables and standard components (e.g. PS2 Keyboards).
3. Tests that require special cables and hardware. Test Setup: The following section describes the test setup required for running all tests. A subset of tests can be performed if not all external cables and test-boards are available. The tests that require special hardware will fail if the hardware is not connected. Parts Required:
Two known good NanoBoards, in the state at the end of the RAM Test.
NanoBoard Power supply Plugpack (PSU)
Two 2.5mm DC♂ 2.5mm DC♂ cables
3.5mm stereo ♂ 3.5mm stereo ♂ shielded audio cable
Two 500mm 10-way NanoTalk IDC ribbon cables
300mm 10-way NanoTalk IDC ribbon cable
20-way IDC User Header Loop-back cable
DB9 ♂ RS-232 Loop-back Adapter (RXD TXD and RTS CTS)
DB9 ♀ ♀ CAN cable
Two PS2 Keyboards
VGA color monitor
Real Time Clock (RTC) Adapter PCB
Small screwdriver Test Preparation:
Open the project NanoBoardTester.PRJFPG
Turn off ‘S1’ on all three NanoBoards.
Connect NanoBoard PSU Plugpack to ‘J6’ on DUT
Connect DC cable from ‘J7’ on DUT to ‘J6’ on second NanoBoard. Label second NanoBoard.
Connect DC cable from ‘J7’ on second NanoBoard to ‘J6’ on third NanoBoard. Label third NanoBoard. Connect 500mm 10-way NanoTalk IDC ribbon cable from ‘NanoTalk Slave’ (HDR4) on DUT to ‘NanoTalk Master’ (HDR1) on the 2nd NanoBoard
Connect 500mm 10-way NanoTalk IDC ribbon cable from ‘NanoTalk Master’ (HDR1) on DUT to ‘NanoTalk Slave’ (HDR4) on the 3rd NanoBoard
NanoBoard NB1 Technical Reference
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54 TR0102 (v1.0) January 25, 2004
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Connect 300mm 10-way NanoTalk IDC ribbon cable from ‘Master I/O’ (HDR2) to ‘Slave I/O’ (HDR5) on DUT
Connect 20-way IDC User Header Loop-back cable from ‘USER HEADER A’ (HDR9) to ‘USER HEADER B’ (HDR10) on DUT
Set jumper ‘JP4’ to position ‘3V3’
Insert RTC Adapter PCB into ‘I2C/DAC/ADC’ header (HDR8) on DUT
Connect 3.5mm stereo ♂ 3.5mm stereo ♂ shielded audio cable from ‘AUDIO OUT’(J11) ‘AUDIO IN’(J10) on DUT
Plug DB9 ♂ RS-232 Loop-back Adapter into DUT’s RS232 connector
Plug VGA color monitor into DUT’s VGA connector Plug the two PS2 keyboards into the DUT’s two PS2 sockets (‘J4, J5’)
Connect DB9 ♀ ♀ CAN cable from CAN-Socket on DUT to CAN-Socket on the 3rd NanoBoard.
Switch all 8 DIP-switches on DUT to the “off” position Remove ‘NanoTalk Parallel’ cable from DUT and connect to ‘NanoTalk Parallel’ header on the 3rd NanoBoard. Power up all three NanoBoards by turning on S1 on each board
Test Procedure:
Uncheck the Live checkbox ( ) and recheck it again.
Verify that the Nexar Devices View shows three NanoBoards in the JTAG chain, the leftmost will represent the 3rd NanoBoard, the middle DUT and the rightmost the 2nd NanoBoard:
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3rd NB 2nd NB DUT
This verifies the correct operation of the NanoTalk Master and Slave connection. • Disconnect ‘NanoTalk Slave’ connector from DUT. Verify that the 2nd NanoBoard disappears
from the JTAG chain and the Nexar Devices view is now showing two NanoBoard Controller icons, the left representing the 3rd NanoBoard, the right representing DUT:
NanoBoard NB1 Technical Reference
3rd NB DUT
• Highlight the Spartan2E FPGA on the 3rd NanoBoard and in the configuration dropdown select NanoboardMemoryTester / Memory Tester Spartan, then select Program FPGA .
Highlight DUT Spartan2E FPGA and in the configuration dropdown select NanoBoardTester / NanoBoard Tester Spartan, then select Program FPGA .
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Verify that both TSK51A_D processors are present in the JTAG chain. Highlight the 3rd NanoBoard TSK51A_D processor. If the firmware status indicator is not green (Up to Date) choose Compile first to compile the source. The firmware indicator is now showing the green Up to Date message.
Choose Download to download the firmware. Right-click on the 3rd NanoBoard TSK51A_D processor icon and choose Continue. Wait for the memory test to conclude and the message Ready for CAN Bus Echo Test to appear on the 3rd NanoBoard’s LCD display. Highlight DUT TSK51A_D processor. If the firmware status indicator is not green (Up to Date) choose Compile first to compile the source. The firmware indicator is now showing the green Up to Date message.
Choose Download to download the firmware. We are now ready to conduct the main test.
Right-click on the 3rd NanoBoard TSK51A_D processor icon and choose Continue.
The main test sequence will run automatically. Any errors during the test will be indicated by an ERROR message on the LCD display and an acoustic error indication. Error messages must be acknowledged by pressing the ‘TEST/RESET’ button (SW17).
The main test sequence consists of the following tests: LCD and LED After a brief Status Message, the LCD displays the full character set. Verify that there are no gaps in the character sequences. At the same time each LED on the NanoBoard will be turned on sequentially. Verify that each LED lights up independently of its neighbors. ADC Init This initializes the ADC converter and looks for a correct ACK response on the I2C bus.
TR0102 (v1.0) January 25, 2004 55
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ADC Config Writes the ADC configuration registers and verifies correct ACK response on the I2C bus. On-Board FLASH Reads the device ID from both SPI flash chips Clock Generator Programs the variable clock generator to two different frequencies and verifies the two frequencies using the 20MHz crystal reference and an FPGA-internal hardware frequency counter. Keypad Test This test verifies functionality of each key.
When prompted, press all keys on the keypad in any sequence. The keys recognized as activated will be blocked out on the LCD display. As each key is pressed a unique acoustic indication is given. Finish by pressing the ‘TEST/RESET’ button when prompted. DIP-Switches This test verifies that each DIP switch is functional and independent of its neighbor.
Briefly move each DIP switch to the “on” position, then return to the “off” position. This can be achieved quickly by running a fingernail along the row of DIP switches. As DIP switch is activated an acoustic indication is given and the number of the DIP switch number is blocked out on the LCD display. At the same time the DIP switch status is mirrored on the row of LEDs below. Config Jumpers This test verifies that all configuration jumpers are functional and independent of their neighbors. Briefly short out each position on the configuration jumper row (JP2). This can be done quickly by running a small screwdriver tip along the header row. As each jumper is activated, an acoustic indication is given and the number of the jumper number is blocked out on the LCD display. At the same time the DIP switch status is mirrored on the row of LEDs to the right. PS2 Ports This sends a command to each of the two PS2 keyboards connected to the DUT’s PS2 connectors and checks for the correct response. RS-232 TXD->RXD Sends a serial character sequence out through the RS-232 TXD output and verifies the response on the RXD input. Requires a loop-back plug. RS-232 RTS->CTS Sends a serial character sequence out through the RS-232 RTS output and verifies the response on the CTS input. Requires a loop-back plug. User IO Verifies correct wiring on ‘USER HEADER A’ and ‘USER HEADER B’.
Outputs a running pattern of 1 on ‘USER HEADER A’ and reads response back on ‘USER HEADER B’. Requires a loop-back cable. Master-Slave I/O
NanoBoard NB1 Technical Reference
TR0102 (v1.0) January 25, 2004 57
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Verifies all signals on ‘Master I/O’ and’ Slave I/O’ headers. Outputs a running pattern of 1 on ‘Master I/O’ port and reads response back on ‘Slave I/O’ port. Requires Loop-back cable. Audio Codec Adj Allows gain adjustment of audio codec. Outputs square wave on DAC and digitizes input signal on ADC. Adjust ‘VR2’ as prompted on the LCD until the message Any Key=Continue indicates a correct gain of 1.0 in the signal path.
Press any key to proceed to the next test.
Requires an audio loop-back cable. CAN-BUS Outputs a character on the CAN bus. The 3rd NanoBoard will toggle some bits the character with a bit-mask and echo it back. On reception the character is masked with the same bit-mask and compared to the transmitted character. The 3rd NanoBoard will acknowledge each character it receives by flashing all LEDs for a short time. Requires CAN cable and second NanoBoard running Memory Tester Software. Crystal Osc Freq This test measures the frequency of the NanoBoard crystal oscillator. Since there is no second fixed oscillator on the NanoBoard it uses an external real time clock chip (RTC) to generate the reference timing for the frequency counter. This verifies the external I2C bus at the same time, since the RTC chip is programmed via the external I2C bus.
Requires an RTC adapter PCB. ADC/DAC Test This tests the A/D and D/A sections. NOTE: JP4 must be jumpered to ‘3V3’ for this test. The four A/D and D/A sections are looped on the RTC adapter PCB. The firmware outputs different voltage levels on each individual DAC and verifies the corresponding voltage on each ADC.
The two LEDs on the RTC adapter PCB indicate the presence of the +5V and +3.3V supply voltages on HDR8.
Requires an RTC adapter PCB. LCD Backlight At the end of the test sequence the LCD backlight will blink. VGA output Observe the test pattern on the VGA color monitor. It must show three levels of intensity for all three primary colors (red, green, blue), two levels of grey and black and white.
If all tests are successful, a SUCCESS message is displayed on the LCD and the speaker will sound an acoustic success signal.
The LCD Backlight will blink and the LEDs on the two PS2 keyboards will show a pattern of lights on the status LEDs.
If one or more tests have failed, the number of failed tests is displayed on the LCD screen and the speaker will sound an acoustic failure signal.
NanoBoard NB1 Technical Reference
58 TR0102 (v1.0) January 25, 2004
At this point individual tests can be performed by pressing the corresponding key on the Keypad (see following table)
Key Test
‘TEST/RESET’ Repeat whole test sequence
1 LCD/LED
2 On-Board FLASH
3 Clock Generator
C 16 Key Keypad
4 Dip Switches
5 Config. Jumpers
6 PS2 Ports
D RS-232 TXD->RXD
7 RS-232 RTS->CTS
8 User IO
9 Master-Slave I/O
E Audio Codec Adj.
A CAN-BUS
0 Crystal Osc Freq
B ADC/DAC Test
F LCD/LED
NanoBoard NB1 Technical Reference
TR0102 (v1.0) January 25, 2004 59
Index ADC...................... 6, 36, 37, 54, 55, 56, 57, 58
assembler .......................................................4
audio codec ...................................... 36, 38, 57
audio jacks......................................................6
button .....................................................38, 56
reset ............................................................6
CAN port...................................................6, 34
clock
programmable..................................... 27, 29
reference.....................................................6
system .......................................... 27, 41, 47
compiler ..........................................................4
configuration
header............................................. 6, 24, 40
LEDs: ....................................................6, 25
connector
daughterboard.......................................6, 28
conventions ....................................................3
DAC........................................ 6, 36, 54, 57, 58
daisychain ........................ 4, 6, 8, 9, 23, 26, 40
daughterboard3, 4, 6, 8, 21, 23, 24, 25, 26, 27, 28, 29, 31, 33, 34, 35, 38, 39, 41, 48, 50, 51
daughterboard connectors........................6, 28
debug .......................................................4, 25
DIP switch.................................................6, 56
expansion header .......................................6, 8
Flash RAM....................................................44
header .......... 12, 25, 26, 30, 33, 36, 40, 54, 56
configuration ................................... 6, 24, 40
I2C........................ 6, 36, 37, 49, 54, 55, 56, 57
Intellectual Property..................................4, 28
JTAG 3, 6, 9, 23, 25, 28, 30, 31, 40, 43, 44, 46, 49, 51, 52, 54, 55
keypad....................................................38, 56
LCD.................6, 31, 37, 49, 51, 55, 56, 57, 58
LED array............................................6, 17, 39
LEDs
configuration..........................................6, 25
indicator.................................................6, 23
motherboard ...................................................4
NanoTalk .2, 4, 6, 9, 11, 12, 23, 24, 25, 27, 28, 29, 40, 41, 42, 44, 49, 50, 53, 54
Nexus................................................31, 40, 46
overview................................................4, 7, 48
PCB ................4, 21, 22, 32, 48, 49, 53, 54, 57
port
CAN.......................................................6, 34
VGA.......................................................6, 35
power connector .................................6, 12, 23
programmable clock................................27, 29
PS2.......................6, 35, 49, 53, 54, 56, 57, 58
reference clock ...............................................6
requirements.......................................9, 23, 28
reset button.....................................................6
RS232.................................................6, 34, 54
screw terminal...............................................36
Serial SPI Flash RAM ...................................32
SPI6, 24, 25, 26, 27, 28, 29, 32, 36, 41, 42, 44, 47, 56
SRAM .................................................6, 31, 37
switch
DIP ........................................................6, 56
test procedures .............................................48
troubleshooting .......................................15, 19
user board.....................................................40
VGA port ...................................................6, 35
VHDL ..............................................................4
NanoBoard NB1 Technical Reference
60 TR0102 (v1.0) January 25, 2004
Revision History
Date Version No. Revision
25-Jan-04 1.0 New product release
Appendix A – NanoBoard and Daughterboard Schematics The following pages include the schematics for the:
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NB1 NanoBoard
NBP1 Xilinx® Spartan™ XC2S300E-6PQ208C
NBP2 Altera® Cyclone™ EP1C12Q240C7
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C C
B B
A A
1
Altium LimitedL3, 12a Rodborough RdFrenchs ForestNSWAustralia 208616
Board-On-Chip Block Diagram1.06
5/02/2004 4:43:47 PMC:\Program Files\Altium2004\Examples\Reference Designs\NanoBoard-NB1\BOC_Top.SchDoc
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:A
RAM_ADDR[0..16]
RAM1_DATA[0..7]
RAM0_WERAM0_OE
RAM1_WERAM1_OE
RAM_CS
RAM0_DATA[0..7]BOC_SRAM
BOC_SRAM.SchDoc
IO[0..35] BOC_IO
BOC_IO.SchDoc
SWC[0..3]SWR[0..3]
TESTBOC_KB
BOC_KB.SchDoc
VREF BOC_PWR
BOC_PWR.SCHDOC
BOC_RTS
BOC_TXBOC_CTS
BOC_RX
BOC_RS232
BOC_RS232.SchDoc
SCLSDA BOC_ADC_DAC
BOC_ADC_DAC.SchDoc
CAN_TXDCAN_RXD BOC_CAN
BOC_CAN.SchDoc
LED[0..7]SW[0..7]BOC_LED_DIPSWITCH
BOC_LED_DIPSWITCH.SchDoc
FPGA_CLK
REF_CLK
C_SPI_CLOCK_SELC_SPI_DINC_SPI_CLOCK_CLK
BOC_CLK_ADJBOC_CLK_ADJ.SchDoc
RAM0_DATA[0..7]
LCD_BCKL
RAM_ADDR[0..16]
BUZZER
LCD_EBOC_LCD
BOC_LCD.SchDoc
RED0RED1GREEN0GREEN1BLUE0BLUE1HDRIVEVDRIVEKBDATAKBCLOCKMOUSEDATAMOUSECLOCK
BOC_VGA_KB_MOUSE
BOC_VGA_KB_MOUSE.SchDoc
FPGA_TDIFPGA_TCKFPGA_TMS
FPGA_TDO
FPGA_DONEFPGA_PROGRAM
FPGA_CCLKFPGA_DIN
FPGA_AUX[0..3]FPGA_M[0..2]
JIOA[0..3]JIOB[0..3]
REF_CLK
FPGA_INIT
NEXUS_TDONEXUS_TDI
NEXUS_TCKNEXUS_TMS
FPGA_CLK_1FPGA_CLK_2
FPGA_INSTALLED
SPI_DINSPI_CLKSPI_SEL
SPI_DOUTSPI_MODE
C_SPI_CLOCK_CLKC_SPI_DIN
C_SPI_CLOCK_SEL
FPGA_ID[0..3]
TCK
TDOTDI
TMS
C_CTRLPARALLEL
MODE_[1..8]
N_TDIN_TDO
N_TCKN_TMS
MODE
FPGA_CLK
BOC_Spartan
BOC_Spartan.SchDoc
FPGA_DONEFPGA_PROGRAM
FPGA_CCLKFPGA_DIN
IO[0..35]
BOC_RTS
BOC_TXBOC_CTS
BOC_RX
CAN_TXDCAN_RXD
JIOA[0..3]JIOB[0..3]
LED[0..7]SW[0..7]
LCD_BCKL
FPGA_AUX[0..3]FPGA_M[0..2]
FPGA_TDIFPGA_TCKFPGA_TMS
FPGA_TDO
RAM_ADDR[0..16]
RAM0_DATA[0..7]
RAM1_DATA[0..7]
RAM0_OERAM0_WE
RAM1_OERAM1_WE
RAM_CS
RED0RED1
GREEN0GREEN1
BLUE0BLUE1
HDRIVEVDRIVE
KBDATAKBCLOCK
MOUSEDATAMOUSECLOCK
SWC[0..3]SWR[0..3]
FPGA_CLK
TEST
SCLSDA
NEXUS_TDINEXUS_TCKNEXUS_TMS
NEXUS_TDO
BUZZER
FPGA_INIT
VREF
SPI_MODESPI_DOUTSPI_SELSPI_CLKSPI_DIN
FPGA_CLK_1FPGA_CLK_2
FPGA_INSTALLED
REF_CLK
FPGA_ID[0..3]
LCD_E
AUDIO_SPI_CSn
BOC_DAUGHTER
BOC_DAUGHTER.SCHDOC
TCK
TDOTDI
TMS
C_CTRLPARALLEL
MODE_[1..8]
N_TDIN_TDO
N_TCKN_TMS
MODE
BOC_Boot
BOC_Boot.SchDoc
AUDIO_SPI_CSnJIOA[0..3]BOC_Audio
BOC_Audio.SchDoc
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3
3
4
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5
5
6
6
D D
C C
B B
A A
2
Altium LimitedL3, 12a Rodborough RdFrenchs ForestNSWAustralia 208616
Board-On-Chip Bootup Circuits1.06
5/02/2004 4:43:49 PMC:\Program Files\Altium2004\Examples\Reference Designs\NanoBoard-NB1\BOC_Boot.SchDoc
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:B
VCC_SENSE
R194K7
R17100R
VCC
123456789
10111213
14151617181920212223242526
Parallel Port
HDR3
70246-2622
STROBE
SELECTINPEBUSYACK
D0D1D2D3D4D5D6D7
AUTOFDERROR
INITSELECT
GNDGNDGNDGNDGNDGNDGNDGND
Printer Pin Names
NC
1
23
D6
BAS40
VCC
R1847R
R1647R
CTRL
MODE
PAR_TDO
PAR_TMSPAR_TCKPAR_TDI
BOOT_TDO
BOOT_TDI
BOOT_TMSBOOT_TCK
OE1
A12
A24
A36
A48 Y4 12Y3 14Y2 16Y1 18
U4A
SN74LVC244ADB
Y4 3Y3 5Y2 7Y1 9A111
A213
A315
A417
OE19U4B
SN74LVC244ADB
BOOT_EN
BOC_EN
VCC
C60100nF
C61100nF
C65100nF
C59100nF
C72100nF
C64100nF
C70100nF
C10
100nF
VCC
C11
100nF
VCC
N_TDI
N_TCK
N_TDO
N_TMS
R221K
C_CTRL
12345 6 7 8
RA94K7
1 2 3 45678
RA34K7
MODE_1MODE_2MODE_3MODE_4MODE_5
TDI
C73100nF
VCC
PARALLEL
R241K
R231K
1 2 3 45678
RA104K7
TDO
TMS
TCK
56
4U3B
SN74LVC00AD
1
23
U3A
SN74LVC00AD
89
10
U3C
SN74LVC00AD
1112
13
U3D
SN74LVC00AD
12345
678
RA6100R
12345
678
RA8100R
PU0PU1PU2PU3PU4PU5
PU6#PU7
BOOT_JTAG_EN
12345 6 7 8
RA54K7
12345 6 7 8
RA74K7
VCC
R284K7
D0 1
DNC 2
CLK3
TDI4
TMS5 TCK6
CF 7
OE/RESET8
DNC 9
CE10
GND11
DNC 12
CEO 13
DNC 14
DNC 15
DNC 16
TDO 17
VCCINT18
VCCO19
VCCJ20U5
XCF01SVO20C
1V8
VCC
1V8
TDI111 TDO 109
PROGRAM73
DONE 71
M237
M035
TMS2
M133 CCLK 107
TCK143
INIT 74DIN105
U8B
XC2S100E-6TQ144C
VCCINT19
VCCINT46
VCCINT51
VCCINT88
VCCINT120
VCCINT130
VCCINT61
VCCINT135
GND 54
GND 62
GND 91
GND 99
GND 136
GND 1
GND 9
GND 16
GND 25
GND 45GND 34
GND 81
GND 110
GND 119
GND 127
GND 70
VCCO17
VCCO144
VCCO36
VCCO53
VCCO90
VCCO72
VCCO108
VCCO128
U8C
XC2S100E-6TQ144C
VCC
VCC
12345678910
1112131415161718
Mode Select Header
JP2
Header 9X2
MODE_6MODE_7MODE_8
1 2 3 45678
RA44K7
R264K7
R254K7
R274K7
VCC
VCC
VCC
INIT
DONE
CCLK
DINPROGRAM
BOOT_TDO-TDI
BOOT_TMSBOOT_TCK
BOOT_TDO
CTRL
VCC
C62100nF
C63100nF
C67100nF
C58100nF
C71100nF
C66100nF
C68100nF
C69100nF
TCK
TDO
TDITMS
C_CTRL
PARALLEL
MODE_[1..8]MODE_[1..8]
MODE
N_TDIN_TCK
N_TDO
N_TMS
N_TDIN_TDO
N_TCKN_TMS
MODE
12
Configuration Mode Select
JP3
Header 2
VCC
SPARTAN_M0C14100nF
C13100nF
C12100nF
VCC
R401K
PARALLEL#N_TMS#
PAR_TDO#N_TDO#
C811nF
C821nF
C831nF
C841nF
C851nF
C861nF
C871nF
C881nF
C76100pF
MODE
PAR_TMSPAR_TCKPAR_TDI
N_TDI
N_TCKN_TMS
CTRL
1
1
2
2
3
3
4
4
D D
C C
B B
A A
3
Altium LimitedL3, 12a Rodborough RdFrenchs ForestNSWAustralia 208616
Board-On-Chip Audio Interface1.06
5/02/2004 4:43:49 PMC:\Program Files\Altium2004\Examples\Reference Designs\NanoBoard-NB1\BOC_Audio.SchDoc
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:A
R7110K
R7210K R62
1K
R671K8
R6110R
R6310K
R6510K
C51220pF
C50220pFLine In
Line Out
C45
1uF
OUT11
IN1-2
IN1+3
GND4 IN2+ 5IN2- 6OUT2 7VDD 8U18
OPA2340UA
VR2100K
5V
Tant
C3810uF
Tant
C3910uF
C37
100nF
1234 5
678
RA19
100R
JIOA[0..3]JIOA[0..3]
AUDIO_SPI_CSn
R464K7
VCC
JIOA0JIOA1JIOA2AUDIO_SPI_CSn
C42100nF
Tant
C46
10uF
C40
470pF
C414700pF
C52220pF
C53220pF
R684K7
R644K7
R6618K
R73560R
R74560R
VDD1
GND2
AIN3
OUT4 CS 5SCLK 6DOUT 7DIN 8U19
MAX1104EUAC43
1uF
R454K7
VCC
GAIN ADJUSTGain = 0.1 to 10
C444700pF
R60470R
C3622nF
35
4
21
J10
ST-3150-5N
35
4
21
J11
ST-3150-5N
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
4
Altium LimitedL3, 12a Rodborough RdFrenchs ForestNSWAustralia 208616
Board-On-Chip Programmable Logic1.06
5/02/2004 4:43:50 PMC:\Program Files\Altium2004\Examples\Reference Designs\NanoBoard-NB1\BOC_Spartan.SchDoc
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:C
FPGA_TDIFPGA_TCKFPGA_TMS
FPGA_TDO
FPGA_TMSFPGA_TCK
FPGA_TDOFPGA_TDI
FPGA_DONEFPGA_PROGRAM
FPGA_CCLKFPGA_DINFPGA_DIN
FPGA_M0FPGA_M1FPGA_M2
FPGA_PROGRAMFPGA_DONE
FPGA_CCLK
C_SPI_SEL_FLSH1C_SPI_DOUTC_SPI_CLKC_SPI_DIN
REF_CLKREF_CLK
REF_CLK
FPGA_INITFPGA_INIT
NEXUS_TDINEXUS_TCKNEXUS_TMS
NEXUS_TDO
NEXUS_TMSNEXUS_TCK
NEXUS_TDONEXUS_TDI
S1
Q2
W3
VSS4 D 5C 6HOLD 7VCC 8U7
M25P80-VMW6
VCC
S1
Q2
W3
VSS4 D 5C 6HOLD 7VCC 8U6
M25P80-VMW6
VCC
R441K
FPGA_TDO
FPGA_M1FPGA_M2
SPI_DOUTSPI_SEL
SPI_MODE
SPI_CLKSPI_DIN
SPI_DOUT
SPI_DINSPI_CLKSPI_SEL
SPI_CLKSPI_DIN
SPI_DOUTSPI_SEL
SPI_MODESPI_MODE
FPGA_INSTALLED FPGA_INSTALLED
FPGA_ID0FPGA_ID1FPGA_ID2
FPGA_INSTALLEDC_SPI_SEL_FLSH2C_SPI_DOUT
C_SPI_CLKC_SPI_DIN
C_SPI_SEL_FLSH2C_SPI_DOUT
C_SPI_CLKC_SPI_DIN
C_SPI_SEL_FLSH1
C_SPI_CLOCK_SELC_SPI_CLOCK_CLK
C_SPI_DIN
C_SPI_CLOCK_SEL
C_SPI_CLOCK_CLKC_SPI_CLOCK_CLK
C_SPI_CLOCK_SEL
C_SPI_DIN
FPGA_ID3
FPGA_ID[0..3]
FPGA_TDI
FPGA_TMS
TDO
TDITMS
TCK
NEXUS_TDINEXUS_TCKNEXUS_TMS
C19100nF
C20100nF
N_TDI
N_TCKN_TDO
N_TMS
MODEC_CTRL
12345
678
RA16
100R
1234 5
678RA13
100R
MODE_1MODE_2MODE_3MODE_4MODE_5
SPL1SPL2SPL3
R36100R
MASTER
MASTER_TDI
MASTER_TCK
MASTER_TDO
MASTER_TMS
SLAVE_TMSSLAVE_TCKSLAVE_TDI
SLAVE_MODE
MASTER_MODE
SLAVE
PARALLEL
SLAVE_TDO
FPGA_TCK
I/O141
I/O
3
I/O
4
I/O
, VR
EF
75
I/O
6
I/O
, VR
EF
7, L
27P
7
I/O
, L26
P_Y
Y10
I/O
, L26
N_Y
Y11
I/O
, VR
EF
7, L
25P
12
I/O
, L25
N13
GCK3, I129
GCK2, I126
I/O
20
I/O
, L24
P21
I/O
, VR
EF
6, L
24N
22
I/O
, L23
P_Y
Y23
I/O
, L22
P26
I/O
, VR
EF
6, L
22N
27
I/O
28
I/O
, VR
EF
629
I/O
30
I/O
, L21
P_Y
Y31
I/O
(DO
UT
, BU
SY),
L6P
_YY
106
I/O, L20N_YY 38I/O, L20P_YY 39I/O 40I/O, VREF 5 41I/O 42I/O, VREF 5, L19N_YY 43I/O, L19P_YY 44I/O, L18N_YY 47I/O, L18P_YY 48I/O, VREF 5 49I/O (DLL), L17N 50
I/O (DLL), L17P 56I/O 57I/O, VREF 4 58I/O, L16N_YY 59I/O, L16P_YY 60I/O, L15N_YY 63I/O, VREF 4, L15P_YY 64I/O 65I/O, VREF 4 66I/O 67I/O, L14N_YY 68
I/O
(D7)
, L13
P_Y
Y75
I/O
76I/
O, V
RE
F 3
77I/
O78
I/O
, VR
EF
3, L
12N
79I/
O (D
6), L
12P
80
I/O
, L11
P_Y
Y83
I/O
84I/
O, V
RE
F 3,
L10
N85
I/O
(D4)
, L10
P86
I/O
87
I/O
93I/
O (D
3), L
9N94
I/O
, VR
EF
2, L
9P95
I/O
96
I/O
(D1)
, L7N
100
I/O
, VR
EF
2, L
7P10
1I/
O10
2I/
O, V
RE
F 2
103
I/O
104
I/O
, L21
N_Y
Y32
I/O (CS), L5P_YY112
I/O (WRITE), L5N_YY113
I/O114
I/O, VREF 1115
I/O116
I/O, VREF 1, L4P_YY117
I/O, L4N_YY118
I/O, L3P_YY121
I/O, L3N_YY122
I/O, VREF 1123
I/O124
I/O
(TR
DY
)18
I/O
(IR
DY
)15
I/O (DLL), L2N131
I/O, VREF 0132
I/O, L1P_YY133
I/O, L1N_YY134
I/O, L0P_YY137
I/O, VREF 0, L0N_YY138
I/O139
I/O, VREF 0140
I/O142
I/O
, L27
N8
I/O
14
I/O
, L23
N_Y
Y24
GCK1, I 52
GCK0, I 55
I/O, L14P_YY 69
I/O
(D5)
, L11
N_Y
Y82
I/O
(TR
DY
)89
I/O
(IR
DY
)92
I/O
, L8N
_YY
97I/
O (D
2), L
8P_Y
Y98
I/O (DLL), L2P125
BAN
K 0
BAN
K 1
BANK 3BANK 2
BAN
K 4
BAN
K 5
BANK 7 BANK 6
U8AXC2S100E-6TQ144C
MODE_[1..8] MODE_[1..8]
MODE
N_TDIN_TCK
N_TDO
N_TMS
N_TDIN_TDO
N_TCKN_TMS
MODE
C_CTRL
PARALLEL
C_CTRL
PARALLEL
TDITDO
TMSTCKTCK
TDOTDI
TMS
MODE_1MODE_2MODE_3MODE_4MODE_5MODE_6MODE_7MODE_8
LED8HSMH-C170
LED9HSMH-C170
LED10HSMH-C170
R5270R
Power5V
LED11HSMH-C170
LED12HSMH-C170
1234 5
678RA14
270R
SPL1SPL2SPL3
Spare LED 1
Spare LED 2
Spare LED 3
1 23 45 67 89 10
User Board A
HDR6
70246-1022
LED13HSMH-C170
Spare LED 4
LED14HSMH-C170
Spare LED 5
LED15HSMH-C170
Spare LED 6
LED16HSMH-C170
Spare LED 7
Spare LED 8
1234 5
678RA15
270R
SPL5SPL6SPL7
SPL4
SPL8
12345
678
RA26
100R
12345
678
RA27
100R
12345
678
RA30
100R
12345
678
RA31
100R
R70100R
R69100R
12345 6 7 8
RA254K7
12345 6 7 8
RA284K7
12345 6 7 8
RA324K7
VCC VCC VCC
TCK_HARDTDO_HARD_A
TDO_HARD_B
TCK_SOFT_ATDO_SOFT_A
TDO_SOFT_B
TMS_HARD
TDI_HARD_A
JTAG_CNCT_A
JTAG_CNCT_B
TCK_HARD_A#
TCK_HARD_B#
TDO_HARD_A#
TDO_HARD_B#
TCK_SOFT_A#
TCK_SOFT_B#
TDO_SOFT_A#
TDO_SOFT_B#
JTAG_CNCT_A#
JTAG_CNCT_B#
TMS_HARD_A#
TMS_HARD_B#
TDI_HARD_A#
TDI_HARD_B#
TMS_SOFT_A#
TMS_SOFT_B#
TDI_SOFT_A#
TDI_SOFT_B#
JIOB0JIOB1JIOB2JIOB3
12345678910
Slave I/O
HDR5
Header 5X2
1 23 45 67 89 10
NanoTalk Slave
HDR4
Header 5X2
12345
678 RA17
100R
SLAVE_TDISLAVE_TCK
SLAVE_TDOSLAVE_TMSSLAVE_MODE
SLAVE
R201K
VCC
R61K
VCC
R214K7
VCC
JIOA0JIOA1JIOA2JIOA3
1 23 45 67 89 10
Master I/O
HDR2
Header 5X2
12345678910
NanoTalk Master
HDR1
Header 5X2
1234 5
678
RA20
100R
MASTER_TDIMASTER_TCK
MASTER_TDOMASTER_TMSMASTER_MODE
MASTER
R71K
R81K
VCC12345
678 RA1
4K7
MASTER_TMS
MASTER_MODE
VCC
MASTER_TCK
MASTER_TDI
JIOA[0..3]JIOA[0..3]
JIOB[0..3]JIOB[0..3]
MODE_6
MODE_7MODE_8
SPL4SPL5SPL6
SPL7SPL8
FPGA_PROGRAMFPGA_M0
NEXUS_TDO
FPGA_DIN
FPGA_INIT
FPGA_DONE
FPGA_CCLK
FPGA_CLKFPGA_CLK
FPGA_CLK
JIOB0#JIOB1#JIOB2#JIOB3#
SLAVE#
JIOA0#JIOA1#JIOA2#JIOA3#
MASTER#
SPL1#SPL2#SPL3#
SPL5#SPL6#SPL7#
SPL4#
SPL8#
MASTER_TDO#
SLAVE_TMS#SLAVE_TCK#SLAVE_TDI#
FPGA_TDO#
NEXUS_TDI#NEXUS_TCK#NEXUS_TMS#
TDI_SOFT_A
TMS_SOFT_A
JTAG_CNCT_A
JTAG_CNCT_B
FPGA_CLK_1FPGA_CLK_2 FPGA_CLK_1FPGA_CLK_1
FPGA_CLK_2FPGA_CLK_2
FPGA_ID0FPGA_ID1FPGA_ID2FPGA_ID3
FPGA_ID[0..3]
FPGA_AUX0FPGA_AUX1FPGA_AUX2FPGA_AUX3
FPGA_AUX0FPGA_AUX1FPGA_AUX2FPGA_AUX3
FPGA_M[0..2]FPGA_M[0..2]
FPGA_AUX[0..3]FPGA_AUX[0..3]
1 23 45 67 89 10
User Board B
HDR7
70246-1022
TDI_HARD_B
TDI_SOFT_B
TCK_SOFT_BTMS_SOFT_B
12345 6 7 8
RA294K7
VCC
TCK_HARDTDO_HARD_A
TDO_HARD_B
TCK_SOFT_ATDO_SOFT_A
TDO_SOFT_B
TMS_HARD
TDI_HARD_A
TDI_SOFT_A
TMS_SOFT_A
TDI_HARD_BTDI_SOFT_BTCK_SOFT_BTMS_SOFT_B
TP_U8-47TP_U8-48
C781nF
C771nF
C801nF
C791nF NOTE:
C77, C78, C79, and C80are NOT fitted.
1
1
2
2
3
3
4
4
D D
C C
B B
A A
5
Altium LimitedL3, 12a Rodborough RdFrenchs ForestNSWAustralia 208616
Board-On-Chip System Clock1.06
5/02/2004 4:43:50 PMC:\Program Files\Altium2004\Examples\Reference Designs\NanoBoard-NB1\BOC_CLK_ADJ.SchDoc
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:A
12
CR1
QC49/SMD
VCC
C29100nF
VCC VCC
C31Do Not Install
C28Do Not Install
VCC
R5133R
FPGA_CLKFPGA_CLK
REF_CLKR5233R
VCC
VCC
20MHz
40MHz
R5433R
R5333R
This PCB contains two possible clock devices, of which only one is actually installed.
Option A - Fixed 40MHz clock Install U13, C32, R53 and R54.
Option B - Adjustable Serial Mode ClockInstall U12, CR1, C29, C30, R50, R51 and R52.
C_SPI_DIN
C_SPI_CLOCK_SEL
C_SPI_CLOCK_CLKC_SPI_CLOCK_CLK
C_SPI_CLOCK_SEL
C_SPI_DIN
CLK26
NC7
SCLK8 STROBE 9
NC 15X2 16
VDD3
NC4
GND5
NC 10CLK1 11DATA 12PDTS 13NC 14
X1/CLK1
NC2
U12
ICS307M-02
GND2
E/D1
OUT 3
VDD 4U13
QSMO_4200
REF_CLK
VCC
C32100nF
Tant
C3010uF
R501K
1
1
2
2
3
3
4
4
D D
C C
B B
A A
6
Altium LimitedL3, 12a Rodborough RdFrenchs ForestNSWAustralia 208616
Board-On-Chip Keyboard1.06
5/02/2004 4:43:50 PMC:\Program Files\Altium2004\Examples\Reference Designs\NanoBoard-NB1\BOC_KB.SchDoc
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:A
12
34SW1
DTSM-61-NR
12
34SW2
DTSM-61-NR
12
34SW3
DTSM-61-NR
12
34SW4
DTSM-61-NR
12
34SW5
DTSM-61-NR
12
34SW6
DTSM-61-NR
12
34SW7
DTSM-61-NR
12
34SW8
DTSM-61-NR
12
34SW9
DTSM-61-NR
12
34
B3FS
SW10
DTSM-61-NR
12
34SW11
DTSM-61-NR
12
34SW12
DTSM-61-NR
12
34SW13
DTSM-61-NR
12
34SW14
DTSM-61-NR
12
34SW15
DTSM-61-NR
12
34SW16
DTSM-61-NR
SWC
0
SWC
1
SWC
2
SWC
3
SWC[0..3]
SWR[0..3]SWR[0..3]
SWC[0..3]
12
34SW17
DTSM-61-NR
VCC
R554K7
TESTTEST/RESET SWITCH
0 1 2 3
4 5 6 7
8 9 A B
C D E F
TEST
SWR0
SWR1
SWR2
SWR3
1 2 3 45678
RA184K7
SWC
0SW
C1
SWC
2SW
C3
VCC
1
1
2
2
3
3
4
4
D D
C C
B B
A A
7
Altium LimitedL3, 12a Rodborough RdFrenchs ForestNSWAustralia 208616
Board-On-Chip LEDs and DIP Switch1.06
5/02/2004 4:43:50 PMC:\Program Files\Altium2004\Examples\Reference Designs\NanoBoard-NB1\BOC_LED_DIPSWITCH.SchDoc
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:A
LED0
HSMH-C170
LED1
HSMH-C170
LED2
HSMH-C170
LED3
HSMH-C170
LED4
HSMH-C170
LED5
HSMH-C170
LED6
HSMH-C170
LED7
HSMH-C170
LED
0
LED
1
LED
2
LED
3
LED
4
LED
5
LED
6
LED
7
LED[0..7]
12345678
16151413121110
9
S2
A6ER-8104
SW0SW1SW2SW3SW4SW5SW6SW7
SW[0..7]
LED[0..7]
SW[0..7]
VCC1 2 3 4
5678
RA214K7
1 2 3 45678
RA224K7
1 2 3 45678
RA24270R
1 2 3 45678
RA23270R
LED
0#
LED
1#
LED
2#
LED
3#
LED
4#
LED
5#
LED
6#
LED
7#
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
8
Altium LimitedL3, 12a Rodborough RdFrenchs ForestNSWAustralia 208616
Board-On-Chip Daughter Connectors1.06
5/02/2004 4:43:51 PMC:\Program Files\Altium2004\Examples\Reference Designs\NanoBoard-NB1\BOC_DAUGHTER.SchDoc
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:B
FPGA_DONEFPGA_PROGRAM
FPGA_CCLKFPGA_DIN
IO[0..35]IO[0..35]
BOC_RTS
BOC_TXBOC_CTS
BOC_RX
BOC_RTS
BOC_TXBOC_CTS
BOC_RX
CAN_TXDCAN_RXDCAN_RXD
CAN_TXD
JIOA[0..3]
JIOB[0..3]
LED[0..7]
SW[0..7]
LED[0..7]
SW[0..7]
LCD_E
LCD_BCKL
LCD_E
LCD_BCKL
FPGA_DIN
FPGA_TDIFPGA_TCKFPGA_TMS
FPGA_TDO
IO0IO1IO2IO3IO4IO5IO6IO7IO8IO9IO10IO11IO12IO13IO14IO15IO16IO17IO18IO19IO20IO21IO22IO23IO24IO25IO26IO27IO28IO29IO30IO31IO32IO33IO34IO35
BUZZER
RAM_ADDR[0..16]RAM_ADDR[0..16]
RAM_ADDR0RAM_ADDR1RAM_ADDR2RAM_ADDR3RAM_ADDR4RAM_ADDR5RAM_ADDR6RAM_ADDR7RAM_ADDR8RAM_ADDR9RAM_ADDR10RAM_ADDR11RAM_ADDR12RAM_ADDR13RAM_ADDR14RAM_ADDR15RAM_ADDR16
RAM0_DATA[0..7]RAM0_DATA[0..7]
RAM0_DATA0RAM0_DATA1RAM0_DATA2RAM0_DATA3RAM0_DATA4RAM0_DATA5RAM0_DATA6RAM0_DATA7
RAM1_DATA[0..7]RAM1_DATA[0..7]
RAM1_DATA0RAM1_DATA1RAM1_DATA2RAM1_DATA3RAM1_DATA4RAM1_DATA5RAM1_DATA6RAM1_DATA7
RAM0_OE
RAM0_WERAM0_WE
RAM0_OE
RAM1_OE
RAM1_WE
RAM_CSRAM_CS
RAM1_WE
RAM1_OE
RED0RED1
GREEN0GREEN1BLUE0BLUE1
HDRIVEVDRIVEKBDATA
KBCLOCKMOUSEDATA
MOUSECLOCK
RED0RED1GREEN0GREEN1BLUE0BLUE1HDRIVEVDRIVEKBDATAKBCLOCKMOUSEDATAMOUSECLOCK
SWC[0..3] SWC[0..3]
SWC0SWC1SWC2SWC3
SWR[0..3] SWR[0..3]
SWR0SWR1SWR2SWR3
FPGA_CLK FPGA_CLK
TEST TEST
SCLSDA
SCLSDA
JIOA0JIOA1JIOA2JIOA3
JIOB0JIOB1JIOB2JIOB3
LED0LED1LED2LED3LED4LED5LED6LED7
SW0SW1SW2SW3SW4SW5SW6SW7
BUZZER
JIOA[0..3]
JIOB[0..3]
FPGA_INIT FPGA_INIT
NEXUS_TDINEXUS_TCKNEXUS_TMS
NEXUS_TDO NEXUS_TDINEXUS_TDO
NEXUS_TCKNEXUS_TMS
FPGA_TDO
FPGA_PROGRAMFPGA_DONE
FPGA_CCLK
FPGA_TDIFPGA_TCKFPGA_TMS
VCC
VREF VREF
SPI_DOUT
SPI_DINSPI_CLKSPI_SEL
SPI_CLKSPI_DIN
SPI_DOUTSPI_SEL
SPI_MODE SPI_MODE
FPGA_ID0FPGA_ID1FPGA_ID2
FPG
A_I
D0
FPG
A_I
D1
FPG
A_I
D2
FPG
A_I
NST
AL
LED
REF_CLK REF_CLK
BO
C_R
TS
BO
C_T
XB
OC
_CT
S
BO
C_R
XR
AM
_AD
DR
0
RA
M_A
DD
R1
RA
M_A
DD
R2
RA
M_A
DD
R3
RA
M_A
DD
R4
RA
M_A
DD
R5
RA
M_A
DD
R6
RA
M_A
DD
R7
RA
M_A
DD
R8
RA
M_A
DD
R9
RA
M_A
DD
R10
RA
M_A
DD
R11
RA
M_A
DD
R12
RA
M_A
DD
R13
RA
M_A
DD
R14
RA
M_A
DD
R15
RA
M_A
DD
R16
RA
M0_
DA
TA0
RA
M0_
DA
TA1
RA
M0_
DA
TA2
RA
M0_
DA
TA3
RA
M0_
DA
TA4
RA
M0_
DA
TA5
RA
M0_
DA
TA6
RA
M0_
DA
TA7
RA
M1_
DA
TA0
RA
M1_
DA
TA1
RA
M1_
DA
TA2
RA
M1_
DA
TA3
RA
M1_
DA
TA4
RA
M1_
DA
TA5
RA
M1_
DA
TA6
RA
M1_
DA
TA7
RA
M0_
WE
RA
M0_
OE
RA
M_C
S
RA
M1_
WE
RA
M1_
OE
JIO
A0
JIO
A1
JIO
A2
FPG
A_D
IN
FPG
A_I
NIT
FPG
A_P
RO
GR
AM
FPG
A_D
ON
E
FPG
A_C
CLK
FPG
A_M
0FP
GA
_M1
FPG
A_M
2FP
GA
_TD
O
FPG
A_T
DI
FPG
A_T
CK
FPG
A_T
MS
NEX
US_
TDI
NEX
US_
TDO
NEX
US_
TCK
NEX
US_
TMS
SPI_
CLK
SPI_
DIN
SPI_
DO
UT
SPI_
SEL
SPI_
MO
DE
CA
N_R
XD
CA
N_T
XD
RE
D0
RE
D1
GR
EEN
0G
REE
N1
BL
UE
0B
LU
E1
HD
RIV
EV
DR
IVE
KB
DA
TAK
BC
LOC
K
MO
USE
DA
TAM
OU
SEC
LOC
K
JIO
B0
JIO
B1
JIO
B2
JIO
B3
FPG
A_C
LKR
EF_
CL
K
JIO
A3
FPG
A_I
D3
SWC
0SW
C1
SWC
2
SWC
3
SWR
0
SWR
1SW
R2
SWR
3
LED
0L
ED1
LED
2L
ED3
LED
4L
ED5
LED
6L
ED7
SW0
SW1
SW2
SW3
SW4
SW5
SW6
SW7
LC
D_E
LC
D_B
CK
LB
UZZ
ER
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
IO8
IO9
IO10
IO11
IO12
IO13
IO14
IO15
IO16
IO17
IO18
IO19
IO20
IO21
IO22
IO23
IO24
IO25
IO26
IO27
IO28
IO29
IO30
IO31
IO32
IO33
IO34
IO35
SCL
SDA
FPGA_ID3
FPGA_ID[0..3]
TES
T
AUDIO_SPI_CSn AUDIO_SPI_CSn
VCCINT
FPG
A_C
LK_1
FPG
A_C
LK_2
FPGA_CLK_1 FPGA_CLK_1
FPGA_CLK_2 FPGA_CLK_2
FPGA_ID[0..3]
FPGA_INSTALLEDFPGA_INSTALLED
VCC
FPG
A_A
UX
0FP
GA
_AU
X1
FPG
A_A
UX
2FP
GA
_AU
X3
FPGA_M0FPGA_M1FPGA_M2
FPGA_AUX0FPGA_AUX1FPGA_AUX2FPGA_AUX3
FPGA_M[0..2]
FPGA_AUX[0..3] FPGA_AUX[0..3]
FPGA_M[0..2]
AU
DIO
_SPI
_CSn
5V
VCCINT
5V
23
45
67
89
10
1 1112
1314
1516
1718
1920
2122 24
2526
2728
2930
3132
23 3334
3536
3738
3940
4142
4344 46
4748
4950
5152
5354
45 5556
5758
5960 10
09997
9695
9493
9291
9089
988887
8685
8483
8281
8079
787775
7473
7271
7069
6867
766665
6463
6261
MH
1M
H2
MH
3M
H4
J853751-1009
23
45
67
89
10
1 1112
1314
1516
1718
1920
2122 24
2526
2728
2930
3132
23 3334
3536
3738
3940
4142
4344 46
4748
4950
5152
5354
45 5556
5758
5960 10
09997
9695
9493
9291
9089
988887
8685
8483
8281
8079
787775
7473
7271
7069
6867
766665
6463
6261
MH
1M
H2
MH
3M
H4
J953751-1009
1
1
2
2
3
3
4
4
D D
C C
B B
A A
9
Altium LimitedL3, 12a Rodborough RdFrenchs ForestNSWAustralia 208616
Board-On-Chip Static Ram 128k1.06
5/02/2004 4:43:51 PMC:\Program Files\Altium2004\Examples\Reference Designs\NanoBoard-NB1\BOC_SRAM.SchDoc
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:A
RAM_ADDR[0..16]
RAM1_DATA[0..7]
VCC
VCC
RAM_ADDR[0..16]
RAM1_DATA[0..7]
RAM0_WE
C75100nF
RAM0_DATA0RAM0_DATA1
RAM0_DATA2RAM0_DATA3
RAM0_DATA4
RAM0_DATA5
RAM0_DATA6
RAM0_DATA7
RAM_ADDR0RAM_ADDR1RAM_ADDR2RAM_ADDR3RAM_ADDR4RAM_ADDR5RAM_ADDR6RAM_ADDR7RAM_ADDR8RAM_ADDR9RAM_ADDR10RAM_ADDR11RAM_ADDR12RAM_ADDR13RAM_ADDR14
RAM1_DATA0RAM1_DATA1RAM1_DATA2RAM1_DATA3RAM1_DATA4RAM1_DATA5RAM1_DATA6RAM1_DATA7
RAM_ADDR0RAM_ADDR1RAM_ADDR2RAM_ADDR3RAM_ADDR4RAM_ADDR5RAM_ADDR6RAM_ADDR7RAM_ADDR8RAM_ADDR9RAM_ADDR10RAM_ADDR11RAM_ADDR12RAM_ADDR13RAM_ADDR14
VCC
C74100nF
RAM0_OE
RAM1_WERAM1_OE
RAM_CS
RAM0_DATA[0..7] RAM0_DATA[0..7]
VCC
RAM_ADDR15RAM_ADDR16
RAM_ADDR15RAM_ADDR16
A1430
A1221
A716
A615
A514
A413
A34
A23
A12
A01
IO06 IO17 IO210G
ND
9V
CC
24
WE 12
A1329
A817 A918
A1120
OE 28
A1019
CS 5
IO727
IO626
IO523
IO422
IO311
A1531 A1632
VC
C8
GN
D25
U15
IDT71V124SA15Y
A1430
A1221
A716
A615
A514
A413
A34
A23
A12
A01
IO06 IO17 IO210
GN
D9
VC
C24
WE 12
A1329
A817 A918
A1120
OE 28
A1019
CS 5
IO727
IO626
IO523
IO422
IO311
A1531 A1632
VC
C8
GN
D25
U14
IDT71V124SA15Y
VCC
R594K7
1
1
2
2
3
3
4
4
D D
C C
B B
A A
10
Altium LimitedL3, 12a Rodborough RdFrenchs ForestNSWAustralia 208616
Board-On-Chip LCD Display1.06
5/02/2004 4:43:47 PMC:\Program Files\Altium2004\Examples\Reference Designs\NanoBoard-NB1\BOC_LCD.SchDoc
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:A
RAM0_DATA[0..7] RAM0_DATA[0..7]
5V
C17100nF
GND1
VDD2
Vo3
RS4
R/W5
E6
DB07
DB18
DB29
DB310
DB411
DB512
DB613
DB714
LED+15
LED-16
LCD1
162A
RAM_ADDR[0..16]
LCD_ELCD_BCKL
RAM0_DATA0RAM0_DATA1RAM0_DATA2RAM0_DATA3RAM0_DATA4RAM0_DATA5RAM0_DATA6RAM0_DATA7
LCD_ERAM_ADDR1RAM_ADDR0
LCD_BCKL
OE 19
DIR 1
A1 3B117
A2 4B216
A3 5B315
A4 6B414
A5 7B513
A6 8B612
A7 9B711
A0 2B018
VCC20
GND 10
U17
SN74LVC245ADB
VCC
C34
100nF
VCC
LCD Address Decoding
Address Function Status========================================
???0H Write Command to LCD Write Only ???1H Write Data to LCD Write Only
???2H Read Status from LCD Read Only ???3H Read Data from LCD Read Only
Address ??? is determined by internal FPGA decoding of the LCD_E signal.
R3410K
R3268R
R3368R
RAM_ADDR[0..1]
BUZZER
R3910K
5V
R384K7
12
http://www.megastar.com/linecard/buzzmode/ABSM-1574-05-2.HTM
SPKR1ABSM-1574-05 Transducer
R294K7
LCD_En
R37
560R
R35560R
R300R
R310R
5V
VCC
VCC_LCD LCD Supply Voltage
Install R30 for 5 Volt LCD or
Install R31 for 3.3 Volt LCD
VCC_LCD
Tant
C9
10uF
INSTALL R30
VR120K
23
1Q12N7002
23
1
Q4
2N7002 23
1
Q3
2N7002
23
1 Q2
BSS84
e.g. Farnell 3876895
L1
330uH
C1822nF
LCD_D0LCD_D1LCD_D2LCD_D3LCD_D4LCD_D5LCD_D6LCD_D7
1234 5
678
RA12 4K7
1234 5
678
RA11 4K7
NC1
A2
GND3 Y 4
VCC 5U16
SN74LVC1G04DBV
VCC
C33
100nF
VCC
1
1
2
2
3
3
4
4
D D
C C
B B
A A
11
Altium LimitedL3, 12a Rodborough RdFrenchs ForestNSWAustralia 208616
Board-On-Chip User Header Ports1.06
5/02/2004 4:43:47 PMC:\Program Files\Altium2004\Examples\Reference Designs\NanoBoard-NB1\BOC_IO.SchDoc
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:A
1 23 45 67 89 1011 1213 1415 1617 1819 20
HDR9
Header 10X2
1 23 45 67 89 1011 1213 1415 1617 1819 20
HDR10
Header 10X2
IO[0..35] IO[0..35]
IO0IO1 IO2IO3 IO4IO5 IO6IO7 IO8IO9 IO10IO11 IO12IO13 IO14IO15 IO16IO17
IO18IO19 IO20IO21 IO22IO23 IO24IO25 IO26IO27 IO28IO29 IO30IO31 IO32IO33 IO34IO35
VCC
USER HEADER A USER HEADER B
5V
1 23 4
JP5
Header 2X2
1 23 4
JP6
Header 2X2
PWR_USER_1 PWR_USER_2
VCC 5V
1
1
2
2
3
3
4
4
D D
C C
B B
A A
12
Altium LimitedL3, 12a Rodborough RdFrenchs ForestNSWAustralia 208616
Board-On-Chip RS232 Serial Interface1.06
5/02/2004 4:43:48 PMC:\Program Files\Altium2004\Examples\Reference Designs\NanoBoard-NB1\BOC_RS232.SchDoc
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:A
13
10
11
8
12
9
14
7
C1+1
C2+4
GND15
C1-3 VCC 16
C2-5
V- 6
V+ 2
U1
MAX3232CSE
C3100nF
C6100nF
C7100nF
C8100nF
VCC
RTS
CTS
RX
BOC_RTS
BOC_TX
BOC_CTS
BOC_RX
R9100R
R1100R
BOC_RTS
BOC_TX
BOC_CTS
BOC_RX
1
2
3
4
5
6
7
8
9
11
10
J1
DB9 Female
TX
RXCTS
RTS
C2100nF Tant
C110uF
VCC
DCE Serial Port Use pin-for-pin DB9 Male-Female
Cable to connect to a PC
TX
1
1
2
2
3
3
4
4
D D
C C
B B
A A
13
Altium LimitedL3, 12a Rodborough RdFrenchs ForestNSWAustralia 208616
Board-On-Chip CAN Interface1.06
5/02/2004 4:43:48 PMC:\Program Files\Altium2004\Examples\Reference Designs\NanoBoard-NB1\BOC_CAN.SchDoc
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:A
TXD1
GND2
VDD3
RXD4
VREF 5
CANL 6CANH 7
RS 8
U2
MCP2551
1
2
3
4
5
6
7
8
9
11
10
J2
D Connector 9_MALE
C4
100nF
5V
5V
R3120R
CANHCANL
CAN_TXD
CAN_RXDR4270R
5V
R215KInsert Jumper 1-2 for High Speed Mode Insert Jumper 3-4 for CAN Load
CAN Bus Connector
CAN_TXD
CAN_RXD
12
34
JP1
Hea
der 2
X2
1
1
2
2
3
3
4
4
D D
C C
B B
A A
14
Altium LimitedL3, 12a Rodborough RdFrenchs ForestNSWAustralia 208616
Board-On-Chip Analog Interface1.06
5/02/2004 4:43:48 PMC:\Program Files\Altium2004\Examples\Reference Designs\NanoBoard-NB1\BOC_ADC_DAC.SchDoc
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:A
SDA
SCL
ADD1
SCL2
VDD3
GND4
SDA5
REF 6
OUTA 7OUTB 8OUTC 9OUTD 10
Maxim
U20
MAX5841MEUB
AIN0 1
AIN1 2
AIN2 3SCL5
SDA6
GND7
VDD8
AIN3/REF 4
Maxim
U21
MAX1037EKA-T
SCL
SDA
R794K7
R774K7
VCCA
VCCA
VCCVCCA
R800R
C47
100nF
C49
100nF
VCC
VCCA
123456789
10
TS1
TS10
VCCA VCCA
R754R7
Tant
C4810uF
AIN0AIN1AIN2AIN3
AOUT0AOUT1AOUT2AOUT3
C54100pF
C55100pF
C56100pF
C57100pF
VREF Header
1234
JP4
Header 2X2
VCCA
1 23 45 67 89 1011 1213 14
HDR8
Header 7X2
5V
Analog GND Power GND
AIN0 AIN1AIN2 AIN3
AOUT0 AOUT1AOUT2 AOUT3
SCL SDA
I2C/Analog Extension Header
VCCA
VREF_AOUT
R76100R
R78100R
SDA#
SCL#
VCC
1
1
2
2
3
3
4
4
D D
C C
B B
A A
15
Altium LimitedL3, 12a Rodborough RdFrenchs ForestNSWAustralia 208616
Board-On-Chip VGA, KB, and Mouse1.06
5/02/2004 4:43:48 PMC:\Program Files\Altium2004\Examples\Reference Designs\NanoBoard-NB1\BOC_VGA_KB_MOUSE.SchDoc
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:A
RED0
RED1
GREEN0
GREEN1
BLUE0
BLUE1
R10680R
R11330R
R12680R
R13330R
R14680R
R15330R
HDRIVE
VDRIVE
KBDATA
KBCLOCK
MOUSEDATA
MOUSECLOCK
123
D1
BA
S40-
04
123
D2
BA
S40-
04
123
D3
BA
S40-
04
123
D4
BA
S40-
04
123
D5
BA
S40-
04
VCC
VCC
Tant
C510uF
VCC
VCC
1716
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
J3Dsub-15-Female-HD
VGA
PS2 KEYBOARD
PS2 MOUSE
1 2 3 45678
RA24K7
123456
S
J4
8918-P6
123456
S
J5
8918-P6
RED#
GREEN#
BLUE#
1
1
2
2
3
3
4
4
D D
C C
B B
A A
16
Altium LimitedL3, 12a Rodborough RdFrenchs ForestNSWAustralia 208616
Board-On-Chip Power Supply1.06
5/02/2004 4:43:49 PMC:\Program Files\Altium2004\Examples\Reference Designs\NanoBoard-NB1\BOC_PWR.SchDoc
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:A
R47120R
R48100R
R49100R
R56120R
R5747R
R585R6
VCC
Tant
C2710uF
Tant
C2510uF
Tant
C2610uF
Tant
C3510uF
IN3 OUT 2
11
U10LM1084IS-ADJ
IN3 OUT 2
11
U11LM1084IS-ADJ
3V3
(Daughter Board Dependant) VCCINT
5V
12
GJ7
Header 2
12
GJ4
Header 2
12
GJ1
Header 2
12
GJ5
Header 2
GROUNDING POINTS
C16470uF 16V
C15470uF 16V
C24470uF 16V
23
1
S1
TL36WW050
12
GJ2
Header 2
VREF
VREF
12
GJ3
Header 2
12
GJ8
Header 2
12
GJ6
Header 2
R42120R
R4147R
R435R6
1V8
Tant
C2210uF
Tant
C2310uF
IN3 OUT 2
11
U9LM1084IS-ADJ
C21470uF 16V
1V8
PWR_IN
6V2 5W
D7SMBJ5341B
1
23
J6
KLD-0202-B
1
23
J7
KLD-0202-B
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
1
Altium LimitedL3, 12a Rodborough RdFrenchs ForestNSWAustralia 20861
Cyclone EP1C12 Daughterboard1.02
23/01/2004 4:06:55 PMC:\Program Files\Altium2004\Examples\Reference Designs\NanoBoard-NB1\Cyclone_EP1C12Q240\BOCD_CycloneEPC12.SchDoc
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:C
FPGA_CCLK
VREF
VCC
VCCINT
VCC
1V5 Decoupling
3V3 Decoupling
C210uF
C410uF
C310uF
VCCINT
VCC
C110uF
DATA025
nCONFIG 26
nCEO32 nCE33
MSEL034
MSEL135
DCLK 36
CONF_DONE 145
nSTATUS 146
TCK147
TMS148
TDO149 TDI155
U1B
Cyclone EP1C12Q240C8
VC
CA
_PLL
127
GNDA_PLL1 30
GNDG_PLL1 31
GNDG_PLL2 150
GNDA_PLL2 151
VC
CA
_PLL
215
4
VC
CIN
T81
VC
CIN
T19
1
VC
CIN
T11
0
VC
CIN
T90
VC
CIN
T72
VC
CIN
T21
1
VC
CIN
T97
VC
CIN
T22
9
VC
CIN
T19
8
VC
CIN
T20
4
VC
CIN
T22
0
VC
CIN
T10
3
VCCIO151 VCCIO122
VCCIO492
VCCIO3157
VCCIO470
VCCIO2189
VCCIO2231
VCCIO3130
GN
D19
0
GND 210
GND 232
GN
D17
1
GND 199GND 205
GN
D14
2
GN
D10
2
GND 212
GN
D12
9G
ND
111
GN
D69
GN
D19
2
GND 230
GN
D40
GN
D10
9
GN
D10
GN
D52
GN
D80
GN
D71
GN
D96
GN
D89
GN
D91
GND 221
VCCIO2209
VCCIO19
VCCIO3172
VCCIO4112
U1CCyclone EP1C12Q240C8
CLK0, LVDSCLK1p28
CLK1, LVDSCLK1n29 CLK3, LVDSCLK2n 152CLK2, LVDSCLK2p 153U1D
Cyclone EP1C12Q240C8
FPGA_M0FPGA_M1
FPGA_TDOFPGA_TDI
FPGA_TCKFPGA_TMS
FPGA_DIN
FPGA_PROGRAM
INIT_DONE
C50.1uF
C60.001uF
C70.1uF
C80.1uF
C90.1uF
C100.1uF
C110.1uF
C120.1uF
C130.1uF
C140.1uF
C150.1uF
C160.1uF
C170.1uF
C180.1uF
C190.1uF
C200.001uF
C210.1uF
C220.1uF
C230.1uF
C240.1uF
C250.1uF
C260.1uF
C270.1uF
C280.1uF
C290.1uF
C300.1uF
C310.1uF
C320.1uF
R14K7
R2DO NOT INSTALL
R347R
IO (ASDO) 37
IO, PLL1_OUTp 38
IO, PLL1_OUTn 39
IO, LVDS7n 41
IO, LVDS6p 42
IO, LVDS6n 43
IO, LVDS5p 44
IO, LVDS5n 45
IO, LVDS4p 46
IO, LVDS4n 47
IO, LVDS3p (DQ0L4) 48
IO, LVDS3n (DQ0L5) 49
IO, DPCLK0 50
IO, LVDS2p (DQ0L6) 53
IO, LVDS2n (DQ0L7) 54
IO, VREF2B1 55
IO 56
IO, LVDS1p 57
IO, LVDS1n 58
IO, LVDS0p 59
IO, LVDS0n 60
IO, L
VD
S50n
181
IO, L
VD
S50p
182
IO, L
VD
S48n
(D
Q0T
0)18
5
IO, L
VD
S48p
(D
Q0T
1)18
6
IO, L
VD
S47n
(D
Q0T
2)18
7
IO, L
VD
S47p
(D
Q0T
3)18
8
IO, D
PCLK
3 (D
QS0
T)
193
IO, V
REF
0B2
194
IO19
5
IO, L
VD
S41n
200
IO, L
VD
S41p
201
IO, L
VD
S40n
202
IO, L
VD
S40p
203
IO, L
VD
S39n
(D
M0T
)20
6
IO, L
VD
S39p
207
IO, V
REF
1B2
208
IO, L
VD
S34p
213
IO, L
VD
S33n
214
IO, L
VD
S33p
215
IO, L
VD
S32n
216
IO, L
VD
S32p
217
IO, L
VD
S31n
218
IO, L
VD
S31p
219
IO, L
VD
S30p
222
IO, L
VD
S29n
223
IO, L
VD
S29p
224
IO, L
VD
S28n
225
IO, L
VD
S28p
226
IO, V
REF
2B2
227
IO, D
PCLK
222
8
IO, L
VD
S27n
(D
Q0T
4)23
3
IO, L
VD
S27p
(D
Q0T
5)23
4
IO, L
VD
S26n
(D
Q0T
6)23
5
IO, L
VD
S26p
(D
Q0T
7)23
6
IO, L
VD
S24n
(DE
V_O
E)
239
IO, L
VD
S24p
(DE
V_C
LRn)
240
IO, L
VD
S46p
197
IO, L
VD
S25n
237
IO, L
VD
S49n
183
IO, L
VD
S49p
184
IO, L
VD
S46n
196
IO, L
VD
S25p
238
BANK 2IO, LVDS23p (INIT_DONE) 1
IO, LVDS23n 2
IO, LVDS22p (CLKUSR) 3
IO, LVDS22n 4
IO, VREF0B1 5
IO 6
IO, LVDS21p (DQ0L0) 7
IO, LVDS21n (DQ0L1) 8
IO, DPCLK1 (DQS0L) 11
IO, LVDS20p (DQ0L2) 12
IO, LVDS20n (DQ0L3) 13
IO, LVDS19p 14
IO, LVDS19n 15
IO, LVDS18p 16
IO, LVDS18n 17
IO, LVDS17p 18
IO, LVDS17n 19
IO, LVDS16p 20
IO, LVDS16n (DM0L) 21
IO, VREF1B1 23
IO (nCSO) 24
BAN
K 1
IO, L
VD
S102
p61
IO, L
VD
S102
n62
IO, L
VD
S100
p65
IO, L
VD
S100
n66
IO, L
VD
S99p
(DQ
1B7)
67IO
, LV
DS9
9n (D
Q1B
6)68
IO, D
PCLK
7 (D
QS1
B)
73IO
, VR
EF2B
474
IO, L
VD
S98p
75IO
, LV
DS9
8n (D
Q1B
5)76
IO, L
VD
S97p
(DQ
1B4)
77IO
, LV
DS9
7n78
IO, L
VD
S96p
79IO
, LV
DS9
5p82
IO, L
VD
S95n
83IO
, LV
DS9
4p84
IO, L
VD
S94n
85IO
, LV
DS9
3p86
IO, L
VD
S93n
87IO
, LV
DS9
2p88
IO, V
REF
1B4
93IO
, LV
DS8
7p (D
M1B
)94
IO, L
VD
S87n
95IO
, LV
DS8
6p98
IO, L
VD
S86n
99IO
, LV
DS8
5p10
0IO
, LV
DS8
5n10
1
IO10
6IO
, VR
EF0B
410
7IO
, DPC
LK6
108
IO, L
VD
S79p
(DQ
1B3)
113
IO, L
VD
S79n
(DQ
1B2)
114
IO, L
VD
S78p
(DQ
1B1)
115
IO, L
VD
S78n
(DQ
1B0)
116
IO, L
VD
S76p
119
IO, L
VD
S76n
120
IO, L
VD
S77n
118
IO, L
VD
S80p
104
IO, L
VD
S101
n64
IO, L
VD
S80n
105
IO, L
VD
S101
p63
IO, L
VD
S77p
117
BANK 4
IO, LVDS75n121 IO, LVDS75p122 IO, LVDS74n123 IO, LVDS74p124 IO, LVDS73n (DQ1R7)125 IO, LVDS73p126 IO, VREF2B3127 IO (DQ1R6)128 IO, DPCLK5 (DQS1R)131 IO, LVDS72n (DQ1R5)132 IO, LVDS72p (DQ1R4)133 IO, LVDS71n134 IO, LVDS71p135 IO, LVDS70n136 IO, LVDS70p137 IO, LVDS69n138 IO, LVDS69p139 IO, LVDS68n140 IO, LVDS68p141 IO, PLL2_OUTn143 IO, PLL2_OUTp144 IO, VREF1B3156 IO, LVDS59n (DM1R)158 IO, LVDS59p159 IO, LVDS58n160 IO, LVDS58p161 IO, LVDS57n162 IO, LVDS57p163 IO, LVDS56n164 IO, LVDS56p165 IO, LVDS55n166 IO, LVDS55p167 IO, LVDS54n168 IO, LVDS54p (DQ1R3)169 IO, DPCLK4170 IO, LVDS53n (DQ1R2)173 IO, LVDS53p (DQ1R1)174 IO (DQ1R0)175 IO, VREF0B3176 IO, LVDS52n177 IO, LVDS52p178 IO, LVDS51n179 IO, LVDS51p180
BAN
K 3
U1ACyclone EP1C12Q240C8
FPGA_INIT
FPGA_INSTALLED
REF_CLKFPGA_CLK
VCC
R4100R
R5100R
R61R
R71R
VCCINT
PLL Decoupling
R833R FPGA_DONE
R94K7
R104K7
R114K7
Nanoboard LOGO - 48mm
JIOA1JIOA0
BO
C_R
TS
BO
C_T
XB
OC
_CT
S
BO
C_R
XR
AM
_AD
DR
0
RA
M_A
DD
R1
RA
M_A
DD
R2
RA
M_A
DD
R3
RA
M_A
DD
R4
RA
M_A
DD
R5
RA
M_A
DD
R6
RA
M_A
DD
R7
RA
M_A
DD
R8
RA
M_A
DD
R9
RA
M_A
DD
R10
RA
M_A
DD
R11
RA
M_A
DD
R12
RA
M_A
DD
R13
RA
M_A
DD
R14
RA
M_A
DD
R15
RA
M_A
DD
R16
RA
M0_
DA
TA
0R
AM
0_D
AT
A1
RA
M0_
DA
TA
2R
AM
0_D
AT
A3
RA
M0_
DA
TA
4R
AM
0_D
AT
A5
RA
M0_
DA
TA
6R
AM
0_D
AT
A7
RA
M1_
DA
TA
0
RA
M1_
DA
TA
1
RA
M1_
DA
TA
2
RA
M1_
DA
TA
3R
AM
1_D
AT
A4
RA
M1_
DA
TA
5
RA
M1_
DA
TA
6
RA
M1_
DA
TA
7
RA
M0_
WE
RA
M0_
OE
RA
M_C
S
RA
M1_
WE
RA
M1_
OE
JIO
A0
JIO
A1
JIO
A2
JIO
A3
VCCINT
GREEN1BLUE0BLUE1HDRIVEVDRIVE
KBDATAKBCLOCK
MOUSEDATAMOUSECLOCK
FPGA_CLK_1FPGA_CLK_2
CAN_RXDCAN_TXD
RED0RED1GREEN0
NEXUS_TDI
NEXUS_TDO
NEXUS_TCKNEXUS_TMS
SPI_CLKSPI_DIN
SPI_DOUTSPI_SEL
SPI_MODE
VCC VCC
VCC
FPG
A_C
LKR
EF_
CL
K
LED
0L
ED1
LED
2L
ED3
LED
4L
ED5
LED
6L
ED7
SW0
SW1
SW2
SW3
SW4
SW5
SW6
SW7
LC
D_E
LC
D_B
CKL
BU
ZZ
ER
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
IO8
IO9
IO10
IO11
IO12
IO13
IO14
IO15
IO16
IO17
IO18
IO19
IO20
IO21
IO22
IO23
IO24
IO25
IO26
IO27
IO28
IO29
IO30
IO31
IO32
IO33
IO34
IO35SC
LSD
A
TES
T
VCC
VCCINT
IO0IO1IO2IO3IO4IO5IO6IO7IO8IO9IO10IO11IO12IO13IO14IO15IO16IO17
SCLSDA
SP0
SP1
SP2
SP3
SP4
SP5
SP6
SP7
SP8
SP9
SP10
SP11
SP12
SP13
SP14
SP15
SP5SP6
SP0SP1SP2SP3SP4
IO18IO19IO20IO21
IO22
IO23IO24IO25IO26IO27IO28IO29IO30IO31IO32IO33IO34IO35
NEXUS_TDO#
FPGA_CCLK#
FPGA_TDO#
FPGA_AUX0FPGA_AUX1FPGA_AUX2FPGA_AUX3
JIO
B0
JIO
B1
JIO
B2
JIO
B3
5V
5V
FPGA_ID2
FPGA_ID1
FPGA_ID0
FPGA_ID3
CA
N_R
XD
CA
N_T
XD
RE
D0
RE
D1
GR
EE
N0
GR
EE
N1
BL
UE
0B
LU
E1
HD
RIV
EV
DR
IVE
KB
DA
TA
KB
CL
OCK
MO
USE
DA
TAM
OU
SEC
LOC
K
FPG
A_C
LK_1
FPG
A_C
LK_2 VCC
FPG
A_D
IN
FPG
A_I
NIT
FPG
A_P
ROG
RA
M
FPG
A_D
ON
E
FPG
A_C
CLK
FPG
A_M
0FP
GA
_M1
FPG
A_T
DO
FPG
A_T
DI
FPG
A_T
CKFP
GA
_TM
S
NE
XU
S_TD
I
NE
XU
S_TD
O
NE
XU
S_TC
KN
EX
US_
TMS
SPI_
CLK
SPI_
DIN
SPI_
DO
UTSP
I_SE
L
SPI_
MO
DE
FPG
A_A
UX
0FP
GA
_AU
X1
FPG
A_A
UX
2FP
GA
_AU
X3
AU
DIO
_SPI
_CSn
SWC
0SW
C1
SWC
2
SWC
3
SWR
0
SWR
1SW
R2
SWR
3
SWC3SWR3
JIOA2JIOA3
LED2
HSMH-C170
LED1
HSMG-C170
R13270R
R12270R
VCC
NC1
A2
GND3 Y 4
VCC 5U2
SN74LVC1G04DBV
VCC
VCC
C33
0.1uF
23
45
67
89
10
1 1112
1314
1516
1718
1920
2122 24
2526
2728
2930
3132
23 3334
3536
3738
3940
4142
4344 46
4748
4950
5152
5354
45 5556
5758
5960 10
09997
9695
9493
9291
9089
988887
8685
8483
8281
8079
787775
7473
7271
7069
6867
766665
6463
6261
HDR254075-1009
23
45
67
89
10
1 1112
1314
1516
1718
1920
2122 24
2526
2728
2930
3132
23 3334
3536
3738
3940
4142
4344 46
4748
4950
5152
5354
45 5556
5758
5960 10
09997
9695
9493
9291
9089
988887
8685
8483
8281
8079
787775
7473
7271
7069
6867
766665
6463
6261
HDR154075-1009
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
1
Altium LimitedL3, 12a Rodborough RdFrenchs ForestNSWAustralia 20861
Spartan 2E 300 Daughterboard1.02
23/01/2004 4:11:25 PMC:\Program Files\Altium2004\Examples\Reference Designs\Spartan2E_XC2S300E-6PQ208\BOCD_SpartanIIE300.SchDoc
Title
Size: Number:
Date:File:
Revision:
Sheet ofTime:C
FPGA_TDO
FPGA_PROGRAM
FPGA_DONEFPGA_CCLK
FPGA_TDI
FPGA_TCKFPGA_TMS
FPGA_M0FPGA_M1FPGA_M2
R14K7
VCC
I/O 3
I/O, VREF 7 4
I/O 5
I/O, VREF 7, L49P_Y 6
I/O, L49N_Y 7
I/O 8
I/O 9
I/O, VREF 7, L48P_Y 10
I/O, L47P_YY 15
I/O, L47N_YY 16
I/O, L46P_YY 17
I/O, L46N_YY 18
I/O, VREF 7, L45P_Y 20
I/O, L45N_Y 21
I/O 22
I/O, L44P_YY 23
I/O (IRDY), L44N_YY 24
I/O (TRDY) 27
I/O 29
I/O, L43P_Y 30
I/O, VREF 6, L43N_Y 31
I/O, L42P_YY 33
I/O, L42N_YY 34
I/O, L41P_YY 35
I/O, L41N_YY 36
I/O, VREF 6, L40N_Y 41
I/O 42
I/O 43
I/O 44
I/O, VREF 6, L39P 45
I/O, L39N 46
I/O, VREF 6 47
I/O, L38P_YY 48
I/O, L38N_YY 49
I/O
, L37
N_Y
Y55
I/O
, L37
P_Y
Y56
I/O
, VR
EF
557
I/O
58I/
O, V
RE
F 5,
L36
N_Y
Y59
I/O
, L36
P_Y
Y60
I/O
, L35
N61
I/O
, L35
P62
I/O
, VR
EF
5, L
34N
_Y63
I/O
, L33
N_Y
68I/
O, L
33P_
Y69
I/O
70I/
O, L
32N
71I/
O, V
RE
F 5,
L32
P73
I/O
74I/
O (D
LL),
L31N
75I/
O (D
LL),
L31P
81I/
O82
I/O
, L30
N_Y
83I/
O, V
RE
F 4,
L30
P_Y
84I/
O, L
29N
_Y86
I/O
, L29
P_Y
87I/
O, L
28N
_Y88
I/O
, L28
P_Y
89
I/O
, VR
EF
4, L
27P_
Y94
I/O
95I/
O96
I/O
, L26
N_Y
Y97
I/O
, VR
EF
4, L
26P_
YY
98I/
O99
I/O
, VR
EF
410
0I/
O, L
25N
_YY
101
I/O
, L25
P_Y
Y10
2
I/O (INIT), L24N_YY107 I/O (D7), L24P_YY108 I/O, VREF 3109 I/O110 I/O, VREF 3, L23N_Y111 I/O, L23P_Y112 I/O113 I/O114 I/O, VREF 3, L22N_Y115
I/O (D5), L21N_YY120 I/O, L21P_YY121 I/O, L20N_YY122 I/O, L20P_YY123 I/O, VREF 3, L19N_Y125 I/O (D4), L19P_Y126 I/O127 I/O (TRDY)129 I/O (IRDY), L18N_YY132 I/O, L18P_YY133 I/O134 I/O (D3), L17N_Y135 I/O, VREF 2, L17P_Y136 I/O, L16N_YY138 I/O, L16P_YY139 I/O, L15N_YY140 I/O (D2), L15P_YY141
I/O, VREF 2, L14P_Y146 I/O147 I/O148 I/O149 I/O, VREF 2, L13N150 I/O, L13P151 I/O, VREF 2152
I/O (DIN, D0), L12N_YY153
I/O (DOUT, BUSY), L12P_YY154
I/O (C
S),
L11
P_Y
Y16
0
I/O
(WR
ITE)
, L11
N_Y
Y16
1
I/O
, VR
EF
116
2
I/O
163
I/O
, VR
EF
1, L
10P_
YY
164
I/O
, L10
N_Y
Y16
5
I/O
166
I/O
167
I/O,
VR
EF
1, L
9P_Y
168
I/O
, L8P
_Y17
3
I/O
, L8N
_Y17
4
I/O
, L7P
_Y17
5
I/O
, L7N
_Y17
6
I/O,
VR
EF
1, L
6P_Y
178
I/O
, L6N
_Y17
9
I/O
180
I/O
(DLL
), L5
P18
1
I/O
(DLL
), L5
N18
7
I/O,
L4P
188
I/O
, VR
EF
0, L
4N18
9
I/O
, L3P
_Y19
1
I/O
, L3N
_Y19
2
I/O
, L2P
_Y19
3
I/O
, L2N
_Y19
4
I/O
, VR
EF
0, L
1N_Y
199
I/O
200
I/O
201
I/O
, L0P
_YY
202
I/O
, VR
EF
0, L
0N_Y
Y20
3
I/O
204
I/O
, VR
EF
020
5
I/O
206
I/O, L48N_Y 11
I/O, L40P_Y 40
I/O
, L34
P_Y
64
I/O
, L27
N_Y
93
I/O (D6), L22P_Y116
I/O (D1), L14N_Y145
I/O
, L9N
_Y16
9
I/O
, L1P
_Y19
8 U1ASpartan XC2S300E-6PQ208C
C130.1uF
C140.1uF
C150.1uF
C160.1uF
C170.1uF
C180.1uF
C270.1uF
C280.1uF
C290.1uF
C300.1uF
C310.1uF
C320.1uF
VCCINT
C50.1uF
C60.1uF
C70.1uF
C80.1uF
C90.1uF
C100.1uF
C110.1uF
C120.1uF
C190.1uF
C200.1uF
C210.1uF
C220.1uF
C230.1uF
C240.1uF
C250.1uF
C260.1uF
VCC
1V8 Decoupling
3V3 Decoupling
C210uF
C410uF
C310uF
VCCINT VCC
REF_CLK
C110uF
GN
D12
4
VC
CIN
T37
GN
D10
3
VC
CIN
T67
GN
D13
1
VC
CIN
T90
GN
D85
VC
CIN
T14
2
GN
D13
7
VC
CIN
T17
2
GN
D79
VC
CIN
T19
5
GN
D15
8V
CC
INT
28
GN
D72
VC
CIN
T11
9
GN
D17
7
VC
CIN
T14
GN
D51
VC
CIN
T76
GN
D18
3
GN
D19
7
GN
D32
VC
CIN
T12
8
GN
D19
0
GN
D17
0
GN
D25
GN
D14
4
GN
D12
GN
D11
7
GN
D19
VC
CIN
T18
6
GN
D39
GN
D92
GN
D1
GN
D65
VC
CO
13V
CC
O26
VC
CO
38
VC
CO
53V
CC
O66
VC
CO
78V
CC
O91
VC
CO
105
VC
CO
118
VC
CO
130
VC
CO
143
VC
CO
156
VC
CO
171
VC
CO
184
VC
CO
196
VC
CO
208
U1BXC2S300E-6PQ208C
GCLK0,I80
GCLK1,I77
GCLK2,I 182
GCLK3,I 185
U1D
XC2S300E-6PQ208C
CCLK 155DONE 104
PROGRAM 106
M0 52M1 50M2 54
TDI 159TDO 157TCK 207TMS 2
U1C
XC2S300E-6PQ208C
FPGA_INIT
JIOA0JIOA1JIOA2JIOA3
IO3IO4IO5IO6IO7IO8IO9IO10IO11IO12IO13
IO14
CAN_RXDCAN_TXD
RED0RED1GREEN0GREEN1BLUE0BLUE1HDRIVEVDRIVE
KBDATAKBCLOCK
MOUSEDATAMOUSECLOCK
IO0IO1IO2
FPGA_CLK
FPGA_DIN
NEXUS_TDI
NEXUS_TDO
NEXUS_TCKNEXUS_TMS
SPI_CLKSPI_DIN
SPI_DOUTSPI_SEL
SPI_MODE
TEST
R4100R
R5
100R
R64K7
R74K7
VCC
Nanoboard LOGO - 48mm
FPGA_INSTALLED
FPGA_ID2
FPGA_ID1
FPGA_ID0
FPGA_ID3
BO
C_R
TS
BO
C_T
X
BO
C_R
XR
AM
_AD
DR
0
RA
M_A
DD
R1
RA
M_A
DD
R2
RA
M_A
DD
R3
RA
M_A
DD
R4
RA
M_A
DD
R5
RA
M_A
DD
R6
RA
M_A
DD
R7
RA
M_A
DD
R8
RA
M_A
DD
R9
RA
M_A
DD
R10
RA
M_A
DD
R11
RA
M_A
DD
R12
RA
M_A
DD
R13
RA
M_A
DD
R14
RA
M_A
DD
R15
RA
M_A
DD
R16
RAM
0_D
AT
A0
RAM
0_D
AT
A1
RAM
0_D
AT
A2
RAM
0_D
AT
A3
RAM
0_D
AT
A4
RAM
0_D
AT
A5
RAM
0_D
AT
A6
RAM
0_D
AT
A7
RA
M1_
DA
TA
0
RA
M1_
DA
TA
1
RA
M1_
DA
TA
2
RA
M1_
DA
TA
3R
AM
1_D
AT
A4
RA
M1_
DA
TA
5
RA
M1_
DA
TA
6
RA
M1_
DA
TA
7
RA
M0_
WE
RA
M0_
OE
RA
M_C
S
RA
M1_
WE
RA
M1_
OE
JIO
A0
JIO
A1
JIO
A2
JIO
A3
CA
N_R
XD
CA
N_T
XD
RE
D0
RE
D1
GR
EE
N0G
RE
EN1
BL
UE
0B
LU
E1
HD
RIV
EV
DR
IVE
KB
DA
TA
KB
CL
OC
K
MO
USE
DA
TAM
OU
SEC
LOC
K
FPG
A_C
LK_1
FPG
A_C
LK_2
FPG
A_D
IN
FPG
A_I
NIT
FPG
A_P
RO
GR
AM
FPG
A_D
ON
E
FPG
A_C
CLK
FPG
A_M
0FP
GA
_M1
FPG
A_T
DO
FPG
A_T
DI
FPG
A_T
CK
FPG
A_T
MS
NE
XU
S_TD
I
NE
XU
S_TD
O
NE
XU
S_TC
KN
EX
US_
TMS
SPI_
CLK
SPI_
DIN
SPI_
DO
UT
SPI_
SEL
SPI_
MO
DE
VCC
FPG
A_M
2
FPG
A_C
LKRE
F_C
LK
SWC
0SW
C1
SWC
2
SWC
3
SWR
0
SWR
1SW
R2
SWR
3
LED
0L
ED1
LED
2L
ED3
LED
4L
ED5
LED
6L
ED7
SW0
SW1
SW2
SW3
SW4
SW5
SW6
SW7
LCD
_E
LCD
_BC
KL
BUZ
ZER
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
IO8
IO9
IO10
IO11
IO12
IO13
IO14
IO15
IO16
IO17
IO18
IO19
IO20
IO21
IO22
IO23
IO24
IO25
IO26
IO27
IO28
IO29
IO30
IO31
IO32
IO33
IO34
IO35SC
LSD
A
TES
TJI
OB
0JI
OB
1JI
OB
2JI
OB
3
VCC
VREF
R2DO NOT INSTALL
R3DO NOT INSTALL
VCCINT
5V
VCC
VCCINT
5V
AU
DIO
_SPI
_CSn
BO
C_C
TS
JIOB1JIOB2JIOB3
IO15IO16IO17IO18IO19IO20IO21IO22IO23IO24IO25IO26IO27IO28IO29IO30IO31IO32IO33IO34IO35
NEXUS_TDO#
JIOB0
FPGA_CLK_1
FPGA_CLK_2
AUDIO_SPI_CSn
SCLSDA
LED2
HSMH-C170
LED1
HSMG-C170
R9270R
R8270R
NC1
A2
GND3 Y 4
VCC 5U2
SN74LVC1G04DBV
VCC
VCC
VCC
C33
0.1uF
23
45
67
89
10
1 1112
1314
1516
1718
1920
2122 24
2526
2728
2930
3132
23 3334
3536
3738
3940
4142
4344 46
4748
4950
5152
5354
45 5556
5758
5960 10
09997
9695
9493
9291
9089
988887
8685
8483
8281
8079
787775
7473
7271
7069
6867
766665
6463
6261
HDR254075-1009
23
45
67
89
10
1 1112
1314
1516
1718
1920
2122 24
2526
2728
2930
3132
23 3334
3536
3738
3940
4142
4344 46
4748
4950
5152
5354
45 5556
5758
5960 10
09997
9695
9493
9291
9089
988887
8685
8483
8281
8079
787775
7473
7271
7069
6867
766665
6463
6261
HDR154075-1009
FPGA_TDO#
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