msp class 5
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Reflections on the CPU and
Instruction Set
Simplicity
The MSP430 was designed from the start for low
power consumption.
Most programs today are written in C so the
processor is designed for efficient compilation
rather than hand-crafted assembly code
A straightforward set of 16 registers that includesall the special-purpose registers as well as the
general-purpose registers for addresses and data
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Is the MSP430 a RISC ?
Small set of general-purpose instructions
Large bank of general-purpose registers
Loadstore architecture
Single-cycle execution
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Conclusions on the Instruction Set
Orthogonality is wonderful : meaning that all
addressing modes can be used with all
instructions
Access to memory is simple and uniform
The constant generator makes programs faster
and more compact with no effort from the
programmer
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Resets
A reset is a sequence of operations that puts
the device into a well-defined state, from
which the users program may start
A reset is also generated if the device detects a
serious fault in hardware or software from
which the users program cannot be expected
to recover
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Resets
MSP430 has two levels of reset, depending on
whether the reset was caused by hardware or
software
Power-on Reset (POR) : This is generated by
severe conditions related to hardware
Power-up Clear (PUC) :This always follows
a power-on reset. It is generated when software
appears to be out of control
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Power-on Reset (POR)
POR is raised if the supply voltage drops to solow a value that the device may not workcorrectly.
Almost all current MSP430s include a brownoutdetector.
A low external signal on the RST/NMI pin resetsthe device if the pin is configured for the resetfunction rather than the nonmaskable interrupt
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Power-on Reset (POR)
Larger variants have a more comprehensive
supply voltage supervisor (SVS).
This is configurable, unlike the brownout
detector.
It sets the SVSFG flag if the voltage falls below
the programmed level and can optionally
reset the device
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Power-up Clear (PUC)
Generated when software appears to be out ofcontrol in the following ways
The watchdog timer overflows in watchdogmode.
The watchdog is active by default and musteither be disabled or regularly cleared before itrolls over
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Power-up Clear (PUC)
An attempt is made to write to the watchdogcontrol register WDTCTL without the correctpassword 0x5A (available as the symbol
WDTPW) in the upper byte
The registers for the flash memory controller,
FCTLn, are protected by a password in thesame way as WDTCTL. The value is 0xA5,available as the constant FWKEY.
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Power-up Clear (PUC)
An attempt to fetch an instruction from the
range of addresses reserved for peripheral
registers
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Conditions after Reset
The RST/NMI pin is configured for reset
Most input/output pins are configured as
digital inputs.
The status register is cleared
The watchdog timer starts in watchdog mode.
The program counter is loaded with the thereset vector, which is stored in the word at
0xFFFE
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Interrupt flag register 1
For large programs or networked systems it
may be necessary to identify the source of a
reset
Most information are in the interrupt flag
register 1
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Interrupt flag register 1
This may contain the following flags, depending on thevariant:
WDTIFG shows that the watchdog timed out or its security
key was violated. OFIFG indicates an oscillator
RSTIFG shows a reset caused by a signal on the RST/NMI
pin.
PORIFG is set for a power-on reset.
NMIIFG flags a nonmaskable interrupt (not reset) caused by a
signal on the
RST/NMI pin.
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Clock System
All microcontrollers contain a clock module to drive
the CPU and peripherals
clock module provides three outputs:
Master clock, MCLK is used by the CPU and a fewperipherals.
Sub-system master clock, SMCLK is distributed to
peripherals. Auxiliary clock, ACLK is also distributed to
peripherals
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Clock System
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Clock System
Most peripherals choose SMCLK, which is
often the same as MCLK and in the megahertz
range
ACLK, which is typically much slower and
usually 32 KHz
The frequencies of all three clocks can be
divided
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Clock System
Up to four sources are available for the clock,
depending on the family and variant
Low- or high-frequency crystal oscillator, LFXT1:
Available in all devices. It is usually used with a low-frequency watch crystal
(32 KHz) but can also run with a high-frequency
crystal (typically a few MHz) in most devices.
An external clock signal can be used instead of a
crystal if it is important to synchronize the MSP430
with other devices in the system.
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Clock System
High-frequency crystal oscillator, XT2:
Similar to LFXT1 except that it is restrictedto high frequencies.
It is available in only a few devices andLFXT1 (or VLO) is used if XT2 is missing
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Clock System
Internal very low-power, low-frequency
oscillator, VLO:
Available in only the more recent
MSP430F2xx devices.
It provides an alternative to LFXT1 when the
accuracy of a crystal is not needed.
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Clock System
Digitally controlled oscillator, DCO:
Available in all devices and one of thehighlights of the MSP430.
It is basically a highly controllable RCoscillator that starts in less than 1micro sec in
newer devices
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Clock System
ACLK comes from a low-frequency crystal oscillatorat 32 KHz.
Both MCLK and SMCLK are supplied by the DCOwith a frequency of around 1 MHz.
This is stabilized by the FLL where present.
frequency can be raised provided that VCC is high
enough to support it
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