logic gates boolean algebra

Logic Gates Logic Gates &

Boolean AlgebraBoolean Algebra

Instructor: Afroza Sultana

Boolean Constants and VariablesBoolean Constants and Variables

• Boolean constants and variables are allowed tohave only two possible values, 0 or 1.

• Boolean 0 and 1 do not represent actual numbersbut instead represent the state of a voltagegvariable, or what is called its logic level.

0/1 d L /Hi h d t f th ti• 0/1 and Low/High are used most of the time.

Logic OperationsLogic Operations

• Three Logic operations:g p- Logical Addition (OR operation)- Logical Multiplication (AND operation)- Logical Inversion (NOT operation)

G• Logic Gates– Digital circuits constructed from diodes,

transistors and resistors whose output is thetransistors, and resistors whose output is theresult of a basic logic operation (OR, AND, NOT)performed on the inputs.

Truth Tables

• How a logic circuit’s output depends on the logic l l t t th i tlevels present at the inputs.

OR Operation with OR gatesOutput is HIGH if any input is HIGH

Symbol truth table & waveform for a th i t OR tthree-input OR gate

And Operation with And GatesO t t i HIGH if ll i t HIGHOutput is HIGH if all inputs are HIGH

A

B

(c)

X

(a) Truth Table (b) Gate Symbol (c) waveform(c)

Truth Table and Symbol for a three-input AND tAND gate

NOT operation

• Truth Table, Symbol, Sample Waveform

O t t i i f th i tOutput is inverse of the input

Describing logic circuits algebraicallyDescribing logic circuits algebraically

• Any logic circuit, no matter how complex, can bel t l d ib d i th th b icompletely described using the three basic

Boolean operations: OR, AND, NOT.

• Example: logic circuit with its Booleanexpression X=A.B+C

Parentheses

• How to interpret A•B+C?Is it A•B ORed with C ? Is it A ANDed with B+C ?– Is it A•B ORed with C ? Is it A ANDed with B+C ?

• Order of precedence for Boolean algebra: AND beforeOR. Parentheses make the expression clearer, butpthey are not needed for the case on the precedingslide.

• Note that parentheses are needed here :• Note that parentheses are needed here :

Circuits Contain INVERTERsCircuits Contain INVERTERs

• Whenever an INVERTER is present in a logic-circuit diagram, its output expression is simplyequal to the input expression with a bar over it.

More Examples

Implementing Circuits From Boolean E iExpressions

• When the operation of a circuit is defined by aWhen the operation of a circuit is defined by aBoolean expression, we can draw a logic-circuitdiagram directly from that expression.

PrecedencePrecedence

• First, perform all inversions of single terms, p g

• Perform all operations with parentheses

• Perform an AND operation before an ORoperation unless parentheses indicateoperation unless parentheses indicateotherwise

• If an expression has a bar over it, perform theoperations inside the expression first and theni t th ltinvert the result

Example

• Draw the circuit diagram to implement theg pexpression

))(( CBBAx ++=

Evaluating Logic Circuit Outputs

Once we have the Boolean expression for a circuit

Evaluating Logic Circuit Outputs

output, we can obtain the output logic level for any set of input and even determine the truth table.E l D t i th t t X f th ditiExample: Determine the output X for the condition where A=0,B=1,C=1 and D=1

X= A B C (A+D)

Evaluating Logic Circuit Outputs

• X=A B C (A +D)0 1 1 (0 1)= 0.1.1.(0+1)

= 1.1.1.1 =1 1 1 0=1.1.1.0=0

• We can also evaluate the output levels by simplifying p y p y gthe logic output using Boolean Algebra.X= A B C (A +D)= A B C (A . D)= A B C D= 0 1 1 1= 0.1.1.1=0

Analysis Using Truth Table

NOR GatesNOR S b l E i l t Ci it T th T bl &• NOR Symbol, Equivalent Circuit, Truth Table & Wave form Output is inverse of the output of OR

ExampleExample

• Determine the Boolean expression for a three-input p pNOR gate followed by an INVERTER

NAND GateS b l E i l t Ci it T th T bl &• Symbol, Equivalent Circuit, Truth Table & Wave form Output is inverse of the output of AND

Example• Implement the logic circuit for the following

expression using only NOR and NAND gates

( )( )DCABx +⋅=

• Determine the output level in last example for A=B=C=1 and D=0

Boolean Theorems (single-variable)

1) X.0 =0 5) X+0 =0

2) X.1 =X 6) X+ 1 =1

3) X. X =X7) X+X =X

4) X. X =0 8) X+X =1

Multivariable Theorems

09. x+y = y+x10. xy = yx Commutativ law

11. x+(y+z) = (x+y)+z 12. (xy)z = x(yz) Associative law( y) (y )

13. (a) x(y+z) = xy+xz(b)(w+x)(y+z)= wy+xy+wz+xz Distributive Law(b)(w+x)(y+z)= wy+xy+wz+xz Distributive Law

14. x+xy = x

15. (a) x + x y = x + y(b) x + x y = x + y( ) y y

Examples

• Simplify the expression DBADBAy +=p y pAns: BAy =

y

( )• Simplify Ans:

( )( )BABAz ++=

Bz =

• Simplify Ans:

BCDAACDx +=BCDACDx +=Ans: BCDACDx +=

Demorgan’s TheoremsDemorgan s Theorems

( ) yxyx ⋅=+( ) yy

( )( ) yxyx +=⋅

Implications of DeMorgan’s Theorems

Example• Determine the output expression for the following• Determine the output expression for the following

circuit and simplify it using DeMorgan’s Theorem

( ) ( )• Simplify the expression to one having only single variables inverted.

( ) ( )DBCAz +⋅+=

ans.) DBCAz +=

Alternate Logic-Gate RepresentationsStandard and alternate symbols for various logic gates and inverter.

Logic-symbol Interpretation

• Active high/low– When an input or output line on a logic circuit symbol has

no bubble on it that line is said to be active-high otherwiseno bubble on it, that line is said to be active-high, otherwiseit is active-low.

Alternate Logic-Gate Representations

AA+B=AB

A

B

AB

X

AB

CC

X X

DCD

X AB (C+D)

C+DC D= C+D

X= AB (C+D)

Original Symbol Alternative Symbol

How to obtain the alternative symbol f t d dfrom standard ones

• Invert each input and output of the standard symbol.This is done by adding bubbles(small circles) oninput and output lines that do not have bubbles andby removing bubbles that are already there.

• Change the operation symbol from AND to OR, orfrom OR to AND. (In the special case of theINVERTER, the operation symbol is not changed.)

Several pointsTh i l b t d d t t ith• The equivalences can be extended to gates withany number of inputs.

• None of the standard symbols have bubbles onNone of the standard symbols have bubbles ontheir inputs, and all the alternate symbols do.

• The standard and alternate symbols for each gaterepresent the same physical circuit.

• NAND and NOR gates are inverting gates, and soboth the standard and the alternate symbols forboth the standard and the alternate symbols foreach will have a bubble on either the input or theoutput.

• AND and OR gates are non-inverting gates, and sothe alternate symbols for each will have bubbles onboth inputs and output.both inputs and output.

Universality of NAND gates

Universality of NOR gate

Example

Exclusive-OR CircuitExclusive OR (XOR) produces a HIGH output wheneverExclusive-OR (XOR) produces a HIGH output wheneverthe two inuts are at opposite levels.

Truth Table

Ex-OR gate

Wave form

Exclusive-NOR Circuit

Exclusive-NOR (XNOR) produces a HIGH outputwhenever the two inputs are at the same level.

Truth Table

Ex-NOR gate

Parity Method

• Parity Bit: An extra bit (single 0 or 1) that isy ( g )attached to a code group that is being transferredfrom one location to another.

• Two parity methods are(a) Even Parity Method(a) Even Parity Method(b) Odd Parity Method

Even Parity Method

• The value of the parity bit is chosen so that thep ytotal no of 1s in the code group is an evennumber.

• Example:i) 101101110010100 – signal without p.b.0101101110010100 – signal with p.b.

ii) 1011101001100 - signal without p.b.11011101001100 - signal with p b11011101001100 - signal with p.b.

Odd Parity Method

• The value of the parity bit is chosen so that the• The value of the parity bit is chosen so that thetotal no of 1s in the code group is an odd number.

• Example:i) 101101110010100 – signal without p.b.1101101110010100 – signal with p b1101101110010100 – signal with p.b.

ii) 1011101001100 - signal without p.b.01011101001100 - signal with p.b.

Even Parity Generator and Checker

Even Parity Generator and Checker

• The set of data to be transmitted is applied to theThe set of data to be transmitted is applied to theparity generator to produce the parity bit P.

• The p.b. is transmitted to the receiver along withthe data.

• At the receiver the data with p.b. enters the paritychecker, which produces an error output E to, p pindicate the error.