irs20124(s)pbf digital audio driver with discrete … sheets/infineon pdfs...irs20124(s)pbf data...
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Digital Audio Driver with Discrete Deadtime and ProtectionProduct Summary
VSUPPLY 200 V max.
IO+/- 1 A / 1.2 A typ.
Selectable Deadtime15 ns, 25 ns, 35 ns, 45 ns typ.
Prop Delay Time 60 ns typ.
Bi-Directional Over- Current Sensing
Package
Typical Application Diagram
IRS20124(S)PbF
Data Sheet No. PD60240
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14-Lead SOIC
Features
• 200 V high voltage ratings deliver up to 1000 Woutput power in Class D audio amplifierapplications
• Integrated deadtime generation and bi-directionalover-current sensing simplify design
• Programmable compensated preset deadtime forimproved THD performances over temperature
• High noise immunity• Shutdown function protects devices from overload
conditions• Operates up to 1 MHz• 3.3 V/5 V logic compatible input
<200V
HO
NC
VS
OCSET 1
OC
VCCSD
DT/SD
COM
OCSET 2
IN
VB
LO
IRS20124
NC
NC
<20V
<20V
IN
OC
• RoHS compliant
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IRS20124S(PbF)
Symbol Definition Min. Max. UnitsVB High-side floating supply voltage -0.3 220Vs High-side floating supply voltage VB-20 VB+0.3
VHO High-side floating output voltage Vs-0.3 VB+0.3VCC Low-side fixed supply voltage -0.3 20VLO Low-side output voltage -0.3 Vcc+0.3VIN Input voltage -0.3 Vcc+0.3VOC OC pin input voltage -0.3 Vcc+0.3
VOCSET1 OCSET1 pin input voltage -0.3 Vcc+0.3VOCSET2 OCSET2 pin input voltage -0.3 Vcc+0.3dVs/dt Allowable Vs voltage slew rate - 50 V/ns
PD Maximum power dissipation - 1.25 WRthJA Thermal resistance, junction to ambient - 100 °C/W
TJ Junction temperature - 150TS Storage temperature -55 150TL Lead temperature (soldering, 10 seconds) - 300
Absolute Maximum RatingsAbsolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parametersare absolute voltages referenced to COM. All currents are defined positive into any lead. The thermal resistance and powerdissipation ratings are measured under board mounted and still air conditions.
DescriptionThe IRS20124 is a high voltage, high speed power MOSFET driver with internal deadtime and shutdownfunctions specially designed for Class D audio amplifier applications.
The internal dead time generation block provides accurate gate switch timing and enables tight deadtimesettings for better THD performances.
In order to maximize other audio performance characteristics, all switching times are designed for immunityfrom external disturbances such as VCC perturbation and incoming switching noise on the DT pin. Logicinputs are compatible with LSTTL output or standard CMOS down to 3.0 V without speed degradation. Theoutput drivers feature high current buffers capable of sourcing 1.0 A and sinking 1.2 A. Internal delays areoptimized to achieve minimal deadtime variations. Proprietary HVIC and latch immune CMOS technologiesguarantee operation down to Vs= –4 V, providing outstanding capabilities of latch and surge immunities withrugged monolithic construction.
V
°C
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IRS20124S(PbF)
Note 1: Logic operational for VS equal to -8 V to 200 V. Logic state held for VS equal to -8 V to -VBS.
Recommended Operating ConditionsFor proper operation, the device should be used within the recommended conditions. The Vs and COMoffset ratings are tested with all supplies biased at a 15 V differential.
Symbol Definition Min. Max. UnitsVB High-side floating supply absolute voltage Vs+10 Vs+18VS High-side floating supply offset voltage Note 1 200
VHO High-side floating output voltage Vs VB
VCC Low-side fixed supply voltage 10 18VLO Low-side output voltage 0 VCCVIN Logic input voltage 0 VCCVOC OC pin input voltage 0 VCC
VOCSET1 OCSET1 pin input voltage 0 VCCVOCSET2 OCSET2 pin input voltage 0 VCC
TA Ambient Temperature -40 125 °C
Dynamic Electrical CharacteristicsVBIAS (VCC, VBS) = 15 V, CL = 1n F and TA = 25 °C unless otherwise specified. Fig. 2 shows the timing definitions.
Symbol Definition Min. Typ. Max. Units Test Conditionston High & low-side turn-on propagation delay — 60 80 VS=0 Vtoff High & low-side turn-off propagation delay — 60 80 VS=200 Vtr Turn-on rise time — 25 40tf Turn-off fall time — 15 35
tsd Shutdown propagation delay — 140 200
toc Propagation delay time from Vs>Vsoc+ to OC — 280 — OCSET1=3.22 VOCSET2=1.20 V
twoc min OC pulse width — 100 —toc filt OC input filter time — 200 —
DT1Deadtime: LO turn-off to HO turn-on (DTLO-HO)& HO turn-off to LO turn-on (DTHO-LO) 0 15 40 VDT>VDT1
DT2Deadtime: LO turn-off to HO turn-on (DTLO-HO)& HO turn-off to LO turn-on (DTHO-LO) 5VDT1>VDT> VDT2
DT3Deadtime: LO turn-off to HO turn-on (DTLO-HO)& HO turn-off to LO turn-on (DTHO-LO)
DT4Deadtime: LO turn-off to HO turn-on (DTLO-HO)
& HO turn-off to LO turn-on (DTHO-LO)VDT= VDT4
ns
V
5 25 50
10 35 60
15 45 70 VDT3>VDT>VDT4
VDT2>VDT>VDT3
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IRS20124S(PbF)
Static Electrical CharacteristicsVBIAS (VCC, VBS) = 15 V and TA = 25 °C unless otherwise specified.
Symbol Definition Min. Typ. Max. Units Test ConditionsVIH Logic high input voltage 2.5 — — Vcc=10 V -20 VVIL Logic low input voltage — — 1.2VOH High level output voltage, VBIAS – VO — — 1.2VOL Low level output voltage, VO — — 0.1
UVCC+ Vcc supply UVLO positive threshold 8.3 9.0 9.7UVCC- Vcc supply UVLO negative threshold 7.5 8.2 8.9UVBS+ High-side well UVLO positive threshold 8.3 9.0 9.7UVBS- High-side well UVLO negative threshold 7.5 8.2 8.9IQBS High-side quiescent current — — 1IQCC Low-side quiescent current — — 4 VDT=VccILK High-to-low-side leakage current — — 50 VB=VS =200 VIIN+ Logic “1” input bias current — 3 10 VIN=3.3 VIIN- Logic “0” input bias current — 0 1.0 V I N = 0 VIo+ Output high short circuit current (source) — 1.0 — Vo=0 V, PW<10 µsIo- Output low short circuit current (sink) — 1.2 — Vo=15 V, PW<10 µs
VDT1 DT mode select threshold 1 0.8(Vcc) 0.89(Vcc) 0.97(Vcc)VDT2 DT mode select threshold 2 0.51(Vcc) 0.57(Vcc) 0.63(Vcc)VDT3 DT mode select threshold 3 0.32(Vcc) 0.36(Vcc) 0.40(Vcc)VDT4 DT mode select threshold 4 0.21(Vcc) 0.23(Vcc) 0.25(Vcc)
VSOC+ OC threshold in Vs 0.75 1.0 1.25 OCSET1=3.22 VOCSET2=1.20 V
VSOC- OC threshold in Vs -1.25 -1.0 -0.75 OCSET1=3.22 VOCSET2=1.20 V
µA
mA
V
V
A
Io=0 A
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IRS20124S(PbF)
14
13
12
11
10
9
8
1
2
3
4
5
6
7
IN
OCSET1
DT/SD
OCSET2
OC
COM
LO VCC
NC
VS
HO
VB
NC
NC
IR20124S 14 Lead SOIC (narrow body)
Lead DefinitionsSymbol DescriptionVCC Low-side logic supply voltageVB High-side floating supplyHO High-side outputVS High-side floating supply returnIN Logic input for high-side and low-side gate driver outputs (HO and LO), in phase with HODT/SD Input for programmable deadtime, referenced to COM. shutdown LO and HO when tied to COMCOM Low-side supply returnLO Low-side outputOC Over-current output (negative logic)OCSET1 Input for setting negative over current thresholdOCSET2 Input for setting positive over current threshold
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IRS20124S(PbF)
Block Diagram
SD
LEVEL SHIFTER
UV DETECT
VB
HO
VS
INDEAD TIME
DT/SD
UV QSR
CURRENTSENSING
UV DETECT
DELAY
OC
OC
SET1
OC
SET2
Vcc
LO
COM
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IRS20124S(PbF)
DT/SD
HO LO
VSD
TSD
90%
Figure 1. Switching Time Waveform Definitions
Figure 2. Shutdown Waveform Definitions
50% 50%
toff(L)ton(L)
90%
10%
90%
10%
DTHO-LO
toff(H)
IN
HO
LO
ton(H)
DTLO-HO
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IRS20124S(PbF)
Figure 4. OC Waveform Definitions
toc filt
HIGH
VS
OC
Vsoct
COM
COM
twoc
VS
OC
VSoc+
tdoc
COM
COM
LO
VSoc-
IN
OCSET1
DT/SD
OCSET2
OC
COM
LO VCC
NC
VS
HO
VB
NC
NC
__
15V
15V
Vsoc+Vsoc-
10k
OC
Vsoc+
Vsoc-COMVS
OC
Figure 5. OC Waveform Definitions
Figure 3. OC Input FilterTime Definitions
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IRS20124S(PbF)
0
40
80
120
160
200
-50 -25 0 25 50 75 100 125
Temperature (oC)
Figure 6A. Turn-On Tim e vs. Temperature
0
40
80
120
160
200
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Figure 6B. Turn-On Tim e vs. Supply Voltage
Turn
-On
Del
ay T
ime
(ns)
Turn
-On
Del
ay T
ime
(ns)
Typ.
Max.
0
30
60
90
120
150
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Figure 7B. Turn-Off Time vs. Supply Voltage
Turn
-Off
Tim
e (n
s)
Typ.
Max.
0
0
0
0
0
0
-50 -25 0 25 50 75 100 125
Temperature (oC)
0
30
60
90
120
150
Turn
-Off
Tim
e (n
s)
Figure 7A. Turn-Off Time vs. Temperature
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IRS20124S(PbF)
10
20
30
40
50
60
-50 -25 0 25 50 75 100 125
Temperature (oC)
Turn
-On
Ris
e Ti
me
(ns)
Fiure 8A. Turn-On Rise Tim evs.Temperature
10
20
30
40
50
60
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Turn
-On
Ris
e Ti
me
(ns)
Figure 8B. Turn-On Rise Time vs. Supply Voltage
0
10
20
30
40
50
-50 -25 0 25 50 75 100 125
Temperature (oC)
Turn
-Off
Fall
Tim
e (n
s)
Figure 9A. Turn-Off Fall Tim e vs. Temperature
0
10
20
30
40
50
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Turn
-Off
Fall
Tim
e (n
s)
Figure 9B. Turn-Off Fall Tim e vs. Supply Voltage
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IRS20124S(PbF)
Min.
1
2
3
4
5
10 12 14 16 18 20
VCC Supply Voltage (V)
Inpu
t Vol
tage
(V)
Figure 10B. Logic "1" Input Voltage vs. Supply Voltage
Max.
0
1
2
3
4
-50 -25 0 25 50 75 100 125
Temperatre (oC)
Inpu
t Vol
tage
(V)
Figure 11A. Logic "0" Input Voltage vs. Temperature
Max.
0
1
2
3
4
10 12 14 16 18 20
VCC Supply Voltage (V)
Inpu
t Vol
tage
(V)
Figure 11B. Logic "0" Input Voltage vs. Supply Voltage
Min.
1
2
3
4
5
-50 -25 0 25 50 75 100 125
Temperature (oC)
Inpu
t Vol
tage
(V)
Figure 10A. Logic "1" Input Voltage vs. Temperature
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IRS20124S(PbF)
Max.
-1
0
1
2
3
4
-50 -25 0 25 50 75 100 125
Temperature (oC)
Hig
h Le
vel O
utpu
t Vol
tage
(V)
Figure 12A. High Level Output vs. Temperature
Max.
0.00
0.05
0.10
0.15
0.20
0.25
-50 -25 0 25 50 75 100 125
Temperature (oC)
Low
Lev
el O
utpu
t Vol
tage
(V)
Figure 13A. Low Level Output vs.Temperature
Max.
0.00
0.05
0.10
0.15
0.20
0.25
10 12 14 16 18 20
VCC Supply Voltage (V)
Low
Lev
el O
utpu
t Vol
tage
(V)
Figure 13B. Low Level Output vs. Supply Voltage
Max.
0
1
2
3
4
10 12 14 16 18 20
VCC Supply Voltage (V)
Hig
h Le
vel O
utpu
t Vol
tage
(V)
Figure 12B. High Level Output vs. Supply Voltage
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IRS20124S(PbF)
Max.
0
50
100
150
200
250
300
-50 -25 0 25 50 75 100 125
Temperature (oC)
Offs
et S
uppl
y Le
akag
e C
urre
nt ( µ
A)
Figure 14A. Offset Supply Leakage Current vs. Temperature VB= 200 V
Max.
Typ.
-10
10
30
50
70
90
110
50 80 110 140 170 200
VB Boost Voltage (V)
Offs
et S
uppl
y Le
akag
e C
urre
nt ( µ
A)
Figure 14B. Offset Supply Leakage Current vs. Supply Voltage
0.0
0.5
1.0
1.5
2.0
2.5
-50 -25 0 25 50 75 100 125
Temperature (oC)
VB
S S
uppl
y C
urre
nt (µ
A)
Figure 15A. VBS Supply Current vs. Temperature
0
1
1
2
2
3
10 12 14 16 18 20
VBS Supply Voltage (V)
VB
S Su
pply
Cur
rent
(µA
)
Figure 15B. VBS Supply Current vs. Supply Voltage
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IRS20124S(PbF)
Max.
0
2
4
6
8
10
-50 -25 0 25 50 75 100 125
Temperature (oC)
Vcc
Sup
ply
Cur
rent
( µA)
Figure 16A. VCC Supply Current vs. Temperature
Max.
0
2
4
6
8
10
10 12 14 16 18 20
VCC Supply Voltage (V)
Vcc
Sup
ply
Cur
rent
( µΑ
)
Figure 16B. VCC Supply Current vs. Supply Voltage
0
6
12
18
24
30
-50 -25 0 25 50 75 100 125
Temperature (oC)
Logi
c "1
" Inp
ut C
urre
nt (µ
A)
Figure 17A. Logic "1" Input Current vs. Temperature
0
6
12
18
24
30
10 12 14 16 18 20
VCC Supply Voltage (V)
Logi
c "1
" Inp
ut C
urre
nt (µ
A)
Figure 17B. Logic "1" Input Current vs. Supply Voltage
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IRS20124S(PbF)
Typ.
Max.
Min.
6
7
8
9
10
11
-50 -25 0 25 50 75 100 125
Temperature (oC)
Vc c
S u p
p l
y C
u r r e
n t
(µΑ
)
Figure 19. VCC Undervoltage Threshold (+) vs. Temperature
Typ.
Max.
Min.
6
7
8
9
10
11
-50 -25 0 25 50 75 100 125
Temperature (oC)
Vc c S
u p
p l
y C
u r r e
n t
(µ Α
)
Figure 20. VCC Undervoltage Threshold (-) vs. Temperature
Max
0
1
2
3
4
5
6
-50 -25 0 25 50 75 100 125
Temperature (°C)
Logi
c "0
" Inp
ut B
ias
Cur
rent
(µA
)
Max
0
1
2
3
4
5
6
10 12 14 16 18 20
Supply Voltage (V)
Logi
c "0
" Inp
ut B
ias
Cur
rent
(µA
)
Figure 18A. Logic "0" Input Bias Current
vs. TemperatureFigure 18B. Logic "0" Input Bias Current
vs. Voltage
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IRS20124S(PbF)
Typ.
0.5
0.7
0.9
1.1
1.3
1.5
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Out
put S
ourc
e C
urre
nt ( Α
)
Figure 23. Output Source Current vs. Supply Voltage
Typ.
0.5
0.7
0.9
1.1
1.3
1.5
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Out
put S
ink
Cur
rent
( Α)
Figure 24. Output Sink Current vs. Supply Voltage
6
7
8
9
10
11
-50 -25 0 25 50 75 100 125
Temperature (oC)
V BS
Sup
ply
Cur
rent
(µA
)
Figure 21. VBS Undervoltage Threshold (+) vs. Tem perature
6
7
8
9
10
11
-50 -25 0 25 50 75 100 125
Temperature (oC)
V BS
Sup
ply
Cur
rent
(µA
)
Figure 22. VBS Undervoltage Threshold (-) vs. Tem perature
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IRS20124S(PbF)
Typ.
-15
-13
-11
-9
-7
-5
10 12 14 16 18 20
VBS Floting Supply Voltage (V)
V S O
ffset
Sup
ply
Volta
ge (V
)
Figure 25. Maximum VS Negative Offset vs. Supply Voltage
Typ.
Max.
Min.
11
12
13
14
15
16
-50 -25 0 25 50 75 100 125
Temperature (oC)
V DT1
(V)
Figure 26. DT Mode Select Threshold (1) vs. Temperature
Typ.
Max.
Min.
6
7
8
9
10
11
-50 -25 0 25 50 75 100 125
Temperature (oC)
V DT2
(V)
Figure 27. DT Mode Select Threshold (2) vs. Temperature
Typ.
Max.
Min.
3
4
5
6
7
8
-50 -25 0 25 50 75 100 125
Temperature (oC)
V DT3
(V)
Figure 28. DT Mode Select Threshold (3) vs. Temperature
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IRS20124S(PbF)
Typ.
20
28
36
44
52
60
-50 -25 0 25 50 75 100 125
Temperature (oC)
DT LO
-HO
(ns
)
Figure 30. DT LO Turn-Off to HO TurnOon (3) vs. Temperature
2.0
2.5
3.0
3.5
4.0
4.5
-50 -25 0 25 50 75 100 125
Temperature (oC)
VD
T4 (V
)
Figure 29. DT Mode Select Threshold (4) vs. Temperature
Typ.
Max.
Min.
-1.8
-1.5
-1.2
-0.9
-0.6
-0.3
-50 -25 0 25 50 75 100 125
Temperature (oC)
Neg
ativ
e O
C T
H (V
)
Figure 32. Negative OC Threshold(-) in VS vs. Temperature
Typ.
Max.
Min.
0.0
0.4
0.8
1.2
1.6
2.0
-50 -25 0 25 50 75 100 125
Temperature (oC)
Posi
tive
OC
TH
(V)
Figure 31. Positive OC Threshold(+) in VS vs. Temperature
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IRS20124S(PbF)
140V
70V
0V
15
25
35
45
55
65
1 10 100 1000
Frequency (kHz)
Tem
pera
ture
(o C)
Figure 32. IRS20124S vs. Frequency (IRFBC20) Rgate=33 Ω , VCC=12 V
140v
70v
0v
15
25
35
45
55
65
1 10 100 1000
Frequency (kHz)
Tem
pera
ture
(o C)
Figure 33. IRS20124S vs. Frequency (IRFBC30)Rgate=22 Ω , VCC=12 V
140V
70V
0V
15
25
35
45
55
65
1 10 100 1000
Frequency (kHz)
Tem
pera
ture
(o C)
Figure 34. IRS20124S vs. Frequency (IRFBC40) Rgate=15 Ω , VCC=12 V
140V
70V
0V
15
25
35
45
55
65
75
1 10 100 1000
Frequency (kHz)
Tem
pera
ture
(o C)
Figure 35. IRS20124S vs. Frequency (IRFPE50) Rgate=10 Ω , VCC=12 V
33. 34 .
35. 36.
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IRS20124S(PbF)
Functional description
Programmable Dead-time
The IRS20124 has an internal deadtime generationblock to reduce the number of external componentsin the output stage of a Class D audio amplifier.Selectable deadtime through the DT/SD pin volt-age is an easy and reliable function, which re-quires only two external resistors. The deadtimegeneration block is also designed to provide aconstant deadtime interval, independent of Vccfluctuations. Since the timings are critical to theaudio performance of a Class D audio amplifier,the unique internal deadtime generation block isdesigned to be immune to noise on the DT/SDpin and the Vcc pin. Noise-free programmabledeadtime function is available by selectingdeadtime from four preset values, which are opti-mized and compensated.
How to Determine Optimal Deadtime
Please note that the effective deadtime in an actualapplication differs from the deadtime specified inthis datasheet due to finite fall time, tf. Thedeadtime value in this datasheet is defined as thetime period from the starting point of turn-off onone side of the switching stage to the startingpoint of turn-on on the other side as shown in Fig.5. The fall time of MOSFET gate voltage must besubtracted from the deadtime value in thedatasheet to determine the effective dead time ofa Class D audio amplifier.
(Effective deadtime)= (Deadtime in datasheet) – (fall time, tf)
HO (or LO)
LO (or HO)
tf
Dead-time
Effective dead-time
10%
10%
90%
Effective Deadtime
A longer deadtime period is required for a MOSFETwith a larger gate charge value because of thelonger tf. A shorter effective deadtime setting isalways beneficial to achieve better linearity in theClass D switching stage. However, the likelihoodof shoot-through current increases with narrowerdeadtime settings in mass production. Negativevalues of effective deadtime may cause excessiveheat dissipation in the MOSFETs, potentiallyleading to their serious damage. To calculate theoptimal deadtime in a given application, the falltime (tf)for both output voltages, HO and LO, inthe actual circuit needs to be measured. Inaddition, the effective deadtime can also vary withtemperature and device parameter variations.Therefore, a minimum effective deadtime of 10 nsis recommended to avoid shoot-through currentover the range of operating temperatures andsupply voltages.
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IRS20124S(PbF)
DT/SD pin
DT/SD pin provides two functions: 1) setting dead-time and 2) shutdown. The IRS20124 determinesits operation mode based on the voltage appliedto the DT/SD pin. An internal comparatortranslates which mode is being used by comparinginternal reference voltages. Threshold voltages foreach mode are set internally by a resistive voltagedivider off Vcc, negating the need of using a preciseabsolute voltage to set the mode.
Vcc 0.89xVcc 0.57xVcc 0.36xVcc 0.23xVcc
Shutdown
45nS
35nS
25nS
15nS
Operational Mode
VDT
Dead-time
Deadtime Settings vs VDT Voltage
Design Example
Table 1 shows suggested values of resistance forsetting the deadtime. Resistors with up to 5%tolerance can beused if theselisted values arefollowed.
Vcc
COM
DT/SD
>0.5mA
R1
R2
IRS20124
Table 1. Suggested Resistor Values for DeadtimeSettings
Shutdown
Since IRS20124 has internal deadtime generation,independent inputs for HO and LO are no longerprovided. Shutdown mode is the only way to turnoff both MOSFETs simultaneously to protect themfrom over current conditions. If the DT/SD pin de-tects an input voltage below the threshold, VDT4,the IRS20124 will output 0 V at both HO and LOoutputs, forcing the switching output node to gointo a high impedance state.
Over Current Sensing
In order to protect the power MOSFET, IRS20124has a feature to detect over-current conditions,which can occur when speaker wires are shortedtogether. The over-current shutdown feature canbe configured by combining the current sensingfunction with the shutdown mode via the DT/SD pin.
Load Current Direction in Class D AudioApplication
In a Class D audio amplifier, the direction of theload current alternates according to the audio in-put signal. An over current condition can thereforehappen during either a positive current cycle or anegative current cycle. It should be noted thatExternal Resistor
Deadtime mode
R1 (Ω)
R2 (Ω)
DT/SD (V)
DT1 <10k Open 1.00 (Vcc) DT2 3.3k 8.2k 0.71 (Vcc) DT3 5.6k 4.7k 0.46 (Vcc) DT4 8.2k 3.3k 0.29 (Vcc)
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IRS20124S(PbF)
each MOSFET carries a part of the load currentin an audio cycle. Bi-directional current sensingoffers over current detection capabilities in bothcases by monitoring only the low side MOSFET.
Load Current
0
Bi-Directional Current Sensing
IRS20124 has an over-current detection functionutilizing RDS(ON) of the low side switch as a currentsensing shunt resistor. Due to the proprietary HVICprocess, the IRS20124 is able to sense negativeas well as positive current flow, enabling bi-direc-tional load current sensing without the need forany additional external passive components.
Direction in MOSFET Current and Load Current
vs
Vsoc+
Vsoc-
COM
~~ ~~ ~~~~ ~~ ~~ ~~ ~~ ~~ ~~~~
(a ) Normal Operation Condition
(b ) Over- Current in Positive Load Current
(c ) Over- Current in Negative Load Current
Vs Waveform in Over-Current Condition
IRS20124 measures the current during the periodwhen the low side MOSFET is turned on. Undernormal operating conditions, Vs voltage for the lowside switch is well within the trip threshold bound-aries, VSOC- and VSOC+. In the case of Fig. 9(b) whichdemonstrates the amplifier sourcing too much cur-rent to the load, the Vs node is found below the triplevel, VSOC-. In Fig. 9(c) with opposite current direc-tion, the amplifier sinks too much current from theload, positioning Vs well above trip level, VSOC+.
Once the voltage in Vs exceeds the preset thresh-old, the OC pin pulls down to COM to detect anover-current condition.
Since the switching waveform usually containsover/under shoot and associated oscillatory arti-facts on their transient edges, a 200 ns blankinginterval is inserted in the Vs voltage sensing blockat the instant the low side switch is engaged.Because of this blanking interval, the OC functionwill be unable to detect over current conditions ifthe low side ON duration less than 200 ns.
OCSET1
OCSET2
VsLO
OC
+
+
-
-
OR AND
Simplified Functional Block Diagram ofBi-Directional Current Sensing
The bi-directional current sensing block has aninternal V level shifter feeding the signal to thecomparator. OCSET1 sets the threshold, and isgiven a trip level at VSOC+, which is OCSET1 -V. Inthe same way, for a given OCSET2, VSOC- is set atOCSET2 -V.
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IRS20124S(PbF)
External Resistor Network to Set OC Threshold
Vcc
COM
OCSET1
>0.5mA
R3
R4
R5 OCSET2
How to set OC Threshold
The positive and negative trip thresholds for bi-directional current sensing are set by the voltagesat OCSET1 and OCSET2.
The trip threshold voltages, VSOC+ and VSOC+, aredetermined by the required trip current levels, ITRIP+
ITRIP-, and RDS(ON) in the low side MOSFET.Since the sensed voltage of Vs is shifted up by2.21 V internally and compared with the voltagesfed to the OCSET1 and OCSET2 pins, the requiredvalue of OCSET1 with respect to COM is
VOCSET1 = VSOC+ + 2.21 V = I x RDS(ON) + 2.21 V
The same relation holds between OCSET2 and VSOC-,
VOCSET2 = VSOC- + 2.21 V = I x RDS(ON) + 2.21 V
In general, RDS(ON) has a positive temperature co-efficient that needs to be considered when thethreshold level is being set. Please also note that,
in the negative load current direction, the sensingvoltage at the Vs node is limited by the body di-ode of the low side MOSFET as explained later.
Design Example
This example demonstrates how to use the exter-nal resistor network to set ITRIP+ and ITRIP- to be±11 A, using a MOSFET that has RDS(ON) =60 µΩ.
VISET1 = VTH+ + 2.21 V = ITRIP+ x RDS(ON) + 2.21 V =11 x 60 µΩ +2.21 V = 2.87 VVISET2 = VTH- + 2.21 V = ITRIP- x RDS(ON) + 2.21 V =(−11) V 60 µΩ +2.21 V = 1.55 V
The total resistance of resistor network is basedon the voltage at the Vcc and required bias cur-rent in this resistor network.
Rtotal =R3 + R4 + R5 = Vcc / Ibias
= 12 V / 1 µΑ = 12 k Ω
The expected voltage across R3 is Vcc- VISET1
= 12 V - 2.87 V=9.13 V. Similarly, the voltagesacross R4 is VSOC+ - VSOC- = 2.87 V - 1.55 V=1.32 V, and the voltage across R5 is VISET2= 1.55V respectively.
R3 =9.13 V/ Ibias = 9.13 kΩR4 =1.32 V/ Ibias = 1.32 kΩR5 =1.55 V/ Ibias = 1.55 kΩ
Choose R3= 9.09 kΩ R4=1.33 kΩ, R5=1.54 k Ωfrom E-96 series.Consequently, actual threshold levels areVSOC+ =2.88 V gives ITRIP+ = 11.2 AVSOC- =1.55 V gives ITRIP- = -11.0 A
Resisters with 1% tolerances are recommended.
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IRS20124S(PbF)
OC Output Signal
The OC pin is a 20 V open drain output. The OCpin is pulled down to ground when an over currentcondition is detected. A single external pull-upresistor can be shared by multiple IRS20124 OCpins to form the ORing logic. In order for a micro-processor to read the OC signal, this informationis buffered with a mono stable multi vibrator toensure 100 ns minimum pulse width.Because of unpredictable logic status of the OCpin, the OC signal should be ignored during powerup/down.
Limitation from Body Diode in MOSFET
When a Class D stage outputs a positive current,flowing from the Class D amp to the load, the bodydiode of the MOSFET will turn on when the drainto source voltage of the MOSFET become largerthan the diode forward drop voltage. In such acase, the sensing voltage at the Vs pin of theIRS20124 is clamped by the body diode. Thismeans that the effective RDS(ON) is now much lowerthan expected from RDS(ON) of the MOSFET, andthe Vs node my not able to reach the thresholdto turn the OC output on before the MOSFET fails.Therefore, the region where body diode clampingtakes a place should be avoided when setting VSOC-.
For further application information for gate driverIC please refer to AN-978 and DT98-2a. For fur-ther application information for class D applica-tion, please refer to AN-1070 and AN-1071.
Body Diode in MOSFET Clamps vs Voltage
VS - COM
ID
Body Diode ClampOCSET2 should be
set in this region
0
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IRS20124S(PbF)
01-601901-3063 00 (MS-012AB)14 Lead SOIC (narrow body)
Case Outline
www.irf.com 26
IRS20124S(PbF)
CA R RI E R T A P E D IM E NS I O N F O R 1 4 S O IC N
Co d e M in M ax M in M axA 7 .9 0 8.1 0 0. 31 1 0 .3 18B 3 .9 0 4.1 0 0. 15 3 0 .1 61C 15 .7 0 1 6. 30 0. 61 8 0 .6 41D 7 .4 0 7.6 0 0. 29 1 0 .2 99E 6 .4 0 6.6 0 0. 25 2 0 .2 60F 9 .4 0 9.6 0 0. 37 0 0 .3 78G 1 .5 0 n/ a 0. 05 9 n/ aH 1 .5 0 1.6 0 0. 05 9 0 .0 62
M etr ic Im p erial
RE E L D IM E NS I O N S F O R 1 4 SO IC N
Co d e M in M ax M in M axA 32 9. 60 3 30 .2 5 1 2 .9 76 13 .0 0 1B 20 .9 5 2 1. 45 0. 82 4 0 .8 44C 12 .8 0 1 3. 20 0. 50 3 0 .5 19D 1 .9 5 2.4 5 0. 76 7 0 .0 96E 98 .0 0 1 02 .0 0 3. 85 8 4 .0 15F n /a 2 2. 40 n /a 0 .8 81G 18 .5 0 2 1. 10 0. 72 8 0 .8 30H 16 .4 0 1 8. 40 0. 64 5 0 .7 24
M etr ic Im p erial
E
F
A
C
D
G
AB H
NOTE : CONTROLLING DIMENSION IN MM
LOADED TAPE FEED DIRECTION
A
H
F
E
G
D
BC
Tape & Reel14-Lead SOIC
www.irf.com 27
IRS20124S(PbF)
SO-14 package is MSL2 qualified.This product has been designed and qualified for the industrial level.
Qualification standards can be found at IR's Web Site http://www.irf.com WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel:(310) 252-7105
Data and specifications subject to change without notice. 12/4/2006
14-Lead SOIC IRS20124SPbF14-Lead SOIC Tape & Reel IRS20124STRPbF
LEADFREE PART MARKING INFORMATION
Lead Free ReleasedNon-Lead FreeReleased
Part number
Date code
IRSxxxxx
YWW?
?XXXXPin 1Identifier
IR logo
Lot Code(Prod mode - 4 digit SPN code)
Assembly site codePer SCOP 200-002
P
? MARKING CODE
ORDER INFORMATION
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