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Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001
Chapter 5Chapter 5Register Transfer LanguagesRegister Transfer Languages
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Chapter OutlineChapter Outline
• Micro-operationsMicro-operations
• RTLRTL
• RTL specificationsRTL specifications
• Realizing RTL specificationsRealizing RTL specifications
• VHDLVHDL
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Micro-operationsMicro-operations
• Specify data transferSpecify data transfer
• Do not specify conditions under which Do not specify conditions under which transfers occurtransfers occur
• Do not specify hardware implementationDo not specify hardware implementation
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Example: X Example: X Y Y
X
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Register Transfer LanguageRegister Transfer Language
• Specify micro-operations and when they Specify micro-operations and when they occuroccur
• Format:Format: conditionsconditions: : micro-operationsmicro-operations
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Example: Example: αα: X : X Y Y
X
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Simultaneous Data TransfersSimultaneous Data Transfersαα: X : X Y, Y Y, Y Z Z
Q D
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Invalid Simultaneous TransfersInvalid Simultaneous Transfers
αα: X : X Y, X Y, X Z Z
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Loading Constant Values into Loading Constant Values into RegistersRegisters
αα: X : X 0 0
ββ: X : X 1 1
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Making Transfers Mutually Making Transfers Mutually ExclusiveExclusive
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Multi-bit Data TransfersMulti-bit Data Transfersαα: X : X Y Y
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Bit and Bit-range TransfersBit and Bit-range Transfers
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Arithmetic and Logical Micro-Arithmetic and Logical Micro-operationsoperations
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Shift Micro-operationsShift Micro-operations
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Specifying Digital Specifying Digital Components: D Flip-FlopComponents: D Flip-Flop
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Specifying Digital Components: Specifying Digital Components: JK Flip-FlopJK Flip-Flop
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Specifying Digital Components: Specifying Digital Components: Left Shift RegisterLeft Shift Register
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Specifying Simple SystemsSpecifying Simple Systems
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System Implementation – Data System Implementation – Data PathsPaths
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System Implementation – Data System Implementation – Data Paths and ControlPaths and Control
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System Implementation Using a System Implementation Using a Bus and 3-State BuffersBus and 3-State Buffers
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System Implementation Using System Implementation Using a Bus and a Multiplexera Bus and a Multiplexer
n o j
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Modulo 6 CounterModulo 6 Counter
• Counts up when U = 1Counts up when U = 1
• Count sequence: 000 Count sequence: 000 001 001 010 010 011 011 100 100 101 101 000 … 000 …
• V is 3-bit output = count valueV is 3-bit output = count value
• C is 1-bit output = 1 when V = 000C is 1-bit output = 1 when V = 000
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Modulo 6 CounterModulo 6 Counter State Table State Table
1 1 11 1 1
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Modulo 6 CounterModulo 6 Counter State Diagram State Diagram
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Modulo 6 CounterModulo 6 Counter RTL RTL SpecificationSpecification
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Modulo 6 CounterModulo 6 Counter System System ImplementationImplementation
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Modulo 6 CounterModulo 6 Counter Another Another System ImplementationSystem Implementation
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Toll Booth ControllerToll Booth Controller
• C = 1 when car is at toll boothC = 1 when car is at toll booth
• I[1..0] indicates coin inputI[1..0] indicates coin input
• Outputs R, G, A:Outputs R, G, A:– Car in toll booth, toll not fully paid: R = 1Car in toll booth, toll not fully paid: R = 1– Toll paid: G = 1Toll paid: G = 1– Car left without paying full toll: R = 1, A = 1Car left without paying full toll: R = 1, A = 1
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Toll Booth Controller StatesToll Booth Controller States
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Toll Booth Controller State TableToll Booth Controller State Table
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Toll Booth Controller State DiagramToll Booth Controller State Diagram
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Toll Booth Controller State Toll Booth Controller State AssignmentsAssignments
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Converting State Transitions Converting State Transitions to RTL Codeto RTL Code
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Converting State Transitions to Converting State Transitions to RTL CodeRTL Code
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Toll Booth Controller RTL Toll Booth Controller RTL Specification (excluding outputs)Specification (excluding outputs)
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Toll Booth Controller RTL Toll Booth Controller RTL Specification (outputs)Specification (outputs)
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VHDL – VHSIC Hardware VHDL – VHSIC Hardware Description LanguageDescription Language
• Formal syntax – portableFormal syntax – portable
• Platform independentPlatform independent
• Design for PLDs, ASICs, or custom Design for PLDs, ASICs, or custom chipschips
• Simulate designsSimulate designs
• Different levels of abstractionDifferent levels of abstraction
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VHDL Design StructureVHDL Design Structure
• Library sectionLibrary section
• Entity sectionEntity section
• Architecture sectionArchitecture section
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VHDL Library SectionVHDL Library Section
library IEEE;library IEEE;
use IEEE.std_logic_1164.all;use IEEE.std_logic_1164.all;
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VHDL Entity SectionVHDL Entity Section
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VHDL Architecture SectionVHDL Architecture Section
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VHDL – High Level of VHDL – High Level of AbstractionAbstraction
• Modulo 6 counterModulo 6 counter
• Designed as a state machineDesigned as a state machine
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Modulo 6 Counter – Library Modulo 6 Counter – Library and Entity Sectionsand Entity Sections
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Modulo 6 Counter – One StateModulo 6 Counter – One State
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Architecture Section – State Architecture Section – State GenerationGeneration
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Architecture Section – State Architecture Section – State Generation (continued)Generation (continued)
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Architecture Section – State Architecture Section – State TransitionTransition
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VHDL – Low Level of AbstractionVHDL – Low Level of Abstraction
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VHDL – Advanced VHDL – Advanced CapabilitiesCapabilities
• ComponentsComponents
• TimingTiming
• SimulationSimulation
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SummarySummary
• Micro-operationsMicro-operations
• RTLRTL
• RTL specificationsRTL specifications
• Realizing RTL specificationsRealizing RTL specifications
• VHDLVHDL
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