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Introduction to Introduction to Tanner Tools Tanner Tools ProProTMTM
Express TrainingExpress TrainingVolume 1 Volume 1
Design Capture and SimulationDesign Capture and Simulation
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About Tanner ResearchAbout Tanner ResearchTanner EDA --- IC Design Tools
Electronic Design Automation Software & Training
Tanner CES --- Consulting & Engineering Services
Development, IP & Consulting for High Performance ASICs
Tanner Labs --- Advanced TechnologiesTechnology Research for Government and Commercial Sectors. MEMS fab.
Manuflex --- Manufacturing ServicesLow and Medium Volume IC Fabrication, FPGA and Mixed-Signal ASIC Conversion Services
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Comprehensive TrainingComprehensive TrainingDay 1: Front End Design• System Setup & Requirements• Begin S-Edit: Schematics, Symbols• Application Setup• Test-bench, Integration to T-Spice• T-Spice Simulation & Analysis• Optimization• Internal Tables• Accuracy, Convergence Control• Intro to External Models
Day 3: Layout Verification & SPR• Design Rule Checking• Design Rule Setup & Optimize• Extract• Post-layout Simulation• LVS Check, Debug• Introduction to T-Cells• Place & Route (SPR)
Day 2: IC Layout with L-Edit• Polygon, Cell Handcrafting• Design Database Components• L-Edit Application Setup• L-Edit Technology Setup• Workgroup Management• Tape-out• Cross-section Viewing• Intro to UPI• Intro to T-Cells
Day 4: Advanced Topics. How UPI works. Creating Interpreted Macros. Creating T-Cells. Layout composition functions. Creating Compiled Macros
Day 5: Advanced Topics. Using Visual Studio. Advanced C Review. Debugging Macros. Common & Advanced UPI tasks
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Course ObjectivesCourse Objectives
Establish an overall understandingof IC design using Tanner Tools.
Master the basic IC design operationsthrough hands-on exercises. (abridged)
Complete an example design from concept to tape-out. (abridged)
Get your chip design questions answered.
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Hardware RequirementsHardware RequirementsTanner Tools Minimum Requirements
Windows 98/ME/NT/2000/XPPentium II machine or equivalent128MB RAM (256MB RAM for DRC)250MB HD space to install the program (varies with packages)3 button mouse, or IntellimouseVideo card with at least 16MB
Tanner Tools Recommended RequirementsPentium III machine or higher with Windows 20001GHz or higher512MB RAM or higherIntellimouse - 2 button mouse with wheel used as 3rd buttonLatest video card with at least 32 MB (NVIDIA Quadro 2 Pro or Matrox Millennium G400)1280 x1024 Resolution - True Color (24-bit)
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Circuit Design /Circuit Design /
Design ConceptDesign ConceptThe objective in this class is …
...to build a trivial circuit…...from concept ...… to tape-out…
…on a deadline.”Product" definition
“AO22” chipAND-OR logic function.Timing=?Power=?I/O characteristics?Technology: 0.25um n-well CMOSSchedule.
A B C D Z0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 10 1 0 0 00 1 0 1 00 1 1 0 00 1 1 1 11 0 0 0 01 0 0 1 01 0 1 0 01 0 1 1 11 1 0 0 11 1 0 1 11 1 1 0 11 1 1 1 1
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Design FlowDesign Flowdesign conceptdesign concept
plotplot plot setup
LVSLVS LVS setup
DRCDRC DRC rule setup
CrossCross--section viewsection view cross-section tech setup
TT--Spice simulationSpice simulation T-Spice device models
SS--Edit schematic entryEdit schematic entryDevice symbols
Subcircuit schematics & symbols
Librarian / Technologist Tasks
Extract rule setupExtractExtract
tape outtape out GDSII layer numbers
L-Edit application setuptechnology setup
device/gate/block layoutsUPI macrosSPRSPR
EDIF/TPR netlistEDIF/TPR netlist
polygon layoutpolygon layout
SDLSDL
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W-EditTM
WaveformViewer
W-EditTM
WaveformViewer
T-SpiceTM
High-PerformanceCircuit Simulator
T-SpiceTM
High-PerformanceCircuit Simulator
TT--Spice ProSpice ProTMTM
SPRPlace and Route
SPRPlace and Route
S-EditTM
SchematicEditor
S-EditTM
SchematicEditor
LL--Edit Edit ProProTMTM
LVSLayout vs.Schematic
LVSLayout vs.Schematic
ExtractDevice
Extractor
ExtractDevice
Extractor
DRCDesign Rule
Checker
DRCDesign Rule
Checker
LL--Edit Edit VerifyVerifyTMTM
Tanner Tools ProTM
Library• Symbol• Schematic• Device
model• Process
setup• Layout• UPI
SPICEEDIF VHDL/Verilog
GDSII
CIF
(DXF)
L-EditTM
Custom Layout EditorCross Section Viewer
User Programmable Interface
L-EditTM
Custom Layout EditorCross Section Viewer
User Programmable Interface
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“S“S--Edit” Schematic EditorEdit” Schematic EditorEasy to use
commands & shortcuts like L-Edit
One file for a complete design
portableIntegration
with T-Spice and W-Edit
Basic featuresLimited
capabilitiescapacity
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Circuit Design /Circuit Design /
Beginning with SBeginning with S--EditEditOpening S-Edit
Desktop Shortcut-or-
Start menu-or-
double-click on “.SDB” fileCommands
Menus-or-
Toolbars-or-
Shortcut Keys
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SS--Edit window RegionsEdit window Regions
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Tanner Tools HelpTanner Tools Help
Adobe Acrobat
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Circuit Design / SCircuit Design / S--Edit / HierarchyEdit / HierarchySchematicsSchematics contain instances of Modulescontain instances of Modules
represented byrepresented by SymbolsSymbols
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Circuit Design /Circuit Design /
Designs in SDesigns in S--EditEditA “.SDB” file contains a complete design.The pieces used to construct hierarchical design schematics are known by various equivalent names:
ModulesOther common terms: Cells, or Components, or Blocks, or Subcircuits
Objects in Schematics and Symbols (slide)Active (influence the netlist output)Inactive (for Annotation, visual only)
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Symbol and schematic objects diagramSymbol and schematic objects diagram“.SDB Files
EDIF schematic “.EDS”
Place & Route“.EDN”
or “.TPR”
Verilognetlist
“.VLG”
VHDL netlist
“.VHD”
T-Spice / LVS “.SP”
Modules
schematicinfo
info
pagesActive:port wirelabelnode cap instance info
Inactive:line box polygon circle comment
symbolActive:port propertyinfo
Inactive: line box polygon circle comment
S-Edit“.SDB”
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Circuit Design / Schematic /Circuit Design / Schematic /
SelectionsSelectionsSelecting Objects
Selection Tool » “F2” shortcut key
Left or Right Mouse button» Suggestion: Use the right mouse button for selecting.
“<ctrl>a” selects all; “<alt>a” deselects all.
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Circuit Design / Schematic /Circuit Design / Schematic /
InstancesInstances
Placing an instance» “i” shortcut key» Tool button in drawing tools» Symbol browser
Instance name vs. module nameAutomatic Instance namesEditing Properties on instances » Ctrl-E shortcut key» “eyeglasses” tool
Inheritance of properties
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Circuit Design / Schematic /Circuit Design / Schematic /
WiresWiresWires
Drawing wires » “wire spool” Tool button» “F3” shortcut
Node Labels» “N” Tool button» “F4” shortcut key
Node Caps» stops global nodes from propagating upward» “stopsign” Tool button» “F5” shortcut key
Ports» 4 Tool buttons» “F6” shortcut key (repeat F6 to cycle)
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Circuit Design / Schematic /Circuit Design / Schematic /
Editing CommandsEditing CommandsMove: Middle mouse buttonStretch: Middle mouse button on an edge
» for wires, lines, shapesFlip: “h”, “v” shortcut keysRotate: “r” shortcut keyCopy: “<ctrl>c”Cut: “<ctrl>x”Paste: “<ctrl>v”Duplicate: “<ctrl>d”
» Remembers offset from the previous object.Undo: “<ctrl>z”Redo: “<ctrl>y”Edit Object (properties): “<ctrl>e”
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Circuit Design / Schematic /Circuit Design / Schematic /
Viewing CommandsViewing Commands<Home> key show full view<+> key zooms in<-> key zooms outArrow keys pan up / down / right / left“z” zooms to drag box“x” key exchanges previous view“w” zooms to selected object“<spacebar>” redraws the screen
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Circuit Design /Circuit Design /
Traversing SchematicsTraversing SchematicsFile/Open
» Multiple files can be open at the same time.» Only one module in one file is visible at a time.» Multiple S-Edit sessions can be open at once (no paste).
Module/Open» Changes the visible (editable) module.» Also can change to another open file. » Open by selection: select instance, open it: “<click>, o, <enter>”» With nothing selected: toggle between two modules: “o, <enter>”» By name: type the beginning of the module name until unique
“o, character, <enter>”
“Find”» “f” shortcut key» Helps traverse up and down the hierarchy.
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Circuit Design / SCircuit Design / S--Edit / ModulesEdit / Modules
name:name:
“NAND2”“NAND2”
Schematic
Schematic
(inside)(inside)
SymbolSymbol(outside)(outside)
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Circuit Design / Symbols / Circuit Design / Symbols /
Symbol EditingSymbol Editing".SDB" File (Schematic DataBase) (diagram)
/ Module/Symbol
Active objects: Port, Info, PropertyOperations are like in a Schematic
Symbols have more inactive shapes .Symbols have no wires.Symbols have properties.
View switching from schematic to symbol» “?” shortcut key» toolbar buttons
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Circuit Design / Symbols / Circuit Design / Symbols /
Symbol PropertiesSymbol PropertiesInactive objects: (do not influence the netlist)
Box » “<shift>F2” shortcut
Circle» “<shift>F3” shortcut
Comment (text)» “<shift>F4” shortcut
Polygons» “<shift>F5” shortcut (cycles)
Lines (do not make connections)» “<shift>F6” shortcut (cycles)
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Circuit Design / Symbols / Circuit Design / Symbols / Symbol Properties Symbol Properties –– Working with PropertiesWorking with Properties
M, NMOS, L=, W=, AS=, AD=, PS=, PD=, [spaces]Literal text, written to the SPICE file unchanged.
%{D}, %{G}, %{S}, %{B}Takes the name of the nodes connected to the pins corresponding to the ports named D, G, S and B.
${W}, ${L}The values of the properties named W and L
${Instance}, ${Page}, ${Info}, ${Author}, ${File}, ${Modified}Predefined properties that allow internal information (such as the name of the file, module, page, and instance) to be inserted in the output string.
W=1.2u, L=0.5u, name=${instance}, model=NMOSDefault values assigned to each property.
M# %{D} %{G} %{S} %{B} ${model} L=${L} W=${W}# - An incremented integer that counts the instances of the module.
\Escape character
\n, \tNewline, tab.
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origin
“NMOS” symbol“NMOS” symbol
Note grid spacing of pins.
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AO22 SymbolAO22 Symbolorigin Note grid spacing of pins.
2 grids
10 grids
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Circuit Design / Symbols / Circuit Design / Symbols /
Symbol PropertiesSymbol PropertiesProperties
» “F7” shortcut to add» “<ctrl>e” to edit
Some properties are arbitrary (user defined)» examples: “L”, “model”, “name”
Pre-defined property names» SPICE OUTPUT (T-Spice netlist format)» SPICE PARAMETER (for hierarchical parameters)» TPR OUTPUT (TPR netlist for SPR/BPR)» EDIF PRIMITIVE (EDIF netlist for SPR/BPR)» PAD (for SPR pad locations)» VHDL PRIMITIVE (VHDL netlist for logic simulation)
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“NAND2” Schematic“NAND2” Schematic
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“AO22” Schematic“AO22” Schematic
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Circuit Design / Circuit Design /
Good design practicesGood design practicesWorking directory
Be aware of it; Keep it pointed to the project directory.Changed by: “OPEN FILE”, any file system access.Visible & reset by: “OPEN FILE”, “SAVE AS”.
Hierarchy for layoutIt is best to match so layout & verification can be done “bottom-up”.
Readabilityuse large textuse large snap grid
Revision control - in the “info” formComments
design notes, truth tables, copy of symbol in schematicLayout instructions, inspection checklistCritical nets, matched devices
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Testbench (a schematic, or an “.sp” file)Voltage & Current SourcesT-Spice device library (file)» “.model”» “.lib” …”.endl”
Control card modules, analysis types.Measure
Exporting the schematicSimulationWaveform Cross Probing
Circuit Design / Circuit Design /
Interface to TInterface to T--SpiceSpice
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Circuit Design/WCircuit Design/W--Edit Edit
“W“W--Edit” Waveform ViewerEdit” Waveform ViewerIntegrated With T-Spice and S-EditMultiple Window and Chart ViewingCustomizable Chart and Trace DisplayTrace operations
expression defined tracesarithmetic traces
Pan, Zoom, Expand/Collapse FeaturesSpectral AnalysisCursors and MeasurementsReport Ready Printer OutputOLE Document EmbeddingDefault settings
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Circuit Design/WCircuit Design/W--Edit Edit
WW--Edit Window RegionsEdit Window Regions
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Circuit Design/WCircuit Design/W--Edit Edit
Spectral AnalysisSpectral Analysis
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“AO22_tb” Test Bench“AO22_tb” Test Bench
Source_v_dc
Source_v_bithightime=50nlowtime=50nset bit pattern
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“AO22_“AO22_tbtb.SP” file.SP” file
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Waveform Cross ProbingWaveform Cross Probing
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Waveform Cross ProbingWaveform Cross Probing
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Circuit Design/TCircuit Design/T--SpiceSpice
“T“T--Spice” Circuit SimulatorSpice” Circuit SimulatorPerformance
High Speed Table Based SimulationUser Defined C-language ModelsQueuing for Batch Simulation
CompatibilityHSPICE CompatibleIndustry Standard Transistor Models (ex. BSIM3v3)
CapabilityUser Defined Models Measurement (.measure)Parametric AnalysisFourier Analysis Monte Carlo AnalysisOptimization
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Circuit Design/TCircuit Design/T--SpiceSpice
“T“T--Spice” Circuit SimulatorSpice” Circuit SimulatorLaunch from S-EditAutomatic netlist generationColor-coded/Syntax highlighting text editorCommand generator toolClick-back to syntax errorRun-time waveform displaySimulation managerBatch Queue
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Circuit Design/TCircuit Design/T--Spice Spice
Introduction to TIntroduction to T--Spice WindowSpice WindowLaunching T-Spice
Desktop Shortcut Start menuDouble-click on .SP fileDrag-and-drop any file onto T-Spice shortcut
Simulation HistoryInput ParametersDrag and Drop EditingTracing syntax errors
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Circuit Design/TCircuit Design/T--Spice Spice
TT--Spice Window RegionsSpice Window RegionsMenu bar
Toolbars
Status Bar
Simulation Manager
Simulation Output
Text Windows
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Circuit Design/TCircuit Design/T--Spice Spice
TT--Spice Command ToolSpice Command Tool
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Circuit Design/TCircuit Design/T--Spice Spice
TT--Spice Header FileSpice Header FileStandard T-Spice input file -contains initialization commands and options.
Processed before input netlist
Recommended options to put in header files:.options echo $echo all input.options list $list all devices.options verbose=2 $Verbose printout of runtime information.options search = ‘C:\Tanner\Library’ $set search path for .lib files
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Circuit Design/TCircuit Design/T--Spice Spice
TT--Spice AnalysisSpice AnalysisCase Sensitivity
Node and Device names:» Default is case insensitive.» “.options casesensitive” or command line switch
Key words are not case sensitive.
Analysis TypesDC operating point - “.op”Transient - “.tran”DC transfer - “.dc”AC analysis - “.ac”
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Circuit Design/TCircuit Design/T--Spice Spice
MeasurementsMeasurementsMeasurement (.measure)
Find-When; Trigger-Target.measure tran delaytime + trig v(1) val=2.5 fall=3+ targ v(2) val=2.5 rise=3
Signal statistics (max, min, avg, pp, rms, etc.).measure ac maxgain max vm(out)
Expression evaluation.param tf= ’1E-6 * sin(pi/ 2)’
Error function (relative difference between outputs)
.measure tran v1 v2 err v(1) v(2)
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Circuit Design/TCircuit Design/T--Spice Spice
Repeated SimulationsRepeated SimulationsParameter Sweep (.step / .data / .sweep)
Model/device parameterSourcetemperature
.alterOptimizationMonte Carlo Analysis
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Circuit Design/TCircuit Design/T--Spice Spice
Internal/External TablesInternal/External TablesInternal Tables (vs. Direct models) - charges and currents at device terminals) are computed “directly”
Direct mode (turn tables off)» “.options deftables=0” (default 1=“tables on”)
Table mode by instance or by device» “tables=1” (1=“tables on”)Finer table resolution » “.gridsize MOS 256 256 128“ (default is 64, 128, 10)
High voltage (default +/- 5 volts)» “.vrange MOS 15”
Generate Table / External Tables - data points are read or interpolated from precomputed tables stored in memory.
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Circuit Design/TCircuit Design/T--Spice Spice
AccuracyAccuracyTable vs. Direct Model Evaluation
Table mode is 1½-2 times faster than Direct modeAccuracy is compromised, generally 1%-2% model accuracyMay introduce switching behavior for some circuits.Best practice – if repeated simulations are done for the same circuit, run once in direct mode, and then in table mode to verify that the accuracy is within acceptable limits
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Circuit Design/TCircuit Design/T--Spice Spice
ConvergenceConvergenceConvergence Control
Visibility» “.options acct verbose=2”» “.options list” - printout detailed information about every element in the
netlistRamp power supplies
» “.tran/powerup”» Source stepping “.option minsrcstep”
Forcing nodes» “.nodeset” starts and iterates to an operating point» “.ic” forces the operating point
Iteration limits» “.options numnd” (DC) “numnt” (transient)» “.options extraiterations=X” – X is an integer, recommended value < 10
tells T-Spice to perform extra Newton Raphson solver iterations after convergence has been achieved.Increases accuracy
.options gmin & gmindc
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Circuit Design/TCircuit Design/T--Spice Spice
Accuracy vs. SpeedAccuracy vs. Speed3 meta-options to control the settings of other options, providing an easy and reliable way to increase the speed/accuracy of simulations.
Fast - sacrifices accuracy for the sake of speeding up simulations. » Recommended only for very stable circuits.
Accurate - increases accuracy of simulations with some slow-down (about 50%).» Recommended for sign-off/final simulations.
Precise - Maximizes accuracy with large performance degradation.» Recommended for very small circuits or when performing device
or transistor characterizations.
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Circuit Design/TCircuit Design/T--Spice Spice
Digital SimulationsDigital SimulationsCircuits that contain very square linear voltage or current source pulse waveforms, with fast rise and fall times, will greatly benefit from the delta-voltagebased timestepping algorithm
lvltim = 1 : Delta voltage algorithm» Recommended for digital-like circuits.
lvltim = 2 : Charge based algorithm» T-Spice default.
lvltime = 3 : Delta voltage plus time reversal. » Provides increased accuracy over lvltim 1 setting.
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Circuit Design/TCircuit Design/T--Spice Spice
External ModelsExternal ModelsPurpose of external models
» New or Improved devices» Higher level blocks or gates» Multiple energy domains, ex. mechanical, thermal (MEMS)
C (or C++) language device models» compiled or interpreted
Model Features» Unlimited number of terminals» User defined model & device parameter names» Support for parasitics, internal nodes, noise models» User defined small-signal parameters» Automatic table generation for speed
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Circuit Design/TCircuit Design/T--Spice Spice
External ModelsExternal ModelsWriting an external model
Examples» C:\Tanner\TSpice90\extmod\win32\…» resist.c, switch.c, diode.c, mos1.c, vco.c» Gate model example
Template file» ...\template.c
Using an external model.model‘x’ instance card (like a subcircuit)
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Circuit Design/TCircuit Design/T--SpiceSpice
TT--Spice Exercise Spice Exercise -- SimulationSimulation-- Use TUse T--Spice “Insert Command” Tool to Setup TestbenchSpice “Insert Command” Tool to Setup Testbench
Export NAND2 schematic
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Circuit Design/TCircuit Design/T--Spice Spice
TT--Spice Exercise Spice Exercise -- SimulationSimulationAdd voltage supply VDD
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Circuit Design/TCircuit Design/T--Spice Spice
TT--Spice Exercise Spice Exercise -- SimulationSimulationAdd input on A
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Circuit Design/TCircuit Design/T--Spice Spice
TT--Spice Exercise Spice Exercise -- SimulationSimulationAdd input on B
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Circuit Design/TCircuit Design/T--Spice Spice
TT--Spice Exercise Spice Exercise -- SimulationSimulationInclude model file (.lib or .include)
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Circuit Design/TCircuit Design/T--Spice Spice
TT--Spice Exercise Spice Exercise -- SimulationSimulationAdd Transient analysis command (.tran)
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Circuit Design/TCircuit Design/T--Spice Spice
TT--Spice Exercise Spice Exercise -- SimulationSimulationAdd print command (.print)
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Circuit Design/TCircuit Design/T--Spice Spice
TT--Spice ExerciseSpice ExerciseMeasure the timing difference between input falling edge & output rising edge
Circuit Design/TCircuit Design/T--Spice Spice
TT--Spice Exercise Spice Exercise -- SimulationSimulationMeasure the timing difference between input falling edge & output rising edge
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Circuit Design/TCircuit Design/T--Spice Spice
TT--Spice Exercise Spice Exercise -- SimulationSimulationRun SimulationView Waveforms in W-Edit.Diff = 0.612 ns
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Circuit Design/TCircuit Design/T--Spice Spice (Optional)(Optional)
TT--Spice Exercise Spice Exercise –– OptimizationOptimizationOptimization specifications:
- Optimize: the Length of the PMOS transistor- Goal: Minimize the delay so that diff is 0.40 ns instead
of 0.612 nsOptimization Preparation- Change the PMOS length values to variables in the netlist:
MP1 OUT IN1 VDD VDD PMOS L='Lp' W=8UMP2 OUT IN2 VDD VDD PMOS L='Lp' W=8U
- Define the variables Lp by adding:.param Lp=2u
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Circuit Design/TCircuit Design/T--Spice Spice
TT--Spice Exercise Spice Exercise -- OptimizationOptimizationDefine the optimization nameDefine the optimization goal
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Circuit Design/TCircuit Design/T--Spice Spice
TT--Spice Exercise Spice Exercise -- OptimizationOptimizationDefine the optimization VariablesDefine the optimization algorithm
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Circuit Design/TCircuit Design/T--Spice Spice
TT--Spice Exercise Spice Exercise -- OptimizationOptimizationInsert the optimization statement
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Run the simulation
Change the optimization goal in the netlist to 0.20 ns and run the simulation again. Is the optimizer able to reach the goal?
Circuit Design/TCircuit Design/T--Spice Spice
TT--Spice Exercise Spice Exercise -- OptimizationOptimization
Introduction to Introduction to Tanner Tools ProTanner Tools ProTMTM
Express TrainingExpress TrainingVolume 2 Volume 2
Layout Editing and VerificationLayout Editing and Verification
Software Solutions
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Design FlowDesign Flowdesign conceptdesign concept
plotplot plot setup
LVSLVS LVS setup
DRCDRC DRC rule setup
CrossCross--section viewsection view cross-section tech setup
TT--Spice simulationSpice simulation T-Spice device models
SS--Edit schematic entryEdit schematic entryDevice symbols
Subcircuit schematics & symbols
Librarian / Technologist Tasks
Extract rule setupExtractExtract
L-Edit application setuptechnology setup
device/gate/block layoutsUPI macrosSPRSPR
EDIF/TPR netlistEDIF/TPR netlist
polygon layoutpolygon layout
tape outtape out GDSII layer numbers
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“L“L--Edit” Layout EditorEdit” Layout EditorFull Custom All-Angle Layout Editor
Technology ConfigurableFully HierarchicalDesign NavigatorCustomizable Keyboard, Palette, RulersUser and Workgroup configurationsCommand Line InterfaceMDI-Layout & TextGDSII, CIF, EPS & DXF supportUser Properties on objectsUPI programmableCross-section ViewerAdvanced Editing Support
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Class Design ProjectClass Design Project
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LL--Edit Colors Edit Colors -- Your choiceYour choice
“Windows style” - white background- solid fills
“Traditional style”- black background- cross-hatch fills
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Layout/ Layout/
Introduction to LIntroduction to L--EditEditLaunch L-Edit
Desktop Shortcut Start menu".TDB" (Tanner layout Database) File
Open FilesDouble-click on .TDBFile… Open…Drag-and-drop onto application or desktop icon
Open cells Design NavigatorCell Open“o” hotkey when instance is selected
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LL--Edit Window RegionsEdit Window Regions
Menu bar
Locator
Design Navigator
Status Bar Mouse Buttons Bar
Drawing tools
Layer Palette
Text Windows /Layout Windows
Details button
Aerial View Toolbar
Toolbars
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Tanner Tools HelpTanner Tools Help
Find(within document)
First/last page
Previous/next page
Previous/next view
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LL--Edit “Files”Edit “Files”
A “file” corresponds to an entire designLayout cells and process informationLocked by single editorData transferred between files via:» “copy across” (also “instance across”)» File… Replace Setup…
Data shared between files via:» XREF cells
Files have Info… and Properties.An L-Edit file corresponds to a single .TDB file on disk.
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Layout/ Layout/
View OperationsView Operations
• Mouse Wheel – Vertical Pan• Shift+Mouse Wheel – Horizontal Pan• Ctrl+Mouse Wheel – Zoom In/Out
tab
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Layout/ Layout/
SelectionSelectionSelecting Objects
Selection Tool» No default shortcut key but you can assign
one yourselfSuggestion: » Use the right mouse button for selecting.
ESC will cancel a drawing or editing operation. ESC again switches to the selection tool. <Ctrl+A> selects all<Alt+A> deselects all
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Layout/ Layout/
SelectionSelectionSelecting Objects
Cycling of selections» Continue to click without moving
the mouse – Watch Status Bar –Last select in the cycle is no selection and cycle repeats
Add to Selection<Shift – Right Mouse Button>
» Watch Mouse Button Bar and cursor pictures
Remove from Selection<Alt – Right Mouse Button>
Select Edge - <Ctrl>Add Edge - <Ctrl+Shift>Remove Edge - <Ctrl+Alt>
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Layout/ Layout/
DrawingDrawingDrawing Objects:
Pick tool for drawing object type, Pick layer.» Box
<left mouse drag>» Polygons: Orthogonal / 45 / all-angle
<left click>, <left click>, … ,<right click>» Wires: Orthogonal / 45 / all-angle Wires (width)
<left click>, <left click>, … ,<right click>» Circle, Pie wedge, Torus» Port» Ruler» Instance
tool button or “i” shortcutAlso drag and drop from the Design Navigator
Cursor indicates drawing mode: Selection ModeDrawing Mode
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Layout/ Layout/
PortsPorts“Port” = region + text
The only text construct in L-EditThe region specifies attachment to the drawings.» Rectangle -or- Line -or- Point
Ports are placed on layers» Layer is important
Text is orientedUses:» Comments» Node names» Cell boundaries» I/O Ports/Pins
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Layout/ Layout/
Edit OperationsEdit Operations
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Layout/ Layout/
“Draw” Operations“Draw” Operations
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Layout/ Layout/
EditingEditingEditing Tools:
» Duplicate – Ctrl+D» Rotate 90 degrees - R» Rotate any angles – Ctrl+R» Flip Horizontal - H» Flip Vertical - V» Horizontal Slice – Shift+- “_”» Vertical Slice – Shift+\ “|”» Nibble – Alt+X» Merge» Boolean/Grow Operation - B» Group – Ctrl+G» Ungroup – Ctrl+U» Edit Object – Ctrl+E» Move By - M
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Layout/ Layout/
Alignment ToolbarAlignment ToolbarEditing Tools:
Align uses the MBB of the selected objects
» Align Left» Align Middle» Align Right
MBBSelectedObjects
Left Middle Right
MBB Top
Center
Bottom
SelectedObjects
»Align Top»Align Center»Align Bottom
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Editing Tools:Align uses the MBB of the selected objects
» Distribute Horizontally» Distribute Vertically
Layout/ Layout/
Alignment ToolbarAlignment ToolbarMBB
Horizontal
Vertical
SelectedObjects
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Editing Tools:Align uses the MBB of the selected objects
» Tile Horizontally» Tile Vertically
Layout/ Layout/
Alignment ToolbarAlignment ToolbarSelectedObjects
HorizontalAligns to the bottom left
corner of the leftmost object
VerticalAligns to the bottom
left corner of the bottommost object
Abutment is the MBB of all objects on the icon layer
This is useful for overlapping.
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Editing Tools:Align uses the MBB of the selected objects
» Tile 2-D Array
Layout/ Layout/
Alignment ToolbarAlignment Toolbar
2D Array
SelectedObjects
Sorts objects into rows starting with the bottom leftmost object. If the center of
the object is within the object’s MBB then they are on the same row.
This is useful for odd-even memory arrays and non-simple arrays.
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Layout/ Layout/
Setup OperationsSetup Operations
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Layout/ Layout/
Application SetupApplication Setup
“Application setups” are the settings common to a user for all designs.
“Setup application” is saved in a personal configuration (also workgroup). Toolbar locations & visibility are included.Status bars visibility is included.Recently used file list is included.No “save” is required.
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LL--Edit/Setup/Application/ Edit/Setup/Application/ GeneralGeneral
Non-default values indicated
• Paste to Cursor – When pasting, objects are attached to the cursor and you can move them around and click to place them. When this is off, the objects get pasted to the center of the screen.
• Active-push rubberbanding –All draw & edit operations are two separate clicks (Start click & end click). When this is off, all draw & edit operations are a single click (Start click, hold button down, release button to end).
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LL--Edit/Setup/Application/ Edit/Setup/Application/
Keyboard Keyboard
Don’t forget to press the assign button.
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LL--Edit/Setup/Application/ Edit/Setup/Application/
Mouse Mouse
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LL--Edit/Setup/Application/ Edit/Setup/Application/
Warnings Warnings
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LL--Edit/Setup/Application/ Edit/Setup/Application/
UPI UPI
• Update display – When this is off, the screen is not redrawn when a UPI macro is running. This can make some macros run faster.
• Show warning dialog boxes –When this is off, all dialogs are suppressed when a UPI macro is running. This is useful for batch processing.
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LL--Edit/Setup/Application/ Edit/Setup/Application/
Rendering Rendering • Hide InstanceLarger value Faster Rendering
• Cache InstanceLarger value Faster RenderingOptimal is 250-750
• Hide objectsLarger value Faster RenderingIf you have trouble seeing vias, reduce this value or switch this value off when zoomed in and turn on when zoomed out.
• RedrawActive only Faster Rendering
• Fill / Interrupt / Show designOff Faster RenderingMay not feel faster
• See Improving Rendering Performance Application Note for more details.
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LL--Edit/Setup/Application/ Edit/Setup/Application/
Selection Selection
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Layout/ Layout/
Cell OperationsCell Operations
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Design NavigatorDesign NavigatorEfficiently traverse the design hierarchy
Drag and drop cells into layout from library files, other design files, or current design databaseConveniently access cell operations Lock & unlock cells to protect the design from changes
»Vi
ew T
ype
»C
olla
pse
All
»Ex
pand
All
»N
ew C
ell
»D
elet
e C
ell
»Sa
ve a
s Te
xt»
Show
all
Cel
ls»
Find
Cel
l
Locked
XrefCell
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Design NavigatorDesign NavigatorView Types
Top Down
Bottom Up
Date Modified
DRC Status
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Configuration ManagementConfiguration Management
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Layout / Layout /
Layout Editing Exercise Layout Editing Exercise
Create a NAND gate layoutCreate a PMOS0p96x0p24 cell Create a NMOS0p96x0p24 cell Create a NAND2 cell » Instance two PMOS0p96x0p24 and two NMOS0p96x0p24
Create a AO22 layoutConnect three NAND2 to AO22
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SchematicSchematic--Driven LayoutDriven Layout
Import SPICEHierarchical
Optionally create layout
Devices: T-CellsInstancesFloorplanning
Show flylinesFind nodes/pins
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Layout/ Layout/
Technology SetupTechnology Setup
“Technology setups” are settings which are stored in the design file, and commonly shared with other design files, including:
Technology nameUnits and Grids» internal unit (lambda) micron display unit
Default settingsExternal librariesLayers & PaletteDesign Rules
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LL--Edit/Setup/Design/ Edit/Setup/Design/
TechnologyTechnologyTypical micron-based units Scaleable lambda-based units
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LL--Edit/Setup/Design/ Edit/Setup/Design/
GridGrid
The display units can be set to a variety of units –Microns, Mils, Millimeters, Inches, Centimeters, and Internal Units.
These are in“Micron” units.
Changing display units does not change the database. It is for viewing only
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LL--Edit/Setup/Design/ Edit/Setup/Design/
GridGrid
0.12 um
• Manufacturing grid is used to check for off-grid, snap to grid, and approximating curves.
• Set this value to the smallest resolution of your foundry.
0.03 um
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LL--Edit/Setup/Design/ Edit/Setup/Design/
SelectionSelection• Selection range – during
select operations, only select objects within this range. This is useful when cycling through selections.
• Edit range – Uses the largest of the two values. When the cursor is this close to an object’s edge, the middle mouse button will do an edit operation. Farther than this distance and it will be a move operation.
• Select drawn objects –Leaves objects selected after drawn. This is useful when drawing an object and then moving it into place.
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LL--Edit/Setup/Design/Edit/Setup/Design/DrawingDrawing
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LL--Edit/Setup/Edit/Setup/
PalettePalette
“Windows” style palette “Traditional” style palette
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Layout/Layout/
File OperationsFile Operations
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“.TDB” file
Technology Objects DiagramTechnology Objects Diagram
Other “.TDB”
“.RUL”
“.TTX”
“ledit.ini”application
settings“Ledit.tdb”
“.GDS” GDSII
(Cells)gridlayersdrawing defaultsdesign settingstechnology setupimport/export optionsDRC rules
TTX and RUL will not be
supported in v11.
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LL--Edit Technology PropagationEdit Technology PropagationSelect technology settings from a .tdb to apply to a new file (File New). This can be any .tdbfile regardless if it has layout in it or not. Default technology setup
C:\Tanner\LEdit101\ledit.tdbUsed when L-Edit is started with the executable & no .tdb file.
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LL--Edit Technology PropagationEdit Technology Propagation
File Replace Setup applies complete or partial technology setups to an existing file from a .tdb file (or a .ttx file).
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LL--Edit Technology PropagationEdit Technology Propagation
File Export Setup writes complete or partial technology setups of an existing file to a .ttx file (text file). TTX format does not support all setup parameters.
Recommend to use .tdbfor all technology
propagation and not .ttx.
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Layout /Layout /
Import/Export Mask DataImport/Export Mask DataFile Import Mask Data
File Export Mask Data
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Layout /Layout /
TapeTape--outoutGDS
GDS file can contain all cells from the TDB,or just a specific cell tree.
CIF: Caltech Interchange Format (ASCII)It is generally a good idea to check for off-grid objects, and self-intersecting polygons beforefinal tape-out.
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CrossCross--Section ViewerSection ViewerViewing the 3rd dimension of layout.Used in layout, documentation, parasitics.
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Layout/ Layout/
CrossCross--Section ViewerSection ViewerIntroduction to process technology
The class example technology is 0.25 um CMOS.Use cross-sections to learn the layers & structures
“.XST” Process Definition file3 operations» “gd” = Grow / Deposit (color from layer, no shapes)» “id” = Implant / Diffuse (color & shapes from layer)» “e” = Etch (shapes from layer, no color)
Specify: layer, depth, angle[80], offset (+)[0]“Label” field is optional.
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LL--Edit CrossEdit Cross--Section viewerSection viewer
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Cross Section Rules FileCross Section Rules File# File: Tech4class.real.xst# “Real" version to show correct process order# **************************************************************************************** # L-Edit#Step Layer Name Depth Label [Angle[offset]] Comment#------ ------------------------ ------------- -------- ---------------------- -------------------------------------gd "ChipSubstrate“ 2.50 p- # 1. Substrate = NOT(NotExists)id "Deep N Well" 1.90 n- 85 # 2. Deep N-Well Implantid "P Well" 0.95 p- 85 # 3. P-Well Implant inside Deep N-Wellid "N Well" 0.95 n- 85 # 4. N-Well Implante "Not Active" 0.40 - # 5. Field etch = NOT(Active)gd "Not Active" 0.40 - # 6. Field oxidee "Active" 0.40 - 101 0.05 # 7. Device areasgd - 0.05 - # 8. Thin Gate oxidee "Not Thin Channel“ 0.05 - # 9. Thin Gate oxide etch = NOT(Active ANDNOT Thick_Active)gd "Thick Active" 0.15 - # 10. Thick Gate oxidee "Not Thick Channel" 0.15 - # 11. Thick Gate oxide etch = NOT(Active AND Thick_Active)gd "Poly" 0.18 - # 12. Polysilicon e "NotPoly" 0.18 - 80 0.032 # 13. Poly etch = NOT(Poly)id “pdiff" 0.15 p+ # 14. P+ Implant = (P Select)id "ndiff" 0.15 n+ # 15. N+ Implant = (N Select)gd - 0.32 - # 16. Contact Oxidee "Poly Contact“ 0.32 - 85 # 17. Poly Contact holese "Active Contact" 0.32 - 85 # 18. Active Contact holesgd "Metal1" 0.32 - # 19. Metal1e "Not Metal1" 0.32 - # 20. Metal1 etch = NOT(Metal1)gd - 1.00 - # 21. Metal1 to Metal2 oxidee "Via1" 1.00 - 85 # 22. Via1 holesgd "Metal2" 1.10 - # 23. Metal2e "Not Metal2" 1.10 - # 24. Metal2 etch = NOT(Metal1)
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Layout/ Layout/
Tools OperationsTools Operations
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“UPI”“UPI”User Programmable InterfaceUser Programmable Interface
Purpose: to extend the capabilities of L-Edit
Automate repetitive tasks» User Defined Hot Keys
Add higher level algorithms for construction & verification
» Parameterized Layout Generation» Batch Verification» Advanced Analysis» Library of Macros » Intellectual Property with
password protectionPalettesPop-up dialogsInterpreted (C) or Compiled (C++)
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module Contact_module {#include "ldata.h"#include "lupi_usr.h"
void Contact_Active_Metal1 ( ) {/********************************************************************/
LCell Cell_Now = LCell_GetVisible ( );LFile File_Now = LCell_GetFile ( Cell_Now );LLayer Layer_Active = LLayer_Find ( File_Now, "Active" );LLayer Layer_Metal1 = LLayer_Find ( File_Now, "Metal1" );LLayer Layer_ActCnt = LLayer_Find ( File_Now, "ActiveContact" );LLayer Layer_N_Sel = LLayer_Find ( File_Now, "N Select" );LPoint Point_Cursor = LCursor_GetPosition ( );LCoord X, Y;
/********************************************************************/X = Point_Cursor.x;Y = Point_Cursor.y;LBox_New ( Cell_Now, Layer_ActCnt, -1 + X, -1 + Y, 1 + X, 1 + Y );LBox_New ( Cell_Now, Layer_Metal1, -2 + X, -2 + Y, 2 + X, 2 + Y );LBox_New ( Cell_Now, Layer_Active, -3 + X, -3 + Y, 3 + X, 3 + Y );LBox_New ( Cell_Now, Layer_N_Sel , -5 + X, -5 + Y, 5 + X, 5 + Y );
}
void cnt_main ( void ) {/********************************************************************/
LMacro_BindToHotKey ( KEY_F1,"Contact, Active-Metal1", "Contact_Active_Metal1" );
}
/********************************************************************/}cnt_main ( );
UPI macroexample
C:\Tanner\LEdit101\Samples\UPI\intrpted\contact\contact.c
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UPI menu: Tools / Macro
It should only show Place via
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TT--CellsCells
ConceptLayout generation macros that are specific to a design and process.Encapsulated in the TDB file (goes with the file for interpreted T-Cells)When creating a cell in L-Edit, you can make a geometry cell (cellcell) or parameterized cell with code (TT--cell)cell)
T-Cell ParametersType - Boolean, Integer, Float, String, LayerDefault Value – When generating a newT-Cell, parameter is initialized to this value
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TT--CellsCells
TerminologyCell – a traditional cell with layout objectsT-Cell – a cell with layout generation code. The code is executed when a T-Cell is instanced and the resulting cell is what is instanced in the cellAuto-generated cell – A generated version of a T-Cell with specific values for each parameter (Normally hidden)
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Using TUsing T--CellsCells
W = 0.36L = 0.36
.
.box(0,0,L,W)..
Parameter Definition
Generator Code
T-Cell: Box
Auto-Generated Cell: Box_Auto_2_1
Auto-Generated Cell: Box_Auto_0.36_0.36
Geometry Cell: Cell1
W = 0.36L = 0.36
Parameter ValuesInstance
W = 2.00L = 1.00
Parameter ValuesInstance
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DevDev--GenGen
Introduction to Introduction to Tanner Tools ProTanner Tools ProTMTM
Express TrainingExpress TrainingVolume 3Volume 3
Layout Verification & SPRLayout Verification & SPR
Software Solutions
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LayersLayers
“Drawn” layersTypically correspond to mask layers (plus a few annotation layers)
“Derived” or “Generated” layersObjects on these layers are automatically created from other objects on other layers
“Special” layersUsed to specify rendering for required L-Edit elements
Layers are used to control rendering
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Special LayersSpecial Layers
First mask layer controls the upper-left corner of the layer paletteError layer is used to create error ports from DRC and SPRCell Outline layer is used to render the outline of cells when Hide Cell Insides is on (also see Icon layer below)Icon layer is used (i) to render cells when Hide Cell Insides and View>Display>Icon is on (if objects are present on the Icon layer), (ii) for abutment boxes in SPR and L-Comp. This is useful for floor planning when cells have to overlap
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LL--Edit/Setup/Layers/ Edit/Setup/Layers/
General General
Create and order layersAssign electrical (and other) properties
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LL--Edit/Setup/Layers/ Edit/Setup/Layers/
RenderingRendering
• Paint – Overwrite• Add – OR of color indices• Subtract – Color index AND NOT this color’s index
Add
Subtract
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LL--Edit/Setup/Layers/ Edit/Setup/Layers/
DerivationDerivation
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Derived Layers: BooleanDerived Layers: BooleanAll derived layers (boolean, select, area, density) are calculated on layers after they have been merged.
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Derived Layers: BooleanDerived Layers: Boolean
Order of Operations
1. Grow
2. NOT
3. AND, OR (in order)
B
A
A AND B
A OR B
NOT A
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Derived Layers: Area SelectionDerived Layers: Area Selection
Example of use: find all contact cuts that are not 0.24 x 0.36 um2
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Derived Layers: SelectDerived Layers: Select
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Select: InsideSelect: Inside
Inside:Totally contained NOT Inside
NOT Inside == Outside OR CutMetal1
Poly
Poly INSIDE Metal1
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Poly OUTSIDE Metal1
Select: OutsideSelect: OutsideOutside:
Mutually exclusive NOT Outside
NOT Outside == Inside OR Cut
Metal1
Poly
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Select: HoleSelect: Hole
Select Poly polygons which exactly fill interior holes in Metal1polygons.
NOT Hole: Select polygons which do NOT exactly fill interior holes
Poly HOLE Metal1
Metal1
Poly
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Select: CutSelect: Cut
Cut: Poly polygon has non-zero area BOTH inside and outside Metal1 polygon
NOT Cut: Poly polygon either inside or outside Metal1 polygon
Poly CUT Metal1
Metal1
Poly
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Select: TouchSelect: TouchTouch: Poly polygon shares an edge with Metal1, and is outside Metal1
NOT Touch
Poly TOUCH Metal1
Metal1
Poly
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Select: EncloseSelect: EncloseEnclose: Poly polygon that completely encloses Metal1 NOT Enclose
Poly ENCLOSE Metal1
Metal1
Poly
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Select: OverlapSelect: OverlapOverlap: Poly polygon that cuts, touches, encloses or is inside Metal1
NOT Overlap: Polypolygon that is entirely outside Metal1 (does
not share edge)
Poly OVERLAP Metal1
Metal1
Poly
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Select: VertexSelect: VertexVertex: Poly polygons that have a specific number of vertices. Useful for checking non-rectangular contacts or gates.
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Select SpeedsSelect SpeedsFastest to Slowest Select Operations
NOT OUTSIDE (OUTSIDE)INTERACT (NOT INTERACT)CUT (NOT CUT)ENCLOSE (NOT ENCLOSE)OVERLAP (NOT OVERLAP)INSIDE (NOT INSIDE)TOUCH (NOT TOUCH)HOLEVERTEX
Slower SELECTS will not be more than 2x slower than the fastest.
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Select: DensitySelect: DensityDensity: Sum of the area of Metal1 divided by the area of the cell extent. Layer is merged before calculating area.
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Select: DensitySelect: DensityDensity: Sum of the all via3 polygons inside of a Pad polygon divided by the area of that polygon.
Sum of the area of these polygons
divided by the area of this polygonpolygon
divided by the area of this polygonpolygon
Sum of the area of these polygons
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Generate LayersGenerate Layers
Automatically mark intermediate layers marks a layer and all derived layers that it depends on.Layers are in alphabetically order.Clear all generated layers first deletes all geometry on derived layers that are marked to be generated (removes old results).
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Integrated Full Chip & Region CheckHierarchical DRCSupports All-angle DRCSimple Location and Repair of ErrorsSupports Complex Ruleswith Boolean OperationsConfigurable for Multiple Foundry Support
“DRC” Design Rule Checker“DRC” Design Rule Checker
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Design Rule Check SpeedupDesign Rule Check Speedup
Guidelines for faster DRCHave enough memory (no swapping).Hierarchical designs.Reduce complexity of derivations.Fix errors at the lowest level.
Hierarchical DRCHuge speedups possible.Encourages hierarchical design.Errors reported where they occur.Best practice: Clean, non-overlapping cell design.» Do not create devices in cell overlaps. Minimize inter-layer
connections that require looking at multiple cells. These will still work, but you will suffer a performance penalty.
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Layout / Layout /
Design Rule Check ProceduresDesign Rule Check ProceduresDRC SetupRun DRCFind Errors using DRC Error NavigatorRepair Errors (in the lowest hierarchy) Hidden Layers are not checked.
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DRC Error NavigatorDRC Error Navigator
Browse and Display DRC errors
Simplifies iterations of the DRC error correction
View DRC errors in top-level or cell context
DRC Error Navigator
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DRC Error NavigatorDRC Error NavigatorDRC Error Navigator (DEN)
» Toggle Error Mark» Next DRC Error – . (period)» Previous DRC Error - , (comma)» DEN Options» View All Rules» View By Rule/Cell» Cell/Top Level Context» DEN Menu» Delete DRC Error» Number of DRC Errors
including hidden errors» DRC Job» Back» Forward
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DRC Error NavigatorDRC Error Navigator
Hint: map F1 to show/hide DRC Error Navigator (Browse DRC) & F2 to show/hide DRC Error marker (Toggle Mark)
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DRC SetupDRC Setup
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Minimum/Exact WidthMinimum/Exact Width
Poly minimum width = 0.24 µm
Exact width = 0.36 µm
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SpacingSpacingLayer 1 (dark) to Layer 2 (light) spacing
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SurroundSurroundLayer 2 (light) surrounds Layer 1 (dark)
This is the distance that is checked –Outside Edge to Inside Edge
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ExtensionExtensionLayer 2 (dark) extend beyond Layer 1 (light)
Typically used to confirm gate and channel extensions to make valid self-aligned FETs
This is the distance that is checked –Inside Edge to Outside Edge
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OverlapOverlapLayer 2 (dark) overlap into Layer 1 (light)
This is the distance that is checked –Inside Edge to Inside Edge
.i.e. N-Select overlap Active
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Geometry FlagsGeometry Flags
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V11 Foundry Compatible DRC V11 Foundry Compatible DRC
Calibre™rule decksDRACULA™rule decksSyntax checking editorRule browser
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LL--Edit ExtractEdit ExtractCreates a SPICE Netlist
from the Layout.for LVSfor post-layout simulation
Extracts: Connectivity of LayoutActive DevicesPassive DevicesDevice Area & PerimeterFringe & Area Parasitic CapacitanceSubcircuit
Process ConfigurableLabels Devices
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Extract Definition FileExtract Definition File... connect(Metal1, Metal2, Via1)connect(Metal2, Metal3, Via2)connect(Metal3, Metal4, Via3)connect(Metal4, Metal4 - Pad, Metal4)connect(LPNP Emitter, pdiff, LPNP Emitter)connect(LPNP Collector, pdiff, LPNP Collector)
# NMOS transistor with poly gatedevice = MOSFET(
RLAYER=ntran; Drain=ndiff, AREA, PERIMETER;Gate=poly wire; Source=ndiff, AREA, PERIMETER;Bulk=Substrate;MODEL=NMOS;)
...
Connection StatementsLayer 1 Layer 2Connection layer
Devices DefinitionsDevice typeDevice recognition layer“rlayer”Pin layerDevice model
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Extract Run OptionsExtract Run Options
Declare devices for LVSor commands for T-Spice
Parasitic extraction
C:\Tanner\MyChips\class\tech\Tech4class.ext
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Extract Output NetlistExtract Output Netlist
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Extract: Naming nodes and Extract: Naming nodes and elementselements
Use ports to assign namesPort box has to be over the appropriate layer » Recognition layer for devices» Electrical layer for nodes – Can be on a layer
used to derive a connect or pin layerAlternately, L-Edit can automatically label devices
Slow, memory intensive but permanentOr, use Tools>Goto Device to locate dynamically named devices. Requires coordinates to be written to the SPICE file.
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Layout/Extract/ Layout/Extract/
Devices and ParametersDevices and ParametersCapacitor
Capacitance (area + fringe)Resistor
Resistance (including odd shapes)Inductors
Inductance (user calculated)BJT
ModelArea (rlayer area | pin area) Area = layout area / nominal area
DiodeModelArea (rlayer area | pin area) Area = layout area / nominal area
MESFETModelArea (rlayer area | pin area) Area = layout area / nominal areaLength and width
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Layout/Extract/ Layout/Extract/
Devices and ParametersDevices and ParametersMOSFET
ModelLength and width (including odd gate shapes)source/drain area/perimeterFraction of gate width to include in perimeter (Gate)GEO
» 1 – drain and source area are not shared» 2 – drain is shared » 3 – source is shared» 4 – both drain and source are shared
JFETModelArea (rlayer area | pin area) Area = layout area / nominal area
Non-Standard and Compound devices – Subcirciut Extraction
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LL--Edit ExtractorEdit ExtractorDevices are located by finding polygons on “recognition layers”Pins are polygons on user-specified layers that overlap or touch the recognition polygon
# NMOS transistor with poly gatedevice = MOSFET(
RLAYER=ntran; Drain=ndiff, AREA, PERIMETER;Gate=poly wire; Source=ndiff, AREA, PERIMETER;Bulk=Substrate;MODEL=NMOS;)
+ +
Drawnlayout
ntran poly wirendiff
ntran = N-Channel AND NOT Capacitor IDN-Channel = Gate AND NOT N Well AND N SelectGate = Poly AND Active
ndiff = diff AND N Selectdiff = field active AND NOT Resistor IDfield active = Active AND NOT Poly
poly wire = Poly AND NOT Resistor ID
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Extract: MOSFETsExtract: MOSFETs
DEVICE=MOSFET (RLAYER = rLayer ;Drain = dLayer {[, AREA] [, PERIMETER [/GATE=#]] | [,GEO]};Gate = gLayer ;Source = sLayer [, AREA] [, PERIMETER [/GATE=#]];[Bulk = [bLayer ];]MODEL = model ;
) [IGNORE_SHORTS]
Mname drn gat src [blk] model L=lengthValue W=widthValue
{[AD=areaValue] [PD=perimeterValue] [AS=areaValue] [PS=perimeterValue] | [GEO=#]}
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Extract: ResistorsExtract: Resistors
DEVICE=RES (RLAYER = rLayer [, LW];Plus = Layer1 ;Minus = Layer2 ;MODEL = [ModelName ];
) [IGNORE_SHORTS]
Rxxx n1 n2 [ModelName] [R=]rValue
LW keyword:
Rxxx n1 n2 [ModelName] L=rLength W=rWidth
rWidth = average length of pin edges shared with RLAYER rLength = RLAYER area / rWidthrValue = rho * rLength / rWidth
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Extract: SubcircuitsExtract: SubcircuitsDEVICE=SUBCKT (
RLAYER = rLayer [, AREA] [, PERIMETER] [, LW];pin1Name = pin1Layer [, AREA] [, PERIMETER] [, WIDTH] [, DEVICEWIDTH];pin2Name = pin2Layer [, AREA] [, PERIMETER] [, WIDTH] [, DEVICEWIDTH];. . .MODEL = model ;[NominalArea = areaVal ;]
) [IGNORE_SHORTS]
Xzzz n1 [n2 ...] cName
[AREA=rLayerArea/areaVal]
[PERI=rLayerPerimeter/areaVal]
[L=cLength W=cWidth]
[AREA_pin1Name=pin1Area/areaVal]
[PERI_pin1Name=pin1Perimeter]
[WIDTH_pin1Name=pin1Width]
[AREA_pin2Name=pin2Area/areaVal]
[PERI_pin2Name=pin2Perimeter]
[WIDTH_pin2Name=pin2Width] ...
DEVICEWIDTH ModifierWIDTH = Average of pin widths that have DEVICEWIDTHLENGTH = AREA/WIDTH
# IC Poly Resistordevice = SUBCKT(
RLAYER=PolyResistor, LW;Plus=PolyWire, DEVICEWIDTH;Minus=PolyWire, DEVICEWIDTH;Bulk=Substrate;MODEL=ICResPoly;
)
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Extract: ConnectionsExtract: Connections
Connections between layers explicitConnect( A, B, C )Connects polygons on layer A and layer B, where (A AND C) overlaps or touches B
The result is a single electrical node
connect(pdiff, Metal1, Active Contact)
connect(n well wire, ndiff, ndiff)
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Extract: ParasiticsExtract: Parasitics
If enabled, nodal capacitances (to ground) are calculated and outputBe careful not to “double count”Does not calculate crosstalk parasitics
Use devices to extract these parasitics
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“LVS” Layout“LVS” Layout--vsvs--SchematicSchematic
Compares NetlistsReads common SPICE format, flat or hierarchical netlists .Compares parameters with user-specified tolerance.Collapsing of Devices» series/parallel R, C, MOSFETS
We want to know if the correct number, type and size of elements in the layout are connected together exactly as they are in the schematicof course, any two netlists can be compared
Single or Batch Mode Verification
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LVS Objects DiagramLVS Objects Diagram
LVS compare
“.LVS” (“.OUT”)
results
“.LIS”device & net
correspondence
“.SP” schematic netlist
S-Edit“.SPC” layout netlist
L-Edit Extract
“.PRE”device & net
prematch
“.VDB”LVS setup
Modeldeclarations
Modeldeclarations
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LVS Window Regions LVS Window Regions -- InputInput
Setup Window
Status Bar
Menu bar
Toolbar
Non-default values
indicated
Run LVS
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LVS / OutputLVS / Output
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LVS / Device ParametersLVS / Device Parameters
Consider L & W
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LVS OptimizationsLVS Optimizations
Polarized componentsMOSFETS (Drain/Source are indistinguishable)Resistors (usually unpolarized)Capacitors (sometimes unpolarized)
Parallel componentsMOSFETS, Rs, Cs (usually OK)
Series componentsMOSFETS (maybe OK), Rs, Cs (usually OK)
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LVS / Merge DevicesLVS / Merge DevicesCaution:
Choices of LVS options
are very important.
Merging by Model Syntax:type_name1, type_name2
type = device abbreviation
nameX = Model name
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LVS / ParasiticsLVS / Parasitics
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LVS / OptionsLVS / Options
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LVS / PerformanceLVS / Performance
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LVS ResultsLVS Results
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Interpreting LVS ResultsInterpreting LVS Results
If LVS reports “circuits are equal”, they are!If LVS reports “circuits are not equal”, then there is a real error between the netlists. Fragmented classes.If LVS reports “circuits are only topologically equal”, then there are parametric errors.
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“SPR” “SPR” Standard Cell Place and RouteStandard Cell Place and Route
The Purpose of SPR80% solution for 10% priceLow cost applications
EDIF inputPlacement optimizer for minimal wire lengthsCell clustering for placementCompact 3 layer channel routing with over-the-cell routeGlobal signal routingCritical net assignmentPadframe generator, pad router
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Layout / Standard cell Place & Route / Layout / Standard cell Place & Route /
SPR SPR OperationsOperationsDesign flow steps:1) Core Place&Route2) Padframe placement3) Pad routing
Core only for “macro functions”Placement optimization parameterPad location control
Core, Padframe, and Pad Route menusWire capacitance outputSDF timing output
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Schematic Preparation for SPRSchematic Preparation for SPR
Add PadOut to input/output portsAdd PadVdd
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“NAND2” Layout “NAND2” Layout ––Draw “Metal2” Layer Signal PortsDraw “Metal2” Layer Signal Ports
Ports”A”,”B”,”Out” on Metal2H=0, W=0.36 umPurpose: show SPR where to connect signal wires.
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“AO22” Core Layout “AO22” Core Layout -- shows library cells fitting shows library cells fitting togethertogether
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“AO22” “AO22” -- Completed SPR LayoutCompleted SPR Layout
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Layout / Layout /
PlotPlot
L-Edit Plot(an optional module)
independent colors & fillsbetter resolutionlegendsscalestitlesmemory
management
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Beyond TrainingBeyond Training
Physical Design of CMOS Integrated Circuits Using L–EditTM
by John P. Uyemura - ISBN 0-534-94326-8The Art of Analog Layout by Alan Hastings –ISBN 0-13-087061-7IC Layout Basics by Christopher Saint/Judy Saint –ISBN 0-07-138625-4IC Mask Design by Christopher Saint/Judy Saint –ISBN 0-07-138996-2CMOS IC Layout by Dan Clein - ISBN 0-750-67194-7Design of Analog CMOS Integrated Circuitsby Behzad Razavi - ISBN 0-07-238032-2Absolute Beginner's Guide to C by Greg Perry –ISBN 0-672-30510-0
Tanner Customer Support877-304-5544 (Toll Free)
(626) 685-5969 (International)support@tanner.com
Tanner CES(Consulting & Engineering Services)
(626) 792-3000
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Layout / Layout /
GlossaryGlossary.SDB – S-Edit Database file..TPR – Tanner Place and Route file, a proprietary format for use by L-Edit..EDN – EDIF (Electronic Design Interchange Format) file use by L-Edit for place and route..EDS – EDIF schematic file used for porting schematics to other software..SP – Default extension for SPICE netlists generated by S-Edit..SPC – Default extension for SPICE netlists generated by L-Edit..TDB – Tanner Database is an L-Edit’s database file.SPR – Standard Place and Route.DRC – Design Rule Checker.LVS – Layout vs. Schematic.UPI – User Programmable Interface (Macros)..GDS or GDSII – Standard file format for transferring/archiving 2D graphical design data..CIF – Caltech Intermediate FormatT-Cell – Parameterized cell..EXT – L-Edit’s extraction definition file,.XST – Cross-section definition file for use with L-Edit’s Cross-section Viewer..TTX – Tanner Text Format File – contain L-Edit’s technology information in text format..SDF – Standard Delay Format file – Generated by SPR which contains pin-to-pin delay information..LIB - Synopsys® Liberty file that contains pin characteristics for standard cells. SPR uses this information to generate SDF file.Xref – External reference cell.LMB – Left mouse button.MMB – Middle mouse button or Minimum Bounding Box.RMB – Right mouse button.
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