cmos beyond si: nanometer-scale iii-v mosfets slides.pdfintel microprocessors. intel...

CMOS beyond Si:Nanometer-Scale III-V MOSFETs

J. A. del Alamo, X. Cai, J. Lin, W. Lu, A. Vardi, and X. ZhaoMicrosystems Technology Laboratories

Massachusetts Institute of Technology

IEEE Bipolar/BiCMOS Circuits and Technology MeetingMiami, FL, October 19-21, 2017

Acknowledgements:• Students and collaborators: D. Antoniadis, E. Fitzgerald• Sponsors: Applied Materials, DTRA, KIST, Lam Research, Northrop Grumman,

NSF, Samsung, SRC• Labs at MIT: MTL, EBL

Moore’s Law at 50: the end in sight?

2

3

Moore’s Law

4

?

How far can Si support Moore’s Law?

The problem: Transistor scaling Voltage scaling Performance suffers

5

Transistor current density:

What can we do about this?

Intel microprocessorsIntel microprocessors

Supply voltage:

6

Moore’s Law: it’s all about MOSFET scaling

1. New device structures with improved scalability:

2. New materials with improved transport characteristics:

n-channel: Si Strained Si SiGe InGaAsp-channel: Si Strained Si SiGe Ge InGaSb

Planar bulk MOSFET Thin-body SOI MOSFET

Nanowire MOSFETFinFET

7

III-V electronics in your pocket!

8

Historical evolution: InGaAs High-Electron Mobility Transistor

Transconductance (gm=dID/dVGS):

9

InGaAs MOSFETs vs. HEMTs

*

*inversion-mode

Transconductance (gm=dID/dVGS):

10

InGaAs MOSFETs vs. HEMTs

Lin, EDL 2016

What happened here?

*

*inversion-mode gm=3.45 mS/μm

Transconductance (gm=dID/dVGS):

11

Huang, APL 2005

ALD eliminates residual native oxides that pin Fermi level “Self cleaning”

Clean, smooth interface without native oxides

Atomic Layer Deposition (ALD)of gate oxide

• First with Al2O3, then with other high-K dielectrics• First in GaAs, then in other III-Vs

n-MOSFETs in Intel’s nodes at nominal voltage

Planar Si and InGaAs MOSFET Benchmark

12

Comparisons always fraught with danger…

Transconductance exceeds Si MOSFETs

InGaAs FinFETs

13

FinFETs

Bottom-up InGaAs FinFETs

14

Si

Waldron, VLSI Tech 2014

Aspect-Ratio TrappingFiorenza, ECST 2010

Epi-grownfin insidetrench

Sun, VLSI Tech 2017

InGaAs FinFETs @ MIT

15

Vardi, DRC 2014, EDL 2015, IEDM 2015

Key enabling technologies: BCl3/SiCl4/Ar RIE + digital etch

• Sub-10 nm fin width• Aspect ratio > 20• Vertical sidewalls

InGaAs FinFETs @ MIT

16

Vardi, VLSI Tech 2016

• Si-compatible process• Contact-first, gate-last process• Fin etch mask left in place double-gate MOSFET

Vardi, EDL 2016

InAlAs

InGaAs

n+-InGaAs

W/Mo Lg

SiO2

HSQHigh-K

InP

δ - Si

InP

Mo Mo

HSQ

High-K

InGaAs

17

Most aggressively scaled FinFETWf=7 nm, Lg=30 nm, Hc=40 nm (AR=5.7), EOT=0.6 nm:

Vardi, EDL 2016

At VDS=0.5 V:• gm=900 µS/µm• Ron=320 Ω.µm• Ssat=100 mV/dec -0.4 -0.2 0.0 0.2 0.4

0

200

400

600

800

1000

VDS=0.5 V

gm max=900 µS/µm

g m [µ

S/µm

]

VGS [V]

-0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.41E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

VDS=50 mVDIBL=90 mV/V

I d [A/

µm]

VGS [V]

Ssat=100 mV/dev

VDS=500 mV

0.0 0.1 0.2 0.3 0.4 0.50

100

200

300

400

500

I d [µA

/µm

]

VDS [V]

VGS=-0.5 to 0.75∆VGS=0.25 V

Current normalized by 2xHc

18

0 100 200 300 400 500 600 7000

50

100

150

200

250 A: Al2O3, EOT=2.8 nm B:Al2O3/HfO2, EOT=1 nm C: HfO2, EOT=0.6 nm

S sat [

mV/

dec]

Lg [nm]

EOT↓60 mV/dec

0 100 200 300 400 500 600 700

0

200

400

600

800

1000

1200

1400

1600

EOT↓

VDS=0.5 VWf=20-22 nm

g m [µ

S/µm

]

Lg [nm]

Classical scaling with Lg and EOT

Lg and EOT scaling (Wf~20 nm)

Vardi, EDL 2016

100 10000

50

100

150

Wf=7 nm Wf=12 nm Wf=17 nm Wf=22 nm

S sat,m

in [m

V/de

c]Lg [nm]

60 mV/dec

Fin-width scaling (EOT=0.6 nm)

19

• Non-ideal fin width scaling• Sources:

• High Dit (~5x1012 cm-2.eV-1)?• mobility degradation? • line edge roughness?

Contaminated bygate leakage

0 100 200 300 400 500 600

0

200

400

600

800

1000

1200

1400

1600

7

∆Wf= 5 nm

g m m

ax [µ

S/µm

]

Lg [nm]

Wf=22 nm

Vardi, EDL 2016

0 20 40 600

5

10

15

20

0.452.2

0.321

1.8

0.570.8

5.73.3

2.3

1.8InGaAs FinFETs

5.3

4.3

IntelSi FinFETs (VDD=0.8 V)

g m/W

f [m

S/µm

]

Wf [nm]

0.630.6

0.230.66 1 0.18

InGaAs FinFET benchmarking

20

gm normalizedby fin width

• First InGaAs FinFETs with Wf<10 nm• Doubled gm over earlier InGaAs FinFETs• Short of Si FinFETs sidewall quality?

Our work (VDS=0.5 V)Wf

Target

channelaspect ratio

See latest at IEDM 2017!

21

InGaAs Vertical Nanowire MOSFETs

VNW MOSFET

22

Vertical nanowire MOSFET: ultimate scalable transistor

Vertical NW MOSFET: uncouples footprint scaling from Lg, Lspacer, and Lc scaling

Lc

Lg

Lspacer

Key enabling technologies:• RIE = BCl3/SiCl4/Ar chemistry• Digital Etch (DE) = self-limiting O2 plasma oxidation + H2SO4 or HCl oxide removal

23

• Radial etch rate=1 nm/cycle• Sub-20 nm NW diameter• Aspect ratio > 10• Smooth sidewalls

RIE + 5 cycles DE

Zhao, IEDM 2013Zhao, EDL 2014Zhao, IEDM 2014

InGaAs Vertical Nanowires @ MIT

24

InGaAs VNW-MOSFETsby top-down approach @ MIT

Top-down approach: flexible and manufacturable

n+ InGaAs, 70 nm

i InGaAs, 80 nm

n+ InGaAs, 300 nm

Starting heterostructure:

n+: 6×1019 cm-3 Si doping

VNW-MOSFET I-V characteristics: D=40 nm

25

Single nanowire MOSFET: • Lch= 80 nm• 3 nm Al2O3 (EOT = 1.5 nm)

-0.2 0.0 0.2 0.4 0.610-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3 Vds=0.5 V

Vgs(V)

I s (A

/µm

) Vds=0.05 V

0.0 0.1 0.2 0.3 0.4 0.50

50

100

150

200

250

300 Vgs=-0.2 V to 0.7 V in 0.1 V step

Vds (V)

I s (µ

A/µm

)

-0.2 0.0 0.2 0.4 0.60

100200300400500600700800

Vgs(V)

g m (µ

S/µm

)

Vd= 0.5 V

gm,pk=720 μS/μm

Slin = 70 mV/decSsat = 80 mV/decDIBL = 88 mV/V

Zhao, CSW 2017

Benchmark with Si/Ge VNW MOSFETs

26

• InGaAs competitive with Si• Need to demonstrate VNW MOSFETs with D<10 nm

0 20 40 60 80 1000

200

400

600

800

1000

1200

1400

1V1 V

1

1 V

1.2 V

1.2 Vg m,p

k (µS

/µm

)

Si/Ge InGaAs

Diameter (nm)

Peak gm of InGaAs (VDS=0.5 V), Si and Ge VNW MOSFETs

Target

Our work (VDS=0.5 V)

InGaAs VNW Mechanical Stability for D<10 nm

27

Yield = 0%

Broken NW

Difficult to reach 10 nm VNW diameter due to breakage

8 nm InGaAs VNWs after 7 DE cycles:

InGaAs VNW Mechanical Stability for D<10 nm

28

Yield = 0%

Broken NW

Difficult to reach 10 nm VNW diameter due to breakage

Water-based acid is problem:

Surface tension (mN/m):• Water: 72 • Methanol: 22 • IPA: 23

Solution: alcohol-based digital etch

Alcohol-Based Digital Etch

29

10% HCl in IPAYield = 97%

10% HCl in DI waterYield = 0%

Alcohol-based DE enables D < 10 nm

Broken NW

Radial etch rate: 1.0 nm/cycle Radial etch rate: 1.0 nm/cycle

8 nm InGaAs VNWs after 7 DE cycles: Lu, EDL 2017

D=5.5 nm VNW arrays

30

90% yield10% H2SO4 in methanol

• H2SO4:methanol yields 90% at D=5.5 nm!• Viscosity matters: methanol (0.54 cP) vs. IPA (2.0 cP)

InGaAs Digital Etch

31

First demonstration of D=5 nm diameter InGaAs VNW (Aspect Ratio > 40)

32

0.0 0.1 0.2 0.3 0.4 0.50

50

100

150

200 Vgs= 0 V to 0.6 V in 0.1 V stepRon= 5500 Ω⋅µmMo contactD = 15 nm300 oC N2 RTA

Vds (V)

I d (µ

A/µm

)Latest! D=15 nm InGaAs VNW MOSFET

Single nanowire MOSFET: • Lch= 80 nm• 2.5 nm Al2O3 (EOT = 1.3 nm)

Zhao, IEDM 2017

Benchmark with Si/Ge VNW MOSFETs

33

Most aggressively scaled VNW MOSFET ever

Peak gm of InGaAs (VDS=0.5 V), Si and Ge VNW MOSFETs

Target

Our latest work (VDS=0.5 V)

Even better results at IEDM 2017!

InGaAs Vertical Nanowires on Si by direct growth

34

Selective-Area Epitaxy (SAE)

Au seed

Vapor-Solid-Liquid (VLS) Technique

InAs NWs on Si by SAE

Riel, MRS Bull 2014

Riel, IEDM 2012

VNW MOSFETs: path for III-V integration on Si for future CMOS

35

Vertical nanowire MOSFET for 5 nm node

Yakimets, TED 2015Bao, ESSDERC 2014

Vertical NW: power, performance and area gains w.r.t. Lateral NW or FinFET

5 nm node

30% area reduction in 6T-SRAM19% area reduction in 32 bit multiplier

Conclusions1. Great recent progress on planar, fin and nanowire

InGaAs MOSFETs

2. Device performance still lacking for 3D architecture designs

3. III-V Vertical-Nanowire MOSFETs: most likely architecture for future integration with Si

4. Many, MANY issues to work out:

sub-10 nm fin/nanowire fabrication, self-aligned contacts,

device asymmetry, introduction of mechanical stress, VT control, sidewall roughness, device variability, BTBT and parasitic HBT gain, oxidetrapping, self-heating, reliability, NW survivability, co-integration on n- and p-channel devices on Si, interface states, metal routing, contact resistance < 10-9 Ω.cm-2, off-state leakage, TDDB, etc.…

36