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Chapter 2 -Introduction of IC Fabrication
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Objectives
•Define yield and explain its importance•Describe the basic structure of a cleanroom.•Explain the importance of cleanroom protocols•List four basic operations of IC processing•Name at least six process bays in an IC fab•Explain the purposes of chip packaging•Describe the standard wire bonding and flip-chip
bump bonding processes
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Wafer Process Flow
Materials
Design
Masks
IC Fab
Test
Packaging
Final Test
ThermalProcesses
Photo-lithography
EtchPR strip
ImplantPR strip
Metallization CMP Dielectricdeposition
Wafers
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Fab Cost
•Fab cost is very high, > $1B for 8”fab•Clean room•Equipment, usually > $1M per tool•Materials, high purity, ultra high purity•Facilities•People, training and pay
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Wafer Yield
total
goodW Wafers
WafersY
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Die Yield
total
goodD Dies
DiesY
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Packaging Yield
total
goodC Chips
ChipsY
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Overall Yield
YT = YWYDYC
Overall Yield determines whether a fab ismaking profit or losing money
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How Does Fab Make (Loss)Money
•Cost:–Wafer (8”): ~$150/wafer*–Processing: ~$1200 ($2/wafer/step, 600 steps)–Packing: ~$5/chip
•Sale:–~200 chips/wafer–~$50/chip (low-end microprocessor in 2000)
*Cost of wafer, chips per wafer, and price of chip varies, numbers here are choosingrandomly based on general information.
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How Does a Fab Make (Loss) Money
•100% yield: 150+1200+1000 = $2350/wafer•50% yield: 150+1200+500 = $1850/wafer•0% yield: 150+1200 = $1350/wafer
•100% yield: 20050 = $10,000/wafer•50% yield: 10050 = $5,000/wafer•0% yield: 050 = $0.00/wafer
•100% yield: 10000 2350 = $7650/wafer•50% yield : 5000 1850 = $3150/wafer•0% yield : 0 1350 = $1350/wafer
Cost:
Sale:
ProfitMargin:
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Question
•If yield for every process step is 99%, whatis the overall processing yield after 600process steps?
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Answer
•It equals to 99% times 99% 600 times
•0.99600 = 0.0024 = 0.24%
•Almost no yield
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Throughput
•Number of wafers able to process–Fab: wafers/month (typically 10,000)–Tool: wafers/hour (typically 60)
•At high yield, high throughput brought
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Defects and Yield
nDAY
)1(1
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Yield and Die Size
Y = 28/32 = 87.5% Y = 2/6 = 33.3%
Killer Defects
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Illustration of a ProductionWafer
Test die
Die
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Illustration of a ProductionWafer
Scribe Lines
Dies
TestStructures
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Clean Room
•Artificial environment with low particlecounts
•Started in medical application for post-surgery infection prevention
•Particles kills yield
•IC fabrication must in a clean room
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Clean Room
•First used for surgery room to avoidbacteria contamination
•Adopted in semiconductor industry in1950
•Smaller device needs higher grade cleanroom
•Less particle, more expensive to build
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Clean Room Class
•Class 10 is defined as less than 10particles with diameter larger than 0.5m per cubic foot.
•Class 1 is defined as less than 1 suchparticles per cubic foot.
•0.18 mm device require higher thanClass 1 grade clean room.
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Cleanroom Classes
0.1
1
10
100
1000
10000
100000
Class 100,000Class 10,000Class 1,000
Class 100
Class 10Class 1
#of
part
icle
s/f
t3
0.1 1.0 10Particle size in micron
Class M-1
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Definition of Airborne ParticulateCleanliness Class per Fed. Std.
209EClass
Particles/ft3
0.1 m 0.2 m 0.3 m 0.5 m 5 m
M-1 9.8 2.12 0.865 0.28
1 35 7.5 3 1
10 350 75 30 10
100 750 300 100
1000 1000 7
10000 10000 70
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Effect of Particles on Masks
Particleson Mask
Stumpon +PR
Hole onPR
Film Film
Substrate Substrate
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Effect of Particle Contamination
Partially Implanted Junctions
Particle
Ion Beam
Photoresist
Screen Oxide
Dopant in PR
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Cleanroom Structure
Process Area
Equipment AreaClass 1000
Equipment AreaClass 1000
Raised Floorwith Grid Panels
Return Air
HEPA Filter
Fans
Pump, RFand etc.
ProcessTool
ProcessTool
Makeup Air Makeup Air
Class 1
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Mini-environment
•Class 1000 cleanroom, lower cost•Boardroom arrangement, no walls
between process and equipment•Better than class 1 environment around
wafers and the process tools•Automatic wafer transfer between process
tools
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Mini-Environment Cleanroom
Class 1000
Class 1000
Raised Floorwith Grid Panels
Return Air
HEPA Filter
Fans
Pump, RFand etc.
ProcessTool
Makeup Air Makeup Air
ProcessTool
HEPA Filter
< Class 1
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Gowning AreaGown Racks
Benches
Shelf of Gloves, Hairand Shoe Covers Disposal Bins
Wash/CleanStations
Storage
Shelf ofGloves
Shelf ofGloves
Entrance
ToCleanroom
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IC Fabrication Process Module
Photolithography
Thin film growth,dep. and/or CMP
Etching
PR Stripping PR Stripping
Ion Implantation
RTA or Diffusion
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Illustration of Fab Floor
Process Bays
Gowning Area
Corridor
Equipment Areas
Sliding Doors
Service Area
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Mini-environment Fab Floor
Gowning AreaEmergency Exits
Service Area
Process andmetrologytools
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Wet Processes
DryDryEtch, PR strip, or clean Rinse
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Horizontal Furnace
Center Zone
Flat Zone
Distance
Temperature
Heating Coils
QuartzTube Gas flow
Wafers
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Vertical FurnaceProcessChamber
Wafers
Tower
Heaters
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Schematic of a Track StepperIntegrated System
Hot Plates
PrepChamber
Chill Plates
Chill PlatesSpin Coater
Developer
Stepper
WaferMovement
Wafer
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Cluster Tool with Etch andStrip Chambers
TransferChamber
PR StripChamber
Loading Station
EtchChamber
PR StripChamber
EtchChamber
Unloading Station
Robot
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Cluster Tool with Dielectric CVDand Etchback Chambers
TransferChamber
Loading Station
PECVDChamber
O3-TOESChamber
Unloading Station
Robot
Ar SputteringChamber
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Cluster Tool with PVDChambers
TransferChamber
Loading Station
Ti/TiNChamber
AlCuChamber
Unloading Station
Robot
AlCuChamber
Ti/TiNChamber
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Dry-in Dry-out CMP System
Wafer Loadingand Standby
Post-CMP Clean
Rinse
Dryer and WaferUnloading
Multi-head Polisher
PolishingPad
Clean Station
PolishingHeads
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Process Bay and EquipmentAreas
Process Area
Equ
ipm
entA
rea
Equ
ipm
entA
rea
Process Tools
Tab
les
ForP
Can
dM
etro
logy
Too
ls
Service Area
Sliding Doors
Wafer Loading Doors
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Test Results
Failed die
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Chip-Bond Structure
Chip (Silicon)Chip BacksideMetallization
SolderSubstrateMetallization Substrate (Metal or Ceramic)
Microelectronics Devices and Circuits
Melt andCondense
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Wire Bonding
Metal Wire
Formation ofmolten metal ball
Bonding Pad Bonding Pad Bonding Pad
Press to makecontact
Head retreat
Wire Clamp
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Wire Bonding
LeadBonding Pad Bonding Pad Lead
Lead contact withpressure and heat
Clamp closed with heaton to break the wire
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IC Chip with Bonding Pads
Bonding Pads
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IC Chip Packaging
Pins
ChipBondingPad
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Chip with Bumps
Bumps
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Flip Chip Packaging
Chip
Bumps
Socket Pins
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Bump Contact
Chip
Bumps
Socket Pins
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Heating and Bumps Melt
Chip
Bumps
Socket Pins
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Flip Chip Packaging
Chip
Socket Pins
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Molding Cavity for PlasticPackaging
Bonding Wires IC Chip
Lead Frame
PinsChip Bond Metallization
Top Chase
Bottom Chase
Molding Cavity
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Ceramic Seal
Ceramic Cap
Bonding Wires IC Chip
Lead Frame, Layer 1
Pins
Cap SealMetallization
Chip Bond Metallization
Layer 2Layer 2
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Summary
•Overall yield•Yield determines losing money or making
profit•Cleanroom and cleanroom protocols•Process bays•Process, equipment, and facility areas•Die test, wafer thinning, die separation,
chip packaging, and final test
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