ahcal updates: spiroc and dif mathias reinecke, felix sefkow calice/eudet electronics meeting...
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AHCAL updates:SPIROC and DIF
Mathias Reinecke,Felix Sefkow
CALICE/EUDET electronics meetingLondon, January 10, 2008
Tile Hadron Calorimeter Felix Sefkow January 10, 2008 2
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Topics
• SPIROC tests and future development
• AHCAL specific DIF
• Towards the EUDET module
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SPIROC tests at DESY
• Started with strong support from LAL group– Merci, Ludovic, Stephane, Christophe!
still needs real electronics expert support,
not just an issue of developing control software
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First measurements
• Initially focus on analogue part• Gain, noise, linearity
– Limited by set-up, ADC and DAQ being prepared this week
Some instabilities:
B.Lutz, R.Fabbri
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SPIROC tests: status and outlook
• Confirm first LAL measurements on gain, noise • But also inconsistencies, actively being sorted out in close
contact with LAL
• Once chip handling stabilizes, would like to work on 2 set-ups in parallel – Support from Heidelberg (W.Shen)
• Also addressing digital issues– involve and inspire DIF designer
• Need to organize task sharing and code development
• For discussion: define realistic time scale to understand the chip
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SPIROC wish lists
For the next version• Bypass for fail-safe set-up• Smaller package
For future versions beyond EUDET• Channel-by-channel triggering and memory management• Individual chip addressing for fail-safe set-up• Explore possibilities to increase signal/noise and reduce pick-
up – for use with lower gain SiPMs and more robust gain calibration– Input coupling, pre-amp design
• Support functionalities– DAC for calibration voltage Vcalib
– Read-out internal and external temperature sensor
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Failsafe Setup
Mathias Reinecke EUDET annual meeting – Paris 8.-10. Oct. 2007
Up to 24 SPIROCs (864 detector channels) in slow-control and readout chain (AHCAL).
A broken chip would disable the complete chain.Proposal:
Implementation in next ASIC versions agreedScheme for input selection to be decided. Proposals:
input detection logic at bypass instatic signal from previous chip: 2 extra pinssolder bridge (least elegant)
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Package
• Technical prototype should demonstrate feasibility of compact read-out gap and have realistic signal density and heat couplng
• Aim at 1.5mm total height of PCB + components • Present SPIROC prototype package is 4.3mm high
– 240 pins, not all used, many redundant• Goal TQFP 100 pins 1.0mm
– intermediate? LQFP 144 pins, 1.4 mm• pin list proposal exists• Risk of layout moddif.?
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SPIROC signals
Signal connector
Power connector
2 lines per slab(1.5 MHz) ?
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DIF – AHCAL specific part
Mathias Reinecke CALICE meeting – DESY Dec. 2007
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AHCAL Half Sector - Reminder
Mathias Reinecke CALICE meeting – DESY Dec. 2007
AHCAL Slab6 HBUs in a row
HBUHCAL Base Unittyp. 12 x 12 tiles
SPIROCtyp. 4 on a HBU
HEBHCAL Endcap BoardHosts mezzanine modules:DIF, CALIB and POWER
HLDHCAL Layer Distributor
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AHCAL: Unit CALIB
Mathias Reinecke CALICE meeting – DESY Dec. 2007
POWER CALIB DIF
To LDA
Gain calibration, -monitoring and operational tests by controlling the:
-Charge injection circuits (SPIROC‘s charge inj. inputs)
-Light calibration (LED) system
-External trigger (without or in combination with LCS)
-Power cycling for calibration electronics inside detector layer (two lines, very low current)
Unit CALIB is fully controlled by the DIF (slave operation).
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AHCAL: Unit POWER+Monitoring
Mathias Reinecke CALICE meeting – DESY Dec. 2007
POWER CALIB DIF
To LDA
Power supply for the HBUs,monitoring of temperature and supply voltages-Provide +3.5V, +5V and SiPM bias voltages (+GND) to the HBUs
-Read temperature monitors from HBUs (inside gap)
-Read voltage/current monitors of supply voltages (outside gap).
-Power cycling for electronics inside detector layer
Unit POWER is fully controlled by the DIF (slave operation)- ossibly via CALIB, no second µControler needed.
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DIF: AHCAL specific part
Mathias Reinecke CALICE meeting – DESY Dec. 2007
Very first ideaabout a possiblesetup.
X
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Interconnection
Mathias Reinecke CALICE meeting – DESY Dec. 2007
HBU Interconnection„Flexlead“(4 layers in 300µm)
Connector stacking height(both parts): 800µm
POWER CALIB DIF Probably need something more roust here (outside the gap)
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EUDET module
• One (or two) layers:– 12 HBUs, 1728 channels
• Test daisy-chained readout in long and tin gap with final channel density
• For layer to layer integration and shower-like signal activity:
• Minical (12 layers, 36x36 cm2
• Use 2, 3, 4, 6 or 12 DIFs.
2 cm steel
0.5 cm active
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Prototyping
• Next: HBU prototype– Ingredients are there– SPIROC, embedded LEDs,
tiles, connectors
• DIF prototype:– Commercial evaluation
board– Separate CALIB and
POWER cards– Use existing µController
piggy-back– Ready to follow ECAL DIF
Example SPARTAN3
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Conclusion
• SPIROC test effort broadening– Feedback to SPIROCbis and DIF design just coming
in– Optimize schedule for next ASIC
• DIF building blocks defined– entering detailed design phase– Some decisions needed
• Mechanics: starting – Cassette– Absorber: re-evaluate TESLA design
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Back-up slides
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SPIROC tests
• Analogue part (with basic soft):– Observables: shaped signals, trigger discri out, DAC voltages– Preamp + shaper: Gain, noise, linearity (dynamic range), cross talk– Trigger: threshold scan, time walk, jitter– Both: impact of SiPM pulse shape variations– DACs (trigger threshold and SiPM bias): linearity, dispersion– Charge injection (level control?)– No hold scan (sample and hold only via SCA digital part)
• Digital part (as soft comes along):– Hold scan, dispersion, effect of time walk and input shape variation – ADC and TDC linearity (int, diff)– Readout and trigger timing– Memory management, multi-channel inputs
Timing with SiPM: New feature
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Integrated layer design
Sector wall
Reflector Foil100µm
Polyimide Foil100µm PCB
800µm
Bolt with innerM3 threadwelded to bottom plate
SiPM
Tile3mm
HBU Interface500µm gap
Bottom Plate600µm
ASICTQFP-1001mm high
Top Plate600µm steel
Component Area: 900µm highHBU height:6.1mm(4.9mm without covers => absorber)
AbsorberPlates(steel)
Spacer1.7mm
Top Plate fixing
DESY
integrated
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