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AC to DC Converter for
Low Power Applications
Vinh Nguyen
Stewart Thomas
ECE 262: Final Report
Abstract
Goal: Convert 125 kHz AC signal with magnitude ~2.5V to DC level capable of driving logic
Frequency later changed to 100-200 MHz to allow use of reasonable charge pump capacitor sizes
Should be able to supply at least 1 mW continuously
This type of circuit is used in many applications that require the conversion of AC signal to a DC level that is many times larger than magnitude of the AC signal
Top Level Schematic
AC-DC converter consists of a rectifying charge pump
followed by a DC voltage regulator
Charge pump converts AC signal to DC level while boosting voltage
Regulator limits output voltage to safe level
Pin Diagram
Tied to Gnd
AC In DC Out
Unregulated
Out
Enable
Charge Pump
Charge Pump- Basic Concept
Basic concept based on Dickson charge pump
Uses diodes and charging/discharging capacitors to change AC signal to higher voltage DC signal
Designed in stages
L. Pylarinos, "Charge Pumps: An Overview." 2009 Toronto. http://www.eecg.utoronto.ca/~kphang/ece1371/chargepumps.pdf
Charge Pump Design
While AC signal positive, current flows through diodes and charges capacitors
While AC signal neg, no current flows through diodes and capacitors discharge
Use of multiple stages results in better rectifying ability while boosting output voltage
Frequency limited by capacitor size and diode “switching” speed
Implemented Single Stage
Replaced diodes with diode-connected MOS devices to simplify SCMOS implementation
Diode-Connected NMOS Device
Diode-Connected NMOS Device used in previous schematic
4-Stage Implementation
Final charge pump consists of 4 cascaded stages
Charge Pump Unregulated Output
(No Load)
All simulations presented run using ELDO
Transient simulations were run since the circuit is non-linear
Good output characteristics from 100MHz to ~1GHz with no load
Input Frequency
Input
Am
plit
ude (
V)
Charge Pump Unregulated Output
(10k Load)
Good output characteristics from 100MHz to ~1GHz with 10kΩ load
In general, presence of 10kΩ load drops output voltage
Effect less evident at higher frequencies
Input
Am
plit
ude (
V)
Unregulated Output Power
(10k load)
Output power increases with increasing input voltage amplitude
Increasing the input frequency also to increase output power due to the charging/discharging time of the capacitors
Previous Charge Pump Area Estimate
Single Stage
Each stage has 2 capacitors and 2 MOS devices
MOS devices: 2(10um x 1um) = 20um2
Caps: 2(33um x 33um) ≈ 2000um2
Total area ≈ 2020um2
N-stages
Total area ≈ 2020*N um2
Charge Pump Layout
Single Stage Charge Pump Layout
Diode Layout
Voltage Regulator
Voltage Regulator - Introduction
Depending on input voltage, charge pump output voltage can be very high
To be able to drive digital logic, we need to limit the AC-DC converter output to a more reasonable voltage (~5 Volts)
This is accomplished using a voltage regulator
Simple Voltage Regulator
A simple voltage regulator consists of N diodes arranged in series between the output and ground
Limits the output voltage to N*V
th
Tends to draw significant current as the input voltage gets large
Other, more complicated regulator architectures tend to draw much less current
J. L. Hood, The Art of Linear Electronics, 4th ed. Oxford, UK: Butterworth-Heinemann Ltd., 1993.
Implemented Single Stage Replaced diodes with diode-
connected PMOS devices to simplify SCMOS implementation
Also added PMOS DC switch and decoupling PMOS MOSCap
The sum of the diode-connected PMOS device threshold voltages determine output voltage
Diode-connected PMOS devices need to be common-centroided
Simulated DC-DC Operating Char
(No input or output loads)
DC sweep results show that regulator successfully limits output voltage to less than 7 Volts even as input voltage goes to 20 Volts
Regulator does not begin “pulling down” output voltage until input exceeds ~5 volts
Enable Bit Issues
PMOS device used as DC switch between voltage regulator input and diode chain
To disable the regulator, a high voltage needs to be applied to this PMOS device
Unfortunately, the high input voltage to the regulator means that to disable the regulator (and hence the AC-DC converter) we need to apply a voltage greater than the input voltage to the enable pin
Enable Bit Simulation
Simulation results show that the regulator enables itself if the
input voltage exceeds the enable bit voltage
Regulator Layout- Overview
Diode-connected
PMOS devices are
common centroided
Dummy devices used
as decoupling
MOSCaps
Regulator Layout- Output
Used Gnd-Signal-Gnd output line to shield/decouple output
Also used guard rings to try to isolate regulator from noise sources
Gnd-Signal-Gnd line
Guard rings
Enable PMOS
Regulator Layout- Input
Enable PMOS
Device
Decoupling
MOSCaps
Regulator Layout- Common Centroid
Diode-connected
PMOS Devices
Decoupling
MOSCaps
Integrated Design
Integrated Design Schematic
Charge-pump output tied to voltage regulator input
Integrated Output
(200 MHz, Enabled)
Output voltage very flat for 200 MHz input
Voltage regulator enabled (EN pin grounded)
Integrated Output
(200 MHz, Disabled)
Output voltage negligible for 200 MHz input
Voltage regulator disable (EN pin tied to charge pump output)
Regulated Output Power
(10k load)
Output power increases with increasing input voltage amplitude
Output power levels at higher input voltage amplitudes due to regulator
Integrated Layout Overview
Total area used: 2202µm x 1629µm (~3.6 mm2)
Original estimated area: ~8080 µm2)
Charge
Pump Voltage
Regulator
Design Challenges
Had to common centroid capacitors and
regulator PMOS devices
Needed to make extensive use of guard rings
and decoupling techniques
Encountered issues with enable bit biasing
Summary
Designed and simulated charge-pump
rectifying circuit with voltage regulator and
enable bit
With a 2.5V, 200 MHz AC input, the circuit
supplies approximately 5.5 VDC with an
output power of approximately 3 mW
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