8085 slides
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Microprocessors
Multipurpose, Programmable integrated device
that has computing and decision making
capability similar to that of CPU.
CPU on
chip
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Intel 8008
8-bit micrprocessor
Introduced on April 1, 1972
Clock rate 500 kHz (80081: 800 kHz) Bus Width 8 bits.
Enhancement load PMOS logic
Addressable memory 16 KB
http://en.wikipedia.org/wiki/PMOS_logichttp://en.wikipedia.org/wiki/PMOS_logic -
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Intel 8080
Introduced April 1, 1974
Clock rate 2 MHz
Bus Width 8 bits data, 16 bits address
Enhancement load NMOS logic Assembly language downwards compatible
with 8008.
Addressable memory 64 KB
http://en.wikipedia.org/wiki/NMOS_logichttp://en.wikipedia.org/wiki/Assembly_languagehttp://en.wikipedia.org/wiki/Assembly_languagehttp://en.wikipedia.org/wiki/NMOS_logic -
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Intel 8085
8-bit microprocessor
Introduced March 1976
Clock rate 2 MHz
Bus Width 8 bits data, 16 bits address
Depletion load NMOS logic
High level of integration, operating for the first
time on a single 5 volt power supply, from 12 volts
previously. Also featured serial I/O,3 maskableinterrupts,1 Non-maskable interrupt,1 externally
expandable interrupt [8259], status, DMA.
http://en.wikipedia.org/wiki/NMOS_logichttp://en.wikipedia.org/wiki/Maskable_interrupthttp://en.wikipedia.org/wiki/Maskable_interrupthttp://en.wikipedia.org/wiki/Maskable_interrupthttp://en.wikipedia.org/wiki/Maskable_interrupthttp://en.wikipedia.org/wiki/NMOS_logic -
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Intel 8086
Introduced in June 8, 1978
Clock rates:
4.77 MHz with 0.33 MIPS[3]
8 MHz with 0.66 MIPS 10 MHz with 0.75 MIPS
The memory is divided into odd and even banks.It accesses both the banks simultaneously in
order to read 16 bit of data in one clock cycle.
Bus Width 16 bits data, 20 bits address
Addressable memory 1 megabyte
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8085 INTRODUCTION
The features of INTEL 8085 are :
It is an 8 bit processor.
It is a single chip N-MOS device with 40 pins.
It has multiplexed address and data bus.(AD0-AD7).
It works on 5 Volt dc power supply.
The maximum clock frequency is 3 MHz while
minimum frequency is 500kHz.
It provides 74 instructions with 5 different addressing
modes.
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Processor System Architecture
The typical processor system consists of:
CPU (central processing unit)
ALU (arithmetic-logic unit)
Control Logic
Registers, etc
Memory
Input / Output interfaces
Interconnections between these units:
Address Bus
Data Bus
Control Bus
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8085 hardware model
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Bus and CPU
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Bus: A shared group of wires used for communicating signals among devices
address bus: the device and the location within the device that is
being accessed
data bus: the data value being communicated
control bus: describes the action on the address and databuses
CPU: Core of the processor, where instructions are executed
High-level language: a = b + c Assembly language: add r1 r2 r3
Machine language: 0001001010111010101
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The 8085 Bus Structure
Address Bus
Consists of 16 address lines: A15 A0
Operates in unidirectional mode: The address bits are always sent from
the MPU to peripheral devices, not reverse.
16 address lines are capable of addressing a total of 216 = 65,536 (64k)
memory locations.
Address locations: 0000 (hex) FFFF (hex)
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The 8085 Bus Structure
Data Bus
Consists of 8 data lines: D0 D7
Operates in bidirectional mode: The data bits are sent from the MPU to
peripheral devices, as well as from the peripheral devices to the MPU.
Data range: 00 (hex) FF (hex)
Control Bus
Consists of various lines carrying the control signals such as read / write
enable, flag bits.
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The 8085: CPU Internal Structure
Registers
Six general purpose 8-bit registers: B, C, D, E, H, L
They can also be combined as register pairs to
perform 16-bit operations: BC, DE, HL
Registers are programmable (data load, move, etc.)
Accumulator
Single 8-bit register that is part of the ALU !
Used for arithmetic / logic operations the result is always stored in
the accumulator.
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The 8085: CPU Internal Structure
Flag Bits
Indicate the result of condition tests.
Carry, Zero, Sign, Parity, etc.
Conditional operations (IF / THEN) are executed based on the condition of
these flag bits.
Program Counter (PC)
Contains the memory address (16 bits) of the instruction that will be
executed in the next step.
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The 8085: CPU Internal Structure
The Stack pointer
The stack pointer is also a 16-bit register that is
used to point into memory.
The memory this register points to is a specialarea called the stack.
The stack is an area of memory used to hold data
that will be retreived soon.
The stack is usually accessed in a Last In First Out
(LIFO) fashion.
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Memory model
This microprocessor can access 64K ( = 65536 ) bytes of memory
Each byte has 8 bits, therefore it can access 64K 8 bits of
memory
64K of memory is the maximum limit, sometimes a system based
on this CPU can have less memory
Use memory to map I/O Same instructions to use for
accessing I/O devices and memory
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The 8085: Registers
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Flag register
Flag Register is given by:
S: Sign flag
Z: Zero flag
Ac: Auxiliary carry flag
CY: Carry flagP: Parity flag
Rest are dont care flip flops.
S Z X AC X P X CY
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The sign flag, S, indicates the sign of a value
calculated by an arithmetic or logical instruction. The zero flag, Z, is set to 1 if an arithmetic or logical
operation produces a result of 0; otherwise set to 0.
Theparity flag, P, is set to 1 if the result of an
arithmetic or logical operation has an even number of1s; otherwise it is set to 0.
The carry flag, CY, is set when an arithmetic
operation generates a carry out.
The auxiliary carry flag, AC, very similar to CY, but
it denotes a carry from the lower half of the result to
the upper half.
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Programming Model
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The 8085 Bus Structure
The 8-bit 8085 CPU (or MPU Micro Processing Unit) communicates with the other
units using a 16-bit address bus, an 8-bit data bus and a control bus.
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Microprocessor Architecture
The microprocessor can be programmed to
perform functions on given data by writing
specific instructions into its memory.
The microprocessor reads one instruction at a
time, matches it with its instruction set, and
performs the data manipulation specified.
The result is either stored back into memory ordisplayed on an output device.
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TIMING AND STATE DIAGRAM
The P operates with reference to clock signal. The rise andfall of the pulse of the clock gives one clock cycle.
Each clock cycle is called a T state and a collection of several T
states gives a machine cycle.
Important machine cycles are :1. Op-code fetch.
2. Memory read.
3. Memory write.
4. I/Op-read.
5. I/O write.
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TIMING AND STATE DIAGRAM
Op-code Fetch: It basically requires 4 T states from T1-T4
The ALE pin goes high at first T state always.
AD0-AD7 are used to fetch OP-code and store the lower byteof Program Counter.
A8-A15 store the higher byte of the Program Counter whileIO/M will be low since it is memory related operation.
RD will only be low at the Op-code fetching time.
WR will be at HIGH level since no write operation is done.
S0=1,S1=1 for Op-code fetch cycle.
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TIMING AND STATE DIAGRAMOp-code fetch cycle :
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TIMING AND STATE DIAGRAM
Memory write Cycle: It basically requires 3T states from T1-T3 .
The ALE pin goes high at first T state always.
AD0-AD7 are used to fetch data from CPU and store thelower byte of address.
A8-A15 store the higher byte of the address while IO/M willbe low since it is memory related operation.
RD will be HIGH since no read operation is done.
WR will be at LOW level only when data fetching is done.
S0=1,S1=0 for Memory write cycle.
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Instruction set
No of bits in a given machine is fixed andcombination of these bits is called instruction.
p 8085 has 74 different instructions in its
instruction set, that determines what functionsthe microprocessor can perform.
Categories of instruction set are:
Data transfer(copy) operation
Arithmetic operation Logical operation
Branching operation
Machine control operation
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8085 Instruction Types
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8085 Instruction Types
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8085 Instruction Types
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ADDRESSING MODES OF 8085
Immediate addressing:Immediate data is transferred to address or register.
Example:
MVI A,20H. Transfer immediate data 20H to accumulator.
Number of bytes:
Either 2 or 3 bytes long.
1st byte is opcode.
2nd
byte 8 bit data .3rd byte higher byte data of 16 bytes.
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ADDRESSING MODES OF 8085
Register addressing:Data is transferred from one register to other.
Example:
MOV A, C : Transfer data from C register to accumulator.
Number of bytes:Only 1 byte long.
One byte is opcode.
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ADDRESSING MODES OF 8085
Direct addressing: Data is transferred from direct address to other
register or vice-versa.
Example:
LDA C200H .Transfer contents from C200H to Acc.Number of bytes:
These are 3 bytes long.
1st byte is opcode.
2nd
byte lower address.3rd byte higher address.
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ADDRESSING MODES OF 8085
Indirect addressing:
Data is transferred from address pointed by the data in a
register to other register or vice-versa.
Example:
MOV A, M: Move contents from address pointed by M to Acc.
Number of bytes:
These are 3 bytes long.
1st
byte is opcode.2nd byte lower address.
3rd byte higher address.
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ADDRESSING MODES OF 8085
Implicit addressing: These dont require any operand. The data is specified in
Opcode itself.
Example: RAL: Rotate left with carry.
Number of Bytes:
These are single byte instruction or Opcode only.
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Simple Data Transfer Operations
Examples:
MOV B,A 47 From ACC to REG
MOV C,D 4A Between two REGs
MVI D,47 16 Direct-write into REG D
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Simple Data Transfer Operations
Example:
OUT 05 D3
05
Contents of ACC sent to output port number 05.
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Simple Memory Access Operations
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Simple Memory Access Operations
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Arithmetic Operations
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Arithmetic Operations
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Arithmetic Operations
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Arithmetic Operations
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Overview of Logic Operations
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Logic Operations
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Logic Operations
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Logic Operations
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Branching Operations
Note: This is an unconditional jump operation. It will always force the program
counter to a fixed memory address continuous loop !
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Conditional jump operations are very useful for decision making during theexecution of the program.
Branching Operations
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Conditional Call Instructions.
CC (Call if Carry flag is set)
CNC (Call if Carry flag is reset)
CZ (Call if zero flag set) CNZ (Call if zero flag is reset)
CPE (Call if parity flag is set)
CPO (Call if parity odd or P flag is reset )
CP (Call if sign flag reset )
CM (Call if sign flag is set or minus)
Branching Operations
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The 8085: CPU Internal Structure
The internal architecture of the 8085 CPU is
capable of performing the following operations:
Store 8-bit data (Registers, Accumulator)
Perform arithmetic and logic operations (ALU)
Test for conditions (IF / THEN)
Sequence the execution of instructions
Store temporary data in RAM during execution
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DATA TRANSFER GROUP
Example: Write a program to exchange contents of memory
location D000H to D001H
LDA D000H Load Acc with data from D000
MOV B,A Move the data to BLDA D001H Load Acc with data from D001
STA 2000H Store Acc data at 2000
MOV A,B Move Bs data to A
STA 2001H Store data from D000 to D001
HLT Stop.
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Example
Write a 8085 machine code program:
Read two different memory locations
Add the contents
Send the result to output port 02 (display)
if there is no overflow
Display FF if there is an overflow
Stop
E l
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Example
2000 LDA 2050 3A
2001 50
2002 20
2003 MOV B,A 47
2004 LDA 2051 3A
2005 51
2006 20
2007 ADD B 802008 JNC XXYY D2
2009 YY
2010 XX
2011 MVI A,FF 3E
2012 FF2013 OUT 02 D3
2014 02
2015 HLT 76
Load contents of memory location
2050 into accumulator
Load contents of memory location
2051 into accumulator
Save the first number in B
Add accumulator with B
Jump to XXYY if no carry !
Direct write FF into accumulator
Display accumulator contents at
output port 02
Stop
U d t d C d
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Updated Code
2000 LDA 2050 3A
2001 50
2002 20
2003 MOV B,A 47
2004 LDA 2051 3A
2005 51
2006 20
2007 ADD B 802008 JNC 2013 D2
2009 13
2010 20
2011 MVI A,FF 3E
2012 FF2013 OUT 02 D3
2014 02
2015 HLT 76
Load contents of Memory
location 2050 in to accumulator
Load contents of Memory
location 2051 in to accumulator
Save the first number in B
Add accumulator with B
Jump to 2013 if no carry !
Direct write FF int o accumulator
Display accumulator contents at
output port 02
Stop
ll d
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Externally Initiated Operations
External devices can initiate (start) one of
the 4 following operations: Reset
All operations are stopped and the programcounter is reset to 0000.
Interrupt
The microprocessors operations are interruptedand the microprocessor executes what is called a
service routine. This routine handles the interrupt, (perform the
necessary operations). Then the microprocessorreturns to its previous operations and continues.
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Externally Initiated Operations
Ready The 8085 has a pin called RDY. This pin is used by external
devices to stop the 8085 until they catch up.
As long as the RDY pin is low, the 8085 will be in a waitstate.
Hold
The 8085 has a pin called HOLD. This pin is used byexternal devices to gain control of the busses.
When the HOLD signal is activated by an external device,
the 8085 stops executing instructions and stops using thebusses.
This would allow external devices to control theinformation on the busses. Example DMA.
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Pin Diagram of 8085
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Pin Diagram of 8085
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8085 PIN DESCRIPTION
Some important pins are :
AD7-AD0: Multiplexed Address and data lines.
A15-A8: Tri-stated higher order address lines.
ALE: Address latch enable is an output signal. It goes high
when operation is started by processor .
S0,S1: These are the status signals used to indicate type of
operation.
RD: Read is active low input signal used to read data from I/O
device or memory.
WR: Write is an active low output signal used write data on
memory or an I/O device.
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8085 PIN DESCRIPTION
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8085 PIN DESCRIPTION
HOLD&HLDA:HOLD is an input signal .When P receives HOLD
signal it completes current machine cycle and stops executingnext instruction. In response to HOLD P generates HLDA that
is HOLD Acknowledge signal.
RESET IN:This is input signal. When RESET IN is low p
restarts and starts executing from location 0000H. SID: Serial input data is input pin used to accept serial 1 bit
data .
X1X2:These are clock input signals and are connected to
external LC or RC circuit. These are divide by two so if 6 MHzis connected to X1X2,the operating frequency becomes 3
MHz.
VCC&VSS:Power supply VCC=+ -5Volt& VSS=-GND reference.
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