8085 processor
DESCRIPTION
8085 processor. Bus system in microprocessor. Intel 8085 Block Diagram. Intel 8085 Signals. Stored program organization. Basic computer registers and memory. List of Registers for the Basic Computer. Computer Instructions. each computer has its own unique instruction set. - PowerPoint PPT PresentationTRANSCRIPT
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8085 processor
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Bus system in microprocessor
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Intel 8085 Block Diagram
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Intel 8085 Signals
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Stored program organization
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PC11 0
AR11 0
IR15 0
TR
INPR7 0
OUTR7 0
15 0
DR15 0
AC15 0
Memory4096 words
16 bits per word
Basic computer registers and memory
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RegisterNo of
bitsRegister name Function
DR 16 Data register Holds memory operand
AR 12 Address registerHolds address for
memory
AC 16 Accumulator Processor register
IR 16Instruction
registerHolds instruction code
PC 12 Program counterHolds address of
instruction
TR 16Temporary
registerHolds temporary data
INPR 8 Input register Holds input character
OUTR 8 Output register Holds output character
List of Registers for the Basic Computer
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INPR
IR
LD
TR
LD INR CLR
OUTR
LD
AR
LD INR CLR
PC
LD INR CLR
DR
LD INR CLR
AC
LD INR CLR
Memory Unit4096 x 16
Write Read
Bus
16-bit common bus
Address
CLK
Adderand
Logic
E
S2S1S0
7
1
2
3
4
5
6
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Computer Instructions
each computer has its own unique instruction set.
Instruction types and formats
The basic computer has three instruction code formats Each format has 16 bits. The operation code (opcode) part of the
instruction contains three bits the meaning of the remaining 13 bits depends
on the operation code encountered
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1) A memory-reference instructionuses 12 bits to specify an address and one bit to specify the addressing mode I. The I bit is equal to 0 for direct address
1 for indirect address
2) The register-reference instructions
are recognized by the operation code 111 with a 0 in the leftmost bit (bit 15) of the instruction
3) input-output instruction
are recognized by the operation code 111 with a 1 in the leftmost bit (bit 15) of the instruction
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Direct and Indirect Address
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effective address
to be the address of the operand in a computation-type instruction.
1. Thus the effective address in the instruction in memory address 22 is 457
2. and the effective address in the instruction in memory address 35 in the instruction is 1350.
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Instruction Cycle
In the basic computer each instruction cycle consists of the following phases:
1.Fetch an instruction from memory.2.Decode the instruction.
• Define the operation.• Read the effective address from memory
if the instruction has an indi rect address.3.Execute the instruction.
• read operand or data if any.• execute the specified operation on the
data
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Fetch and Decode
The microoperations for the fetch and decode phases can be specified by the following register transfer statements
SC is cleared to 0
T0: AR PC
T1: IR M[AR], pc pc+1
T2 : D0,.D7 Decode IR(12-14), I IR(15), AR IR(0-11)
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Register transfers for the fetch phase
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Execute Instruction
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Register-reference instructions are recognized by the control when D7 = 1 and I = 0.
These instructions use bits 0 through 11 of the instruction code to specify one of 12 instructions. These 12 bits are available in IR(0-ll).
They were also transferred to AR during time T2
Register-Reference Instructions
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Execution of Register-Reference Instructions
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Memory-Reference Instructions
Memory-Reference Instructions
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BSA: Branch and Save Return Address
Example of BSA instruction execution
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Hexadecimal code
Symbol I = 0 I = 1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load memory word to AC
STA 3xxx Bxxx Store content of AC in memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero
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Hexadecimal code
Symbol I = 0 I = 1 Description
CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 increment AC
SPA 7010 Skip next instruction if AC positive
SNA 7008 Skip next instruction if AC neg
SZA 7004 Skip next instruction if AC zero
SZE 7002 Skip next instruction if E is 0
HLT 7001 Halt computer
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Hexadecimal code
Symbol I = 0 I = 1 Description
INP F800 Input character to AC
OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off
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Timing and Control
The timing for all registers in the basic computer is controlled by a master clock generator.
The clock pulses do not change the state of a register unless the register is enabled by a control signal.
The control signals are generated in the control unit and provide control inputs for :
multiplexers in the common bus, control inputs in processor registers, and micro-operations for the accumulator
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There are two major types of control organization:o hardwired control ando micro-programmed control
oIn the HW the control logic is implemented with gates, flip-flops, decoders, and other digital circuits
oIn micro., the control information is stored in a control memory.
The control memory is programmed to initiate the required sequence of microoperations
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15 14 13 12 11 - 0
3 x 8Decoder
I
4 x 16Decoder
ControlLogicGates
4-bitSequenc Counter
(SC)
15 14 ......... 2 1 0
7 6 5 4 3 2 1 0
Instruction Register (IR)
Other Inputs
ControlOutputs
Increment (INR)
Clear (CLR)
Clock
D0
D7
......
T15
T0
......
Timing and Control Block Diagram
Control unit of basic computer
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It consists of two decoders, a sequence counter, and a number of control logic gates. An instruction read from memory is placed in the instruction register (IR).
it is divided into three parts:• the I bit, (a flip-flop )• the operation code (decoded with a 3 x 8 decoder)
D0 through D7
• and bits 0 through 11. (Bits 0 - 11 are applied to the control logic gates). The 4-bit sequence counter can count in binary
from 0 through 15. The outputs of the counter are decoded into 16
timing signals T0 through T15.
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Example of control timing signals
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Complete Computer DescriptionThe control functions and microoperations for the entire computer are summarized in the Table.
The register transfer statements describe in a concise form the internal organization of the basic computer. They also give all the information necessary for the design of the logic circuits of the computer.
The control functions and conditional control statements listed in the table formulate the Boolean functions for the gates in the control unit.
The list of microoperations specifies the type of control inputs needed for the registers and memory. A register transfer language is useful not only for describing the internal organization of a digital system but also for specifying the logic circuits needed for its design.
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Control functions and microoperations for basic computer
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Design of Accumulator LogicThe circuits associated with the AC register consists of: The adder and logic circuit has three sets of
inputs. One set of 16 inputs comes from the outputs
of AC. Another set of 16 inputs comes from the data
register DR. A third set of eight inputs comes from the
input register INPR. The outputs of the adder and logic circuit
provide the data inputs for the register. In addition, it is necessary to include logic
gates for controlling the LD, INR, and CLR in the register and for controlling the operation of the adder and logic circuit
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Block Diagram of Design an Accumulator Logic
Circuits associated with AC
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In order to design the logic associated with AC, it is necessary to go over the register transfer statements as shown and extract all the statements that change the content of AC.
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Control of AC RegisterThe gate structure that controls the LD,INR, and CLR inputs of AC
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The control function for the clear microoperation is rB11 where r = D7 I T3 and B11 = IR (11).
The output of the AND gate that generates the control function is connected to the CLR input of the register.
Similarly, the output of the gate that implements the increment microoperation is connected to the INR input of the register.
The other seven microoperations are generate (in the adder and logic circuit and are loaded into AC at the proper time. The outputs of the gates for each control function is marked with a symbolic name These outputs are used in the design of the adder and logic circuit
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Adder and Logic Circuit
Output of OR Gate in the last fig.