8051 microcontroller intro
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Saturday, April 8, 2023 Mahdi Hassanpour
• Section 1
Microprocessors course
Dr. S.O.Fatemi
By: Mahdi Hassanpour
Saturday, April 8, 2023 Mahdi Hassanpour
Contents:IntroductionBlock Diagram and Pin Description of the 8051RegistersSome Simple InstructionsStructure of Assembly language and Running an 8051 programMemory mapping in 8051 8051 Flag bits and the PSW registerAddressing Modes16-bit, BCD and Signed Arithmetic in 8051Stack in the 8051LOOP and JUMP InstructionsCALL InstructionsI/O Port Programming
Saturday, April 8, 2023 Mahdi Hassanpour
Introduction
CPU
General-Purpose Micro-processor
RAM ROM I/O Port
TimerSerial COM Port
Data Bus
Address Bus
General-Purpose Microprocessor System
• CPU for Computers
• No RAM, ROM, I/O on CPU chip itself
• Example : Intel’s x86, Motorola’s 680x0
Many chips on mother’s board
General-purpose microprocessor
Saturday, April 8, 2023 Mahdi Hassanpour
RAM ROM
I/O Port
TimerSerial COM Port
Microcontroller
CPU
• A smaller computer
• On-chip RAM, ROM, I/O ports...
• Example : Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X
A single chip
Microcontroller :
Saturday, April 8, 2023 Mahdi Hassanpour
Microprocessor
• CPU is stand-alone, RAM, ROM, I/O, timer are separate
• designer can decide on the amount of ROM, RAM and I/O ports.
• expansive
• versatility
• general-purpose
Microcontroller
• CPU, RAM, ROM, I/O and timer are all on a single chip
• fix amount of on-chip ROM, RAM, I/O ports
• for applications in which cost, power and space are critical
• single-purpose
Microprocessor vs. Microcontroller
Saturday, April 8, 2023 Mahdi Hassanpour
• Embedded system means the processor is embedded into that application.
• An embedded product uses a microprocessor or microcontroller to do one task only.
• In an embedded system, there is only one application software that is typically burned into ROM.
• Example : printer, keyboard, video game player
Embedded System
Saturday, April 8, 2023 Mahdi Hassanpour
1. meeting the computing needs of the task efficiently and cost effectively
• speed, the amount of ROM and RAM, the number of I/O ports and timers, size, packaging, power consumption
• easy to upgrade
• cost per unit
2. availability of software development tools
• assemblers, debuggers, C compilers, emulator, simulator, technical support
3. wide availability and reliable sources of the microcontrollers.
Three criteria in Choosing a Microcontroller
Saturday, April 8, 2023 Mahdi Hassanpour
Block Diagram
CPU
On-chip RAM
On-chip ROM for program code
4 I/O Ports
Timer 0
Serial PortOSC
Interrupt Control
External interrupts
Timer 1
Timer/Counter
Bus Control
TxD RxDP0 P1 P2 P3
Address/Data
Counter Inputs
Saturday, April 8, 2023 Mahdi Hassanpour
Feature 8051 8052 8031
ROM (program space in bytes) 4K 8K 0K
RAM (bytes) 128 256 128
Timers 2 3 2
I/O pins 32 32 32
Serial port 1 1 1
Interrupt sources 6 8 6
Comparison of the 8051 Family Members
Saturday, April 8, 2023 Mahdi Hassanpour
Saturday, April 8, 2023 Mahdi Hassanpour
Pin Description of the 8051PDIP/Cerdip
1234567891011121314151617181920
4039383736353433323130292827262524232221
P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7RST
(RXD)P3.0(TXD)P3.1
(T0)P3.4(T1)P3.5
XTAL2XTAL1
GND
(INT0)P3.2(INT1)P3.3
(RD)P3.7(WR)P3.6
VccP0.0(AD0)P0.1(AD1)P0.2(AD2)P0.3(AD3)P0.4(AD4)P0.5(AD5)P0.6(AD6)P0.7(AD7)EA/VPPALE/PROGPSENP2.7(A15)P2.6(A14)P2.5(A13)P2.4(A12)P2.3(A11)P2.2(A10)P2.1(A9)P2.0(A8)
8051(8031)
Saturday, April 8, 2023 Mahdi Hassanpour
Pins of 8051 ( 1/4)
• Vcc ( pin 40 ):– Vcc provides supply voltage to the chip.
– The voltage source is +5V.
• GND ( pin 20 ): ground
• XTAL1 and XTAL2 ( pins 19,18 ):– These 2 pins provide external clock.
– Way 1 : using a quartz crystal oscillator
– Way 2 : using a TTL oscillator – Example 4-1 shows the relationship between XTAL and the
machine cycle.
Saturday, April 8, 2023 Mahdi Hassanpour
Pins of 8051 ( 2/4)
• RST ( pin 9 ): reset
– It is an input pin and is active high ( normally low ) .
• The high pulse must be high at least 2 machine cycles.
– It is a power-on reset.
• Upon applying a high pulse to RST, the microcontroller will reset and all values in registers will be lost.
• Reset values of some 8051 registers – Way 1 : Power-on reset circuit – Way 2 : Power-on reset with debounce
Saturday, April 8, 2023 Mahdi Hassanpour
Pins of 8051 ( 3/4)
• /EA ( pin 31 ): external access
– There is no on-chip ROM in 8031 and 8032 .
– The /EA pin is connected to GND to indicate the code is stored externally.
– /PSEN & ALE are used for external ROM.
– For 8051, /EA pin is connected to Vcc.
– “/” means active low.
• /PSEN ( pin 29 ): program store enable
– This is an output pin and is connected to the OE pin of the ROM.
– See Chapter 14.
Saturday, April 8, 2023 Mahdi Hassanpour
Pins of 8051 ( 4/4)
• ALE ( pin 30 ): address latch enable
– It is an output pin and is active high.
– 8051 port 0 provides both address and data.
– The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.
• I/O port pins
– The four ports P0, P1, P2, and P3.
– Each port uses 8 pins.
– All I/O pins are bi-directional.
Saturday, April 8, 2023 Mahdi Hassanpour
Figure 4-2 (a). XTAL Connection to 8051
C2
30pF
C1
30pF
XTAL2
XTAL1
GND
• Using a quartz crystal oscillator
• We can observe the frequency on the XTAL2 pin.
Saturday, April 8, 2023 Mahdi Hassanpour
Figure 4-2 (b). XTAL Connection to an External Clock Source
NC
EXTERNALOSCILLATORSIGNAL
XTAL2
XTAL1
GND
• Using a TTL oscillator
• XTAL2 is unconnected.
Saturday, April 8, 2023 Mahdi Hassanpour
Example :
Find the machine cycle for(a) XTAL = 11.0592 MHz (b) XTAL = 16 MHz.
Solution:
(a) 11.0592 MHz / 12 = 921.6 kHz; machine cycle = 1 / 921.6 kHz = 1.085 s(b) 16 MHz / 12 = 1.333 MHz; machine cycle = 1 / 1.333 MHz = 0.75 s
Saturday, April 8, 2023 Mahdi Hassanpour
RESET Value of Some 8051 Registers:
0000DPTR
0007SP
0000PSW
0000B
0000ACC
0000PC
Reset ValueRegister
RAM are all zero.
Saturday, April 8, 2023 Mahdi Hassanpour
Figure 4-3 (a). Power-On RESET Circuit
30 pF
30 pF
8.2 K
10 uF
+
Vcc
11.0592 MHz
EA/VPPX1
X2
RST
31
19
18
9
Saturday, April 8, 2023 Mahdi Hassanpour
Figure 4-3 (b). Power-On RESET with Debounce
EA/VPPX1
X2RST
Vcc
10 uF
8.2 K
30 pF
9
31
Saturday, April 8, 2023 Mahdi Hassanpour
Pins of I/O Port
• The 8051 has four I/O ports
– Port 0 ( pins 32-39 ): P0 ( P0.0 ~ P0.7 )– Port 1 ( pins 1-8 ) : P1 ( P1.0 ~ P1.7 )– Port 2 ( pins 21-28 ): P2 ( P2.0 ~ P2.7 )– Port 3 ( pins 10-17 ): P3 ( P3.0 ~ P3.7 )– Each port has 8 pins.
• Named P0.X ( X=0,1,...,7 ) , P1.X, P2.X, P3.X
• Ex : P0.0 is the bit 0 ( LSB ) of P0
• Ex : P0.7 is the bit 7 ( MSB ) of P0
• These 8 bits form a byte.
• Each port can be used as input or output (bi-direction).
Saturday, April 8, 2023 Mahdi Hassanpour
Registers
A
B
R0
R1
R3
R4
R2
R5
R7
R6
DPH DPL
PC
DPTR
PC
Some 8051 16-bit Register
Some 8-bitt Registers of the 8051
Saturday, April 8, 2023 Mahdi Hassanpour
Some Simple InstructionsMOV dest,source ; dest = source
MOV A,#72H ;A=72H
MOV A, #’r’ ;A=‘r’ OR 72H
MOV R4,#62H ;R4=62H
MOV B,0F9H ;B=the content of F9’th byte of RAM
MOV DPTR,#7634H
MOV DPL,#34H
MOV DPH,#76H
MOV P1,A ;mov A to port 1
Note 1:MOV A,#72H ≠ MOV A,72H
After instruction “MOV A,72H ” the content of 72’th byte of RAM will replace in Accumulator.
8086 8051MOV AL,72H MOV A,#72H
MOV AL,’r’ MOV A,#’r’
MOV BX,72H
MOV AL,[BX] MOV A,72H
Note 2:MOV A,R3 ≡ MOV A,3
Saturday, April 8, 2023 Mahdi Hassanpour
ADD A, Source ;A=A+SOURCE
ADD A,#6 ;A=A+6
ADD A,R6 ;A=A+R6
ADD A,6 ;A=A+[6] or A=A+R6
ADD A,0F3H ;A=A+[0F3H]
Saturday, April 8, 2023 Mahdi Hassanpour
SETB bit ; bit=1CLR bit ; bit=0
SETB C ; CY=1SETB P0.0 ;bit 0 from port 0 =1SETB P3.7 ;bit 7 from port 3 =1SETB ACC.2 ;bit 2 from ACCUMULATOR =1SETB 05 ;set high D5 of RAM loc. 20h
Note:
CLR instruction is as same as SETBi.e:
CLR C ;CY=0
But following instruction is only for CLR:CLR A ;A=0
Bit Addressable Page 359,360
Saturday, April 8, 2023 Mahdi Hassanpour
SUBB A,source ;A=A-source-CY
SETB C ;CY=1
SUBB A,R5 ;A=A-R5-1
ADC A,source ;A=A+source+CY
SETB C ;CY=1
ADC A,R5 ;A=A+R5+1
Saturday, April 8, 2023 Mahdi Hassanpour
DEC byte ;byte=byte-1INC byte ;byte=byte+1
INC R7DEC ADEC 40H ; [40]=[40]-1
CPL A ;1’s complementExample:
MOV A,#55H ;A=01010101 BL01: CPL A
MOV P1,AACALL DELAYSJMP L01
NOP & RET & RETI
All are like 8086 instructions.
CALL
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ANL - ORL - XRL
EXAMPLE:
MOV R5,#89H
ANL R5,#08H
RR – RL – RRC – RLC A
EXAMPLE:RR A
Saturday, April 8, 2023 Mahdi Hassanpour
Structure of Assembly language and Running an 8051 program
ORG 0H MOV R5,#25H MOV R7,#34H MOV A,#0 ADD A,R5 ADD A,#12H
HERE: SJMP HERE END
EDITORPROGRAM
ASSEMBLERPROGRAM
LINKERPROGRAM
OHPROGRAM
Myfile.asm
Myfile.obj
Other obj fileMyfile.lst
Myfile.abs
Myfile.hex
Saturday, April 8, 2023 Mahdi Hassanpour
Memory mapping in 8051
• ROM memory map in 8051 family
0000H
0FFFH
0000H
1FFFH
0000H
7FFFH
8751AT89C51 8752
AT89C52
4k
DS5000-32
8k 32k
from Atmel Corporationfrom Dallas Semiconductor
Saturday, April 8, 2023 Mahdi Hassanpour
• RAM memory space allocation in the 8051
7FH
30H
2FH
20H
1FH
17H
10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Saturday, April 8, 2023 Mahdi Hassanpour
8051 Flag bits and the PSW register • PSW Register
CY AC F0 RS1 OVRS0 P--
CYPSW.7Carry flagACPSW.6Auxiliary carry flag--PSW.5Available to the user for general purpose
RS1PSW.4Register Bank selector bit 1RS0PSW.3Register Bank selector bit 0OVPSW.2Overflow flag--PSW.1User define bitPPSW.0Parity flag Set/Reset odd/even parity
RS1 RS0 Register Bank Address
0 0 0 00H-07H
0 1 1 08H-0FH
1 0 2 10H-17H
1 1 3 18H-1FH
Saturday, April 8, 2023 Mahdi Hassanpour
Instructions that Affect Flag Bits:
Note: X can be 0 or 1
Saturday, April 8, 2023 Mahdi Hassanpour
Example:MOV A,#38HADD A,#2FH
38 00111000+2F +00101111 ---- -------------- 67 01100111
CY=0 AC=1 P=1
Example:MOV A,#88HADD A,#93H
88 10001000+93 +10010011 ---- -------------- 11B 00011011
CY=1 AC=0 P=0
Example:MOV A,#9CHADD A,#64H
9C 10011100+64 +01100100 ---- -------------- 100 00000000
CY=1 AC=1 P=0
Saturday, April 8, 2023 Mahdi Hassanpour
Addressing Modes
• Immediate
• Register
• Direct
• Register Indirect
• Indexed
Saturday, April 8, 2023 Mahdi Hassanpour
Immediate Addressing ModeMOV A,#65HMOV A,#’A’MOV R6,#65HMOV DPTR,#2343HMOV P1,#65H
Example :
Num EQU 30…MOV R0,NumMOV DPTR,#data1…ORG 100Hdata1: db “IRAN”
Saturday, April 8, 2023 Mahdi Hassanpour
Register Addressing Mode
MOV Rn, A ;n=0,..,7
ADD A, Rn
MOV DPL, R6
MOV DPTR, A
MOV Rm, Rn
Saturday, April 8, 2023 Mahdi Hassanpour
Direct Addressing ModeAlthough the entire of 128 bytes of RAM can be accessed using direct addressing mode, it is most often used to access RAM loc. 30 – 7FH.
MOV R0, 40HMOV 56H, AMOV A, 4 ; ≡ MOV A, R4MOV 6, 2 ; copy R2 to R6
; MOV R6,R2 is invalid !
SFR register and their address
MOV 0E0H, #66H ; ≡ MOV A,#66HMOV 0F0H, R2 ; ≡ MOV B, R2MOV 80H,A ; ≡ MOV P1,A
Bit Addressable Page 359,360
Saturday, April 8, 2023 Mahdi Hassanpour
Register Indirect Addressing Mode• In this mode, register is used as a pointer to the data.
MOV A,@Ri ; move content of RAM loc.Where address is held by Ri into A
( i=0 or 1 )MOV @R1,B
In other word, the content of register R0 or R1 is sources or target in MOV, ADD and SUBB insructions.
Example:Write a program to copy a block of 10 bytes from RAM location sterting at 37h to RAM location starting at 59h.
Solution:MOV R0,37h ; source pointerMOV R1,59h ; dest pointer MOV R2,10 ; counter
L1: MOV A,@R0MOV @R1,AINC R0INC R1DJNZ R2,L1
jump
Saturday, April 8, 2023 Mahdi Hassanpour
Indexed Addressing Mode And On-Chip ROM Access
• This mode is widely used in accessing data elements of look-up table entries located in the program (code) space ROM at the 8051
MOVC A,@A+DPTRA= content of address A +DPTR from ROM
Note:Because the data elements are stored in the program (code ) space ROM of the 8051, it uses the instruction MOVC instead of MOV. The “C” means code.
Saturday, April 8, 2023 Mahdi Hassanpour
• Example:Assuming that ROM space starting at 250h contains “Hello.”, write a program to transfer the bytes into RAM locations starting at 40h.
Solution:ORG 0MOV DPTR,#MYDATAMOV R0,#40H
L1: CLR AMOVC A,@A+DPTRJZ L2MOV @R0,AINC DPTRINC R0SJMP L1
L2: SJMP L2;-------------------------------------
ORG 250HMYDATA: DB “Hello”,0
END
Notice the NULL character ,0, as end of string and how we use the JZ instruction to detect that.
Saturday, April 8, 2023 Mahdi Hassanpour
• Example:Write a program to get the x value from P1 and send x2 to P2, continuously .
Solution:ORG 0MOV DPTR, #TAB1MOV A,#0FFHMOV P1,A
L01:MOV A,P1MOVC A,@A+DPTRMOV P2,ASJMP L01
;----------------------------------------------------ORG 300H
TAB1: DB 0,1,4,9,16,25,36,49,64,81
END
Saturday, April 8, 2023 Mahdi Hassanpour
16-bit, BCD and Signed Arithmetic in 8051
Exercise:
Write a program to add n 16-bit number. Get n from port 1. And sent Sum to LCDa) in hexb) in decimal
Write a program to subtract P1 from P0 and send result to LCD(Assume that “ACAL DISP” display A to LCD )
Saturday, April 8, 2023 Mahdi Hassanpour
MUL & DIV
• MUL AB ;B|A = A*BMOV A,#25HMOV B,#65HMUL AB ;25H*65H=0E99
;B=0EH, A=99H• MUL AB ;A = A/B, B = A mod B
MOV A,#25MOV B,#10MUL AB ;A=2, B=5
Saturday, April 8, 2023 Mahdi Hassanpour
Stack in the 8051
• The register used to access the stack is called SP (stack pointer) register.
• The stack pointer in the 8051 is only 8 bits wide, which means that it can take value 00 to FFH. When 8051 powered up, the SP register contains value 07.
7FH
30H
2FH
20H
1FH
17H10H
0FH
07H
08H
18H
00HRegister Bank 0
(Stack )Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM
Saturday, April 8, 2023 Mahdi Hassanpour
Example:MOV R6,#25HMOV R1,#12HMOV R4,#0F3HPUSH 6PUSH 1PUSH 4
0BH
0AH
09H
08H
Start SP=07H
25
0BH
0AH
09H
08H
SP=08H
F3
12
25
0BH
0AH
09H
08H
SP=08H
12
25
0BH
0AH
09H
08H
SP=09H
Saturday, April 8, 2023 Mahdi Hassanpour
LOOP and JUMP Instructions
DJNZ:
Write a program to clear ACC, then
add 3 to the accumulator ten time
Solution:
MOV A,#0;
MOV R2,#10
AGAIN: ADD A,#03
DJNZ R2,AGAING ;repeat until R2=0 (10 times)
MOV R5,A
Saturday, April 8, 2023 Mahdi Hassanpour
• Other conditional jumps :
JZ Jump if A=0
JNZ Jump if A/=0
DJNZ Decrement and jump if A/=0
CJNE A,byte Jump if A/=byte
CJNE reg,#data Jump if byte/=#data
JC Jump if CY=1
JNC Jump if CY=0
JB Jump if bit=1
JNB Jump if bit=0
JBC Jump if bit=1 and clear bit
Saturday, April 8, 2023 Mahdi Hassanpour
SJMP and LJMP:
LJMP(long jump)LJMP is an unconditional jump. It is a 3-byte instruction in which the first byte is the opcode, and the second and third bytes represent the 16-bit address of the target location. The 20byte target address allows a jump to any memory location from 0000 to FFFFH.
SJMP(short jump)In this 2-byte instruction. The first byte is the opcode and the second byte is the relative address of the target location. The relative address range of 00-FFH is divided into forward and backward jumps, that is , within -128 to +127 bytes of memory relative to the address of the current PC.
Saturday, April 8, 2023 Mahdi Hassanpour
CJNE , JNC
Exercise:
Write a program that compare R0,R1.
If R0>R1 then send 1 to port 2,
else if R0<R1 then send 0FFh to port 2,
else send 0 to port 2.
Saturday, April 8, 2023 Mahdi Hassanpour
CALL Instructions
Another control transfer instruction is the CALL instruction, which is used to call a subroutine.
• LCALL(long call)
In this 3-byte instruction, the first byte is the opcode an the second and third bytes are used for the address of target subroutine. Therefore, LCALL can be used to call subroutines located anywhere within the 64K byte address space of the 8051.
Saturday, April 8, 2023 Mahdi Hassanpour
• ACALL (absolute call)
ACALL is 2-byte instruction in contrast to LCALL, which is 13 bytes. Since ACALL is a 2-byte instruction, the target address of the subroutine must be within 2K bytes address because only 11 bits of the 2 bytes are used for the address. There is no difference between ACALL and LCALL in terms of saving the program counter on the stack or the function of the RET instruction. The only difference is that the target address for LCALL can be anywhere within the 64K byte address space of the 8051 while the target address of ACALL must be within a 2K-byte range.
Saturday, April 8, 2023 Mahdi Hassanpour
I/O Port Programming
Port 1 ( pins 1-8 )
• Port 1 is denoted by P1.
– P1.0 ~ P1.7
• We use P1 as examples to show the operations on ports.
– P1 as an output port (i.e., write CPU data to the external pin)
– P1 as an input port (i.e., read pin data into CPU bus)
Saturday, April 8, 2023 Mahdi Hassanpour
A Pin of Port 1
8051 IC
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus
M1
P1.X pinP1.X
TB1
TB2
P0.x
Saturday, April 8, 2023 Mahdi Hassanpour
Hardware Structure of I/O Pin
• Each pin of I/O ports
– Internal CPU bus : communicate with CPU
– A D latch store the value of this pin
• D latch is controlled by “Write to latch”
– Write to latch = 1 : write data into the D latch
– 2 Tri-state buffer :• TB1: controlled by “Read pin”
– Read pin = 1 : really read the data present at the pin
• TB2: controlled by “Read latch”
– Read latch = 1 : read value from internal latch
– A transistor M1 gate
• Gate=0: open
• Gate=1: close
Saturday, April 8, 2023 Mahdi Hassanpour
Tri-state Buffer
Output Input
Tri-state control (active high)
L H Low
Highimpedance (open-circuit)
HH
L H
Saturday, April 8, 2023 Mahdi Hassanpour
Writing “1” to Output Pin P1.X
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus
M1
P1.X pinP1.X
8051 IC
2. output pin is Vcc1. write a 1 to the pin
1
0 output 1
TB1
TB2
Saturday, April 8, 2023 Mahdi Hassanpour
Writing “0” to Output Pin P1.X
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus
M1
P1.X pinP1.X
8051 IC
2. output pin is ground1. write a 0 to the pin
0
1 output 0
TB1
TB2
Saturday, April 8, 2023 Mahdi Hassanpour
Port 1 as Output ( Write to a Port )• Send data to Port 1 :
MOV A,#55H BACK: MOV P1,A
ACALL DELAYCPL ASJMP BACK
– Let P1 toggle.– You can write to P1 directly.
Saturday, April 8, 2023 Mahdi Hassanpour
Reading Input v.s. Port Latch • When reading ports, there are two possibilities :
– Read the status of the input pin. ( from external pin value )• MOV A, PX
• JNB P2.1, TARGET ; jump if P2.1 is not set
• JB P2.1, TARGET ; jump if P2.1 is set
• Figures C-11, C-12
– Read the internal latch of the output port.
• ANL P1, A ; P1 ← P1 AND A
• ORL P1, A ; P1 ← P1 OR A
• INC P1 ; increase P1
• Figure C-17
• Table C-6 Read-Modify-Write Instruction (or Table 8-5)
• See Section 8.3
Saturday, April 8, 2023 Mahdi Hassanpour
Reading “High” at Input Pin
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus
M1
P1.X pin
P1.X
8051 IC
2. MOV A,P1
external pin=High1. write a 1 to the pin MOV
P1,#0FFH
1
0
3. Read pin=1 Read latch=0 Write to latch=1
1
TB1
TB2
Saturday, April 8, 2023 Mahdi Hassanpour
Reading “Low” at Input Pin
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus
M1
P1.X pin
P1.X
8051 IC
2. MOV A,P1
external pin=Low1. write a 1 to the pin
MOV P1,#0FFH
1
0
3. Read pin=1 Read latch=0 Write to latch=1
0
TB1
TB2
Saturday, April 8, 2023 Mahdi Hassanpour
Port 1 as Input ( Read from Port )• In order to make P1 an input, the port must be programmed by writing 1 to
all the bit.
MOV A,#0FFH ;A=11111111B
MOV P1,A ;make P1 an input port
BACK: MOV A,P1 ;get data from P0
MOV P2,A ;send data to P2
SJMP BACK
– To be an input port, P0, P1, P2 and P3 have similar methods.
Saturday, April 8, 2023 Mahdi Hassanpour
Instructions For Reading an Input Port
Mnemonics Examples Description
MOV A,PX MOV A,P2Bring into A the data at P2 pins
JNB PX.Y,.. JNB P2.1,TARGET Jump if pin P2.1 is low
JB PX.Y,.. JB P1.3,TARGET Jump if pin P1.3 is high
MOV C,PX.Y MOV C,P2.4 Copy status of pin P2.4 to CY
• Following are instructions for reading external pins of ports:
Saturday, April 8, 2023 Mahdi Hassanpour
Reading Latch
• Exclusive-or the Port 1 :MOV P1,#55H ;P1=01010101
ORL P1,#0F0H ;P1=11110101
1. The read latch activates TB2 and bring the data from the Q latch into CPU.
• Read P1.0=0
2. CPU performs an operation.
• This data is ORed with bit 1 of register A. Get 1.
3. The latch is modified.
• D latch of P1.0 has value 1.
4. The result is written to the external pin.
• External pin (pin 1: P1.0) has value 1.
Saturday, April 8, 2023 Mahdi Hassanpour
Reading the Latch
D Q
Clk Q
Vcc
Load(L1)
Read latch
Read pin
Write to latch
Internal CPU bus
M1
P1.X pin
P1.X
8051 IC
4. P1.X=12. CPU compute P1.X OR 1
0
0
1. Read pin=0 Read latch=1 Write to latch=0 (Assume P1.X=0 initially)
1
TB1
TB2
3. write result to latch Read pin=0 Read latch=0
Write to latch=1
1
0
Saturday, April 8, 2023 Mahdi Hassanpour
Read-modify-write Feature
• Read-modify-write Instructions– Table C-6
• This features combines 3 actions in a single instruction :1. CPU reads the latch of the port
2. CPU perform the operation
3. Modifying the latch
4. Writing to the pin– Note that 8 pins of P1 work independently.
Saturday, April 8, 2023 Mahdi Hassanpour
Port 1 as Input ( Read from latch )
• Exclusive-or the Port 1 : MOV P1,#55H ;P1=01010101
AGAIN: XOR P1,#0FFH ;complement
ACALL DELAY
SJMP AGAIN
– Note that the XOR of 55H and FFH gives AAH.
– XOR of AAH and FFH gives 55H.
– The instruction read the data in the latch (not from the pin).
– The instruction result will put into the latch and the pin.
Saturday, April 8, 2023 Mahdi Hassanpour
Read-Modify-Write Instructions
ExampleMnemonics
SETB P1.4SETB PX.Y
CLR P1.3CLR PX.Y
MOV P1.2,CMOV PX.Y,C
DJNZ P1,TARGETDJNZ PX, TARGET
INC P1INC
CPL P1.2CPL
JBC P1.1, TARGETJBC PX.Y, TARGET
XRL P1,AXRL
ORL P1,AORL
ANL P1,AANL
DEC P1DEC
Saturday, April 8, 2023 Mahdi Hassanpour
You are able to answer this Questions:
• How to write the data to a pin ?• How to read the data from the pin ?
– Read the value present at the external pin.
• Why we need to set the pin first ?– Read the value come from the latch ( not from the external
pin ) .
• Why the instruction is called read-modify write?
Saturday, April 8, 2023 Mahdi Hassanpour
Other Pins
• P1, P2, and P3 have internal pull-up resisters.
– P1, P2, and P3 are not open drain.
• P0 has no internal pull-up resistors and does not connects to Vcc inside the 8051.
– P0 is open drain.
– Compare the figures of P1.X and P0.X. • However, for a programmer, it is the same to program P0, P1,
P2 and P3.
• All the ports upon RESET are configured as output.
Saturday, April 8, 2023 Mahdi Hassanpour
A Pin of Port 0
8051 IC
D Q
Clk Q
Read latch
Read pin
Write to latch
Internal CPU bus
M1
P0.X pinP1.X
TB1
TB2
P1.x
Saturday, April 8, 2023 Mahdi Hassanpour
Port 0 ( pins 32-39 )• P0 is an open drain.
– Open drain is a term used for MOS chips in the same way that open collector is used for TTL chips.
• When P0 is used for simple data I/O we must connect it to external pull-up resistors.
– Each pin of P0 must be connected externally to a 10K ohm pull-up resistor.
– With external pull-up resistors connected upon reset, port 0 is configured as an output port.
Saturday, April 8, 2023 Mahdi Hassanpour
Port 0 with Pull-Up Resistors
P0.0P0.1P0.2P0.3P0.4P0.5P0.6P0.7
DS5000
8751
8951
Vcc10 K
Port 0
Saturday, April 8, 2023 Mahdi Hassanpour
Dual Role of Port 0
• When connecting an 8051/8031 to an external memory, the 8051 uses ports to send addresses and read instructions.
– 8031 is capable of accessing 64K bytes of external memory.
– 16-bit address : P0 provides both address A0-A7, P2 provides address A8-A15.
– Also, P0 provides data lines D0-D7.
• When P0 is used for address/data multiplexing, it is connected to the 74LS373 to latch the address.
– There is no need for external pull-up resistors as shown in Chapter 14.
Saturday, April 8, 2023 Mahdi Hassanpour
74LS373
D
74LS373ALE
P0.0
P0.7
PSEN
A0
A7
D0
D7
P2.0
P2.7
A8
A15
OE
OC
EA
G
8051 ROM
Saturday, April 8, 2023 Mahdi Hassanpour
Reading ROM (1/2)
D
74LS373ALE
P0.0
P0.7
PSEN
A0
A7
D0
D7
P2.0
P2.7
A8
A12
OE
OC
EA
G
8051 ROM
1. Send address to ROM
2. 74373 latches the address and send to
ROM
Address
Saturday, April 8, 2023 Mahdi Hassanpour
Reading ROM (2/2)
D
74LS373ALE
P0.0
P0.7
PSEN
A0
A7
D0
D7
P2.0
P2.7
A8
A12
OE
OC
EA
G
8051 ROM
2. 74373 latches the address and send to
ROM
Address
3. ROM send the instruction back
Saturday, April 8, 2023 Mahdi Hassanpour
ALE Pin
• The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.– When ALE=0, P0 provides data D0-D7.– When ALE=1, P0 provides address A0-A7.– The reason is to allow P0 to multiplex address and
data.
Saturday, April 8, 2023 Mahdi Hassanpour
Port 2 ( pins 21-28 )• Port 2 does not need any pull-up resistors since
it already has pull-up resistors internally.
• In an 8031-based system, P2 are used to provide address A8-A15.
Saturday, April 8, 2023 Mahdi Hassanpour
Port 3 ( pins 10-17 )• Port 3 does not need any pull-up resistors since it already has
pull-up resistors internally.• Although port 3 is configured as an output port upon reset,
this is not the way it is most commonly used.• Port 3 has the additional function of providing signals.
– Serial communications signal : RxD, TxD ( Chapter 10 )
– External interrupt : /INT0, /INT1 ( Chapter 11 )– Timer/counter : T0, T1 ( Chapter 9 )– External memory accesses in 8031-based
system : /WR, /RD ( Chapter 14 )
Saturday, April 8, 2023 Mahdi Hassanpour
Port 3 Alternate Functions
17RDP3.7
16WRP3.6
15T1P3.5
14T0P3.4
13INT1P3.3
12INT0P3.2
11TxDP3.1
10RxDP3.0
PinFunctionP3 Bit
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