1 comp541 sequential circuits montek singh feb 1, 2007

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COMP541COMP541

Sequential CircuitsSequential Circuits

Montek SinghMontek Singh

Feb 1, 2007Feb 1, 2007

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AdministrativeAdministrative Advance NoticeAdvance Notice

Test: Week of Feb 19-23Test: Week of Feb 19-23 Covers material through Thursday 2/15Covers material through Thursday 2/15

Short review session on 2/15 in classShort review session on 2/15 in class

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TopicsTopics Sequential CircuitsSequential Circuits

LatchesLatches Flip FlopsFlip Flops

Verilog for sequential designVerilog for sequential design

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Sequential CircuitsSequential Circuits StateState of system is info stored of system is info stored That, and inputs, determine outputsThat, and inputs, determine outputs

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Types of Sequential CircuitsTypes of Sequential Circuits SynchronousSynchronous

State changes synchronized by one or more clocksState changes synchronized by one or more clocks

AsynchronousAsynchronous Changes occur independentlyChanges occur independently

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Clocking of SynchronousClocking of Synchronous Changes enabled by clockChanges enabled by clock

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ComparisonComparison SynchronousSynchronous

Easier to analyze because can factor out gate delaysEasier to analyze because can factor out gate delays Set clock so changes occur before next clock pulseSet clock so changes occur before next clock pulse

AsynchronousAsynchronous Potentially fasterPotentially faster Harder to analyze (more subtle, but more powerful!)Harder to analyze (more subtle, but more powerful!)

Most of my research!Most of my research!

Will look mostly at synchronousWill look mostly at synchronous

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Basic StorageBasic Storage Apply low or high for longer than tApply low or high for longer than tpdpd

Feedback will hold valueFeedback will hold value

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SR (set-reset) LatchesSR (set-reset) Latches Basic storage made from gatesBasic storage made from gates

•S & R both 0 in “resting” state•Have to keep both from 1 at same time

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OperationOperation

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LatchLatch Similar – made from NANDsSimilar – made from NANDs

RS

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Add Control InputAdd Control Input Gates when state can changeGates when state can change

Is there latch w/ no illegal state?Is there latch w/ no illegal state?

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D-type LatchD-type Latch No illegal stateNo illegal state

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Transparency of latchesTransparency of latches As long as C (the As long as C (the control control )) isis high, state can high, state can

changechange This is called This is called transparencytransparency

What’s problem with that?What’s problem with that?

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Effects of TransparencyEffects of Transparency Output of latch may feed backOutput of latch may feed back

May cause further state changesMay cause further state changes Behavior depends on actual gate delaysBehavior depends on actual gate delays

Want to change latch state only Want to change latch state only onceonce Behavior should depend only on logical valuesBehavior should depend only on logical values

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Solution to Transparency: Flip-Solution to Transparency: Flip-FlopsFlops Flip-Flops:Flip-Flops:

Ensure output changes only once per clock cycleEnsure output changes only once per clock cycle

Two commonly-used types of flip-flops:Two commonly-used types of flip-flops: Master-SlaveMaster-Slave

Use a sequence of two latchesUse a sequence of two latches Edge-TriggeredEdge-Triggered

Implementation very different from latchesImplementation very different from latches

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1. Master-Slave Flip-Flop1. Master-Slave Flip-Flop Either Master or Slave is enabled, not bothEither Master or Slave is enabled, not both

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Timing DiagramTiming Diagram

Trace the behaviorTrace the behavior Note illegal stateNote illegal state Is it transparent?Is it transparent?

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Have We Fixed the Problem?Have We Fixed the Problem? Output no longer transparentOutput no longer transparent

Combinational circuit can use last valuesCombinational circuit can use last values New inputs appear at latchesNew inputs appear at latches Not sent to output until clock lowNot sent to output until clock low

But changes at input of FF when clock high do But changes at input of FF when clock high do trigger next statetrigger next state Is this a problem?Is this a problem?

As clock faster, more problemsAs clock faster, more problemsHave to guarantee circuit settles while clock lowHave to guarantee circuit settles while clock low

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2. Edge-Triggered Flip-Flops2. Edge-Triggered Flip-Flops New state latched on New state latched on clock transitionclock transition

Low-to-high or high-to-lowLow-to-high or high-to-low+ve edge-triggered, -ve edge-triggered+ve edge-triggered, -ve edge-triggeredAlso: dual-edge-triggeredAlso: dual-edge-triggered

Changes when clock high are ignoredChanges when clock high are ignored

Note: Master-Slave sometimes called Note: Master-Slave sometimes called pulse pulse triggeredtriggered

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D-Type Edge-TriggeredD-Type Edge-Triggered

Is this +ve or –ve edge-triggered?Is this +ve or –ve edge-triggered?

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Standard Symbols – LatchesStandard Symbols – Latches

Circle at input indicates negationCircle at input indicates negation

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Symbols – Master-SlaveSymbols – Master-Slave Inverted ‘L’ indicates postponed outputInverted ‘L’ indicates postponed output Circle indicates whether enable is positive or Circle indicates whether enable is positive or

negativenegative

JK: like an SR flip-flop, but:JK: like an SR flip-flop, but: If J=K=1, output is toggledIf J=K=1, output is toggled Can make a toggle flip-flop (T flip-flop) from a JKCan make a toggle flip-flop (T flip-flop) from a JK

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Symbols – Edge-TriggeredSymbols – Edge-Triggered

Arrow indicates edge triggerArrow indicates edge trigger

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Direct InputsDirect Inputs Use to force Set/Reset independent of clockUse to force Set/Reset independent of clock

Direct set or Direct set or presetpreset Direct reset or Direct reset or clearclear

Often used for power-up resetOften used for power-up reset

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Flip-Flop TimingFlip-Flop Timing

Setup time – time that D must be steady Setup time – time that D must be steady before clock edgebefore clock edge

Hold time – time that D must continue to be Hold time – time that D must continue to be steady after clock edgesteady after clock edge

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Propagation DelayPropagation Delay Propagation delay – time after edge until Propagation delay – time after edge until

output becomes availableoutput becomes available

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Clock Pulse RequirementsClock Pulse Requirements Determine the max clock frequencyDetermine the max clock frequency

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In Passing: Clock Gating and In Passing: Clock Gating and SkewSkew Can ‘gate’ or freeze clocksCan ‘gate’ or freeze clocks

……to keep any FF from changing statesto keep any FF from changing states Can help reduce power consumptionCan help reduce power consumption

However, can cause clock skewHowever, can cause clock skew Clock edges at different times on different FFsClock edges at different times on different FFs

Clock skew also caused by wire lengths over Clock skew also caused by wire lengths over chip chip

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Next TimeNext Time State DiagramsState Diagrams

Sec. 6-4 and 6-5Sec. 6-4 and 6-5 Pages 258-275Pages 258-275 Skip last part of 6-5Skip last part of 6-5

Verilog to describe state machinesVerilog to describe state machines