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DELTA-SIGMA ALGORITHMIC ANALOG-TO-DIGITAL CONVERSION

GrantMulliken��� �

, FarhanAdil��� �

, GertCauwenberghs�, andRomanGenov

��AdaptiveMicrosystemsLaboratory, ECEDept.,JohnsHopkinsUniversity, Baltimore,MD 21218�

BME Dept.,JohnsHopkinsUniversitySchoolof Medicine,Baltimore,MD 21205�Schoolof ElectricalEngineering,Georgia Tech,Atlanta,GA 30332

E-mail:�grant,farhan,gert,roman� @bach.ece.jhu.edu

ABSTRACT

Delta-sigmamodulationfor analog-to-digitalconversionre-solvesa numberof bits logarithmicin thenumberof mod-ulation cycles, and linear in modulationorder. As an al-ternative to higher-ordernoiseshaping,we presentan al-gorithmicschemethatiteratively resamplesthemodulationresidue,by feeding the integrator output back to the in-put. This yields a bit resolutionlinear in the numberofcycles,similar to analgorithmicanalog-to-digitalconverter.The schemesimplifies the designof the digital decimatorto a singleshifting counter, andavoids interstagegain er-rors in conventionalalgorithmicanalog-to-digitalconvert-ers.Experimentalresultsfrom anintegratedCMOSarrayof128convertersshow theutility of thedesignfor large-scaleparallelquantizationin digital imagingandhybrid analog-digital computing.

1. INTRODUCTION

Delta-sigma( �� ) modulationhasemergedasthearchitec-ture of choice for high-resolutionanalog-to-digital(A/D)conversionusinglow-precisionanalogcomponents[1]. Theincreasedresolutioncomesat the expenseof reducedcon-versionbandwidthor increasedclock speeddue to over-sampling,andincreaseddigital complexity to decimatethemodulatoroutputstream.For very low bandwidthapplica-tions,lowestdigital complexity isachievedwith afirst-order�� incrementalconverter[2], wherea counterimplementsarectangulardecimationfilter. Higher-order �� incremen-tal converters[3] arecapableof attaininghigherconversionbandwidth,usingadditionalanaloganddigital circuitry. Al-ternatively, higherbandwidthcanbe obtainedfrom a first-orderincrementalconverterby furtherrefiningthemodula-tion residueon theintegratorat theendof conversionusinga Nyquist A/D converter[4, 5, 6]. Theprinciple is similarto dual-quantizationoversampledconverters[7, 8], except

This work was supported by ONR N00014-99-1-0612 andONR/DARPA N00014-00-C-0315.ChipfabricationwasprovidedthroughMOSIS.

S/H

+� -MUX Qw� y u�

x�(b)�

A

D

(a)�

COUNTER�

+� -Qw� y u�

A�

DS/H

RST

RST RST

RST SHIFT

COUNTER�

Fig. 1. (a) First-order �� incrementalA/D converter. (b)�� algorithmic A/D converter, with residueresamplingacrossthe accumulator, and shifting counterfor the deci-mator.

thesecondquantizeroperatesat theconversionrateandre-quiresno decimation.

The presentedarchitectureuses the samefirst-ordermodulator, with virtually no overheadin analoganddigitalhardware,to incrementallyconvert the modulationresidueof precedingincrementalconversion. By using the samesignalpathin ratio-insensitivemanner, precisematchingbe-tweenmultiplequantizationresultsis obtained.Matchingisaconcernin theprecisionof multiple-quantizationoversam-pleddataconverters[9], usuallyrequiringcompensationinthe digital domain[10]. The presentedschemeis similarto algorithmic A/D conversion,but avoids interstagegainerrorswhen preciselyratioedanalogcomponentsare notavailable.Very high integrationdensitycanbeachievedbyvirtue of thesimplemodulatoranddecimatorarchitecture.

2. �� INCREMENTAL A/D CONVERSION

For clarity of expositionwe startthe formulationwith thatof thefirst-orderincrementalA/D converter[2], depictedin

Figure1(a).A first-order�� modulatorconvertsananalogsequence��� ��� into abitstream��� ��� , usinga‘resetable’(RST)analogaccumulator�

� ����� � (1)�� �� "!#���

�� ���$ &%(')��� �*�,+-��� �*�).0/�1�2�3/#454#4768+9! (2)�

� 6: "!#����� 6;�,+(%<��� 6=� (3)

andasingle-bitquantizer

�>� �?�@� +A! (4)��� �*�@� BDCFEHGI'�� ���J.K/L�1�M!N/54#4#4D6O4 (5)

A binary counteraccumulatesthe bits1 ��� ��� to produceadecimatedoutput.Therectangulardecimationwindow, andinitial resetof the accumulator, avoid tonesin the quanti-zation noisespectrumat DC input that are characteristicof a conventionalfirst-order �� modulatorwith lowpassdecimationfilter [2]. The quantizationerror (conversionresidue)is directly given by the final accumulatorvalue�� 6P "!#� , asverifiedby summing(2) and(3) over � :QR S T�U ��� ���V�

QXW�YR S T�U ��� �*�$+ !%�� 6P "!#�V4 (6)

For aninput ��� ��� within theconversionrange �Z+A!H/#!#� (in di-mensionlessunits),

�� 6M [!\� in (3) is boundedby therange�Z+]%K/D%^� , andaworst-caseresolutionof _F`HEbaH'c6d. bits is war-

ranted2.Higher resolutionat lower oversampling6 canbe ob-

tained using higher-order incrementalconversion [3]. Alower-complexity alternative is presentednext.

3. �� ALGORITHMIC A/D CONVERSION

TheconversionresidueYe�� 68 f!#� in (6) is convertedfur-

ther into digital form to obtain higher resolution. As inothermultiple-quantizationoversampledconverters[3]-[8],gain mismatchbetweenquantizationsignalpathsis a lim-iting factorin theprecisionavailable[9]. Ratio-insensitivematchingis achievedby resamplingtheresiduethroughthesamesignalpathasusedfor accumulation(2), andemploy-ing thesamemodulatorto convert theresidue.

Assumea constantinput (or its average)g presentedtothe incrementalconverter for 6 initial cycles, ��� ���h�ig ,���2�$/#454#476j+9! ,QR S T�U �>� ���V�26Pgk+ !%

�� 6P 2!\�>4 (7)

1 lKm-n � correspondsto logic 0 for notationalconvenience.2Notethat the lastmodulationcycle (3) contributesonefull bit of res-

olution, since oKp qsr for qutwv in (2) is boundedby��x

in amplitude.The extra zero-inputmodulationcycle (3) canbe avoidedby quantizingoKp qsr#y x{z p qsr insteadof oKp qsr in (5).

C1 C2u

y| w}

(a)~

C1 C2

SAMPLE AND RESET�

C1

SAMPLE�

uC1 C2

ACCUMULATE�

y| w}

C1 C2

RESIDUE FEEDBACK�

w}α

(b)~

C2

S/H�

u

Fig. 2. Invertable, resetableanalog accumulator. (a) Cir-cuit diagram. (b) Operationalmodes.

At theendof conversion,theresidue

�� 68 �!#� is fed back

to theinput for subsequentincrementalconversionover 6��additionalcycles, �V��� �����8�

�� 6� M!#� , �����$/54#45476��I+�! ,

where� representstheresidueresamplinggain.ThusQ��R S T�U � � � ���>�26 � ��� 6P 2!\�,+ !%

� � � 6 � 2!\� (8)

which under the matchingcondition %�����! combineswith (7) to cancelthefirst residue

�� 6P 2!\� :

6 � QR S TIU ��� ���b Q��R S T�U � � � ���>��6�6 � gk+ !%

� � � 6 � 2!\��4 (9)

Theleft-handsideof (9) is readilyavailablein digital form,andtheright-handtermsconformto (6)with effective 6�6�� -level resolution. Therefore,the residueconversion(8) en-hancestheresolutionof (7) by anextra _F`HE a 'c6���. bits. Thealgorithmicrecursioncanbecontinuedto produce_F`HEHab'c6d.bits for every conversionof the precedingresidueover 6incrementalcycles. The recursioncorrespondsto a radix-6 algorithmicA/D converter, but without theneedfor 6 -ratioedanalogcomponents.

The matchingcondition %��j��! for ratio-insensitiveoperationis metusinganinvertablecircuit topologyfor theanalogaccumulator, describednext.

4. IMPLEMENTATION

Thehardwarecomplexity of the �� algorithmicA/D con-verter, depictedin Figure 1(b), is essentiallyidentical to

that of the �� incrementalconverter in Figure1(a). Theaccumulatoris extendedto samplethe residuein ratio-insensitive manner, andthecounteris extendedto shift bitsin betweenresidueconversionsfor proper scaling in thedecimation.

4.1. Invertable, Resetable Analog Accumulator

Critical to attainingratio-insensitivesamplingof theresidueis thedesignof theaccumulator. A simplecircuit achievingmultipleobjectivesis depictedin Figure2 (a),with differentmodesof operationillustratedin Figure2 (b). The circuitis shown with minimum numberof componentsusing aninverting amplifier, but canbe directly extendedto differ-entialdesignsfor higherresolution.Correlateddoublesam-pling (CDS)in theaccumulationof thedifference�1� ���#+u�>� ���accordingto (2) offerstheadvantageof !��N� noiseandoff-set cancellation. The switched-capacitoraccumulatorhasratio-dependentgain %-�f� Y �N� a thatis proneto mismatch;however thismismatchis immaterialin theoperationof thefirst-ordermodulatorwith single-bit quantizer. For ratio-insensitivesamplingof theresidue,thesignalandfeedbackpathof theaccumulatoris invertedby interchangingthe � Yand � a componentsin the circuit topology, shown in Fig-ure2 (b). As a result,the matchingcondition %��"��! be-tween(7) and(8) is satisfiedindependentof � Y and � a , toa precisionlimited by the finite gain of the amplifier, andnoiseandchargeinjectionin thesampling.

4.2. Decimating Shifting Counter

For every algorithmic iteration, the precedingdecimatedoutputneedsto bescaledbyafactor6 , thenumberof incre-mentalcyclesin the residueconversion,prior to continuedcounting. It is particularlyconvenientto assume6 to beradix-� , sothatthescalingis simply performedby a binaryshift in the decimationcount,assuggestedin Figure1(b).A shift registeris readily incorporatedin a binary counter,with little overheadin the circuit complexity of the imple-menteddecimator.

5. EXPERIMENTAL RESULTS FROMINTEGRATED A/D ARRAY

To demonstratethe advantagesof the approachto large-scale,denselyintegratedquantizationin an embeddedap-plication, we implementeda bankof 128 �� algorithmicconvertersas part of a mixed-signalcomputationalarray.The �N�N�(��!���� array performsexternally digital matrix-vector multiplication using internally analogelementsforvery large energeticefficiency ( !�� Y a multiply-accumulatesperWattof power)[11]. Thearraycoreperformsanalogac-cumulationof binary-binarypartialproducts,requiringrow-parallelA/D conversionfor eachof the 128 outputvector

Fig. 3. Micrograph of mixed-signalarray processor[12],containing an array of �H���(��!��N� CID/DRAM multiply-accumulatecells [11], and a row-parallel bankof !��N� al-gorithmic ��� A/D converters. Die sizeis  ¢¡�¡£� ¢¡�¡ in0.5 ¤ m CMOStechnology.

components.Themicrographof the integratedsystem[12]is shown in Figure3. Eachof the128A/D channelsmeasure14 ¤ m by 850 ¤ m.

To maximizeintegrationdensity, theanalogpathof the�� algorithmic architectureof Figure 1(b) usessingle-stagecascodednMOSinvertingamplifiersthroughout,withnominalgainof +] N�N� . Capacitances� Y and � a arenom-inally 0.25 pF and 0.5 pF, respectively, with %��¥�34 � .Sample-and-holdand comparatorblocks are implementedin standardswitched-capacitorcircuitry, with CDS !��N�noiseandoffsetcompensation.Dynamiclogic implementsbinarycounterandregisters.

Exampleconversionwaveformsfrom thefabricatedar-ray are illustratedin Figure 4. Least-squaresfits of inte-gral quantizationerror observed over one channelof thearray, configuredboth for 8-bit incrementaland algorith-mic �� conversion, are within the LSB level as shownin Figure 5. However, incrementalconversion requires��¦§ �!<�:�N�b¨ cycles,while 2-stepalgorithmicconversiontakes �©�ª'*��«b <!�.©�2 �¬ cycles.With a300nsclockin 2-step8-bit algorithmicmode,the128-channelA/D bankdelivers12.8 Msamples/sat 2.6 mW power dissipation,includingdecimation.

Resolutionslarger than10-bit requirehigher-gain am-plifiers at the costof decreasedintegrationdensityandin-creasedpowerdissipation.In digital imagingandotherinte-gratedsensingmodalities,maintaininghigh spatialresolu-tion is usuallyamorestringentrequirementthanincreasingamplituderesolution.

Note that matchingis at stake even at low (8-bit) res-

yy

uu

ww

INPUT RESIDUE

Fig. 4. Observedwaveformsfor two-step �� algorith-mic A/D conversion. Top: Integrator voltage

�� ��� . Cen-

ter: Sample-and-holdvoltage �1� ��� . Bottom: Outputbits �>� ���prior to decimation.

olution. Precisematchingbetweencapacitorswith up to12-bit uncalibratedprecisioncanbeachievedthroughcare-ful layout in centroidgeometry, but not within dimensionspitch-matchedto, say, a45 ­ (14 ¤ m) photosensorpixel.

6. CONCLUSION

Theproposedtechniquecombinesadvantagesof �� mod-ulationandalgorithmic(cyclic) A/D conversionin asingle,simplearchitecture.Both are includedasspeciallimitingcases:a singlealgorithmic iterationreducesto �� incre-mentalconversion,and 6��P� cyclesper iterationyield aratio-insensitiveform of algorithmicA/D conversion.

The reducedhardwarecomplexity and improved com-ponenttoleranceof the architectureoffer a major advan-tagein integratedapplicationscalling for large-scalepar-allel quantizationat low to mediumresolution(8 to 12 bits)but very high integrationdensities,with a potentialfor ex-tremely large combinedquantizationthroughputs(Gsam-ple/srangeat mW power levels). Bandwidthcanbetradedfor resolution in reconfigurablemannerthrough externalcontrol of clock waveforms. Ratio-insensitive matchingmakes the architectureespeciallysuited for applicationsof integrated digital acquisition in spatial sensorarrays.An 128-elementintegratedarray prototypedemonstratedtheprinciplefor applicationsin mixed-signalanalog-digitalcomputing[12].

7. REFERENCES

[1] J.C.CandyandG.C. Temes,“OversampledMethodsfor A/D andD/A Conversion,” in OversampledDelta-SigmaData Converters,IEEEPress,pp1-29,1992.

1.5 2 2.5 3 3.5−0.02

−0.01

0

0.01

0.02

Analog input (V)

Qua

ntiz

atio

n E

rror

(V

)

+1 LSB

−1 LSB

256 incremental

1.5 2 2.5 3 3.5−0.02

−0.01

0

0.01

0.02

Analog input (V)

Qua

ntiz

atio

n E

rror

(V

)

+1 LSB

−1 LSB

16+16 algorithmic

Fig. 5. Integral quantizationresidue, recordedfroma singlechannelof the VLSI A/D array in Figure 3, configured for8-bit conversion. Top: �� incrementalconversion ( 6®��N�N� ). Bottom: �� algorithmic A/D conversion ( 6��¯!5� ,2-step).

[2] J. Robert,G.C. Temes,V. Valencic,R. Dessoulavy, andP. Deval,“A 16-Bit Low-VoltageCMOSA/D Converter,” IEEEJ. Solid-StateCircuits,vol. SC-22, pp157-163,1987.

[3] O.J.A.P. Nys andE. Dijkstra, “On ConfigurableOversampledA/DConverters,” IEEE J. Solid-StateCircuits,vol. 28 (7), pp 736-742,1993.

[4] C. Jansson,“A High-Resolution,Compact,andLow-Power ADCSuitablefor Array Implementationin StandardCMOS,” IEEE T.CircuitsandSystemsI, vol. 42 (11),pp904-912,1995.

[5] R. Harjani andT.A. Lee, “FRC: A Methodfor ExtendingtheRes-olution of NyquistRateConvertersUsingOversampling,” IEEE T.CircuitsandSystemsII, vol. 45 (4), pp482-494,1998.

[6] P. Rombouts,W. De Wilde, andL. Weyten, “A 13.5-b1.2-V Mi-cropower ExtendedCountingA/D Converter,” IEEE J. Solid-StateCircuits,vol. 36 (2), pp 176-183,2001.

[7] T. Hayashi,Y. Inabe,K. Uchimura,T. Kimura,“A MultistageDelta-SigmaModulatorwithout DoubleIntegrationLoop,” ISSCCTech.Dig. Pap., vol. 39, pp182-183,1986.

[8] T.C.LeslieandB. Singh,“An ImprovedSigma-DeltaModulatorAr-chitecture,” Proc.IEEEInt. Symp.CircuitsandSystems(ISCAS’90),pp372-375,1990.

[9] D.B. Ribner, “A Comparisonof Modulator Networks for High-Order OversamplingSigma-DeltaAnalog-to-Digital Conversion,”IEEE T. CircuitsandSystems, vol. 38, pp145-159,1991.

[10] G. CauwenberghsandG.C.Temes,“Adaptive Digital CorrectionofAnalog Errorsin MASH ADCs — Part I. Off-Line andBlind On-Line Calibration,” IEEE Trans.CircuitsandSystemsII , vol. 47 (7),pp.621-628,July 2000.

[11] R. Genov andG. Cauwenberghs,“Charge-ModeParallelArchitec-ture for Matrix-Vector Multiplication,” IEEE Trans. Circuits andSystemsII , vol. 48 (10),Oct.2001.

[12] R. Genov, G. Cauwenberghs,G. Mulliken,andF. Adil, “A 5.9mW6.5GMACSCID/DRAM Array Processor,” submitted.