am a lin

AAPCS GC391/EEE GC391/INSTR GC391

BITS-Pilani Goa Campus

Digital Electronics and Computer Organization (DECO)

CS GC391/EEE GC391/INSTR GC391

1

Lecture-1

A.Amalin Prince



Objective : Introduction to Digital Systems and Characteristics of Digital ICs

2

03-08-07



Digital and Analog Quantities



The Digital Advantage



An Analog Electronic System



A system using Digital and Analog

Methods



Advantages of Digital Techniques

The devices used in digital circuits operate only in one of the two states, resulting in a very simple operation

Requires Boolean Algebra which is very easy to understand

Requires basic concepts of electric network analysis

A large no. of ICs. are available for performing

various operations. These are highly reliable, accurate and speed of operation is very high



Contd..

The effect of fluctuations in the

characteristics of the components, ageing of

the components, temperature and noise is

very small in digital circuits.

Digital circuits have capability of memory

which makes these circuits highly suitable for

computers, calculators, wrist watches etc.

Most Digital Devices are programmable

Cost is very less

Storage and Data transfer is easy.



Applications of Digital Circuits

Communications

Business Transactions

Traffic Control

Space guidance

Medical Treatment

Internet

Weather monitoring etc, etc….



Levels of Integration



Characteristics of Digital ICs

Logic Level

Fan-out

Fan-in

Power Dissipation

Propagation delay

Noise Margin



Logic Families

Digital Integrated circuits are classified not

only by their complexity or logical operation

but also by the specific circuit technology to

which they belong. The circuit technology is

referred to as a Digital Logic Family



Logic Families

RTL Resister-Transistor Logic

DTL Diode-Transistor Logic

TTL Transistor-Transistor Logic

ECL Emitter-coupled Logic

MOS Metal-Oxide Semiconductor

CMOS Complementary Metal-Oxide

Semiconductor



Voltage ranges of logic inputs for positive logic.



Example



Fan-Out

Fan-out: The no. of standard loads that can be

connected to the output of the gate without

degrading its normal operation.

Unit: number

Standard Load: The amount of current needed

by an input of another gate in the same logic

family.



Calculated from the ratio:

whichever is smaller

orOH OL

IH IL

I II I



Fan-In

Fan-In: The number of inputs available in a

Gate

Unit: number



Power Dissipation

It represents the amount of power needed by

the gate.

It refers to the power delivered to the gate

from the power supply.( It does not include

the power delivered from another gate)

Unit: mW

Calculated from :( ) ( )

( )where

2

D avg CC avg CC

CCH CCL

CC avg

P I V

I II

= ×

+=



Propagation delay

It is the average transition delay time for the

signal to propagate from the input to the

output when the binary signal changes in

value.

Unit: ns.



Propagation

delay times



Noise Margin

It is the maximum noise voltage that can be

added to an input signal of a digital circuit

without causing an undesirable change in the

circuit output.

Noise:

• AC noise

• DC noise



Noise effects. (a) Interconnection of two gates with induced noise. (b) Noise margins.



Noise margin is

Smaller of these will be the noise margin

or OH IH IL OL

V V V V− −



The End





1

Lecture-2

A.Amalin Prince



Objective : Number Systems, Codes, Boolean Algebra andLogic Gates

2

06-08-07



Number Systems

Decimal

Binary

Octal

Hexadecimal



Number Conversion



Basic Arithmetic Operations

Addition

Subtraction

Multiplication

Division



Signed numbers and Complements

Addition and Subtraction with r’s-

Complements and (r-1)’s Complements

Where r is the base or radix of the number system.



CODES

Weighted decimal codes

Non-weighted decimal codes

Unit-Distance codes

Alphanumeric codes

Error detecting codes



Weighted decimal codes

Binary Coded Decimal : BCD

BCD are decimal numbers not binary although they use bit in their representation

BCD Arithmetic

Why Weighted?

The corresponding decimal digit is easily determined by adding the weights associated with

1’s in the code group.



Other BCD Codes

1 1 1 11 1 1 11 0 0 19

1 0 0 01 1 1 01 0 0 08

1 0 0 11 1 0 10 1 1 17

1 0 1 01 1 0 00 1 1 06

1 0 1 11 0 1 10 1 0 15

0 1 0 00 1 0 00 1 0 04

0 1 0 10 0 1 10 0 1 13

0 1 1 00 0 1 00 0 1 02

0 1 1 10 0 0 10 0 0 11

0 0 0 00 0 0 00 0 0 00

7 5 3 -68 4 -2 -15 4 2 12 4 2 18 4 2 1

(BCD)

Decimal

Digit



Non-weighted decimal codes

101001 1 0 01 0 0 19

100101 0 1 11 0 0 08

100011 0 1 00 1 1 17

011001 0 0 10 1 1 06

010101 0 0 00 1 0 15

010010 1 1 10 1 0 04

001100 1 1 00 0 1 13

001010 1 0 10 0 1 02

000110 1 0 00 0 0 11

110000 0 1 10 0 0 00

2-out-of-5-code*Excess-3

Reflected Code

8 4 2 1

(BCD)

Decimal

Digit

* Except for 0, it is a weighted code having the weights 74210

Self

Complementing



U.S. Postal Service bar code corresponding to the ZIP code 14263-1045.



Unit-Distance Codes Binary-to-Gray Code Conversion

The most significant bit (left-most) in the Gray code is the same as the corresponding MSB in

the binary number.

Going from left to right, add (or Ex-OR) each adjacent pair of binary code bits to get the next

Gray code bit. Discard carries.

For example conversion from 10110 to Gray is as

follows 1 0 1 1 0

1 1 1 0 1

Binary

Gray



Unit-Distance Codes Gray-to-Binary Code Conversion

The most significant bit (left-most) in the Binary number is the same as the corresponding MSB in

the Gray code.

Add (or Ex-OR) each binary code bit generated to the Gray code bit in the next adjacent position.

Discard carries.

For example conversion from 11011 to Gray is as

follows 1 1 0 1 1

1 0 0 1 0

Gray

Binary



Unit-Distance Codes

1 0 0 01 1 1 1150 1 0 00 1 1 17

1 0 0 11 1 1 0140 1 0 10 1 1 06

1 0 1 11 1 0 1130 1 1 10 1 0 15

1 0 1 01 1 0 0120 1 1 00 1 0 04

1 1 1 01 0 1 1110 0 1 00 0 1 13

1 1 1 11 0 1 0100 0 1 10 0 1 02

1 1 0 11 0 0 190 0 0 10 0 0 11

1 1 0 01 0 0 080 0 0 00 0 0 00

Gray

Code

BinaryDecimal

Digit

Gray

Code

BinaryDecimal

Digit



Angular position encoders. (a) Conventional binary encoder. (b) Gray code encoder.



Angular position encoders with misaligned photosensingdevices. (a) Conventional binary encoder. (b) Gray code encoder.



Alphanumeric codes

ASCII Code



Error detecting codes

Parity Code

Hamming Code etc..



Logic

Gates



Boolean Algebra

Boolean Algebra is used to simply/rearrange

Boolean equation to make simple logic

circuit.



Laws of Boolean Algebra

Commutative Laws

Law 1: A+B = B+A Law 2: AB = BA

Associative Laws

Law 1: A+(B+C) = (A+B)+C Law 2: A(BC)= (AB)A

Distributive Laws

Law : A(B+C) = AB+AC



(AB)+(AC)=A(B+C)(A+B)(A+C)=A+BC8.

A(A+B)=ABAbsorptionA+AB=A+B7.

A(A+B)=AAbsorptionA+AB=A6.

InvolutionA=A5.

A.A=AIdempotentA+A=A4.

A.A=0ComplementaryA+A=13.

A.0=0A+1=12.

A.1=AA+0=A1.

Rules (Dual)LawRulesNo.



Duality Theorem

The duality theorem says that, starting with a

Boolean relation, you can derive another

Boolean relation by

Changing each OR sign to an AND sign

Changing each AND sign to an OR sign

Complementing any 0 or 1 appearing in the expression



Theorems

Consensus theorem

Law : AB+AC+BC = AB+AC

Dual of Consensus theorem

Law : (A+B)(A+C)(B+C) = (A+B)(A+C)

DeMorgan’s

Law 1: A.B = A+B Law 2: A+B = A.B



Operator Precedence

Parentheses

NOT

AND

OR



Reduce the following

1. F XY XYZ XY Z XYZ= + + +

2. AB A AB+ +

3. ( )AB AC ABC AB C+ + +



The End





1

Lecture-3

A.Amalin Prince



Objective : Simplification of Boolean functions (Gate Level Minimization)

2

08-08-07



Combinational circuits can be specified in

one of the following ways

A set of statements

Boolean expression

Truth table



Canonical and Standard Forms

Minterm or Standard product

Maxterm or Standard sum



Minterms and Maxterms for three binary variables

M7X’+Y’+Z’m7XYZ111

M6X’+Y’+Zm6XYZ’011

M5X’+Y+Z’m5XY’Z101

M4X’+Y+Zm4XY’Z’001

M3X+Y’+Z’m3X’YZ110

M2X+Y’+Zm2X’YZ’010

M1X+Y+Z’m1X’Y’Z100

M0X+Y+Zm0X’Y’Z’000

DesignationTermDesignationTermZYX

MaxtermsMinterms



Function table of three variables

11111

01011

11101

00001

10110

00010

10100

00000

Function F2Function F1RQP



Sum of Minterms (SOP form)

Product of Maxterms (POS form)

2 (1,3,5,7)F m=∑

1 (0,1, 2,3, 4)F M= ∏

1 (5,6,7)F m=∑

2 (0,2,4,6)F M= ∏

SOP

POS

Conversion between canonical forms



Convert the given expression in canonical

SOP form

Y=AC+AB+BC

Y=ABC+ABC’+AB’C+AB’C’

Convert the given expression in canonical

POS form

Y=A(A+B)(A+B+C)

Y=(A+B+C)(A+B’+C)(A+B+C’)(A+B’+C’)

Try yourself

AAP



Digital DesignOptimizations and

Tradeoffs



Introduction We now know how to build digital circuits

How can we build better circuits?

Let’s consider two important design criteria Delay – the time from inputs changing to new correct stable output

Size – the number of transistors

For quick estimation, assume

Every gate has delay of “1 gate-delay”

Every gate input requires 2 transistors

Ignore inverters16 transistors

2 gate-delays

F1

wxy

wxy

F1 = wxy + wxy’

(a)

4 transistors

1 gate-delay

F2

F2 = wx

(b)

w

x

si

= wx(y+y’) = wx

Transforming F1 to F2

represents an optimization:

Better in all criteria of interest

z

e

(c)

20

15

10

5(t

r

t

ors)

F1

F2

1 2 3 4delay (gate-delays)

siz

e(t

ran

sis

tors

)



Introduction

Tradeoff

Improves some, but worsens other, criteria of interest

z

e

Transforming G1 to G2

represents a tradeoff: Some

criteria better, others worse.

14 transistors

2 gate-delays

12 transistors

3 gate-delays

G1 G2

w w

x

y

z

x

w

y

zG1 = wx + wy + z G2 = w(x+y) + z

20

15

10

5

G1G2

1 2 3 4delay (gate-delays)

siz

e(t

ran

sis

tors

)



Introduction

We obviously prefer optimizations, but often

must accept tradeoffs

You can’t build a car that is the most comfortable, and has the best fuel efficiency, and is the fastest –

you have to give up something to gain other things.

si

z

e

ansis

si

delay

z

e

si

delay

z

e

OptimizationsTradeoffs

All criteria of

interest

are improved (or at

least kept the same)

Some criteria of

interest are improved,

while others are

worsenedsiz

e

siz

e



Combinational Logic Optimization and Tradeoffs Two-level size optimization using

algebraic methods

Goal: circuit with only two levels (ORedAND gates), with minimum transistors

Though transistors getting cheaper

(Moore’s Law), they still cost something

Define problem algebraically

Sum-of-products yields two levels

F = abc + abc’ is sum-of-products; G =

w(xy + z) is not.

Transform sum-of-products equation to have fewest literals and terms

Each literal and term translates to a gate

input, each of which translates to about

2 transistors

Ignore inverters for simplicity

F = xyz + xyz’ + x’y’z’ + x’y’z

F = xy(z + z’) + x’y’(z + z’)

F = xy*1 + x’y’*1

F = xy + x’y’

0

1

x’ y’

n

y’

x’

0

1

m

m

n

n

F

0

1

y

m

y

x

x

F

x

y

x’

y’

m

n

4 literals + 2 terms = 6 gate inputs

6 gate inputs = 12 transistors

Note: Assuming 4-transistor 2-input AND/OR circuits;

in reality, only NAND/NOR are so efficient.

Example



Algebraic Two-Level Size Minimization

Previous example showed common algebraic minimization method

(Multiply out to sum-of-products, then)

Apply following as much possible

ab + ab’ = a(b + b’) = a*1 = a

“Combining terms to eliminate a variable”

(Formally called the “Uniting theorem”)

Duplicating a term sometimes helps

Note that doesn’t change function

c + d = c + d + d = c + d + d + d + d ...

Sometimes after combining terms, can

combine resulting terms


F = xy(z + z’) + x’y’(z + z’)

F = xy*1 + x’y’*1

F = xy + x’y’

F = x’y’z’ + x’y’z + x’yz

F = x’y’z’ + x’y’z + x’y’z + x’yz

F = x’y’(z+z’) + x’z(y’+y)

F = x’y’ + x’z

G = xy’z’ + xy’z + xyz + xyz’

G = xy’(z’+z) + xy(z+z’)

G = xy’ + xy (now do again)

G = x(y’+y)

G = x



Karnaugh Maps for Two-Level Size Minimization

Two variable map



Three variable k-map



Easy to miss “seeing” possible opportunities to

combine terms

Karnaugh Maps (K-maps)

Graphical method to help us find opportunities to

combine terms

Minterms differing in one variable are adjacent in the map Notice not in binary order

X’Y’Z’ X’Y’Z X’YZ X’YZ’

XY’Z’ XY’Z XYZ XYZ’1

Treat left & right as adjacent too

00 01 11 10

0

Fyz

x



The End





1

Lecture-4

A.Amalin Prince




2

10-08-07



Karnaugh Maps for Two-Level Size Minimization

Two variable map



Three variable k-map



Can clearly see opportunities to combine terms – look for adjacent 1s

For F, clearly two opportunities

Top left circle is shorthand for x’y’z’+x’y’z = x’y’(z’+z)

= x’y’(1) = x’y’

Draw circle, write term that has all the literals except the one that changes in the circle Circle xy, x=1 & y=1 in both cells of

the circle, but z changes (z=1 in one cell, 0 in the other)

Minimized function: OR the final terms

F = x’y’z + xyz + xyz’ + x’y’z’

0 0

0 0

00 01 11 10

0

1

F yzx

1

x’y’ xy

1

1 1

F = x’y’ + xy

Easier than all that algebra:


F = xy(z + z’) + x’y’(z + z’)

F = xy*1 + x’y’*1

F = xy + x’y’

0 0

0 0

00 01 11 10

0

1

F yzx

1

11

1



K-maps

Four adjacent 1s

means two variables

can be eliminated

Makes intuitive sense – those two variables

appear in all combinations, so one must be true

Draw one big circle –shorthand for the

algebraic transformations above

G = xy’z’ + xy’z + xyz + xyz’

G = x(y’z’+ y’z + yz + yz’) (must be true)

G = x(y’(z’+z) + y(z+z’))

G = x(y’+y)

G = x

Draw the biggest circle possible, oryou’ll have more terms than really needed

0 0 0 0

00 01 11 10

1 1

0

1 1 1

G yz

x

x

0 0 0 0

00 01 11 10

1 1

0

1 1 1

G yzx

xyxy’



K-maps Four adjacent cells can be in

shape of a square

OK to cover a 1 twice

Just like duplicating a term

Remember, c + d = c + d + d

No need to cover 1s more than once

Yields extra terms – not minimized

0 1 0 0

00 01 11 10

1 1

0

1 1 1

I yz

x

x

y’z

The two circles are shorthand for:I = x’y’z + xy’z’ + xy’z + xyz + xyz’

I = x’y’z + xy’z + xy’z’ + xy’z + xyz + xyz’

I = (x’y’z + xy’z) + (xy’z’ + xy’z + xyz +

xyz’)

I = (y’z) + (x)

H = x’y’z + x’yz + xy’z + xyz(xy appears in all combinations)

0 1 1 0

00 01 11 10

0 1

0

1 1 0

H yz

x

z

1 1 0 0

00 01 11 10

0 1

0

1 1 0

J yz

x

xz

y’zx’y’



K-maps Circles can cross left/right sides

Remember, edges are adjacent

Minterms differ in one variable only

Circles must have 1, 2, 4, or 8 cells – 3, 5, or 7 not allowed

3/5/7 doesn’t correspond to

algebraic transformations that combine terms to eliminate a

variable

Circling all the cells is OK

Function just equals 1

0 1 0 0

00 01 11 10

1 0

0

1 0 1

K yz

x

xz’

x’y’z

0 0 0 0

00 01 11 10

1 1

0

1 1 0

L yz

x

1 1 1 11

00 01 11 10

1 1

0

1 1 1

E yz

x



An illustrative three-variable Boolean function.

x’z’

xy’ f xy’+x’z’



Try yourself

Simplify

1. f(x,y,z) = Σm(0,1,2,3,5,7)

2. Y=A’B’C’+A’BC+AB’C’+ABC



K-maps for Four Variables



K-maps for Four Variables Four-variable K-map follows

same principle

Adjacent cells differ in one variable

Left/right adjacent

Top/bottom also adjacent

G=z

F=w’xy’+yz

0 0 1 0

00 01 11 10

1 1

00

01 1 0

0 0 1 0

0 0

11

10 1 0

F yzwx

yz

w

’

x

y

’

0 1 1 0

00 01 11 10

0 1

00

01 1 0

0 1 1 0

0 1

11

10 1 0

G yzwx

z



Minimize:

H = a’b’(cd’ + c’d’) + ab’c’d’ +

ab’cd’ + a’bd + a’bcd’

1. Convert to sum-of-products:

H = a’b’cd’ + a’b’c’d’ + ab’c’d’+ ab’cd’ + a’bd + a’bcd’

2. Place 1s in K-map cells

3. Cover 1s

4. OR resulting terms

Two-Level Size Minimization Using K-maps

– Four Variable Example

1 1

00 01 11 10

00

01 1 1 1

1

11

10

0 0

0

0 0 0 0

0 0 1

H cdab

a’bd

a’bc

b’d’

Funny-looking circle,

but remember that

left/right

adjacent, and

top/bottom adjacent

a’b’c’d’

ab’c’d’ a’bd

a’b’cd’

ab’cd’

a’bcd’

H = b’d’ + a’bc + a’bd



Karnaugh map for f(w,x,y,z) = ΣΣΣΣm(1,2,3,5,6,7,8,13)



Try Yourself

( , , , ) (0,1,4,8,9,10)F P Q R S m=∑



K-maps for Five Variables



1

1

1 1

1 1 1 1

1 1

1

1

1



Simplify F=ΣΣΣΣm(0,2,4,6,9,13,21,23,25,29,31)



5 and 6 variable maps exist

But hard to use

Two-variable maps exist

But not very useful – easy to do algebraically by hand



The End





1

Lecture-5

A.Amalin Prince




2

13-08-07



Don’t Care Input Combinations What if particular input combinations can

never occur?

e.g., Minimize F = xy’z’, given that x’y’z’(xyz=000) can never be true, and that xy’z(xyz=101) can never be true

So it doesn’t matter what F outputs when x’y’z’ or xy’z is true, because those cases will never occur

Thus, make F be 1 or 0 for those cases in a way that best minimizes the equation

On K-map

Draw Xs for don’t care combinations

Include X in circle ONLY if minimizes

equation

Don’t include other Xs

Good use of don’t cares

X

1 X

0 0 0

00 01 11 10

0

1 0 0

F yz y’z’

x

Unnecessary use of don’t

cares; results in extra term

X 0 0 0

00 01 11 10

1 X

0

1 0 0

F yz y’z’ unneeded

xy’

x



Minimizization Example using Don’t Cares

Minimize:

F = a’bc’ + abc’ + a’b’c

Given don’t cares: a’bc, abc

Note: Use don’t cares with

caution

Must be sure that we really don’t

care what the function outputs for that input combination

If we do care, even the slightest,

then it’s probably safer to set the output to 0

00 01 11 10

0

0 0

0

1

F bc

a

’ca b

1 1

1

X

X

F = a’c + b



Minimization with Don’t Cares Example: Sliding Switch

Switch with 5 positions

3-bit value gives position in

binary

Want circuit that

Outputs 1 when switch is in

position 2, 3, or 4

Outputs 0 when switch is in

position 1 or 5

Note that the 3-bit input can never output binary 0, 6, or 7

Treat as don’t care input combinations

2,3,4,detector

x

y

z

1 2 3 4 5

G

Without don’t

cares:

F = x’y + xy’z’ 0 0 1 1

00 01 11 10

1 0

0

1 0 0

G yzx x’y

xy’z’

With don’t

cares:

F = y + z’

X 0 1 1

00 01 11 10

1 0

0

1 X X

G yz

xy

z’



Try yourself

( , , , ) (1,3,7,11,15) (0,2, 4)F P Q R S m d= +∑ ∑



Automating Two-Level Logic Size Minimization

Minimizing by hand

Is hard for functions with 5 or

more variables

May not yield minimum cover depending on order we choose

Is error prone

Minimization thus typically

done by automated tools

Exact algorithm: finds optimal

solution

Heuristic: finds good solution, but not necessarily optimal

1 1 1 0

00 01 11 10

1 0

0

1 1 1

I yz

x

y’z’ x’y’ yz

(a)

(b)

1 1 1 0

00 01 11 10

1 0

0

1 1 1

I yz

x

y’z’ x’z

xy4 terms

xyOnly 3 terms



Basic Concepts Underlying Automated Two-Level

Logic Minimization

Definitions On-set: All minterms that define

when F=1

Off-set: All minterms that define when F=0

Implicant: Any product term (minterm or other) that when 1 causes F=1

On K-map, any legal (but not necessarily largest) circle

Cover: Implicant xy coversminterms xyz and xyz’

Expanding a term: removing a variable (like larger K-map circle)

xyz xy is an expansion of xyz

0 1 0 0

00 01 11 10

0 0

0

1 1 1

F yz

x

xy

xyz’

xyz

x’y’z

4 implicants of F

Note: We use K-maps here just for

intuitive illustration of concepts;

automated tools do not use K-maps.

• Prime implicant: Product term obtained by combining the maximum possible number of adjacent squares in the map.

• x’y’z, and xy, above

• But not xyz or xyz’ – they can be expanded



Basic Concepts Underlying Automated Two-

Level Logic Minimization

Definitions (cont)

Essential prime implicant: If a minterm in a square is

covered by only one prime implicant, that prime implicantis essential prime implicat.

Importance: We must include all

essential PIs in a function’s

cover

In contrast, some, but not all,

non-essential PIs will be included

1 1 0

0

0

00 01 11 10

1

0

1 1 1

G yz

x

not essential

not essentialy’z

x’y’xz xyessential

1

essential

1



Automated Two-Level Logic Minimization Method

Steps 1 and 2 are exact

Step 3: Hard. Checking all possibilities: exact, but computationally expensive. Checking some but not all: heuristic.



Example of Automated Two-Level Minimization

1. Determine all prime implicants

2. Add essential PIs to cover

Italicized 1s are thus already

covered

Only one uncovered 1 remains

3. Cover remaining mintermswith non-essential PIs

Pick among the two possible PIs

1 1 1 0

00 01 11 10

1 0

0

1 0 1

I yzx

y’z’

x’z

xz’

(c)

1 1 0

00 01 11 10

1 0

0

1 0 1

I yzx

1 1 1 0

00 01 11 10

1 0

0

1 0 1

I yzx

x’y’y’z’

x’z

xz’

(b)

x’y’y’z’

x’z

xz’

(a)1

1

1



The End





1

Lecture-6

A.Amalin Prince




2

17-08-07

AAP



Quine-McCluskey Method



Motivation

Karnaugh maps are very effective for the minimizationof expressions with up to 5 or 6 inputs. However theyare difficult to use and error prone for circuits withmany inputs.

Karnaugh maps depend on our ability to visuallyidentify prime implicants and select a set of primeimplicants that cover all minterms. They do notprovide a direct algorithm to be implemented in acomputer.

For larger systems, we need a programmable method!!



Quine-McCluskey

Quine, Willard, “A way to simplify truth functions.”American Mathematical Monthly, vol. 62, 1955.

Quine, Willard, “The problem of simplifying truth functions.”American Mathematical Monthly, vol. 59, 1952.

Willard van Orman Quine 1908-2000, Edgar Pierce Chair of Philosophy at Harvard University.http://members.aol.com/drquine/wv-quine.html

McCluskey Jr., Edward J. “Minimization of Boolean Functions.”Bell Systems Technical Journal, vol. 35, pp. 1417-1444, 1956

Edward J. McCluskey, Professor of ElectricalEngineering and Computer Science at Stanfordhttp://www-crc.stanford.edu/users/ejm/McCluskey_Edward.html



Outline of the Quine-McCluskey

Method

1. Produce a minterm expansion (standard sum-of-products form) for a function F

2. Eliminate as many literals as possible bysystematically applying XY + XY’ = X.

3. Use a prime implicant chart to select aminimum set of prime implicants thatwhen ORed together produce F, and thatcontains a minimum number of literals.



Determination of Prime Implicants

AB’CD’ + AB’CD = AB’C

1 0 1 0 + 1 0 1 1 = 1 0 1 -

(The dash indicates a missing variable)

A’BC’D + A’BCD’

0 1 0 1 + 0 1 1 0

We can combine the minterms above because theydiffer by a single bit.The minterms below won’t combine



Quine-McCluskey Method An Example

1. Find all the prime implicants

∑= )14,10,9,8,7,6,5,2,1,0(),,,( mdcbaf

group 0

group 1

group 2

group 3

0 0000

1 00012 00108 10005 01016 01109 100110 10107 011114 1110

Group the mintermsaccording to the numberof 1s in the minterm.

This way we only have tocompare minterms fromadjacent groups.

Decimal binary

0 0000

1 0001

2 0010

5 0101

6 0110

7 0111

8 1000

9 1001

10 1010

14 1110




An Example

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

Column I Column II

Combining

group 0 and

group 1:




An Example

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

Column I Column II

0,1 000-

Combining

group 0 and

group 1:




An Example

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

Column I Column II

0,1 000-

0,2 00-0

Combining

group 0 and

group 1:




An Example

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

Column I Column II

0,1 000-

0,2 00-0

0,8 -000

Does it makesense to nocombine group 0with group 2 or 3?

No, there are atleast two bits thatare different.




An Example

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

Column I Column II

0,1 000-

0,2 00-0

0,8 -000

Does it makesense to nocombine group 0with group 2 or 3?

No, there are atleast two bits thatare different.

Thus, next we combine group 1and group 2.




An Example

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

Column I Column II

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

Combine group 1

and group 2.




An Example

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

Column I Column II

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

Combine group 1

and group 2.




An Example

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

Column I Column II

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

Combine group 1

and group 2.




An Example

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

Column I Column II

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

Combine group 1

and group 2.




An Example

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

Column I Column II

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

Combine group 1

and group 2.




An Example

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

Column I Column II

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

Again, there is

no need to try

to combine group

1 with group 2.




An Example

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

Column I Column II

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

Again, there is

no need to try

to combine group

1 with group 3.

Lets try to combine

group 2 with

group 3.




An Example

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

Column I Column II

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

5,7 01-1

Combine group 2

and group 3.




An Example

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

Column I Column II

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

5,7 01-1

6,7 011-

Combine group 2

and group 3.




An Example

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

Column I Column II

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

5,7 01-1

6,7 011-

6,14 -110

Combine group 2

and group 3.




An Example

Column I Column II

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

5,7 01-1

6,7 011-

6,14 -110

10,14 1-10

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

We have now

completed the

first step. All

minterms in

column I were

included.

We can divide

column II into

groups.




An Example

Column I Column II

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

5,7 01-1

6,7 011-

6,14 -110

10,14 1-10




An Example

Column I Column II

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

5,7 01-1

6,7 011-

6,14 -110

10,14 1-10

Column III




An Example

Column I Column II

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

5,7 01-1

6,7 011-

6,14 -110

10,14 1-10

Column III

0,1,8,9 -00-




An Example

Column I Column II

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

5,7 01-1

6,7 011-

6,14 -110

10,14 1-10

Column III

0,1,8,9 -00-

0,2,8,10 -0-0




An Example

Column I Column II

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

5,7 01-1

6,7 011-

6,14 -110

10,14 1-10

Column III

0,1,8,9 -00-

0,2,8,10 -0-0

0,8,1,9 -00-




An Example

Column I Column II

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

5,7 01-1

6,7 011-

6,14 -110

10,14 1-10

Column III

0,1,8,9 -00-

0,2,8,10 -0-0

0,8,1,9 -00-

0,8,2,10 -0-0




An Example

Column I Column II

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

5,7 01-1

6,7 011-

6,14 -110

10,14 1-10

Column III

0,1,8,9 -00-

0,2,8,10 -0-0

0,8,1,9 -00-

0,8,2,10 -0-0

2,6,10,14 --10




An Example

Column I Column II

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

5,7 01-1

6,7 011-

6,14 -110

10,14 1-10

Column III

0,1,8,9 -00-

0,2,8,10 -0-0

0,8,1,9 -00-

0,8,2,10 -0-0

2,6,10,14 --10

2,10,6,14 --10




An Example

Column I Column II

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

5,7 01-1

6,7 011-

6,14 -110

10,14 1-10

Column III

0,1,8,9 -00-

0,2,8,10 -0-0

0,8,1,9 -00-

0,8,2,10 -0-0

2,6,10,14 --10

2,10,6,14 --10

No more combinationsare possible, thus westop here.




An Example

Column I Column II

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

5,7 01-1

6,7 011-

6,14 -110

10,14 1-10

Column III

0,1,8,9 -00-

0,2,8,10 -0-0

0,8,1,9 -00-

0,8,2,10 -0-0

2,6,10,14 --10

2,10,6,14 --10

We can eliminate repeatedcombinations




An Example

Column I Column II

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

5,7 01-1

6,7 011-

6,14 -110

10,14 1-10

Column III

0,1,8,9 -00-

0,2,8,10 -0-0

2,6,10,14 --10

f = a’c’d

Now we form f with theterms not checked




An Example

Column I Column II

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

5,7 01-1

6,7 011-

6,14 -110

10,14 1-10

Column III

0,1,8,9 -00-

0,2,8,10 -0-0

2,6,10,14 --10

f = a’c’d + a’bd




An Example

Column I Column II

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

5,7 01-1

6,7 011-

6,14 -110

10,14 1-10

Column III

0,1,8,9 -00-

0,2,8,10 -0-0

2,6,10,14 --10

f = a’c’d + a’bd + a’bc




An Example

Column I Column II

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

5,7 01-1

6,7 011-

6,14 -110

10,14 1-10

Column III

0,1,8,9 -00-

0,2,8,10 -0-0

2,6,10,14 --10

f = a’c’d + a’bd + a’bc + b’c’




An Example

Column I Column II

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

5,7 01-1

6,7 011-

6,14 -110

10,14 1-10

Column III

0,1,8,9 -00-

0,2,8,10 -0-0

2,6,10,14 --10


+ b’d’




An Example

Column I Column II

group 0

group 1

group 2

group 3

0 0000

1 0001

2 0010

8 1000

5 0101

6 0110

9 1001

10 1010

7 0111

14 1110

0,1 000-

0,2 00-0

0,8 -000

1,5 0-01

1,9 -001

2,6 0-10

2,10 -010

8,9 100-

8,10 10-0

5,7 01-1

6,7 011-

6,14 -110

10,14 1-10

Column III

0,1,8,9 -00-

0,2,8,10 -0-0

2,6,10,14 --10


+ b’d’ + cd’




An Example

f = a’c’d + a’bd + a’bc + b’c’ + b’d’ + cd’

But, the form below is not minimized, using a Karnaugh map we can obtain:

a

1

b

c

d1

abcd

f

00 01 11 10

00

01

11

10




An Example



a

1

1

b

c

d1

abcd

f

00 01 11 10

00

01

11

10




An Example



a

1

1

1

b

c

d1

abcd

f

00 01 11 10

00

01

11

10




An Example



a

1

1

1

1

1

1

b

c

d1

abcd

f

00 01 11 10

00

01

11

10




An Example



a

1

1

1

1

1

1

1 1

b

c

d1

abcd

f

00 01 11 10

00

01

11

10




An Example


But, the form below is not minimized. Using a Karnaugh map we can obtain:

a

1

1

1

1

1

1

1 1 1

b

c

d1

abcd

f

00 01 11 10

00

01

11

10




An Example



a

1

1

1

1

1

1

1 1 1

b

c

d1

F = a’bd

abcd

f

00 01 11 10

00

01

11

10




An Example



a

1

1

1

1

1

1

1 1 1

b

c

d1

F = a’bd + cd’

abcd

f

00 01 11 10

00

01

11

10




An Example



a

1

1

1

1

1

1

1 1 1

b

c

d1

F = a’bd + cd’ + b’c’

abcd

f

00 01 11 10

00

01

11

10




An Example


What are the extra terms in the solution obtainedwith the Quine-McCluskey method?

a

1

1

1

1

1

1

1 1 1

b

c

d1

F = a’bd + cd’ + b’c’

Thus, we need a method to eliminate this redundant termsfrom the Quine-McCluskey solution.

abcd

f

00 01 11 10

00

01

11

10



The Prime Implicant Chart

The prime implicant chart is the second part ofthe Quine-McCluskey procedure.

It is used to select a minimum set of prime implicants.

Similar to the Karnaugh map, we first selectthe essential prime implicants, and then weselect enough prime implicants to cover allthe minterms of the function.



Prime Implicant Chart (Example)

0 1 2 5 6 7 8 9 10 14 (0,1,8,9) b’c’ X X X X (0,2,8,10) b’d’ X X X X (2,6,10,14) cd’ X X X X (1,5) a’c’d X X (5,7) a’bd X X (6,7) a’bc X X

Question: Given the prime implicant chart above,how can we identify the essential primeimplicants of the function?

mintermsP

rim

e I

mplic

an

ts





Similar to the Karnaugh map, all we have to do is to look for minterms that are covered by a singleterm.

mintermsP

rim

e I

mplic

an

ts





Once a term is included in the solution, all theminterms covered by that term are covered.

Therefore we may now mark the covered mintermsand find terms that are no longer useful.

mintermsP

rim

e I

mplic

an

ts





mintermsP

rim

e I

mplic

an

ts





As we have not covered all the minterms withessential prime implicants, we must chooseenough non-essential prime implicants to cover the remaining minterms.

mintermsP

rim

e I

mplic

an

ts





What strategy should we use to find a minimumcover for the remaining minterms?

mintermsP

rim

e I

mplic

an

ts





We choose first prime implicants that cover themost minterms. Should this strategy always work??

mintermsP

rim

e I

mplic

an

ts





Therefore our minimum solution is:

f(a,b,c,d) = b’c’ + cd’ + a’bd

mintermsP

rim

e I

mplic

an

ts



Cyclic Prime Implicant Chart

F(a,b,c) = Σ m(0, 1, 2, 5, 6, 7)

0 000

1 001

2 010

5 101

6 110

7 111

0,1 00-

0,2 0-0

1,5 -01

2,6 -10

5,7 1-1

6,7 11-

0 1 2 5 6 7 (0,1) a’b’ X X (0,2) a’c X X (1,5) b’c X X (2,6) bc’ X X (5,7) ac X X (6,7) ab X X

Which ones are the essential prime implicantsin this chart?

There is no essential prime implicants, how we proceed?

minterms

Prim

e I

mplic

an

ts




F(a,b,c) = Σ m(0, 1, 2, 5, 6, 7)

0 000

1 001

2 010

5 101

6 110

7 111

0,1 00-

0,2 0-0

1,5 -01

2,6 -10

5,7 1-1

6,7 11-


Also, all implicants cover the same number of minterms. We will have to proceed by trial and error.

minterms

Prim

e I

mplic

an

tsF(a,b,c) = a’b’




F(a,b,c) = Σ m(0, 1, 2, 5, 6, 7)

0 000

1 001

2 010

5 101

6 110

7 111

0,1 00-

0,2 0-0

1,5 -01

2,6 -10

5,7 1-1

6,7 11-


Also, all implicants cover the same number of minterms. We will have to proceed by trial and error.

minterms

Prim

e I

mplic

an

tsF(a,b,c) = a’b’ + bc’




F(a,b,c) = Σ m(0, 1, 2, 5, 6, 7)

0 000

1 001

2 010

5 101

6 110

7 111

0,1 00-

0,2 0-0

1,5 -01

2,6 -10

5,7 1-1

6,7 11-


Thus, we get the minimization:

F(a,b,c) = a’b’ + bc’ + ac

minterms

Prim

e I

mplic

an

ts




F(a,b,c) = Σ m(0, 1, 2, 5, 6, 7)

0 000

1 001

2 010

5 101

6 110

7 111

0,1 00-

0,2 0-0

1,5 -01

2,6 -10

5,7 1-1

6,7 11-


Lets try another set of prime implicants.

minterms

Prim

e I

mplic

an

ts




F(a,b,c) = Σ m(0, 1, 2, 5, 6, 7)

0 000

1 001

2 010

5 101

6 110

7 111

0,1 00-

0,2 0-0

1,5 -01

2,6 -10

5,7 1-1

6,7 11-



minterms

Prim

e I

mplic

an

tsF(a,b,c) = a’c




F(a,b,c) = Σ m(0, 1, 2, 5, 6, 7)

0 000

1 001

2 010

5 101

6 110

7 111

0,1 00-

0,2 0-0

1,5 -01

2,6 -10

5,7 1-1

6,7 11-



minterms

Prim

e I

mplic

an

tsF(a,b,c) = a’c + b’c’




F(a,b,c) = Σ m(0, 1, 2, 5, 6, 7)

0 000

1 001

2 010

5 101

6 110

7 111

0,1 00-

0,2 0-0

1,5 -01

2,6 -10

5,7 1-1

6,7 11-



minterms

Prim

e I

mplic

an

tsF(a,b,c) = a’c + b’c’+ ab




F(a,b,c) = Σ m(0, 1, 2, 5, 6, 7)

0 000

1 001

2 010

5 101

6 110

7 111

0,1 00-

0,2 0-0

1,5 -01

2,6 -10

5,7 1-1

6,7 11-


This time we obtain:

F(a,b,c) = a’c + b’c’+ ab

minterms

Prim

e I

mplic

an

ts




Which minimal form is better?

F(a,b,c) = a’b’ + bc’ + ac

F(a,b,c) = a’c + b’c’+ ab

Depends on what terms we must form for otherfunctions that we must also implement.

Often we are interested in examining all minimalforms for a given function.

Thus we need an algorithm to do so.



Try Yourself: Simplify

F=Σm(0,1,9,15,24,29,30) + d(8,11,31)



F=Σm(0,5,7,8,9,12,13,23,24,25,28,29,37,40

,42,44,46,55,56,57,60,61)



The End





1

Lecture-7

A.Amalin Prince



Objective : Combinational Logic & MSI Components

2

20-08-07



Combinational Networks

Block diagram of a combinational network



Analysis Procedure



Design Procedure

From the specification of the circuit, determine the required number of inputs and out-puts and assign a symbol to each.

Derive the truth table that defines the required relationship between inputs and outputs.

Obtain the simplified Boolean function for each output as a function of the input variables.

Draw the logic diagram and verify the corrections of the diagram.



Code Converter

What is a code converter?

Why it is needed?

Design a BCD to Excess-3 code converter?Possibilities?

Step1:

BCD to Excess-3Code Converter

BC

D In

pu

t

Exces

s-3

Ou

tpu

t

A

B

C

D

W

X

Y

Z



Step 2

1 1 0 01 0 0 1

1 0 1 11 0 0 0

1 0 1 00 1 1 1

1 0 0 10 1 1 0

1 0 0 00 1 0 1

0 1 1 10 1 0 0

0 1 1 00 0 1 1

0 1 0 10 0 1 0

0 1 0 00 0 0 1

0 0 1 10 0 0 0

W X Y Z A B C D

Excess-3 OutputBCD Input



Step-3

(5,6,7,8,9) (10,11,12,13,14,15)

(1,2,3, 4,9) (10,11,12,13,14,15)

(0,3, 4,7,8) (10,11,12,13,14,15)

(0,2, 4,6,8) (10,11,12,13,14,15)

W m d

X m d

Y m d

Z m d

= +

= +

= +

= +

∑

∑

∑

∑



Step-4

AAP



Binary Adder-Subtractor



Half-Adder Half-adder: Adds 2 bits,

generates sum and carry

Design using combinational design process

s

0

1

1

0

co

0

0

0

1

b

0

1

0

1

a

0

0

1

1

Inputs Outputs

Step 1: Capture the function

Step 2: Convert to equations

Step 3: Create the circuit

co = ab

s = a’b + ab’ (same as s = a xor b)

a b

co

co s

a b

s

Half-adder



Full-Adder Full-adder: Adds 3 bits,

generates sum and carry

Design using combinational design process

Step 1: Capture the function

s

0

1

1

0

1

0

0

1

co

0

0

0

1

0

1

1

1

ci

0

1

0

1

0

1

0

1

b

0

0

1

1

0

0

1

1

a

0

0

0

0

1

1

1

1

Inputs OutputsStep 2: Convert to equations

co = a’bc + ab’c + abc’ + abc

co = a’bc +abc +ab’c +abc +abc’ +abc

co = (a’+a)bc + (b’+b)ac + (c’+c)ab

co = bc + ac + ab

s = a’b’c + a’bc’ + ab’c’ + abc

s = a’(b’c + bc’) + a(b’c’ + bc)

s = a’(b xor c)’ + a(b xor c)

s = a xor b xor c

Step 3: Create the circuit

co

ciba

s

Full

adder



Implementation of Full adder using Two

Half adders and an OR Gatea

b

ci

s

co



Half Subtractor Subtracting a single-bit binary value Y from anther X (I.e. X -Y )

produces a difference bit D and a borrow out bit B-out.

This operation is called half subtraction and the circuit to realize

it is called a half subtractor.

X

0

0

1

1

Y

0

1

0

1

D

0

1

1

0

B-out

0

1

0

0

Half Subtractor Truth Table

Inputs Outputs

D(X,Y) = ΣΣΣΣ (1,2)

D = X’Y + XY’

D = X ⊕⊕⊕⊕ Y

B-out(x, y, C-in) = ΣΣΣΣ (1)

B-out = X’Y

Half

Subtractor

X

Y

D

B-OUT

X

Y

Difference

D

B-out



Full Subtractor Subtracting two single-bit binary values, Y,

B-in from a single-bit value X produces a

difference bit D and a borrow out B-out

bit. This is called full subtraction.

X

0

0

0

0

1

1

1

1

Y

0

0

1

1

0

0

1

1

D

0

1

1

0

1

0

0

1

B-out

0

1

1

1

0

0

0

1

B-in

0

1

0

1

0

1

0

1

Full Subtractor Truth TableInputs Outputs

S(X,Y, C-in) = ΣΣΣΣ (1,2,4,7)

C-out(x, y, C-in) = ΣΣΣΣ (1,2,3,7)

Difference D

B-in

X

0

1

00 01 11 10

Y

B-in

XY

0

1

2

3

6

7

4

5

1

1 1

1

B-in

X

0

1

00 01 11 10

Y

B-in

XY

0

1

2

3

6

7

4

5

1

11 1

Borrow B-out

S = X’Y’(B-in) + XY’(B-in)’ + XY’(B-in)’ + XY(B-in)

S = X ⊕ Y ⊕ (C-in)

B-out = X’Y + X’(B-in) + Y(B-in)



Full Subtractor Circuit Using AND-OR

X’Y

YB-in

B-outX’B-in

X’

X’

Y

B-in

Y

B-in

Y Y’

Y

X X’

X

B-in B-in’

B-in

X’Y’B-in

XY’B-in’

Difference DX’YB-in’

XYB-in

X’

X’

X

X

Y’

Y

Y

B-in

Y

B-in’

B-in’

B-in’

Full

Subtractor

X Y

D

B-inB-out



Full Subtractor Circuit Using XOR

Difference D

X

Y

B-in

X’Y

YB-in

B-outX’B-in

X’

X’

Y

B-in

Y

B-in

Full

Subtractor

X Y

D

B-inB-out



Method to Design an Parallel Adder: Imitate

Adding by Hand

Create

component

for each

column

Adds that

column’s bits,

generates sum and

carry bits

0

1 1 1 1

+ 0 1 1 0

1

10101

b

co s

0

a ci

A:

B:+ 0

1 1 1 1

1

b

co s

1

a ci

1

b

co s

0

a ci

1

1 1 0

b

co s

1 SUM

a

0

A:

B:

1

Half-adderFull-adders



Carry-Ripple Adder

Using half-adder and full-adders, we can build adder that adds like we would by hand

Called a carry-ripple adder 4-bit adder shown: Adds two 4-bit numbers, generates 5-bit

output

5-bit output can be considered 4-bit “sum” plus 1-bit “carry out”

Can easily build any size addera3

co s

FA

co

b3 a2b2

s3 s2 s1

ciba

co s

FA

ciba

a1b1

co s

FA

ciba

s0

a0 b0

co s

HA

ba

(a)

a3a2a1a0 b3

s3s2 s1s0co

b2b1b0

(b)

4-bit adder



Carry-Ripple Adder Using full-adder instead of half-adder for first

bit, we can include a “carry in” bit in the addition Will be useful later when we connect smaller

adders to form bigger adders

a3

co s

FA

co

b3 a2b2

s3 s2 s1

ciba

co s

FA

ciba

a1b1

co s

FA

ciba

s0

a0 b0 ci

co s

FA

ciba

(a)

a3a2a1a0 b3

s3s2 s1s0co

ci

b2b1b0

(b)

4-bit adder



Carry-Ripple Adder’s Behavior

0 1 1 10 0 0 1 0111+ 0001(answer should be 01000)

0

co s

FA

0 0

0 0 0

0 0 00 0 0

0 0

ciba

co s

FA

ciba

0 0

co s

FA

ciba

0

0 0

co s

FA

ciba

0

Assume all inputs initially 0

Output after 2 ns (1FA delay)0 0 1 1 0

co s

FA

0 0

0 0 0

co2 co1 co0

ciba

co s

FA

ciba

co s

FA

ciba

co s

FA

ciba

0

01

Wrong answer -- something wrong? No -- just need more

time for carry to ripple through the chain of full adders.



0 00

co s

FA

1 1 1

1 10 1 0

ciba

co s

FA

ciba

1 0

co s

FA

ciba

0 0 0

1 1

co s

FA

ciba

(d)Output after 8ns (4 FA delays)

Carry-Ripple Adder’s Behavior0

co s

FA

0 0 1

co1

0 1 0

ciba

co s

FA

ciba

1 0

co s

FA

ciba

0 0 1 0 0

1 1

co s

FA

ciba

(b)

10 1

0 0 0

0

1

0 1

1

Outputs after 4ns (2 FA delays)

00

co s

FA

1 1

0 1

co2

0 1 0

ciba

co s

FA

ciba

1 0

co s

FA

ciba

0 0

1 10

co s

FA

ciba

(c)Outputs after 6ns (3 FA delays)

0111+0001(answer should be 01000)

1

Correct answer appears after 4 FA delays



Cascading Adders

a3a2a1a0 b3

s3s2s1s0co

s7s6s5s4co

ci

b2b1b0

a7a6a5a4 b7b6b5b4

(a) (b)

4-bit adder

a3a2a1a0 b3

s3s2s1s0

s3s2s1s0

co

ci

b2b1b0

a3a2a1a0 b3b2b1b0

4-bit adder

a7.. a0 b7.. b0

s7.. s0co

ci8-bit adder



Adder Example: DIP-Switch-Based Adding Calculator Goal: Create calculator that adds two 8-bit binary numbers,

specified using DIP switches

DIP switch: Dual-inline package switch, move each switch up or down

Solution: Use 8-bit adder DIP switches

1

0

a7..a0 b7..b0

s7..s0

8-bit carry-ripple adder

co

ci 0

CALC

LEDs



Adder Example: DIP-Switch-Based Adding Calculator

To prevent spurious values from appearing at output, can place register at output Actually, the light flickers from spurious values would be too fast for humans to detect --

but the principle of registering outputs to avoid spurious values being read by external devices (which normally aren’t humans) applies here.

DIP switches

1

0

a7..a0 b7..b0

s7..s0

8-bit adder

8-bit register

co

ci 0

CALC

LEDs

e

clk

ld



display register

to display

1Weight

Adjusterclk

ld

0 0 0 0 0

0

4

7

5

1

3

6 2

weight

sensor

Adder Example: Compensating Weight Scale

Weight scale with compensation amount of 0-7 To compensate for inaccurate sensor due to physical wear

Use 8-bit adder

a7..a0 b7..b0

s7..s0

8-bit adder

co

ci 0

01000010 000

01000010

010

01000100



The End





1

Lecture-8

A.Amalin Prince




2

22-08-07



Carry-Ripple Adder’s Behavior

0 1 1 10 0 0 1 0111+ 0001(answer should be 01000)

0

co s

FA

0 0

0 0 0

0 0 00 0 0

0 0

ciba

co s

FA

ciba

0 0

co s

FA

ciba

0

0 0

co s

FA

ciba

0

Assume all inputs initially 0

Output after 2 ns (1FA delay)0 0 1 1 0

co s

FA

0 0

0 0 0

co2 co1 co0

ciba

co s

FA

ciba

co s

FA

ciba

co s

FA

ciba

0

01

Wrong answer -- something wrong? No -- just need more

time for carry to ripple through the chain of full adders.



0 00

co s

FA

1 1 1

1 10 1 0

ciba

co s

FA

ciba

1 0

co s

FA

ciba

0 0 0

1 1

co s

FA

ciba

(d)Output after 8ns (4 FA delays)

Carry-Ripple Adder’s Behavior0

co s

FA

0 0 1

co1

0 1 0

ciba

co s

FA

ciba

1 0

co s

FA

ciba

0 0 1 0 0

1 1

co s

FA

ciba

(b)

10 1

0 0 0

0

1

0 1

1

Outputs after 4ns (2 FA delays)

00

co s

FA

1 1

0 1

co2

0 1 0

ciba

co s

FA

ciba

1 0

co s

FA

ciba

0 0

1 10

co s

FA

ciba

(c)Outputs after 6ns (3 FA delays)

0111+0001(answer should be 01000)

1

Correct answer appears after 4 FA delays



Carry LookCarry Look--Ahead AddersAhead Adders: Carry

Propagation

i i iG A B=

i i iG A B=

i i iP A B= ⊕

i i iG A B=

i i iS P C= ⊕

1i i i iC G PC

+= +



0C input carry=

1 0 0 0C G P C= +

2 1 1 1 1 1 0 0 0

1 1 0 1 0 0

( )

C G PC G P G P C

G PG PP C

= + = + +

= + +

3 2 2 2 2 2 1 2 1 0 2 1 0 0C G P C G P G P PG P PP C= + = + + +

For a 4-bit carry look-ahead adder the

expanded expressions for all carry bits are given by:



The additional circuits needed to realize the expressions are usually referred to as the carry look-ahead logic.

Using carry-ahead logic all carry bits are available after three gate delays regardless of the size of the adder.



Binary Subtractor

1

A3 A2 A1 A0

1

B’3 B’2 B’1 B’0



Adder Subtractor

A3 A2 A1 A0

0

B3 B2 B1 B0



Adder Subtractor

A3 A2 A1 A0

1

B’3 B’2 B’1 B’0



The End





1

Lecture-9

A.Amalin Prince




2

24-08-07


BITS-Pilani Goa Campus 191 1 0 0 11 0 0 1 1

181 1 0 0 01 0 0 1 0

171 0 1 1 11 0 0 0 1

161 0 1 1 01 0 0 0 0

151 0 1 0 10 1 1 1 1

141 0 1 0 00 1 1 1 0

131 0 0 1 10 1 1 0 1

121 0 0 1 00 1 1 0 0

111 0 0 0 10 1 0 1 1

101 0 0 0 0 0 1 0 1 0

90 1 0 0 10 1 0 0 1

80 1 0 0 00 1 0 0 0

70 0 1 1 10 0 1 1 1

60 0 1 1 00 0 1 1 0

50 0 1 0 10 0 1 0 1

40 0 1 0 00 0 1 0 0

30 0 0 1 10 0 0 1 1

20 0 0 1 00 0 0 1 0

10 0 0 0 10 0 0 0 1

00 0 0 0 0 0 0 0 0 0

C S8 S4 S2 S1K Z8 Z4 Z2 Z1

DecimalBCD SumBinary Sum

Decimal

Adder



Decimal Adder



Digital Comparator

N-bit comparator

A B

A>B A=B A<B



XOR Comparator

Compare two numbers and decide if they are

equal.



0101 1 1 1

0011 1 1 0

0011 1 0 1

0011 1 0 0

1001 0 1 1

0101 0 1 0

0011 0 0 1

0011 0 0 0

1000 1 1 1

1000 1 1 0

0100 1 0 1

0010 1 0 0

1000 0 1 1

1000 0 1 0

1000 0 0 1

0100 0 0 0

A<BA=BA>BA1 A0 B1 B0

OutputsInputs



Logic Diagram



7485 4-bit Magnitude Comparator



Truth table for a 74HC85 (7485, 74LS85) four-

bit magnitude comparator.



Function Table

1

0

1

1

0

0

0

0

0

0

0

1

0

0

Χ

1

0

1

Χ

0

Χ

Χ

0

0

0

1

0

Χ

0ΧA<B

01

10

00

0Χ

11A=B

1ΧA>B

Outputs

A>B A=B A<B

Cascading Inputs If

I(A>B) I(A=B) I(A<B)

Comparing Inputs AB



Design 74HC85 wired as a four-bit

comparator



Design an 8-bit comparator using 74HC85s



Design a 5-bit comparator using one 7485.



Decoder

A decoder accepts a set of inputs that

represents a binary number and activates

only the output that corresponds to that input

number.



General Decoder Diagram



Decoders

Decoder: Popular combinational logic building block, in addition to logic gates

Converts input binary number to one high output

2-input decoder: four possible input binary numbers

So has four outputs, one for each possible input binary number

2.9

i0

i1

d0

d1

d2

d3 1

1

1

0

0

0

i0

i1

d0

d1

d2

d3 0

0

0

0

0

1

i0

i1

d0

d1

d2

d3

i0

i1

d0

d1

d2

d30

0

1

0

1

0

0

1

0

1

0

0



Internal design

AND gate for each

output to detect input combination

Decoder with enable e

Outputs all 0 if e=0

Regular behavior if e=1

n-input decoder: 2n

outputs

i0

i1

d0

d1

d2

d3e 1

1

1

1

0

0

0

e

i0

i1

d0

d1

d2

d3 0

1

1

0

0

0

0

i0

d0

d1

d2

d3

i1

i1’i0’

i1’i0

i1i0’

i1i0



A 3-to-8-line decoder. Truth table

Logic Symbol



Logic Diagram



Realization of the Boolean expressions f1(x2,x1,x0) =

ΣΣΣΣm(1,2,4,5) and f2(x2,x1,x0) =

ΣΣΣΣm(1,5,7) with a 3-to-8-line decoder and two or-gates.



Realization of the Boolean expressions

f1(x2,x1,x0) =

ΣΣΣΣm(0,1,3,4,5,6) = ΣΣΣΣm(2,7) and f2(x2,x1,x0) =

ΣΣΣΣm(1,2,3,4,6) = ΣΣΣΣm(0,5,7) with a 3-to-8-line decoder and two nor-gates.



A decoder realization of f1(x2,x1,x0) = ΠΠΠΠM(0,1,3,5) and f2(x2,x1,x0) = ΠΠΠΠM(1,3,6,7) (a) Using output or-gates. (b) Using output nor-gates.



A 3-to-8-line decoder using nand-gates.

Symbol Truth table



Logic Diagram



Realization of the pair of maxtermcanonical expressions

f1(x2,x1,x0) =

ΠΠΠΠM(0,3,5) and f2(x2,x1,x0) =

ΠΠΠΠM(2,3,4) with a 3-to-8-line decoder and two and-gates.



Realization of the Boolean expressions

f1(x2,x1,x0) =

ΠΠΠΠM(0,1,3,4,7) = ΠΠΠΠM(2,5,6) and f2(x2,x1,x0) =

ΠΠΠΠM(1,2,3,4,5,6) =ΠΠΠΠM(0,7) with a 3-to-8-line decoder and two nand-gates.



A decoder realization of f1(x2,x1,x0) = ΣΣΣΣm(0,2,6,7) and f2(x2,x1,x0) = ΣΣΣΣm(3,5,6,7) (a) Using output and-gates. (b) Using output nand-gates.



And-gate 2-to-4-line decoder with an enable input. (a) Logic diagram. (b) Compressed truth table. (c) Symbol.



Nand-gate 2-to-4-line decoder with an enable input. (a) Logic diagram. (b) Compressed truth table. (c) Symbol.



Construct 4×16 decoder using 3×8 Decoders.



Decoder Example

New Year’s Eve Countdown Display

Microprocessor counts from 59 down to 0 in

binary on 6-bit output

Want illuminate one of

60 lights for each binary number

Use 6x64 decoder

4 outputs unused

d0d1d2d3

i0i1i2i3i4i5

e

6x64dcd

d58d59d60d61d62d63

M

ic

r

op

r

o

c

essor

0

123

5859

0

1

0

0

0

0

0

0

1

0

0

0

2 211

0

0

0

0

0

0

1

0

0

0

0

10

0

0

0

0

0

1

0

0

0

0

0

0 0



The End





1

Lecture-10

A.Amalin Prince




2

27-08-07



realize f1(x2,x1,x0) = ΠΠΠΠM(0,1,3,5) and f2(x2,x1,x0) = ΠΠΠΠM(1,3,6,7) (a) Using Decoder and output OR-gates. (b) Using Decoder and output NOR-gates.



A 3-to-8-line decoder using nand-gates.

Symbol Truth table



Logic Diagram



Realize the pair of maxtermcanonical expressions f1(x2,x1,x0) =

ΠΠΠΠM(0,3,5) and f2(x2,x1,x0) =

ΠΠΠΠM(2,3,4) with a 3-to-8-line decoder and two AND-gates.



Realize the Boolean expressions

f1(x2,x1,x0) =

ΠΠΠΠM(0,1,3,4,7) = ΠΠΠΠM(2,5,6) and f2(x2,x1,x0) =

ΠΠΠΠM(1,2,3,4,5,6) =ΠΠΠΠM(0,7) with a 3-to-8-line decoder and two NAND-gates.



realize f1(x2,x1,x0) = ΣΣΣΣm(0,2,6,7) and f2(x2,x1,x0) = ΣΣΣΣm(3,5,6,7) (a) Using Decoder and output AND-gates. (b) Using Decoder and output NAND-gates.



And-gate 2-to-4-line decoder with an enable input. (a) Logic diagram. (b) Compressed truth table. (c) Symbol.



Nand-gate 2-to-4-line decoder with an enable input. (a) Logic diagram. (b) Compressed truth table. (c) Symbol.



Construct 4×16 decoder using 3×8 Decoders.



Construct a 4-to-

16-line decoder

from 2-to-4-line

decoder.



Encoders

Has several inputs only of which one is usually active at a time.

Produces an N-bit output code dependent upon which input is activated. (opposite of decoding)



8-Line-To-3-Line Encoder

Note that A0 is not internally connected (A1…A7=1111111, then Q2Q1Q0=000

Only one input should be low. Example: If A3 = A5 =0, and all other are High, then Q2Q1Q0=0112 (=310), NOT ACCEPTABLE



Priority Encoders

Priority encodersWhen 2 or more inputs are activated, the output code will correspond to the highest-numbered input. Example:If both A3 and A5 are low, then output code = 101 (510)If A6, A2, and A0 are all low, then output code = 110 (610)

The 74148, 74LS148, and 74HC148 octal to binary priority encoders



Truth table for a priority encoder (assume active high input)

1111XXX

10101XX

110001X

1000001

0XX0000

VYXD3D2D1D0

OutputsInputs



Priority Encoders

74147 decimal-to-BCD priority encoder.

Nine active low inputs representing decimal 1 thru 9 Output: inverted BCD code corresponding to the highest numbered

activated input. Outputs can be converted to normal BCD by putting each through an inverter.

No A0. When all inputs are high, it corresponds to decimal 0



Priority EncodersThe 74147 as a Decimal-to-BCD switch encoder

Example: a keyboard switch or a calculator

Simultaneous key depressions will produce the BCD code for the higher-numbered key.



Priority Encoders

The 74148, 74LS148, and 74HC148 octal

to binary priority encoders

It has Enable Input (EI) and Enable Output

(EO) that can be used to cascade two IC’s

producing a hexadecimal-to-binary encoder



Gate Delays

In verilog delay is specified in terms of time

units and the symbol #.

Compiler directive ‘timescale (Compiler

directive start with the ‘ [backquote symbol])

Usage

‘timescale <reference_time_unit>/<time_precision>

Example ‘timescale 100 ns/1 ps



// Description of circuit with delay

‘timescale 1ns/100ps

module cir_delay (A,B,C,x,y);

input A,B,C;

output x,y;

wire e;

and #(30) g1(e,A,B);

or #(20) g3(x,e,y);

not #(10) g2(y,C);

endmodule



Output of gates after delay

0 1 11 1 150

0 1 01 1 140

0 1 01 1 130

0 0 11 1 120

0 0 11 1 110

1 0 11 1 1--------

1 0 10 0 0--------

Output

y e x

Input

A B C

Time Units (ns)



Self Study: System Tasks and Compiler

Directives

Refer Ch.3.3 of Sameer Palnitkar



The End





1

Lecture-11

A.Amalin Prince




2

29-08-07

AAP



Multiplexer



Multiplexer (Mux) Mux: Another popular combinational building block

Routes one of its N data inputs to its one output, based on binary value of select inputs

4 input mux needs 2 select inputs to indicate which input to route through

8 input mux 3 select inputs

N inputs log2(N) selects

Like a railyard switch



Multiplexers (Data Selectors)

A multiplexer (MUX) selects 1 out of N input data sources and transmits the selected data to a single output



Mux Internal Design

s0

d

i0

i1

2×1

i1

i0

s01

d

2×1

i1

i0

s00

d

2×1

i1

i0

s0

d

0

i0 (1*i0=i0)

i0

(0+i0=i0)

1

0

2x1 mux

i0

4⋅⋅⋅⋅ 1

i2

i1

i3

s1 s0

d

s0

d

i0

i1

i2

i3

s1

4x1 mux

0



Mux Example City mayor can set four switches up or down, representing

his/her vote on each of four proposals, numbered 0, 1, 2, 3

City manager can display any such vote on large green/red

LED (light) by setting two switches to represent binary 0, 1, 2,

or 3

Use 4x1 mux

i0

4x1

i2

i1

i3

s1 s0

d

1

2

3

4

Mayor’s switches

manager'sswitches

Green/RedLED

on/off



Muxes Commonly Together -- N-bit

Mux

Ex: Two 4-bit inputs, A (a3 a2 a1 a0), and B (b3 b2 b1 b0)

4-bit 2x1 mux (just four 2x1 muxes sharing a select line) can select between A or B

i0

s0i1

2⋅⋅⋅⋅ 1d

i0

s0i1

2⋅⋅⋅⋅ 1d

i0

s0i1

2⋅⋅⋅⋅ 1d

i0

s0i1

2⋅⋅⋅⋅ 1d

a3

b3

I0

s0

s0

I1

4-bit

2x1

D C

A

B

a2

b2

a1b1

a0

b0

s0

4

C4

4

4

c3

c2

c1

c0

is short

for

Simplifying

notation:



N-bit Mux Example

Four possible display items

Temperature (T), Average miles-per-hour (A), Instantaneous mph (I), and Miles remaining (M) -- each is 8-bits wide

Choose which to display using two inputs x and y

Use 8-bit 4x1 mux



Eight-input multiplexer: The 74151



74157 Quad Two-Input Mux



Multiplexers

Realize 8 to 1 mux using 4 to 1 mux.



Multiplexers

Implement 16 to 1 mux using

74HC151s



Multiplexer Applications

Applications include data selection, data routing, operation sequencing, parallel to serial conversion, waveform generation, and logic function generation.

Data routing

Parallel to serial conversion

Operation sequencing

Logic function generation



Multiplexer

Applications

Parallel to serial conversion



Realization of a three-variable function using a 8-to-1-line multiplexer. (a) Three-variable truth table. (b) General realization.

Multiplexer Applications cont.



Realization of f(x,y,z) =

ΣΣΣΣm(0,2,3,5). (a) Truth table. (b) 8-to-1-line multiplexer realization.




Realization of

f(x,y,z) = ΣΣΣΣm(0,2,3,5) using a 4-to-1-line multiplexer.


I7I6I5I4

I3I2I1I0X’

X

X’ X’ X’X



Multiplexer

Applications cont.

y z



I5

I3I2

I0

Realization of

f(x,y,z) = ΣΣΣΣm(0,2,3,5) using a 4-to-1-line multiplexer.


ZZ’

I7I6

I4

I1Z’

1

Z

0



The End





1

Lecture-12

A.Amalin Prince




2

31-08-07



I5

I3I2

I0

Realization of f(x,y,z) = ΣΣΣΣm(0,2,3,5) using a 4-to-1-line multiplexer.


ZZ’

I7I6

I4

I1Z’

1

Z

0



Multiplexer

Applications cont.



Implement F=Σm(1,2,7) using 74151



Demultiplexers (Data Distributors)

A demultiplexer (DEMUX) distributes a single input to multiple

outputs.



Demultiplexers (Data Distributors)A 1-line-to-8line demultiplexer



Demultiplexer

Applications

serial to Parallel conversion



Demultiplexers (Data Distributors)

a) The 74ALS138 decoder can function as a demultiplexer with E1 used as the data

input; (b) typical waveforms for a select code of A2A1A0 = 000 show that O0 is identical to

the data input I on E1.



Implement full subtractor using demultiplexer

We know

D(A,B,C)=

Σm(1,2,4,7)

and

Bout(A,B,C)=

Σm(1,2,3,7)



The End

AAP



Behavioral Modeling



Self Study: System Tasks and Compiler

Directives

Refer Ch.3.3 of Sameer Palnitkar



Structured Procedures

Initial statement

Always statement



Initial statementmodule stimulus;reg x,y, a,b, m;Initialm= 1’b0; //single statement; does not need to be groupedinitialbegin#5a =1’b1; //multiple statements; need to be grouped#25 b=1’b0;

endinitialbegin#10x = 1’b0;#25y = 1’b1;endinitial#50 $finish;endmodule



Always Statement

module clock_gen (output reg clock);

//initialize clock at time zero

initial

clock = 1’b0;

//toggle clock every half-cycle (time period =20)

always

#10 clock =~clock

Initial

#1000 $finish;

endmodule



Procedural Assignments

Updates values of reg, integer, real or time register variable or a memory element .

The value placed on a variable will remain unchanged until another procedural assignment updates the variable with different value.

Two types

Blocking

Unblocking



Blocking Assignments

reg x,y,z;

reg [15:0] reg_a, reg_b;

integer count;

//All behavioral statements must be inside an initial or always block initial

begin

x =0;y =1; // scalar assignments

count =0; //Assignment to integer variables

reg_a = 16’b0; reg_b =reg_a; //initialize vectors

#15reg_a[2] =1’b1; //Bit selectassignment with delay

#10 reg_b[15:13] = x,y,z //Assign result of concatenation to

//part select of a vector

count = count +1; //Assiggnment to an integer (increment)

end



Nonblocking Assignments

reg x,y,z;

reg[15:0]reg_a,reg_b;

integer count;

//All behavioral statements must be inside an initial or always block initial

begin

x =0;y =1;z =1; //Scalar assignments

count = 0; //Assignment to integer variables

reg_a =16’b0; reg_b =reg_a; //Initialize vectors

reg_a[2] <=#15 1’b1; //Bit select assignment with delay

reg_b[15:13]<=#10x,y,z; //Assign result of concatenation

//to part select of a vector

count <= count+1; //Assignment to an integer (increment)



Timing Controls

Delay-Based Timing Control

Event-Based Timing Control

Level-Sensitive Timing Control



Event-Based Timing Control

Regular event control

Named event control

Event OR control



Regular event control

@(clock)q =d; //q=d is executed whenever signal clock changes value

@(posedge clock)q =d; //q =d is executed whenever signal clock does

//a positive transition (0 to 1,x or z,

//x to 1,z to 1)

@(negedge clock)q =d; //q =d is executed whenever signal clock does

//a negative transition (1 to 0,x orz

//z to 0,z to 0)

q = @(posedge clock) d; //d is evaluated immediately and assigned

//to q at the positive edge clock



Named event control

//This is an example of a data buffer storing data the

//last packet of data has arrived.

event received_data; //Define an event called recevied_data

always@(posedge clock) //check at each clock edge

begin

If (last_data_packet) //If this is the last data packet

->recevied_data; //trigger the event recevied_data

end

always@(recevied_data) //Await triggering of event recevied_data

//when event is triggered data in data buffer

//use concatenation operator

data_buf =data_pkt[10], data_pkt[1],data_pkt[2],data_pkt[3];



Event OR control

//A level-sensitive latch with asynchronous reset

always@(reset or clock or a)

//wait for reset or clock or d to change

begin

if (reset) //if reset signal is high ,set q to 0.

q =1’b0;

else if(clock) //if clock is high ,latch input

q =d;

end



//A level –sensitive latch with asynchronous reset

always@(reset, clock, d)//Wait for reset or clock or d to change

begin

if (reset) //if reset signal is high ,set q to 0.q = 1’b0;

else if(clock) //if clock is high ,latch input q =d;

end

//A positive edge triggered D flipflop with asynchronous falling //reset can be modeled as shown below

always @(posedge clk,negedge reset) //Note use of comma operatorif (!reset)

q<=0;else

q<=d;



Conditional Statements

if and else

case statement

casex, casez keywords

Loops

while loop

for loop

repeat loop

forever loop

while and forever are not synthesizable only used

for simulation



Behavioral Modeling

Refer Ch.7 of Sameer Palnitkar

http://www.asic-

world.com/verilog/vbehave.html



Verilog code for a 2-to-4 Decodermodule dec2to4 (o,i);output [3:0]o;input [1:0]i;reg [3:0]o;Always @ (i)begincase(i)

2’b00:0=4’h0;2’b01:0=4’h1;2’b10:0=4’h2;2’b11:0=4’h3;

default:begin

$display (“error”);0=4’h0;

endendcaseendendmodule



Verilog code for a 2-to-1 mux

module mux2to1 (a,b,select,out);

input a,b,select;

output out;

reg out;

always @ (select or a or b)

if (select==1) out=a;

else out=b;

endmodule



The End





1

Lecture-13

A.Amalin Prince



Objective : Digital Integrated Circuits

2

03-09-07



Switches

Electronic switches are the basis of binary digital circuits

Electrical terminology

Voltage: Difference in electric potential

between two points

Analogous to water pressure

Current: Flow of charged particles

Analogous to water flow

Resistance: Tendency of wire to resist

current flow

Analogous to water pipe diameter

V = I * R (Ohm’s Law)

4.5 A

4.5 A

4.5 A

2 ohms

9V

0V 9V

+–



Switches

A switch has three parts

Source input, and output

Current wants to flow from source

input to output

Control input

Voltage that controls whether that

current can flow

The amazing shrinking switch

1930s: Relays

1940s: Vacuum tubes

1950s: Discrete transistor

1960s: Integrated circuits (ICs)

Initially just a few transistors on IC

Then tens, hundreds, thousands...

“off”

“on”

outputsourceinput

outputsourceinput

controlinput

controlinput

(b)

relay vacuum tube

discrete transistor

IC

quarter(to see the relative size)



Moore’s Law

IC capacity doubling about every 18 months for several decades

Known as “Moore’s Law” after Gordon

Moore, co-founder of Intel

Predicted in 1965 predicted that components

per IC would double roughly every year or so

Book cover depicts related phenomena

For a particular number of transistors, the IC

shrinks by half every 18 months

Notice how much shrinking occurs in just about 10 years

Enables incredibly powerful computation in incredibly tiny devices

Today’s ICs hold billions of transistors

The first Pentium processor (early 1990s)

needed only 3 million

An Intel Pentium processor IC

having millions of transistors



The Diode



The Bipolar Transistor



The CMOS Transistor

CMOS transistor

Basic switch in modern ICs

gate

source drain

oxide

A positivevoltage here...

...attracts electrons here,turning the channel

between source and draininto aconductor.

(a)

IC package

IC

does notconduct

0

conducts

1gate

nMOS

does notconduct

1gate

pMOS

conducts

0

Silicon -- not quite a conductor or insulator:

Semiconductor



Boolean Logic GatesBuilding Blocks for Digital Circuits (Because Switches are Hard to Work With)

“Logic gates” are better digital circuit building blocks than switches

(transistors)

Why?...



Characteristics of Digital ICs

Logic Level

Fan-out

Fan-in

Power Dissipation

Propagation delay

Noise Margin



Logic Families

RTL Resister-Transistor Logic

DTL Diode-Transistor Logic

TTL Transistor-Transistor Logic

ECL Emitter-coupled Logic

MOS Metal-Oxide Semiconductor

CMOS Complementary Metal-Oxide Semiconductor



RTL Logic Family



DTL Logic Family



The End





1

Lecture-14

A.Amalin Prince




2

05-09-07



TTL Logic Family

Transistor Transistor Logic (TTL) is one of the most popular and widespread of all logic families.

Very high number of SSI and MSI devices available in the market.

Several number of sub-families that provide a wide range of speed and power consumption.

Sub families:

74xx : The original TTL family.

These devices had a propagation delay of 10ns and a power consumption of 10mW, and they were introduced in the early 60’s.



TTL Logic Family

Sub families:

74Hxx : High speed.

Speed was improved by reducing the internal resistors. Note that this improvement caused an increase in the power consumption.

74Lxx : Low power.

Power consumption was improved by increasing the internal resistances, and the speed decreased.



TTL Logic Family

Sub families:

74Sxx : Schottky.

The use of Schottky transistors improved the speed. The power dissipation is less than the 74Hxx sub-family.

74LSxx : Low power Schottky.

Uses Schottky transistors to improve speed. High internal resistances improves power consumption.



TTL Logic Family

Sub families:

74ASxx : Advanced Schottky.

Twice as fast as 74Sxx with approximately the same power dissipation.

74ALSxx : Advanced Low power Schottky.

Lower power consumption and higher speed than 74LSxx .

74Fxx : Fast.

Performance is between 74ASxx and 74ALSxx.



TTL Logic Family

Note that parameters like VOHMin , VIHMin ,

VILMax , and VOLMax are all the same for the

different sub-families, but parameters like

IILMax , IIHMax , IOLMax , and IOHMax may differ.

Most TTL sub-families have a corresponding

54-series (military) version, and these series

operate in a wider temperature and voltage

ranges.



TTL Logic Family

Output configurations

Open-collector output

Totem-pole output

Three-State (or tristate) output



Open collector output



Open Collector Devices

Can be used to drive a load, such as LEDs, relays or other device.

It is important to calculate a suitable resistor R.

The current through the load must not exceed IOLMax .




Wired AND Logic – When two or more open-collector outputs are tied together with an external pull-up resistor, the circuit behaves as if the gates were connected to an AND gate.




Common Bus – Several

open collector outputs

may be connected together to create a

common bus.

The decoder, in the

circuit shown below,

selects which device

outputs to the common bus by sending a high

to the open collector

output NAND gate

connected to the

chosen device.

1 0

0

0

1

0

1

1

0

1

1

0 1

0 1

1 0



TTL : Faster Switching To obtain faster switching

Take advantage of input diodes being realised in terms of transistors

change the circuit the following

A

+5 V

Output

BC

R2

Q1

Q3

R1

• Now the charge on the base of Q1 is removed through transistor Q3

– Results in a considerable reduction in the saturation delay time ts.



TTL : Collector Capacitance

Another factor limiting transition speed is the collector capacitance

Must be charged as output voltage switches from low to high value

only path for charging capacitance is via the collector resistor R2

Can reduce value of R2

⇒ increases charging speed

but also increases power dissipation

• Output circuit of this form known as passive pull-up circuit.

– Output capacitance is “pulled-up” via passive element R2.



Passive Pull up Circuit

A

+5 V

Output

BC

R2

Q1

Q3

R1



TTL : Active Pull Up Circuit (Totem-Pole Output)

An alternative which provides faster charging without increased power

dissipation

the active pull-up circuit.

A

+5 V

OutputBC

D1

Q4

R1

Q3

Q2

Q1

Totem-Pole



In output Low condition The phase splitter transistor Q3 is in saturation

The saturation current through R1 large enough to cause positive voltage drop

⇒ This positive voltage causes Q1 to saturate.

Base of Q2 is at 0.9 V

due to VBE of Q1 at 0.7 V

and VCE of Q3 at 0.2 V

Because of D1,

emitter of Q2 is more positive than collector of Q3

⇒ Q2 is off

D1 in the circuit to ensure that Q2 is cut-off when Q1 saturated.

A

+5 V

OutputBC

D1

Q4

R1

Q3

Q2

Q1



In output High condition Output High due to one of the inputs dropping low

⇒ Q3 and Q1 go into cut-off

However output remains momentarily low

as voltage across load capacitance cannot change instantaneously

As soon as Q3 turns off

⇒ Q2 conducts as its base is connected to VCC via resistor.

Current needed to charge load capacitance causes Q2 to momentarily saturate

⇒ output voltage rises with a time constant RC

A

+5 V

OutputBC

D1

Q4

R1

Q3

Q2

Q1



In output High condition

But as the Resistance R is typically :

Collector resistance of 130Ω +

resistance of the diode + saturation resistance of Q2

= 150Ω

The value of R is << passive pull-up resistance used in the open collector circuit

Transition from Low to High is much faster



Changes in Capacitive load

As the capacitive load charges

⇒⇒⇒⇒ the output voltage rises and current in Q4 decreases

⇒⇒⇒⇒ brings transistor into active region when in steady state condition

Q2 acts as an emitter follower as output terminal essentially at its emitter

In contrast to other transistors Q2 is in active region due to charging of capacitive loads

⇒ Thus the output circuit effectively acts as a two pole switch switching the output between ground and the supply voltage



Metrics VOH, VOL

VCC = +5 V but due to voltage drops in the output circuit

⇒⇒⇒⇒ VOL = 0.2 V (VCE of Q1)

⇒⇒⇒⇒ VOH = 3.6 V (VCC- (VBE of Q2 +D1))

Speed

• standard TTL is 3 times faster than DTL

Fan-out

• 8-10

NOTE

• High inputs at A, B and C will have to supply a small diode leakage current , IIH = 10 uA

• If one or more inputs are low, substantial current will flow through input terminal to ground, IIL = 1 mA



Metrics : With Q1 on

⇒ Vout will be a very low voltage

VOL depends on how much collector current Q1 conducts

With Q2 off• No current from +5 V supply through collector resistance.

• Can only come from inputs to which gate is connected.

• Q1 performs a current sinking action

• called the pull-down transistor

With Q2 on• Q2 supplies input current required by Q4 of other load gates

• Performs current sourcing actions

• called the pull-up transistor



Advantages of the Totem Pole Output Stage

1. Same output could be generated without Q2 and D1 and connecting resistor to collector of Q1.

However

⇒ Q1 would conduct a fairly large current in saturation state

with Q2 in circuit

⇒ no current through collector resistance in low state

⇒ keeps power dissipation in circuit low.



Advantages of the Totem Pole Output Stage

2. In the high state

• Q2 acts as an emitter follower with associated low o/p impedance

(10 Ω)

• Provides a short time constant for charging capacitive load on

the output

• This action, known as active pull-up provides faster switching

times



Disadvantages of the Totem Pole Output Stage

1. In transition from Low – High output state• Q1 turns off much faster than Q2 turns on

⇒ few nanoseconds when BOTH conduct.

• relatively high current 30 –40 mA will be drawn from supply.

• current spike generates noise on power supply distribution line

• if change in state is frequent

⇒ power dissipation increases.



The End

Walter Schottky

b. July 23, 1886, Zürich, Switzerlandd. March 4, 1976, Pretzfeld, W.Germany





1

Lecture-15

A.Amalin Prince




2

07-09-07



TTL : Active Pull Up Circuit (Totem-Pole Output)

An alternative which provides faster charging without increased power

dissipation

the active pull-up circuit.

A

+5 V

OutputBC

D1

Q4

R1

Q3

Q2

Q1

Totem-Pole



The Standard TTL series Characteristics

The propagation delay of a transistor which goes into saturation.

depends on two factors

Saturation delay (storage time delay)

RC time constant

By reducing resistor values

reduces RC time constant

decreases propagation delay

Trade-off is high power dissipation

lower resistance draws more current from the power supply



Low Power, 74L series

Similar as standard TTL

But all resistor values have been increased.

⇒ low power dissipation 1 mW

⇒ greater propagation delay 33 nseconds

good for applications with low frequency, battery operated circuits

calculators etc.



High Speed, 74H series

Similar as standard TTL

But all resistor values have been reduced.

Emitter follower has been replaced by a double emitter follower (Darlington

Pair)

⇒ faster switching ⇒ propagation delay 6 nseconds

but

⇒ increased power dissipation 23 mW



How to increase speed ?

Whatever is done to the value of the resistors

Speed is ultimately limited by the time required to pull the output transistors out of saturation.

74, 74L and 74H series all operate with saturated switching

many of the transistors, when conducting will be in a saturated condition

As has been seen this causes a saturation delay (storage delay), when

switching from ON to OFF

limits the circuit’s switching speed.



Schottky TTL, 74S series

Can this be improved ?

In Schottky TTL (STTL)

Transistors kept out of saturation by using Schottky barrier diodes (SD)

Formed by a junction of a metal and semiconductor

conventional diode with a junction of p-type and n-type semiconductor material

SD connected between the base and the collector

Do not allow the transistors to go as deeply into saturation

SD has a forward voltage drop of 0.4V




When the Collector-Base junction becomes forward biased at the on-set of saturation

⇒ SD will conduct, diverting some input current away from base.

⇒ this has effect of reducing the excess base current.

⇒ decreases saturation (storage time) delay at turn-off

74S00 NAND has average propagation delay of 3 nsecs

twice as fast as the 74H00

makes the 74H series redundant nowadays




A

+5 V

OutputBC

Q1

370ΩΩΩΩ

Q2

Q3

Q5

Q4

Q6

350ΩΩΩΩ

3.5kΩΩΩΩ

55ΩΩΩΩ

2.8kΩΩΩΩ 760ΩΩΩΩ




Schottky Transistor used 3 Schottky diodes inserted to limit negative inputs values

no diode in the Totem-pole output

Circuit also uses smaller resistor values to improve switching times

Improves the circuit average power dissipation to 20 mW

NOTE

All transistor are Schottky Transistors.

Q4 is not required to be a Schottky as it does not saturate but stays in active region




New combination of Q3 and Q6 still gives the two VBE drops

necessary to prevent Q4 from conducting when the output is low.

Combination comprises a double-emitter follower (Darlington pair)

Provides high current gain and extremely low resistance

needed during the low-to high swing of the output

rapid output rise time when switching ON-to-OFF

⇒ Results in a decrease in propagation delay.



Low Power Schottky TTL, 74LS series

74 LS is a low powered version of the 74S series

uses Schottky clamped configuration

but with larger resistor values then 74S

Low circuit power requirements

but at the expense of increase in switching times.

Power Dissipation 2 mW

Propagation Delay 9.5 nseconds

This is the mainstay of the TTL family

Found in nearly all new designs that do not require max speed.



Advanced Schottky TTL, 74AS series

As a result of the recent development in IC design and manufacturing process

High speed Schottky diodes

Power Dissipation 8 mW

Propagation Delay 1.7 nseconds



Advanced Low-Power Schottky TTL, 74ALS series

Improvement in both power and speed.

· Power Dissipation 1.2 mW

· Propagation Delay 4 nseconds

This series has

· the lowest speed-power product of the TTL series

· very close to the lowest gate power dissipation (c.f. 74L)

This will eventually replace 74LS as the most widely used TTL series.



Comparison of TTL Series Characteristics

74 74L 74H 74S 74LS 74AS 74

ALS

Performanc

e Ratings

Propagation

Delay (nSec)

9 33 6 3 9.5 1.7 4

Power

Dissipation

(mW)

10 1 23 20 2 8 1.2

Speed

Power

(pJ)

90 33 138 60 19 13.6 4.8

Max Clock

rate (MHz)

35 3 50 125 45 200 70

Fan-out

(same

series)

10 20 10 20 20 40 20

Voltage

Parameters

VOH(min) 2.4 2.4 2.4 2.7 2.7 2.5 2.5

VOL(max) 0.4 0.4 0.4 0.5 0.5 0.5 0.4

VIH(min) 2.0 2.0 2.0 2.0 2.0 2.0 2.0

VIL(max) 0.8 0.7 0.8 0.8 0.8 0.8 0.8

All of the performance ratings are for a NAND gate in each series.



Tri-State Devices

This kind of device include a third electrical state called high impedance or Hi-Z.

This new state is controlled by an input control line called output enable. When this input is asserted the device behaves like a normal gate, otherwise, the output behaves like an open circuit.



Tri-state Inverter



Tri-State Devices

One application of tri-state devices is to be used to connect several devices to a single bus. When changing which output is connected to bus one must ensure that all outputs must first go into the hi-Z state thus avoiding the possibility that two outputs would be connected to the bus simultaneously.



CMOS Logic Family

Complementary metal oxide semiconductor (CMOS) replaced TTL devices in the 90’s due to advances in the design of MOS circuits made in mid 80’s.

Advantages: Operate with a wider range of voltages that any other

logic family.

Has high noise immunity.

Dissipates very low power at low frequencies.

It requires an extremely low driving current.

High fanout.



CMOS Logic Family

Disadvantages: Power consumption increases with frequency.

Susceptible to ESD - electro-static discharges.

Sub-families: 40xx : Original CMOS family.

Fairly slow, but it has a low power dissipation.

74HCxx : High speed CMOS. Better current sinking and sourcing than 40xx. It uses

voltage supply between 2 and 6 volts.

Higher voltage →higher speed.

Lower voltage →lower power consumption.



CMOS Logic Family

Sub-families:

74HCTxx : High speed CMOS, TTL compatible.

Better current sinking and sourcing than 40xx. It uses voltage supply of 5V. Compatible with TTL family.

74ACxx : Advanced CMOS.

Very fast. It can source and sink high currents. Not TTL compatible.

74ACTxx : Advanced CMOS, TTL compatible.

Same as 74ACxx, but it is compatible with TTL family.



Logic Families

Sub-families: 74FCTxx : Fast CMOS, TTL compatible.

It is faster and has lower power dissipation than the 74ACxxand 74ACTxx sub-families. Compatible with TTL family.

Prefixes, usually added to device designation to identify the manufacturer. SN : Texas Instrument.

MN : Motorola.

DM : National

N : Signetics

P : Intel

H : Harris

AMD : Advanced Micro Devices



Logic Families

Prefixes, usually added to device designation to identify the manufacturer.

SN : Texas Instrument.

MN : Motorola.

DM : National

N : Signetics

P : Intel

H : Harris

AMD : Advanced Micro Devices

Suffixes, identifies the packaging.

N : Plastic DIP (dual in-line package)

P : Plastic DIP

J : Ceramic DIP

W : Ceramic flat package.

D : Plastic ‘small outline’ package



CMOS logic Circuit



Transmission Gate (TG)



Bilateral Switch



Components of a Simulation

Design Block

Stimulus Block



Test Bench



Example (2-1 Mux)//designblockmodule mm(a,b,s, o);

input a,b,s;output o;

assign o=s ? a:b;endmodule

//stimulus blockmodule testmux;reg ta,tb,ts;wire y;mm mux (ta,tb,ts,y); //instantiate mux

initialbegints=1;ta=0;tb=1;#10 ta=1;tb=0;#10 ts=0;#10 ta=0;tb=1;end

initial$monitor("s=%b a=%b b=%b o=%b time=%0d", ts,ta,tb,y,$time);

endmodule



Walter Schottkyb. July 23, 1886, Zürich, Switzerland

d. March 4, 1976, Pretzfeld, W.Germany

Walter Schottky was a German physicist whose research in solid-state physics and electronics yielded many effects and devices that now bear his name (Schottky effect, Schottky barrier, Schottkydiod).

The End

A.Amalin Prince EEE/INSTR Group

CS GC391/EEE GC391/INSTR GC391 Digital Electronics and Computer Organization




Lecture-16

A.Amalin Prince




Objective : Sequential Logic,Latches and Flip-Flops

10-09-07




Sequential Circuits




Introduction

• Sequential circuit

– Output depends not just on present inputs (as in

combinational circuit), but on past sequence of inputs

• Stores bits, also known as having “state”

– Simple example: a circuit that counts up in binary

• In sequential Logic, we will:

– Design a new building block, a flip-flop, that stores

one bit

– Combine that block to build multi-bit storage – a

register

– Describe the sequential behavior using a finite state

machine

– Convert a finite state machine to a controller – a

sequential circuit having a register and combinational

logic

si

z

e

ansis

Combinationaldigital circuit

1a

b

1F0

1a

b

? F0

Must know

sequence of

past inputs to

know output

Sequentialdigital circuit




Example Needing Bit Storage

• Flight attendant call button

– Press call: light turns on

• Stays on after button released

– Press cancel: light turns off

– Logic gate circuit to implement this?

QCall

Cancel

Doesn’t work. Q=1 when Call=1, but

doesn’t stay 1 when Call returns to 0

Need some form of “feedback” in the

circuit

BitStorage

Blue lightCallbutton

Cancelbutton

1. Call button pressed – light turns on

BitStorage


Cancelbutton

2. Call button released – light stays on

BitStorage


Cancelbutton

3. Cancel button pressed – light turns

off




First attempt at Bit Storage

• We need some sort of feedback

– Does circuit on the right do what we want?

• No: Once Q becomes 1 (when S=1), Q stays 1

forever – no value of S can bring Q back to 0

QS

t

0t

0Q

S0

1

0

1

0

1

0Q

t

S

0t

1Q

S0

0t

1Q

S1

1t

1Q

S1

1t

0 QS1




0

0

1

R=1

S=0t

Q

1

0

1

0R

S

1

0t

1

0Q

Bit Storage Using an SR Latch

Q

S (set) SR latch

R (reset)

• Does the circuit to the right, with cross-coupled NOR gates, do what we want?– Yes! How did someone come up with that circuit?

Maybe just trial and error, a bit of insight...

1

0 0

10

1

t

Q

S=0

R=0

t

Q

S=1

R=0

0

1

1

t

Q

R=0

S=0

1

01

0

0

01

1

X0

R

ecall...

Recall…




Example Using SR Latch for Bit Storage

• SR latch can serve as bit storage in previous example

of flight-attendant call button

– Call=1 : sets Q to 1

• Q stays 1 even after Call=0

– Cancel=1 : resets Q to 0

• But, there’s a problem...

R

S

Q

Call

but ton

Blue light

Cancelbut ton

BitStorage


Cancelbutton




Problem with SR Latch

• Problem

– If S=1 and R=1 simultaneously, we don’t know what value Q will take

R=1

S=1

0

0

0

0

t

Q

R=0

S=0

0

0

1

1

t

Q

R=0

S=0

1

1

0

0

t

Q

0

1

0

1

0

1

0

1

S

R

Q

t

1t

0

1Q

0

Q may oscillate. Then, because one path will be

slightly longer than the other, Q will eventually

settle to 1 or 0 – but we don’t know which.




Problem with SR Latch

• Problem not just one of a user pressing two buttons at same time

• Can also occur even if SR inputs come from a circuit that supposedly never sets S=1 and R=1 at same time

– But does, due to different delays of different paths1

0

1

0

1

0

1

0

X

Y

S

R

SR = 11The longer path from X to R than to S causes SR=11 for

short time – could be long enough to cause oscillation

RY

XS SR latch

Q

Arbitrarycircuit




SR NOR Latch




SR Latch with NAND Gates (SR Latch)




Solution: Level-Sensitive SR Latch

• Add enable input “C” as shown

– Only let S and R change when C=0

• Enure circuit in front of SR never sets SR=11, except briefly due to path delays

– Change C to 1 only after sufficient time for S and R to be stable

– When C becomes 1, the stable S and R value passes through the two AND gates to the SR latch’s S1 R1 inputs.

R1

S1S

C

R

Level-sensitive SR latch

Q

Though SR=11 briefly...

...S1R1 never = 11

S

CQ’

QR

Level-sensitive SR latch symbol

R1

S1S

X

Y

CClk

R


Q

0

1

0

1

0

1

0

1

0S

R

C

S1

R1

1




Clock Signals for a Latch

• How do we know when it’s safe to set C=1?– Most common solution –make C pulse up/down

• C=0: Safe to change X, Y

• C=1: Must not change X, Y

• We’ll see how to ensure that later

– Clock signal -- Pulsing signal used to enable latches

• Because it ticks like a clock

– Sequential circuit whose storage components all use clock signals: synchronous circuit

• Most common type

• Asynchronous circuits – important topic, but left for advanced course

R1

S1S

X

Y

CClk

R

Q





Clocks

• Clock period: time interval between pulses

– Above signal: period = 20 ns

• Clock cycle: one such time interval

– Above signal shows 3.5 clock cycles

• Clock frequency: 1/period

– Above signal: frequency = 1 / 20 ns = 50 MHz

• 1 Hz = 1/s

100 GHz

10 GHz

1 GHz

100 MHz

10 MHz

0.01 ns

0.1 ns

1 ns

10 ns

100 ns

PeriodFreq




The End






Lecture-17

A.Amalin Prince




Objective :Synchronous Sequential Logic

Flip-Flops and Register

12-09-07




Solution: Level-Sensitive SR Latch

• Add enable input “C” as shown

– Only let S and R change when C=0

• Enure circuit in front of SR never sets SR=11, except briefly due to path delays

– Change C to 1 only after sufficient time for S and R to be stable

– When C becomes 1, the stable S and R value passes through the two AND gates to the SR latch’s S1 R1 inputs.

R1

S1S

C

R


Q

Though SR=11 briefly...

...S1R1 never = 11

S

CQ’

QR

Level-sensitive SR latch symbol

R1

S1S

X

Y

CClk

R


Q

0

1

0

1

0

1

0

1

0S

R

C

S1

R1

1




Clock Signals for a Latch

• How do we know when it’s safe to set C=1?– Most common solution –make C pulse up/down

• C=0: Safe to change X, Y

• C=1: Must not change X, Y

• We’ll see how to ensure that later

– Clock signal -- Pulsing signal used to enable latches

• Because it ticks like a clock

– Sequential circuit whose storage components all use clock signals: synchronous circuit

• Most common type

• Asynchronous circuits – important topic, but left for advanced course

R1

S1S

X

Y

CClk

R

Q





Clocks

• Clock period: time interval between pulses

– Above signal: period = 20 ns

• Clock cycle: one such time interval

– Above signal shows 3.5 clock cycles

• Clock frequency: 1/period

– Above signal: frequency = 1 / 20 ns = 50 MHz

• 1 Hz = 1/s

100 GHz

10 GHz

1 GHz

100 MHz

10 MHz

0.01 ns

0.1 ns

1 ns

10 ns

100 ns

PeriodFreq




Level-Sensitive D Latch

• SR latch requires careful design to ensure SR=11 never occurs

• D latch relieves designer of that burden

– Inserted inverter ensures R always opposite of S

R

SD

C

D latch

Q

1

0D

C

S

R

Q

1

0

1

0

1

0

1

0

D Q’

QC

D latch symbol




Problem with Level-Sensitive D Latch

• D latch still has problem (as does SR latch)– When C=1, through how many latches will a signal travel?

– Depends on for how long C=1

• Clk_A -- signal may travel through multiple latches

• Clk_B -- signal may travel through fewer latches

– Hard to pick C that is just the right length

• Can we design bit storage that only stores a value on the rising edge of a clock signal?

D1 Q1 D2 Q2 D3 Q3 D4

C4C3C2C1

Q4Y

Clk

Clk_A Clk_B

Clk

rising edges




D Flip-Flop

• Flip-flop: Bit storage that stores on clock edge, not level

• One design -- master-servant (master-slave)

– Two latches, output of first goes to input of second, master latch has inverted clock signal

– So master loaded when C=0, then servant when C=1

– When C changes from 0 to 1, master disabled, servant loaded with value that was at D just before C changed -- i.e., value at D during rising edge of C

Clk

D/Dm

Qm/Ds

Cm

Cs

Qs

Clk

rising edges

Note: Hundreds of different flip-flop designs exist

D latch

master

D latch

servant

DDm Ds

Cs

Qm Qs’

QsQ

Q’

Cm

Clk

D flip-flop




D Flip-Flop

D Q’

Q

Q’D

Q

Symbol for rising-edge

triggered D flip-flop

Symbol for falling-edge

triggered D flip-flop

Clk

rising edges

Clk

falling edges

Internal design: Just

invert servant clock

rather than masterThe triangle

means clock

input, edge

triggered




D Flip-Flop

• Solves problem of not knowing through how many latches a signal travels when C=1

– In figure below, signal travels through exactly one flip-flop, for Clk_A or Clk_B

– Why? Because on rising edge of Clk, all four flip-flops are loaded simultaneously -- then all four no longer pay attention to their input, until thenext rising edge. Doesn’t matter how long Clk is 1.

Two latches inside each flip-flop

D1 Q1 D2 Q2 D3 Q3 D4 Q4Y

Clk

Clk_A Clk_B

T

w

o l

a

t

ches

inside each

fli

p

-flop




D Latch vs. D Flip-Flop

• Latch is level-sensitive: Stores D when C=1

• Flip-flop is edge triggered: Stores D when C changes from 0 to 1– Saying “level-sensitive latch,” or “edge-triggered flip-flop,” is

redundant

– Two types of flip-flops -- rising or falling edge triggered.

• Comparing behavior of latch and flip-flop:

Clk

D

Q (D latch)

Q (D flip-flop) 10

87

654

9

3

1 2




Flight-Attendant Call Button Using D Flip-Flop

• D flip-flop will store bit

• Inputs are Call, Cancel, and present value of D flip-flop, Q

• Truth table shown below

Preserve value: if

Q=0, make D=0; if

Q=1, make D=1

Cancel -- make

D=0

Call -- make D=1

Let’s give priority

to Call -- make

D=1

Circuit derived from truth table, using Chapter 2

combinational logic design process

Call

button

Cancel

button

Flightattendant

call-buttonsystem

Bluelight

D Q’

QClk

Call

button

Cancelbutton

Bluelight

Call

Cancel

Q




Bit Storage Summary

• We considered increasingly better bit storage until we arrived at the robust D flip-flop bit storage

D flip-flop

D latch

master

D latch

servant

DmQm

Cm

DsD

Clk

Qs’

Cs Qs

Q’

Q

S

R

D

Q

C

D latch

Feature: Only loads D value present at rising clock edge, so values can’t propagate to other flip-flops during same clock cycle. Tradeoff: uses more gates internally than D latch, and requires more external gates than SR – but gate count is less of an issue today.

Feature: SR can’t be 11 if D is stable before and while C=1, and will be 11 for only a brief glitch even if D changes while C=1. Problem: C=1 too long propagates new values through too many latches: too short may not enable a store.

S1

R1

S

Q

C

R


Feature: S and R only have effect when C=1. We can design outside circuit so SR=11 never happens when C=1. Problem: avoiding SR=11 can be a burden.

R (reset)

S (set)

Q

SR latch

Feature: S=1 sets Q to 1, R=1 resets Q to 0. Problem: SR=11 yield undefined Q.




More on Flip-Flops

• Other flip-flop types

– SR flip-flop: like SR latch, but edge triggered

– JK flip-flop: like SR (SJ, RK)

• But when JK=11, toggles

• 10, 01

– T flip-flop: JK with inputs tied together

• Toggles on every rising clock edge

– Previously utilized to minimize logic outside flip-flop

• Today, minimizing logic to such extent is not as important

• D flip-flops are thus by far the most common




SR Flip-Flop




D Flip-Flop




JK Flip-Flop




T Flip-Flop




Flip-Flop Set and Reset Inputs (Asynchronous inputs)

• Some flip-flops have additional inputs

– Synchronous reset: clears Q to 0 on next clock edge

– Synchronous set: sets Q to 1 on next clock edge

– Asynchronous reset: clear Q to 0 immediately (not dependent on clock edge)

• Example timing diagram shown

– Asynchronous set: set Q to 1 immediately

D Q’

QR

Q’

AR

D

Q

Q’

AS

ARD

Q

cycle 1 cycle 2 cycle 3 cycle 4

clk

D

AR

Q




D Flip-Flop with Asynchronous reset




Active Low Inputs

• We’ve assumed input action occur when input is 1

– Some inputs are instead active when input is 0 -- “active low”

– Shown with inversion bubble

– So to reset the shown flip-flop, set R=0. Else, keep R=1.

D Q’

QR




Basic Register

• Typically, we store multi-bit items– e.g., storing a 4-bit binary number

• Register: multiple flip-flops sharing clock signal– From this point, we’ll use registers for bit storage

• No need to think of latches or flip-flops

• But now you know what’s inside a register

DQ

DQ

DQ

DQ

I2I3

Q2Q3 Q1 Q0

I1 I0

clk

4-bit register

I3 I2 I1 I0

Q3 Q2 Q1 Q0

reg(4)




Example Using Registers: Temperature Display

• Temperature history display

– Sensor outputs temperature as 5-bit binary number

– Timer pulses C every hour

– Record temperature on each pulse, display last three recorded values

(In practice, we would actually avoid connecting the timer outputC to a clock input, instead only connecting an oscillator output to a clock input.)

a4x4

x3

x2

x1

x0

C

a3 a2 a1 a0

t

empe

r

a

tu

r

e

sensor

timer

Display

Present

b4 b3 b2 b1 b0

Display

TemperatureHistoryStorage

1 hour ago

c4 c3 c2 c1 c0

Display

2 hours ago

We will

design later




Example Using Registers: Temperature Display

• Use three 5-bit registers

15 18 20

0

0

0

18

0

0

21

18

0

24

21

18

25

24

21

26

25

24

27

26

25

21 21 22 24 24 24 25 25 26 26 26 27 27 27 27x4...x0

C

Ra

Rb

Rc

Q4

C

x4

x3

x2

x1

x0

Q3

Q2

Q1

Q0

Ra Rb

I4

I3

I2

I1

I0

Q4

a4 a3 a2 a1 a0

Q3

Q2

Q1

Q0

I4

I3

I2

I1

I0

Rc

Q4

b4 b3 b2 b1 b0

Q3

Q2

Q1

Q0

I4

I3

I2

I1

I0

c4 c3 c2 c1 c0





The End






Lecture-18

A.Amalin Prince





Registers and Shift Registers

14-09-07




Introduction to datapath components

• Chapters 4 & 5: Introduced increasingly complex digital building blocks

– Gates, multiplexors, decoders, basic registers, and controllers (yet to be discussed)

• Controllers good for systems with control inputs/outputs

– Control input: Single bit (or just a few), representing environment event or state

• e.g., 1 bit representing button pressed

– Data input: Multiple bits collectively representing single entity

• e.g., 7 bits representing temperature in binary

• Need building blocks for data

– Datapath components, aka register-transfer-level (RTL) components, store/transform data

• Put datapath components together to form a datapath

• Here I introduce numerous datapath components, and simple datapaths

– In chapter 8 : will combine controllers and datapaths into “processors”

si

z

e

ansis




Registers

• Can store data, very common in datapaths

• Basic register : Loaded every cycle

– Useful for implementing FSM -- stores encoded state

– For other uses, may want to load only on certain

cycles

si

z

e

ansis

Combinationallogic

State register

s1 s0

n1

n0

xb

clk

I3 I2 I1 I0

Q3 Q2 Q1 Q0

reg(4)

Basic register loads on every clock cycle

load

How extend to only load on certain cycles?

D

Q

D

Q

D

Q

D

Q

I2I3

Q2Q3 Q1 Q0

I1 I0

clk

4-bit register




Register with Parallel Load




Register with Parallel Load

• Add 2x1 mux to front of each flip-flop

• Register’s load input selects mux input to pass

– Either existing flip-flop value, or new value to load

1 0

D

Q

Q3

I3

1 0

D

Q

Q2

I2

1 0

Q

Q1

I1

1 0

D

Q

Q0

I0

load

= 0

1 0

2⋅ 1

D

Q

Q3

I3

load

load

1 0

D

Q

Q2

I2

1 0

D

Q

Q1

I1

1 0

D

Q

Q3

I3

1 0

D

Q

Q2

I2

1 0

D

Q

Q1

I1

1 0

D

Q

Q0

I0

load

= 1

(b)

(c)(a)

1 0

D

Q

Q0

I0

I3 I2 I1 I0

Q3 Q2 Q1 Q0

D




Basic Example Using Registers

• This example will show how registers load simultaneously

on clock cycles

– Notice that all load inputs set to 1 in this example -- just for demonstration purposes

Q3 Q2 Q1 Q0

a3 a2 a1 a0

I3 I2 I1 I0

Q3 Q2 Q1 Q0

I3ld1 I2 I1 I0

ld1 ld1

Q3 Q2 Q1 Q0

I3 I2 I1 I0

R1

R0

R2

clk




Basic Example Using Registers

Q3 Q2 Q1 Q0

a3 a2 a1 a0

I3 I2 I1 I0

Q3 Q2 Q1 Q0

I3ld1 I2 I1 I0

ld1 ld1

Q3 Q2 Q1 Q0

I3 I2 I1 I0

R1

R0

R2

clk

????

????

R1

????

R2

–>1111

R0

clk

a3..a0

R0

R1

R2

giv

en

????

1111

R1

????

R2

1111–>0001

R0

1111

0001

R1

0000

R2

0001–>1010

R0

0001

1010

R1

1110

R2

1010

R0

1010

1010

R1

0101

R2

1010

R0

1010

1010

R1

0101

R2

1010

R0

(a)

(b)

1111

????

????

????

????

????

0001

1111

1111

0000

0001

0001

1110

1010

1010

0101

1010

1010

0101

1010

1010

1 2 3 4 5




Register Example using the Load Input: Weight Sampler

• Scale has two displays

– Present weight

– Saved weight

– Useful to compare

present item with previous

item

• Use register to store weight

– Pressing button causes

present weight to be

stored in register

• Register contents

always displayed as

“Saved weight,” even

when new present

weight appears

Scale

Saved weight

Weight Sampler

Present weight clk

bSave

I3 I2 I1 I0

Q3 Q2 Q1 Q0

load3 pounds

0 0 1 1

0 0 1 1

3 pounds

0 0 1 0

2 pounds1




Register Example: Temperature History Display

• Recall example– Timer pulse every hour

– Previously used as clock. Better design only connects oscillator to clock inputs -- use registers with load input, connect to timer pulse.

Q4

C

x4

x3

x2

x1

x0

Q3

Q2

Q1

Q0

Ra Rb

I4

I3

I2

I1

I0

Q4

a4 a3 a2 a1 a0

Q3

Q2

Q1

Q0

I4

I3

I2

I1

I0

Rc

Q4

b4 b3 b2 b1 b0

Q3

Q2

Q1

Q0

I4

I3

I2

I1

I0

c4 c3 c2 c1 c0


Q4

Clk

C

t4

t3

t2

t1

t0

Q3

Q2

Q1

Q0

ld

Ra Rb Rc

ld

I4

I3

I2

I1

I0

Q4

a4 a3 a2 a1 a0

Q3

Q2

Q1

Q0

I4

I3

I2

I1

I0

ld

Q4

b4 b3 b2 b1 b0

Q3

Q2

Q1

Q0

I4

I3

I2

I1

I0

c4 c3 c2 c1 c0

TemperatureHistoryStoragetimer

osc

new line




Register Example: Above-Mirror Display

C

d0

d1

d2

d3e

i0

i0

i1

i2

i3

a0

a1

load

i1

2⋅ 4F

r

omthe car's

c

e

n

t

r

al

c

ompu

t

er

8

8

8

8

8Dd

8

x y

s1 s0

8-bit4×1

T

o the ab

o

v

e

mi

r

r

or displ

a

y

load

load

load

load

reg0

reg1

reg2

reg3

T

A

I

M

• Lecture-11 example: Four simultaneous values from car’s computer

• To reduce wires: Computer writes only 1 value at a time, loads into one of four registers

– Was: 8+8+8+8 = 32 wires

– Now: 8 +2+1 = 11 wires

0

1

0001010

1

1

0001010

Loaded on clock edge

8

Shorthand notation




Register Example: Computerized Checkerboard

• Each register holds values for one column of lights

– 1 lights light

• Microprocessor loads one register at a time

– Occurs fast

enough that

user sees

entire board

change at once

LED

R7 R6

d6 d5 d4 d3 d2 d1 d0d7

8

D

R5 R4 R3 R2 R1 R0

e i2 i1 i0 3⋅ 8 decoder

microprocessor

lit LED

1

1

0

0

0

0

0

1

Q

IR0

load10100010

fromdecoder

frommicroprocessor

(b)

(a)




Register Example: Computerized Checkerboard

010000101 101000101010001010100010 10100010010000101 010000101 010000101

001 (R1) 100 (R4)010 (R2)000 (R0) 110 (R6)011 (R3) 101 (R5) 111 (R7)

clk

e

i2,i1,i0

D

LED

lit LED

10100010 10100010 10100010 10100010

01000101 01000101 01000101 01000101

R7 R6 R5 R4 R3 R2 R1 R0




Shift Register

• Shift right

– Move each bit one position right

– Shift in 0 to leftmost bit

1 1 0 1Register contentsbefore shift right

0 1 1 0

0

Register contentsafter shift right

Q: Do four right shifts on 1001, showing value after each shift

A: 1001 (original)

0100

0010

0001

0000 shr_in

• Implementation: Connect flip-flop

output to next flip-flop’s input




Shift Register

• To allow register to either shift or retain, use 2x1 muxes

– shr: 0 means retain, 1 shift

– shr_in: value to shift in

• May be 0, or 1

• Note: Can easily design shift register that shifts left instead

1 02⋅ 1

D

Q

Q3

1 0

D

Q

Q2

1 0

D

Q

Q1

1 0

D

Q

Q0

shr=

11 0

2⋅ 1

D

Q

Q3

shr

shr_in

shr

shr_in

1 0

D

Q

Q2

1 0

D

Q

Q1 (b)

(c)

(a)

1 0

D

Q

Q0

Q3 Q2 Q1 Q0




Rotate Register

• Rotate right: Like shift right, but leftmost bit comes from

rightmost bit

1 1 0 1

1 1 1 0

Register contentsbefore shift right

Register contentsafter shift right




Shift Register Example: Above-Mirror Display

• Earlier example: 8 +2+1 = 11wires from car’s computer to above-mirror display’s four registers

– Better than 32 wires,

but 11 still a lot --

want fewer for

smaller wire bundles

• Use shift registers

– Wires: 1+2+1=4

– Computer sends one

value at a time, one

bit per clock cycle

C

d0

d1

d2

d3e

i0

i0

i1

i2

i3

a0

a1

load

i1

2⋅ 4

From

the

car's

cent

ralc

ompu

ter

8

8

8

8

8Dd

8

x y

s1 s0

8-bit4⋅ 1

To the abovem

irror display

load

load

load

load

reg0

reg1

reg2

reg3

T

A

I

M

11 w

ires

c

d0

d1

d2

d3e

i0

i0s1 s0

x y

i1

i2

i3

a0

a1

shift

i1

2⋅ 48

8

8

8Dd

8

4×1

shrshr_in

shrshr_in

shrshr_in

shrshr_in

reg0

reg1

reg2

reg3

T

A

I

M

Note: this line is 1 bit, rather than 8 bits like before




Multifunction Registers

• Many registers have multiple functions– Load, shift, clear (load all 0s)

– And retain present value, of course

• Easily designed using muxes– Just connect each mux input to achieve

desired function

s1

shr_in

s0

3 2 1

I3

0

D

Q

Q3

Q2 Q1 Q0Q3

I2 I1 I0I3

Q2

0

3 2 1

I2

0

D

Q

0

Q1

3 2 1

I1

0

D

Q

0

Q0

3 2 1

I0

0

D

Q

0

4⋅ 1 shr_ins1s0

(a)

(b)

Functions:Operation

Maintain present value

Parallel load

Shift right

(unused - let's load 0s)

s0

0

1

0

1

s1

0

0

1

1




Multifunction Registers

shr_inshl_in

3 2 1

I3

0

D

Q

Q3

Q2 Q1 Q0Q3

I2 I1 I0I3

Q2

3 2 1

I2

0

D

Q

Q1

3 2 1

I1

0

D

Q

Q0

3 2 1

I0

0

D

Q

shl_inshr_ins1s0

(a) (b)

Operation

Maintain present value

Parallel load

Shift right

Shift left

s0

0

1

0

1

s1

0

0

1

1




Maintain valueShift leftShift rightShift rightParallel loadParallel loadParallel loadParallel load

NoteOperations0s1

01110000

01001111

OutputsInputs

01010101

00110011

00001111

ld shr shl

Truth table for combinational circuit

Multifunction Registers with Separate Control

Inputs

Maintain present valueShift leftShift rightShift right – shr has priority over shlParallel loadParallel load – ld has priorityParallel load – ld has priorityParallel load – ld has priority

Operationshlshrld

00001111

00110011

01010101

Q2 Q1 Q0Q3

Q2 Q1 Q0Q3

I2 I1 I0I3

I2 I1 I0I3

s1shr_in

shr_in

shr

shl

ld

s0shl_in

shl_in

?combi-nationalcircuit

s1 = ld’*shr’*shl + ld’*shr*shl’ + ld’*shr*shl

s0 = ld’*shr’*shl + ld




Register Operation Table

• Register operations typically shown using compact version of table

– X means same operation whether value is 0 or 1

• One X expands to two rows

• Two Xs expand to four rows

– Put highest priority control input on left to make reduced table simple

Maintain value

Shift left

Note

Operations0s1

0

1

0

1

OutputsInputs

0

1

0

0

0

0

Shift right

Shift right

1

1

0

0

0

1

1

1

0

0

Parallel load

Parallel load

Parallel load

Parallel load

0

0

0

0

1

1

1

1

0

1

0

1

0

0

1

1

1

1

1

1

ld shr shl

Maintainvalue

Shift left

Operationld shr shl

0

1

0

0

0

0

Parallel loadXX1

Shift rightX10




Register Design Process

• Can design register with desired operations using simple four-step process




Register Design Example

• Desired register operations

– Load, shift left, synchronous clear, synchronous set

Step 1: Determine mux size

5 operations: above, plus maintain

present value (don’t forget this one!)

--> Use 8x1 mux

Step 2: Create mux operation table

Step 3: Connect mux inputs

Step 4: Map control lines

Operation

Maintain present valueParallel loadShift leftSynchronous clearSynchronous setMaintain present valueMaintain present valueMaintain present value

s0

01010101

s1

00110011

s2

00001111

D

Q

Qn

7 6 3 2 1

In

05 4

1 0

s2s1s0

fromQn-1

Operation

Maintain present valueShift left

Parallel load

Set to all 1s

Clear to all 0s

s0

00

1

0

1

s1

01

0

0

1

s2

00

0

1

0

shl

01

X

X

X

ld

00

1

X

X

clr

00

0

0

1

Inputs Outputs

set

00

0

1

X

s2 = clr’*set

s1 = clr’*set’*ld’*shl + clr

s0 = clr’*set’*ld + clr




Register Design Example

Step 4: Map control lines

Operation

Maintain present valueShift left

Parallel load

Set to all 1s

Clear to all 0s

s0

00

1

0

1

s1

01

0

0

1

s2

00

0

1

0

shl

01

X

X

X

ld

00

1

X

X

clr

00

0

0

1

Inputs Outputs

set

00

0

1

X

s2 = clr’*set

s1 = clr’*set’*ld’*shl + clr

s0 = clr’*set’*ld + clr

Q2 Q1 Q0Q3

Q2 Q1 Q0Q3

I2 I1 I0I3

I2 I1 I0I3

s1ld

shl

s0shl_in

shl_incombi-nationalcircuit

set

clr

s2




The End






Lecture-19

A.Amalin Prince





Counters

17-09-07




Counters

• Synchronous Counters

• Ripple Counters

• Counter with unused states or Self Correcting Counters

• Counters based on Shift Registers

– Ring Counter

– Johnson Counter




Ring Counter




Johnson Counter (Switch-tail Counter)

DC = (A+C)B




Ripple Counters

• The Flip-Flop output transition serves as a source for triggering other Flip-Flops

• All Flip-Flops are not triggered by same clock




Binary Ripple Counter




BCD Ripple Counter




BCD Ripple Counter

1 0 0 1

1 0 0 0

0 1 1 1

0 1 1 0

0 1 0 1

0 1 0 0

0 0 1 1

0 0 1 0

0 0 0 1

0 0 0 0

Q8 Q4 Q2 Q1




Three decade decimal counter




The End

HDL FOR SEQUENTIAL

CIRCUITS

LECTURE- 20

• PREFER BEHAVIORAL MODELING

• TWO KINDS OF BEHAVIORAL STATEMENTS– initial – Always

• Syntax

initial always@(event control expn)begin begin

block of statements block of statementsend end

• Keywords for positive and negative edge trigeringposedge and negedge

D Latch

module Latch(Q,D,EN);

output Q; input D,EN;

reg Q;

always@(EN,D)

if(EN) Q=D;

endmodule

D -FLIP FLOP

module DFF(Q,D,CLK);

output Q; input D,CLK;

reg Q;

always@(posedge CLK)

Q=D;

endmodule

D ff with asynchronous reset

module DFF(Q,D,CLK,RST);

output Q; input D,CLK,RST;

reg Q;

always@(posedge CLK,negedge RST)

if (~RST) Q=1’b0;

else Q=D;

endmodule

T ff from DFF

module Tff(Q,T,CLK,RST);

output Q; input T,CLK,RST;

wire DT;

assign DT = Q^T;

DFF (Q,DT,CLK,RST);

endmodule

Sequential statements

PARALLEL BLOCKS

• Keyword –fork and join

• All statement execute concurrently inside the initial statement

initial

fork

x=1’bo; //completes at time 0

#5 y = 1’b1; // completes at time 5

#10 z = x,y; //completes at time 10

join

Counter –counts 0 to N.

Shift registers

• 8 bit shift registers

• It shifts 1 bit right when r_l =1 other wise it shifts left

• Barrel shifter






Lecture-21

A.Amalin Prince





Counters

28-09-07




Counters

• Synchronous Counters

• Ripple Counters

• Counter with unused states or Self Correcting Counters

• Counters based on Shift Registers

– Ring Counter

– Johnson Counter




COUNTER TYPESAsynchronous Counter (a.k.a. Ripple or Serial Counter):each FF is triggered one at a time with output of one FF serving as clock input of next FF in the chain.

Synchronous Counter (a.k.a. Parallel Counter): all the FF’s in the counter are clocked at the same time.

Up Counter: counter counts from zero to a maximum count.

Down Counter: counter counts from a maximum count down to zero.

BCD Counter: counter counts from 0000 to 1001 before it recycles.

Pre-settable Counter: counter that can be preset to any starting count either synchronously or asynchronously

Ring Counter: shift register in which the output of the last FF is connected back to the input of the first FF.

Johnson Counter: shift register in which the inverted output of the last FF is connected to the input of the first FF.




Synchronous Counters

• N-bit up-counter: N-bit register that can increment (add 1) to its

own value on each clock cycle

– 0000, 0001, 0010, 0011, ...., 1110, 1111, 0000

– Note how count “rolls over” from 1111 to 0000

• Terminal (last) count, tc, equals1

during value just before rollover

• Internal design

– Register, incrementer, and N-input AND gate to detect terminal count

cnt

tc C

4-bit up-counter

4

0000

01

00010010001101000101...11100 111110 00000001

ld4-bit register

Ctc

4

4 4

4

cnt

4-bit up-counter

+1




Incrementer

• Counter design used incrementer

• Incrementer design

– Could use carry-ripple adder with B input set to 00...001

• But when adding 00...001 to another number, the leading 0’s

obviously don’t need to be considered -- so just two bits being

added per column

– Use half-adders (adds two bits) rather than full-adders (adds three bits)

0 0 1 1

0 1 1

1+

carries:

unused

0000 1

(a)

(b)

a3 a2 a1 a0 1

s0s1s2s3co

a b

co s

HA

a b

co s

HA

a b

co s

HA

a b

co s

HA

I

r

n

t

a3

co s3s2

+1

s1s0

a2 a1 a0




Incrementer

• Can build faster incrementerusing combinational logic

design process

– Capture truth table

– Derive equation for each output

• c0 = a3a2a1a0

• ...

• s0 = a0’

– Results in small and fast circuit

– Note: works for small N -- larger N leads to exponential growth, like for N-bit adder

s2

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

s1

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

s0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

s3

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

c0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

a0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

a1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

a3

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

Inputs Outputs

a2

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1




Counter Example: Mode in Above-Mirror Display

• Recall above-mirror display already discussed– Assumed component that incremented xy input each time button

pressed: 00, 01, 10, 11, 00, 01, 10, 11, 00, ...

– Can use 2-bit up-counter

• Assumes mode=1 for just one clock cycle during each button press

– Remember “Button press synchronizer”

cnt

tc c1c0

x y

2-bit up countermode

clk




Counter Example: 1 Hz Pulse Generator Using 256 Hz Oscillator

• Suppose have 256 Hz oscillator, but want 1 Hz

pulse

– 1 Hz is 1 pulse per second -- useful for keeping time

– Design using 8-bit up-counter, use tc output as pulse

• Counts from 0 to 255 (256

counts), so pulses tc every

256 cycles

cnt

tc C

(unused)

8-bit up-counter1

osc(256 Hz) 8

p(1 Hz)




Down-Counter

• 4-bit down-counter

– 1111, 1110, 1101, 1100, …, 0011, 0010, 0001, 0000, 1111, …

– Terminal count is 0000

• Use NOR gate to detect

– Need decrementer (-1) –design like designed incrementer

ld4-bit register

Ctc

4

4 4

4

cnt

4-bit down-counter

–1




Up/Down-Counter

• Can count either up or down

– Includes both incrementer and decrementer

– Use dir input to select, using 2x1: dir=0 means up

– Likewise, dir selects appropriate terminal count value

ld 4-bit register

Ctc

4

44 44

4

cntclr

clr

dir

4-bit up/down counter

4 4

–1 +1

1 02x1

1 04-bit 2 x1




Counter Example: Light Sequencer

• Illuminate 8 lights from right to left, one at a time, one per

second

• Use 3-bit up-counter to

counter from 0 to 7

• Use 3x8 decoder to illuminate appropriate light

• Note: Used 3-bit counter with 3x8 decoder

– NOT an 8-bit counter – why not?

lights

0 0 00 0 10 1 0

3-bit up-countercnt

tc c2 c1 c0

3x8 dcd i2 i1 i0

unused

1

clk

(1 Hz)

d7 d6 d5 d4 d3 d2 d1 d0




Counter with Parallel Load

• Up-counter that can be loaded with external

value

– Designed using 2x1 mux– ld input selects incremented value or external value

– Load the internal register when loading external value or when counting

ld4-bit register

Ctc

4

4 4

cnt

ld

+1

1 04-bit 2x1

L 4

4




Counter with Parallel Load

• Useful to create pulses at specific multiples of clock– Not just at N-bit counter’s natural

wrap-around of 2N

• Example: Pulse every 9 clock cycles– Use 4-bit down-counter with

parallel load

– Set parallel load input to 8 (1000)

– Use terminal count to reload

• When count reaches 0, next cycle loads 8.

– Why load 8 and not 9? Because 0 is included in count sequence:

• 8, 7, 6, 5, 4, 3, 2, 1, 0 9 counts

cnt

ld

tc C

L

1

clk

4

4

1000

4-bit down-counter




4-bit binary counter with parallel load

No change001

Count to

next state

101

Load

inputs

X11

Clear to 0XXX0

FunctionCountLoadCLKClear




BCD Counter using a Counter with Parallel Load

Counter with

Parallel Load

Counter with

Parallel Load




Counter Example: New Year’s Eve Countdown Display

• Above example previously used microprocessor to counter from 59 down to 0 in binary

• Can use 8-bit (or 7- or 6-bit) down-counter instead, initially loaded with 59

d0i0

i1

i2

i3

i4

i5

c0

c1

c2

c3

c4

c5

c6

c7

tc

d1

d2

d3

d58

d59

d60

d61

d62

d636x64dcd

8-bitdown-counter

598

L

ld

cnt

clk(1 Hz)

reset

fireworks

HappyNewYear

0

1

2

3

58

59

countdown




Counter Example: 1 Hz Pulse Generator from 60 Hz Clock

• U.S. electricity standard uses 60 Hz signal

– Device may convert that to 1 Hz signal to count seconds

• Use 6-bit up-counter

– Can count from 0 to 63

– Create simple logic to detect 59 (for 60 counts)

• Use to clear the counter

back to 0 (or to load 0)

Ctc

p

1

osc

(60 Hz)

(1 Hz)

clr

cnt 6-bit up counter

59 in binary 111011




Timer

• A type of counter used to measure time

– If we know the counter’s clock frequency and the count, we know the time that’s been counted

• Example: Compute car’s speed using two sensors

– First sensor (a) clears and starts timer

– Second sensor (b) stops timer

– Assuming clock of 1kHz, timer output represents time to travel between sensors. Knowing the distance, we can compute speed




IC ASYNCHRONOUS COUNTERS

___CPo

___CP1

Qo(LSB)

Q1 Q2 Q3(MSB)MR1

MR2*All J, K inputs internally

connected HIGH

Logic Diagram for 7493

JCPK

RQN

QJCPK

RQN

QJCPK

RQN

Q JCPK

RQN

Q

Qo

7493___

CPo

___

CP1

Q1

Q2

Q3

MR1

MR2




7493 AS A MOD-16 COUNTER

___CPo

___CP1

Qo(LSB)

Q1 Q2 Q3(MSB)MR1


connected HIGH

Logic Diagram for 7493

JCPK

RQN

QJCPK

RQN

QJCPK

RQN

Q JCPK

RQN

Q

Qo

7493___

CPo

___

CP1

Q1

Q2

Q3MR1 MR2

10 kHz

F= 10 kHz/16 = 625 Hz




TEST

Build a MOD 10 counter with a 7493Build a MOD 10 counter with a 7493

10 kHz

MR2

Qo

7493___

CPo

___

CP1

Q1

Q2

Q3MR1

F= 10 kHz/10 = 1KHz

___CPo

___CP1

Qo(LSB)

Q1 Q2 Q3(MSB)MR1


connected HIGH

JCPK

RQN

QJCPK

RQN

QJCPK

RQN

Q JCPK

RQN

Q




BCD COUNTER

•Binary counter that counts from 0000 to 1001 before it recycles (MOD-10).

•Widespread applications where pulses or events are to be countedand the results displayed on a decimal numerical read-out.

•Also used for dividing a pulse frequency exactly by 10.

BCDcounter

Tens

ABCD

Decoder/display0-9

BCDcounter

Units

ABCD

Decoder/display0-9

BCDcounter

Hundreds

ABCD

Decoder/display0-9

Input

Cascading BCD counters to count and display from 000 to 999.




MR2

Qo

7493___

CPo

___

CP1

Q1

Q2

Q3MR1MR2

Qo

7493___

CPo

___

CP1

Q1

Q2

Q3

notused

MOD-60 COUNTER

MOD 10MOD 6

Two 7493s can be combined to produce a MODTwo 7493s can be combined to produce a MOD--60 Counter60 Counter

fin/10f

out = f

in/60

fin




DIGITAL CLOCK




Counters with unused states

(Self Correcting Counter)

What happens if we fall in unused states?

In this case, 111 results in 000. 011 results in

100.

The Counter is self-correcting.

Design a counter: 000-001-010-100-101-110-000…




Counters with unused states

Present State Next State Flip-Flop InputsA B C A B C JA KA JB KB JC KC0 0 0 0 0 1 0 X 0 X 1 X0 0 1 0 1 0 0 X 1 X X 10 1 0 1 0 0 1 X X 1 0 X1 0 0 1 0 1 X 0 0 X 1 X1 0 1 1 1 0 X 0 1 X X 1

1 1 0 0 0 0 X 1 X 1 0 X

JA=KA=B

JB=C, KB=1

JC=B’ KC=1




The End






Lecture-22

A.Amalin Prince




Objective :Analysis of Clocked Sequential Circuits, FSM (Finite State Machine)and Controller Design

01-10-07




Synchronous Sequential (Clocked) Networks

General model of a sequential network




Structure an Operation of Clocked Synchronous

Sequential Networks

Structure of a clocked synchronous sequential

network




Models

• The Synchronous or Clocked sequential circuits are represented by two models

– Mealy circuit: The output

depends on both the

present state of the flip-

flop(s) and on the

input(s).

– Moore Circuit: The

output depends only on

the present state of the

flip-flop(s)

a) Its output is a function of present state only

b) Input changes does not affect the output

c) It requires more number of states for implementing same function.

a) Its output is a function of present state as well as present input

b) Input changes may affect the output

c) It requires less number of states for implementing same function.

Moore Machine

(Model)

Mealy Machine

(Model)




Mealy Machine

Mealy model of a clocked synchronous sequential network

( , )Q f X Q+

= ( , )Z g X Q=




Moore Machine

( , )Q f X Q+

= ( )Z g Q=

Moore model of a clocked synchronous sequential network




Analysis of Clocked Synchronous Sequential Networks

• Two main reason for beginning the study of clocked

sequential networks with

analysis

– Useful when sequential networks are to be designed

– The steps involved in the synthesis of clocked synchronous sequential network are basically the reverse of those involved in the analysis procedure

The analysis procedure




Example: Mealy Machine

1 2 1 2

2 21 2

E x ita tio n ex p ress io n s

D

D

x Q Q Q

x Q Q Q

= +

= +

1 1 2

Output expressions

z= xQ xQ Q+





• Transition Equations

– By substituting the excitation expressions for a flip-flop into its

characteristic equation, an algebraic description of the next state of the

flip-flop is obtained. These expressions are referred to as transition

equations

1 1 2 1 2

2 2 1 21

Q D xQ Q Q

Q D xQ Q Q

+

+

= = +

= = +





• Transition Table

– The transition table is

the tabular

representation of the

transition and output

equations.

01000011

01001010

00111101

10011000

1010

Input (x)Input (x)

Output

(z)

Next state

(Q1+ Q2

+)

Present State

(Q1Q2)





• Excitation Tables

01000011

01001010

00111101

10011000

1010

Input (x)Input (x)

Output

(z)

Excitation

(D1 D2)

Present State

(Q1Q2)





• State Tables

01AA11D

01AC10C

00DD01B

10BC00A

1010

Input (x)Input (x)

Output

(z)

Next state

(Q1+ Q2

+)

Present State

(Q1Q2)

11

10

01

00

0000

0010

1111

0110

A,0A,1D

A,0C,1C

D,0D,0B

B,1C,0A

10

Input (x)

Next state,

Output

(Q1+ Q2

+)

Present State

(Q1Q2)





• State Diagrams

A,0A,1D

A,0C,1C

D,0D,0B

B,1C,0A

10

Input (x)

Next state,

Output

(Q1+ Q2

+)

Present State

(Q1Q2)




Example: Moore Machine

1 1 2

2 1 21 1

E x ita tio n ex p ress io n s

J ,

,

y K y x Q

J x Q x yQ K x y y Q

= = +

= + = +

1 1 2

2 1 2

Output expressions

z Q Q

z Q Q

=

= +

Logic diagram for Example





• Transition Equations

– By substituting the excitation expressions for a flip-flop into its

characteristic equation, an algebraic description of the next state of the

flip-flop is obtained. These expressions are referred to as transition

equations

1 1 1 1 1

1 1 21

2 2 2 2 2

1 2 2 21 2 2 1 1

Q J Q K Q

yQ x yQ yQ Q

Q J Q K Q

xQ Q xyQ Q x yQ xQ Q yQ Q

+

+

= +

= + +

= +

= + + + +





• Transition Table

– The transition table is

the tabular

representation of the

transition and output

equations.

010010001111

110000011010

001100110101

011101100000

11100100

Inputs (xy)

Output

(z)

Next state

(Q1+ Q2

+)

Present State

(Q1Q2)





• Excitation Tables

0111,0100,0111,1100,0011

1111,0101,0111,1100,0010

0011,1000,1111,0000,0001

0111,1001,1111,0000,0000

11100100

Inputs (xy)

Output

(z)

Exitation

(J1K1, J2K2)

Present

State

(Q1Q2)





• State Tables

11D

11

ACAD

10C

00

AABC

01B

01

DADB

00A DBCA

Inputs (xy)

Output

(z)

Next state

(Q1+ Q2

+)

Present State

(Q1Q2)

11

10

01

00

00100011

00000110

11001101

11011000

11100100

01





• State Diagrams

D

11

ACAD

C

00

AABC

B

01

DADB

A DBCA

Inputs (xy)

Output

(z)

Next state

(Q1+ Q2

+)

Present

State

(Q1Q2)

11100100

01




Example: Mealy Machine Network Terminal Behavior

1101001010Output seq.

BADBADBACCAState seq.

1011101100Input seq. x




The End






Lecture-23

A.Amalin Prince




Objective :FSM (Finite State Machine)and Controller Design

03-10-07




Controller Design

• Five step controller design process




Finite-State Machines (FSMs)

• Want sequential circuit with particular behavior over time

• Example: Laser timer

– Push button: x=1 for 3 clock cycles

– How? Let’s try three flip-flops

• b=1 gets stored in first D flip-flop

• Then 2nd flip-flop on next cycle,

then 3rd flip-flop on next

• OR the three flip-flop outputs, so x

should be 1 for three cycles

Controller

x

b

clk

laser

patient

D Q D Q D Q

clk

b

x




Need a Better Way to Design Sequential Circuits

• Trial and error is not a good design method– Will we be able to “guess” a circuit that works for other desired

behavior?

• How about counting up from 1 to 9? Pulsing an output for 1 cycleevery 10 cycles? Detecting the sequence 1 3 5 in binary on a 3-bit input?

– And, a circuit built by guessing may have undesired behavior

• Laser timer: What if press button again while x=1? x then stays one another 3 cycles. Is that what we want?

• Combinational circuit design process had two important things1. A formal way to describe desired circuit behavior

• Boolean equation, or truth table

2. A well-defined process to convert that behavior to a circuit

• We need those things for sequence circuit design




Describing Behavior of Sequential Circuit: FSM

• Finite-State Machine (FSM)– A way to describe desired

behavior of sequential circuit

• Akin to Boolean equations for combinational behavior

– List states, and transitions among states

• Example: Make x change toggle (0 to 1, or 1 to 0) every clock cycle

• Two states: “Off” (x=0), and “On” (x=1)

• Transition from Off to On, or On to Off, on rising clock edge

• Arrow with no starting state points to initial state (when circuit first starts)

Outputs: x

OnOff

x=0 x=1

clk

clk

Off On Off On Off On Off On

cycle 1

Off OffOn On

cycle 2 cycle 3 cycle 4clk

state

x

Outputs:




FSM Example: 0,1,1,1,repeat

• Want 0, 1, 1, 1, 0, 1, 1, 1, ...

– Each value for one clock cycle

• Can describe as FSM

– Four states

– Transition on rising clock edge to next state

Off OffOn1On1On2 On2On3 On3Off

clk

x

State

Outputs:

Outputs: x

On1Off On2 On3

clk^

clk^

clk^x=1x=1x=0 x=1clk^




Extend FSM to Three-Cycles High Laser Timer

• Four states

• Wait in “Off” state while b is

0 (b’)

• When b is 1 (and rising

clock edge), transition to

On1

– Sets x=1

– On next two clock edges, transition to On2, then On3, which also set x=1

• So x=1 for three cycles after

button pressed

Off OffOn1Off Off Off On2 On3Off

clk

State

Outputs:

Inputs:

x

b

On2On1 On3

Off

clk^

clk^

x=1x=1x=1

x=0

clk^

b’*clk^

b*clk^

Inputs: b; Outputs: x




FSM Simplification: Rising Clock Edges Implicit

• Showing rising clock on every transition: cluttered

– Make implicit -- assume every edge has rising clock, even if not shown

– What if we wanted a transition without a rising edge

• We don’t consider such

asynchronous FSMs -- less

common, and advanced topic

• Only consider synchronous

FSMs -- rising edge on every

transition

Note: Transition with no associated condition

thus transistions to next state on next clock cycleOn2On1 On3

Off

x=1x=1x=1

x=0

b’

b


On2On1 On3

Off

x=1x=1x=1

x=0

b’

clk^

clk^

^clk

*clk^

*clk^b





FSM Definition

• FSM consists of

– Set of states

• Ex: Off, On1, On2, On3

– Set of inputs, set of outputs

• Ex: Inputs: x, Outputs: b

– Initial state

• Ex: “Off”

– Set of transitions

• Describes next states

• Ex: Has 5 transitions

– Set of actions

• Sets outputs while in states

• Ex: x=0, x=1, x=1, and x=1


On2On1 On3

Off

x=1x=1x=1

x=0

b’

b

We often draw FSM graphically, known as state diagram

Can also use table (state table), or

textual languages




FSM Example: Secure Car Key

• Many new car keys include tiny computer chip

– When car starts, car’s computer (under engine hood) requests identifier from key

– Key transmits identifier

• If not, computer shuts off car

• FSM

– Wait until computer requests ID (a=1)

– Transmit ID (in this case, 1101)

K1 K2 K3 K4

r=1 r=1 r=0 r=1

Wait

r=0

Inputs: a; Outputs: r

a’a




FSM Example: Secure Car Key (cont.)

• Nice feature of FSM

– Can evaluate output behavior for different input sequence

– Timing diagrams show states and output values for different input waveforms

K1 K2 K3 K4

r=1 r=1 r=0 r=1

Wait

r=0


a’a

Wait Wait K1 K2 K3 K4 Wait Wait

clk

Inputs

Outputs

State

a

r

clk

Inputsa

Wait Wait K1 K2 K3 K4 Wait

Output

State

r

Q: Determine states and r value for

given input waveform:

K1




FSM Example: Code Detector

• Unlock door (u=1) only when buttons pressed in sequence:

– start, then red, blue, green, red

• Input from each button: s, r, g, b

– Also, output a indicates that some colored button pressed

• FSM

– Wait for start (s=1) in “Wait”

– Once started (“Start”)

• If see red, go to “Red1”

• Then, if see blue, go to “Blue”

• Then, if see green, go to “Green”

• Then, if see red, go to “Red2”– In that state, open the door

(u=1)

• Wrong button at any step, return to “Wait”, without opening door

Start

Red

Green

Blue

s

rg

b

a

Doorlock

u

Codedetector

Q: Can you trick this FSM to open the door,

without knowing the code?

A: Yes, hold all buttons simultaneously

Wait

Start

Red1 Red2GreenBlue

s’

a’

ar’ ab’ ag’ ar’

a’

ab ag ar

a’ a’u=0

u=0ar

u=0s

u=0 u=0 u=1

Inputs: s,r,g,b,a;Outputs: u




Improve FSM for Code Detector

• New transition conditions detect if wrong button pressed, returns to “Wait”

• FSM provides formal, concrete means to accurately define desired behavior

Note: small problem still

remains; we’ll discuss later

Wait

Start

Red1 Red2GreenBlue

s’

a’

a’

ab ag ar

a’ a’u=0

u=0ar

u=0s

u=0 u=0 u=1

ar’ ab’ ag’ ar’

Inputs: s,r,g,b,a;

Outputs: u




Standard Controller Architecture

• How implement FSM as sequential circuit?

– Use standard architecture

• State register -- to store the present state

• Combinational logic -- to compute outputs, and next state

• For laser timer FSM– 2-bit state register, can represent four

states

– Input b, output x

– Known as controller

On2On1 On3

Off

x=1x=1x=1

x=0

b’

b


Combinationallogic

State register

s1 s0

n1

n0

xb

clk

FSM

outputs

FS

Min

pu

ts

FS

Mo

utp

uts

General version

Combinationallogic

Sm

m

N

OI

clkm-bit

state register

FS

M

outp

uts

FS

M

inputs




Standard Controller Architecture

General version

Combinationallogic

Sm

m

N

OI

clkm-bit

state register

FS

M

outp

uts

FS

M

inputs

• Flip-flop types for state resister

– SR flip-flop: like SR latch, but edge triggered

– JK flip-flop: like SR (SJ, RK)

• But when JK=11, toggles

• 10, 01

– T flip-flop: JK with inputs tied together

• Toggles on every rising clock edge

– Previously utilized to minimize logic outside flip-flop

• Today, minimizing logic to such extent is not as important

• D flip-flops are thus by far the most common

While designing, depends on the type of FF make changes in the State

Table and Flip-Flop Input Equations

Flip-Flops




The End






Lecture-24

A.Amalin Prince





05-10-07




State Reduction (State Minimization)

x y

if x = 1,1,0,0then y = 0,1,1,0,0

• Goal: Reduce number of states in FSM without changing behavior

– Fewer states potentially reduces size of state register

• Consider the two FSMs below with x=1, then 1, then 0, 0

x

state

y

x

state

y

S0 S0S1 S1S1 S1S2 S0S2 S0

S0 S1

y=0 y=1

S2

y=0

S3

y=1

x

x x

x’

x’

xx’ x’

Inputs: x; Outputs: y

S0 S1

y=0 y=1

x’ x

x

x’

For the same sequence of inputs,the output of the two FSMs is the same




State Reduction: Equivalent States

Two states are equivalent if:

1. They assign the same values to

outputs

– e.g. S0 and S2 both assign y to 0,

– S1 and S3 both assign y to 1

2. AND, for all possible sequences of inputs, the FSM outputs will be the

same starting from either state

– e.g. say x=1,1,0,0,…

• starting from S1, y=1,1,0,0,…

• starting from S3, y=1,1,0,0,…

S0 S1

y=0 y=1

S2

y=0

S3

y=1

x

x x

x’

x’

xx’ x’


States S0 and S2 equivalent

States S1 and S3 equivalent

S0,S2

S1,S3

y=0 y=1

x’ x

x

x’




State Reduction: Example with no Equivalencies

• Another example…

• State S0 is not equivalent with any

other state since its output (y=0) differs from other states’ output S1

y=0 y=1

S2

y=1

S3

y=1

x x

x x

x’

x’

x’

x’


S0

• Consider state S1 and S3

S1

y=0 y=1

S2

y=1

S3

y=1

x x

x x

x’

x’

x’

x’

S0

Start from S1, x=0

S1

y=0 y=1

S2

y=1

S3

y=1

x x

x x

x’

x’

x’

x’

S0

Start from S3, x=0

– Outputs are initially the same (y=1)

– From S1, when x=0, go to S2 where y=1

– From S3, when x=0, go to S0 where y=0

– Outputs differ, so S1 and S3 are not equivalent.




• State reduction through visual inspection (what we did in the last few slides) isn’t reliable and cannot be automated –a more methodical approach is needed: implication tables

• Example:

State Reduction with Implication Tables

S0 S1

y=0 y=1

S2

y=0

S3

y=1

x

x x

x’

x’

xx’ x’


Redundant

Diagonal

S0

S0 S1 S2 S3

S1

S2

S3

– To compare every pair of states, construct a table of state pairs (above right)

– Remove redundant state pairs, and state pairs along the diagonal since a state is equivalent to itself (right)

S0

S0 S1 S2 S3

S1

S2

S3

S0 S1 S2

S1

S2

S3




• Mark (with an X) state pairs with different outputs as non-equivalent:


S0 S1 S2

S1

S2

S3

S0 S1

y=0 y=1

S2

y=0

S3

y=1

x

x x

x’

x’

xx’ x’


– (S1,S0): At S1, y=1 and at S0, y=0. So S1

and S0 are non-equivalent. S0 S1

y=0 y=1

S2

y=0

S3

y=1

x

x x

x’

x’

xx’ x’


– (S2, S0): At S2, y=0 and at S0, y=0. So we

don’t mark S2 and S0 now.

S0 S1

y=0 y=1

S2

y=0

S3

y=1

x

x x

x’

x’

xx’ x’


– (S2, S1): Non-equivalent

S0 S1

y=0 y=1

S2

y=0

S3

y=1

x

x x

x’

x’

xx’ x’



S0 S1

y=0 y=1

S2

y=0

S3

y=1

x

x x

x’

x’

xx’ x’


– (S3, S1): Don’t mark

S0 S1

y=0 y=1

S2

y=0

S3

y=1

x

x x

x’

x’

xx’ x’



S0 S1

y=0 y=1

S2

y=0

S3

y=1

x

x x

x’

x’

xx’ x’


• We can see that S2 & S0 might be equivalent and S3 & S1 might be equivalent, but only if their next states are equivalent (remember the example from two slides ago)

S0 S1

y=0 y=1

S2

y=0

S3

y=1

x

x x

x’

x’

xx’ x’






• We need to check each unmarked state pair’s next states

• We can start by listing what each unmarked state pair’s next states are for every combination of inputs

S0 S1

y=0 y=1

S2

y=0

S3

y=1

x

x x

x’

x’

xx’ x’


S0 S1 S2

S1

S2

S3

– (S2, S0)

• From S2, when x=1 go to S3

From S0, when x=1 go to S1 (S3, S1)

So we add (S3, S1) as a next state pair

• From S2, when x=0 go to S2

From S0, when x=0 go to S0

(S2, S0)

So we add (S2, S0) as a next state pair

– (S3, S1)S0 S1 S2

S1

S2

S3

(S3, S1)

(S2, S0)

• By a similar process, we add the next state

pairs (S3, S1) and (S0, S2)

(S3, S1)

(S0, S2)

S0 S1 S2

S1

S2

S3

(S3, S1)

(S2, S0)

(S3, S1)

(S0, S2)




S0 S1 S2

S1

S2

S3

(S3, S1)

(S2, S0)

(S3, S1)

(S0, S2)


• Next we check every unmarked state pair’s next state pairs

• We mark the state pair if one of its next state pairs is marked

S0 S1

y=0 y=1

S2

y=0

S3

y=1

x

x x

x’

x’

xx’ x’


S0 S1 S2

S1

S2

S3

(S3, S1)

(S2, S0)

(S3, S1)

(S0, S2)

– (S2, S0)

• So we do nothing and move on

• Next state pair (S3, S1) is not marked

S0 S1 S2

S1

S2

S3

(S3, S1)

(S2, S0)

(S3, S1)

(S0, S2)


S0 S1 S2

S1

S2

S3

(S3, S1)

(S2, S0)

(S3, S1)

(S0, S2)– (S3, S1)

S0 S1 S2

S1

S2

S3

(S3, S1)

(S2, S0)

(S3, S1)

(S0, S2)


S0 S1 S2

S1

S2

S3

(S3, S1)

(S2, S0)

(S3, S1)

(S0, S2)

• Next state pair (S0, S2) is not marked S0 S1 S2

S1

S2

S3

(S3, S1)

(S2, S0)

(S3, S1)

(S0, S2)

• So we do nothing and move on

S0 S1 S2

S1

S2

S3

(S3, S1)

(S2, S0)

(S3, S1)

(S0, S2)





• We just made a pass through the implication table

– Make additional passes until no change occurs

• Then merge the unmarked state

pairs – they are equivalent

S0 S1

y=0 y=1

S2

y=0

S3

y=1

x

x x

x’

x’

xx’ x’


S0 S1 S2

S1

S2

S3

(S3, S1)

(S2, S0)

(S3, S1)

(S0, S2)

S0,S2 S1,S3

y=0 y=1

x’ x

x

x’




S0 S1

y=0 y=1

S2

y=1

S3

y=1

x

x x

x’

x’

xx’ x’


S0 S1 S2

S1

S2

S3

State Reduction Example

• Given FSM on the right

– Step 1: Mark state pairs having

different outputs as nonequivalent

S0 S1 S2

S1

S2

S3

S0 S1

y=0 y=1

S2

y=1

S3

y=1

x

x x

x’

x’

xx’ x’


S0 S1

y=0 y=1

S2

y=1

S3

y=1

x

x x

x’

x’

xx’ x’


S0 S1 S2

S1

S2

S3

S0 S1

y=0 y=1

S2

y=1

S3

y=1

x

x x

x’

x’

xx’ x’


S0 S1 S2

S1

S2

S3

S0 S1 S2

S1

S2

S3

S0 S1

y=0 y=1

S2

y=1

S3

y=1

x

x x

x’

x’

xx’ x’


S0 S1

y=0 y=1

S2

y=1

S3

y=1

x

x x

x’

x’

xx’ x’


S0 S1 S2

S1

S2

S3

S0 S1

y=0 y=1

S2

y=1

S3

y=1

x

x x

x’

x’

xx’ x’


S0 S1 S2

S1

S2

S3

S0 S1 S2

S1

S2

S3

S0 S1

y=0 y=1

S2

y=1

S3

y=1

x

x x

x’

x’

xx’ x’





S0 S1

y=0 y=1

S2

y=1

S3

y=1

x

x x

x’

x’

xx’ x’


S0 S1 S2

S1

S2

S3



– Step 1: Mark state pairs having different outputs as nonequivalent

– Step 2: For each unmarked state pair, write the next state pairs for the same input values

S0 S1 S2

S1

S2

S3

S0 S1

y=0 y=1

S2

y=1

S3

y=1

x

x x

x’

x’

xx’ x’


x=0

(S2, S2)

x’

x’

x=1(S2, S2)

S0 S1 S2

S1

S2

S3

S0 S1

y=0 y=1

S2

y=1

S3

y=1

x

x x

x’

x’

xx’ x’


x

x

(S3, S1)

x=0

(S2, S2)

S0 S1 S2

S1

S2

S3

S0 S1

y=0 y=1

S2

y=1

S3

y=1

x

x x

x’

x’

xx’ x’


(S3, S1)

x’

x’

(S0, S2)

x=1

S0 S1 S2

S1

S2

S3

S0 S1

y=0 y=1

S2

y=1

S3

y=1

x

x x

x’

x’

xx’ x’


(S0, S2)

x x

(S3, S1)

x=0

S0 S1

y=0 y=1

S2

y=1

S3

y=1

x

x x

x’

x’

xx’ x’


(S2, S2)

S0 S1 S2

S1

S2

S3

(S3, S1)

(S0, S2)(S3, S1)

x’ x’

(S0, S2)

x=1

S0 S1

y=0 y=1

S2

y=1

S3

y=1

x

x x

x’

x’

xx’ x’


(S2, S2)

S0 S1 S2

S1

S2

S3

(S3, S1)

(S0, S2)(S3, S1)

(S0, S2)

x

x

(S3, S3)

S0 S1

y=0 y=1

S2

y=1

S3

y=1

x

x x

x’

x’

xx’ x’


(S2, S2)

S0 S1 S2

S1

S2

S3

(S3, S1)

(S0, S2)(S3, S1)

(S0, S2)(S3, S3)








– Step 3: For each unmarked state pair, mark state pairs having nonequivalent next state pairs as nonequivalent.

• Repeat this step until no change

occurs, or until all states are marked.

– Step 4: Merge remaining state pairsAll state pairs are marked –

there are no equivalentstate pairs to merge

(S2, S2)

S0 S1 S2

S1

S2

S3

(S3, S1)

(S0, S2)(S3, S1)

(S0, S2)(S3, S3)

S0 S1

y=0 y=1

S2

y=1

S3

y=1

x

x x

x’

x’

xx’ x’





A Larger State Reduction Example




• Repeat this step until no change occurs, or until all states are marked.

– Step 4: Merge remaining state pairs

S3 S0

y=0y=0

y=1 y=1

S1S2

S4x

x’ x’

x’x’x’ x

x x


S2

S1

S3

S4

S0 S1 S2 S3

(S4,S2)(S0,S1)

(S3,S2)(S0,S1)

(S3,S4)(S2,S1)

(S4,S3)(S0,S0)

y=0




S2

S1

S3

S4

S0 S1 S2 S3

(S4,S2)(S0,S1)

(S3,S2)(S0,S1)

(S3,S4)(S2,S1)

(S4,S3)(S0,S0)

A Larger State Reduction Example




• Repeat this step until no change occurs, or until all states are marked.

– Step 4: Merge remaining state pairs

S3 S0

y=0y=0

y=1 y=1

S1S2

S4x

x’ x’

x’x’x’ x

x x


y=0

y=0

y=0

y=1

S0 S1,S2

S3,S4

x

x

xx’

x’

x’





Need for Automation

x’x’

x’

x’x’

x’

x’

x'x’x’

x’

x’

x’

x’

x’

x

xx

xx

x

xx

x

xx

x

x

x

xSO

SM

SI

SNSL

SJ

SK

SG

SHSB

z=0

z=0

z=0

z=1

z=1

z=1

z=1

z=1

z=0

z=0

z=0z=0

z=1

z=0

z=1

SA

SDSC

SE

SF

Inputs: x; Outputs: z• Automation needed

– Table for large FSM too big for humans to work with

• n inputs: each state pair can have 2n

next state pairs.

• 4 inputs 24=16 next state pairs

– 100 states would have table with 100*100=100,000 state pairs cells

– State reduction typically automated

• Often using heuristics to reduce compute time




State Assignment (State Encoding)

10000110100S4

01000010011S3

00100011010S2

00010001001S1

00001000000S0

Assignment-3

One-hot

Assignment-2

Gray code

Assignment-1

Binary

State




The End






Lecture-25

A.Amalin Prince





08-10-07




Controller Design

• Five step controller design process




Controller Design: Laser Timer Example

• Step 1: Capture the FSM

– Already done

• Step 2: Create architecture

– 2-bit state register (for 4 states)

– Input b, output x

– Next state signals n1, n0

• Step 3: Encode the states

– Any encoding with each state unique will work

x=1 x=1 x=1

x=0

b

b’

01

00

10 11On2On1

Off

On3


Combinationallogic

State register

s1 s0

n1

n0

xb

clk

FSM

outputs

FS

Min

pu

ts

FS

Mo

utp

uts




Controller Design: Laser Timer Example (cont)

• Step 4: Create state table

x=1 x=1 x=1

x=0

b

b’

01

00

10 11On2On1

Off

On3


Combinationallogic

State register

s1 s0

n1

n0

xb

clk

FSM

inpu

ts FSM

outp

uts





• Step 5: Implement combinational logic Combinational

logic

State register

s1 s0

n1

n0

xb

clk

FSM

inpu

ts FSM

outp

uts

x = s1 + s0 (note from the table that x=1 if s1 = 1 or s0

= 1)

n1 = s1’s0b’ + s1’s0b + s1s0’b’ + s1s0’b

n1 = s1’s0 + s1s0’

n0 = s1’s0’b + s1s0’b’ + s1s0’b

n0 = s1’s0’b + s1s0’





• Step 5: Implement combinational logic (cont)

x = s1 + s0

n1 = s1’s0 + s1s0’

n0 = s1’s0’b + s1s0’

Combinationallogic

State register

s1 s0

n1

n0

xb

clk

FSM

inpu

ts FSM

outp

uts

n1

n0

s0s1

clk

Combinational Logic

State register

b

FSM outputs

FSM inputs

x




Understanding the Controller’s Behavior

s0s1

b x

n1

n0

x=1 x=1 x=1b

01 10 11On2On1

Off

On3

00

0 0

0

00

0

b’

0

0

0

00

x=0

000

clk

clk

Inputs:

Outputs:

1

0

10

b

1

0

10

0

s0s1

b x

n1

n0

x=1 x=1 x=1

b’

01 10 11On2On1

Off

On3

clk

b

x

00

0 0

x=0

000

state=00 state=00

s0s1

b x

n1

n0

x=1 x=1 x=1

x=0

b

b’

01

00

10 11On2On1

Off

On3

1

0

1

1

0

00

110

clk0 1

01

state=01




Controller Design: Laser Timer Example

• Implement the same design using

– JK FF.

– T FF




State Encoding

• Encoding: Assigning a unique bit representation to each state

• Different encodings may optimize size, or tradeoff size and performance

• Consider 3-Cycle Laser Timer…

– Binary encoding: 15 gate inputs

– Try alternative encoding

• x = s1 + s0

• n1 = s0

• n0 = s1’b + s1’s0

• Only 8 gate inputs

11 10

00

01 10 11

b’

b

x=0

x=1 x=1 x=1


On1 On2 On3

Off

1

1

0

0

1

1

0

0




One-Hot Encoding Example: Three-Cycles-High Laser Timer

• Four states – Use four-bit one-hot encoding

– State table leads to equations:

• x = s3 + s2 + s1

• n3 = s2

• n2 = s1

• n1 = s0*b

• n0 = s0*b’ + s3

– Smaller

• 3+0+0+2+(2+2) = 9 gate inputs

• Earlier binary encoding :

• 15 gate inputs

– Faster

• Critical path: n0 = s0*b’ + s3

• Previously: n0 = s1’s0’b + s1s0’

• 2-input AND slightly faster than 3-input AND

0001

0010 0100 1000

b’

b

x=0

x=1 x=1 x=1


On1 On2 On3

Off




State Encoding: One-Hot Encoding

• One-hot encoding

– One bit per state – a bit being ‘1’

corresponds to a particular state

– Alternative to minimum bit-width

encoding in previous example

– For A, B, C, D: A: 0001, B: 0010, C:

0100, D: 1000

• Example: FSM that outputs 0, 1, 1, 1

– Equations if one-hot encoding:

• n3 = s2; n2 = s1; n1 = s0; x = s3 + s2 + s1

– Fewer gates and only one level of

logic – less delay than two levels, so

faster clock frequency

00

01

Inputs: none; Outputs: x

x=0

x=1

A

B

11

10

D

C

x=1

x=1

1000

0100

0001

0010

clk

s1

n1

x

s0n0

State registerclk

n0

s3 s2 s1 s0

n1n2

n3

State register

x

8

6

4

2

2 3 41delay (gate-delays)

one-hot

binary




Output Encoding

• Output encoding: Encoding method where the state

encoding is same as the

output values

– Possible if enough outputs, all states with unique output values

00

01

Inputs: none; Outputs: x,y

xy=00

xy=11

A

B

11

10

D

C

xy=01

xy=10

Use the output values as the state encoding




Output Encoding Example: Sequence Generator

• Generate sequence 0001, 0011, 1110, 1000, repeat

– FSM shown

• Use output values as state encoding

• Create state table

• Derive equations for next state

– n3 = s1 + s2; n2 = s1; n1 = s1’s0; n0 = s1’s0 + s3s2’

Inputs: none; Outputs: w, x, y, z

wxyz=0001

wxyz=0011

A

B

D

C

wxyz=1000

wxyz=1100

clk

n0

s3 s2 s1 s0

n1n2

n3

State register

wxyz




Controller Example: Button Press Synchronizer

• Want simple sequential circuit that converts button press to single cycle duration, regardless of length of time that

button actually pressed

– We assumed such an ideal button press signal in earlier example,like the button in the laser timer controller

cycle1 cycle2 cycle3 cycle4clk

Inputs:

Outputs:

bi

bo

Button press synchronizer

controller

bi bo




Controller Example: Button Press Synchronizer (cont)

A

B

C

s1

0

0

0

0

1

1

1

1

s0

0

0

1

1

0

0

1

1

bi

0

1

0

1

0

1

0

1

Inputs

n1

0

0

0

1

0

1

0

0

n0

0

1

0

0

0

0

0

0

bo

0

0

1

1

0

0

0

0

Outputs

Combinational logic

unused

Step 4: State table

Step 1: FSM

A B C

bo=1bo=0 bo=0bi

bibi’

bi’

bi’bi

FSM inputs: bi; FSM outputs: bo

Step 3: Encode states

00 01 10

bo=1bo=0 bo=0

bi

bibi’

bi’

bi’bi

FSM inputs: bi; FSM outputs: bo

FSM

Step 5: Create

combinational circuit

clkState register

outputs

bo

bi

s1 s0

n1

n0

Combinational logic

n1 = s1’s0bi + s1s0bi

n0 = s1’s0’bibo = s1’s0bi’ + s1’s0bi = s1s0

Step 2: Create architectureCombinational

logic

n0s1 s0

n1

bobi

clkState register

FS

Min

puts

FS

Moutp

uts




Controller Example: Sequence Generator• Want generate sequence 0001, 0011, 1100, 1000, (repeat)

– Each value for one clock cycle

– Common, e.g., to create pattern in 4 lights, or control magnets of a “stepper motor”

00

01 10

11A

B

D

wxyz=0001 wxyz=1000

wxyz=0011 wxyz=1100

C

Inputs: none; Outputs: w,x,y,z

Step 3: Encode states

Step 4: Create state table clkState register

w

x

y

z

FSM outputs

n0s0s1

n1

Step 5: Create combinational circuit

w = s1x = s1s0’y = s1’s0z = s1’n1 = s1 xor s0n0 = s0’

Step 1: Create FSM

A

B

D

wxyz=0001 wxyz=1000

wxyz=0011 wxyz=1100

C

Inputs: none; Outputs: w,x,y,z

Step 2: Create architecture

Combinationallogic

n0s1 s0

n1

clkState register

wxyz




Controller Example: Secure Car Key• (from earlier example)

K1 K2 K3 K4

r=1 r=1 r=0 r=1

Wait

r=0


a’a

Ste

p 1

FSM

Combinational

logic

s2 s1 s0

n2

ra

n1n0

clk State register

FSM

inputs

outputs

Ste

p 2

a’a

r=0

r=1 r=1 r=0 r=1

000

001 010 011 100

Inputs:a;Outputs:r

Ste

p 3

Step 4We’ll omit Step 5




Example: Seq. Circuit to FSM (Reverse Engineering)

clkState register

y

z

FSM outputs

FSM inputs

n0

n1

s0s1

x

What does this circuit do?

Work backwards

y=s1’

z = s1s0’

n1=(s1 xor s0)x

n0=(s1’*s0’)x

Pick any state names you want

A

D

B

C

states

Outputs:y, z

A

D

B

yz=01yz=00

yz=10yz=10

C

states

with

outputs

A

D

B

yz=00

yz=01

yz=10

yz=10

C

Inputs: x; Outputs:y, z

x’

x’

x’

x

x

x

states with

outputs and

transitions




Common Pitfalls Regarding Transition Properties

• Only one condition should be true

– For all transitions leaving a state

– Else, which one?

• One condition must be true

– For all transitions leaving a state

– Else, where go?

a

b

ab=11 –next state?

a

a’b

a

what ifab=00?

a

a’b

a’b’

a’b




a * a’b

= (a * a’) * b

= 0 * b

= 0

OK!

Answer:

Verifying Correct Transition Properties

• Can verify using Boolean algebra

– Only one condition true: AND of each condition pair (for transitions leaving a state) should equal 0 proves pair can never simultaneously be true

– One condition true: OR of all conditions of transitions leaving a state) should equal 1 proves at least one condition must be true

– Examplea

a’b

a + a’b

= a*(1+b) + a’b

= a + ab + a’b

= a + (a+a’)b

= a + b

Fails! Might not

be 1 (i.e., a=0,

b=0)

Q: For shown transitions, prove whether:* Only one condition true (AND of each pair is always 0)* One condition true (OR of all transitions is always 1)




Evidence that Pitfall is Common

• Recall code detector FSM– We “fixed” a problem with the

transition conditions

– Do the transitions obey the two required transition properties?

• Consider transitions of state Start, and the “only one true”property

Wait

Start

Red1 Red2GreenBlue

s’

a’

a’

ab ag ar

a’ a’u=0

u=0ar

u=0 s

u=0 u=0 u=1

ar * a’ a’ * a(r’+b+g) ar * a(r’+b+g)

= (a*a’)r = 0*r = (a’*a)*(r’+b+g) = 0*(r’+b+g)

= (a*a)*r*(r’+b+g) = a*r*(r’+b+g)

= 0 = 0 = arr’+arb+arg

= 0 + arb+arg

= arb + arg

= ar(b+g)

Fails! Means that two of Start’s

transitions could be true

Intuitively: press red and blue buttons at same time: conditions ar, and a(r’+b+g) will both be true. Which one should be taken?

Q: How to solve?

A: ar should be arb’g’

(likewise for ab, ag, ar)

Note: As evidence the pitfall is common,

we admit the mistake was not intentional.

A reviewer of the book caught it.




Simplifying Notations

• FSMs

– Assume unassigned output implicitly assigned 0

• Sequential circuits

– Assume unconnected clock inputs connected to same external clock

a=0b=1c=0

a=0b=0c=1

b=1 c=1

clk a

a




Non-Ideal Flip-Flop Behavior

• Can’t change flip-flop input too close to clock edge

– Setup time: time that D must be stable before edge

• Else, stable value not present at internal latch

– Hold time: time that D must be held stable after

edge

• Else, new value doesn’t have time to loop around

and stabilize in internal latch

clk

D

clk

D

setup time

hold time

R

SD

C

u

D latch

Q

Q’

1

2

3 4

5 6

7

C

D

S

u

R

Q’

Q

Setup time violation

Leads to oscillation!




Metastability

• Violating setup/hold time can lead to bad situation known as metastable state

– Metastable state: Any flip-flop state other than stable 1 or 0

• Eventually settles to one or other, but we don’t know which

– For internal circuits, we can make sure observe setup time

– But what if input comes from external (asynchronous) source, e.g., button press?

• Partial solution

– Insert synchronizer flip-flop for asynchronous input

• Special flip-flop with very small setup/hold time

– Doesn’t completely prevent metastability

clk

D

Q

setup timeviolation

metastablestate

ai

ai

synchronizer




Metastability

• One flip-flop doesn’t completely solve problem

• How about adding more synchronizer flip-flops?

– Helps, but just decreases probability of metastability

• So how solve completely?

– Can’t! May be unsettling to new designers. But we just can’t guarantee a

design that won’t ever be metastable. We can just minimize the mean time

between failure (MTBF) -- a number often given along with a circuit

ai

synchronizers

lowverylow

veryverylow

incrediblylow

Probability of flip-flop being metastable is…




Flip-Flop Set and Reset Inputs

• Some flip-flops have additional inputs

– Synchronous reset: clears Q to 0 on next clock edge

– Synchronous set: sets Q to 1 on next clock edge

– Asynchronous reset: clear Q to 0 immediately (not dependent on clock edge)

• Example timing diagram shown

– Asynchronous set: set Q to 1 immediately

D Q’

QR

Q’

AR

D

Q

Q’

AS

ARD

Q

cycle 1 cycle 2 cycle 3 cycle 4

clk

D

AR

Q




Initial State of a Controller

• All our FSMs had initial state

– But our sequential circuit designs did not

– Can accomplish using flip-flops with reset/set inputs

• Shown circuit initializes flip-flops to

01

– Designer must ensure reset input is 1 during power up of circuit

• By electronic circuit design

Inputs: x; Outputs: b

On2On1 On3

Off

x=1x=1x=1

x=0

b’

b

D Q’ Q’

QR S

D

Q

State registerclk

reset

s1 s0

n0

n1

b x

Combinational

logic




Glitching

• Glitch: Temporary values on outputs that appear soon after

input changes, before stable

new output values

• Designer must determine

whether glitching outputs may pose a problem

– If so, may consider adding flip-flops to outputs

• Delays output by one clock

cycle, but may be OK

n1

n0

s0s1

clk

Combinational Logic

State register

b

FSM outputs

FSM inputs

x




The End






Lecture-26

A.Amalin Prince




Objective : Modular approach for CPU designRegister-Transfer Level (RTL) Design

10-10-07




Introduction

• U Know: Controllers

– Control input/output: single bit (or just a few) representing event or state

– Finite-state machine describes behavior; implemented as state register and combinational logic

• U know: Datapath components

– Data input/output: Multiple bits collectively representing single entity

– Datapath components included registers, adders, ALU, comparators, register files, etc.

• Discussion: custom processors

– Processor: Controller and datapathcomponents working together to implement an algorithm

si

z

e

ansis

Combinational

logic

n0s1 s0

n1

bobi

clkState register

FS

M

inputs

FS

M

outp

uts

ALU

Comparator

Register file

Register

Combinational

logic

n0s1 s0

n1

bobi

State register

Register file

ALU

Datapath

Controller




RTL Design: Capture Behavior, Convert to Circuit

• Recall

– Chapter 4 T1: Combinational Logic Design

• First step: Capture behavior (using equation

or truth table)

• Remaining steps: Convert to circuit

– Chapter 5 T1: Sequential Logic Design

• First step: Capture behavior (using FSM)

• Remaining steps: Convert to circuit

• RTL Design (the method for creating

custom processors)

– First step: Capture behavior (using high-level state machine, to be introduced)

– Remaining steps: Convert to circuit

Capture behavior

Convert to circuit




RTL Design Method

5th step may be required: Determine the clock frequency




RTL Design Method: “Preview” Example

• Soda dispenser

– c: bit input, 1 when coin deposited

– a: 8-bit input having value of deposited coin

– s: 8-bit input having cost of a soda

– d: bit output, processor sets to 1 when total value of deposited coins equals or exceeds cost of a soda

as

c

dSoda

dispenserprocessor

25

1 025

1

1

500

0

0

0

tot:

25

tot:

50

How can we precisely describe this

processor’s behavior?

as

c

dSoda

dispenserprocessor




Preview Example: Step 1 --Capture High-Level State Machine

• Declare local register tot

• Init state: Set d=0, tot=0

• Wait state: wait for coin

– If see coin, go to Add state

• Add state: Update total value: tot = tot + a

– Remember, a is present coin’s

value

– Go back to Wait state

• In Wait state, if tot >= s, go to Disp(ense) state

• Disp state: Set d=1 (dispense soda)

– Return to Init state

Inputs: c (bit), a (8 bits), s (8 bits)Outputs: d (bit)Local registers: tot (8 bits)

Wait

Add

Disp

Init

d=0tot=0

c’*(tot<s)

d=1

c

tot=tot+a

8 8as

cd

Sodadispenserprocessor

c’*(tot<s)’




Preview Example: Step 2 -- Create Datapath

• Need tot register

• Need 8-bit comparator

to compare s and tot

• Need 8-bit adder to

perform tot = tot + a

• Wire the components

as needed for above

• Create control input/outputs, give

them names

ld

clrtot

8-bit

<

8-bit

adder

8

8

88

s a

Datapath

tot_ld

tot_clr

tot_lt_s

Inputs:c (bit), a(8 bits), s (8 bits)

Outputs: d (bit)

Local registers: tot (8 bits)

Wait

Add

Disp

Init

d=0

tot=0c‘

(tot<s)‘

c‘ ∗∗∗∗(tot<s)

d=1

c

tot=tot+a




Preview Example: Step 3 –Connect Datapath to a Controller

• Controller’s inputs

– External input c(coin detected)

– Input from datapathcomparator’s output, which we named tot_lt_s

• Controller’s outputs

– External output d(dispense soda)

– Outputs to datapathto load and clear the tot register

tot_lt_s

tot_clr

tot_ld

Controller Datapath

s

c

d

a

8 8

ld

clrtot

8-bit

<

8-bit

adder

8

8

88

s a

Datapath

tot_ld

tot_clr

tot_lt_s




Preview Example: Step 4 – Derive the Controller’s

FSM• Same states

and arcs as

high-level

state machine

• But set/read

datapathcontrol

signals for all datapath

operations

and conditions

tot_lt_s

tot_clr

tot_ld

Co

ntr

oll

er

Da

tap

ath

s

c

d

a

8 8

ld

clrtpt

8-bit<

8-bitadder

8

8

88

s a

Datapath

tot_ld

tot_clr

tot_lt_s

Inputs::c, tot_lt_s(bit)

Outputs:d, tot_ld, tot_clr(bit)

Wait

Disp

Init

d=0tot_clr=1

c’* tot_lt_s’

c’*tot_lt_s

d=1

c

tot_ld=1

c

d

tot_ld

tot_clr

tot_lt_s

Controller

Add




Preview Example: Completing the Design

• Implement the FSM as a state register and

logic

– As in Previous lecture

– Table shown on right

d

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

1

1

1

1

0

0

0

0

0

0

n0

1

1

1

1

1

1

0

0

1

0

n1

0

0

0

0

1

0

1

1

0

0

0

1

0

1

0

1

0

1

0

0

c

0

0

1

1

0

0

1

1

0

0

s1

0

0

0

0

0

0

0

0

1

1

s0

0

0

0

0

1

1

1

1

0

1

tot_

lt_s

tot_

ld

tot_

clr

Init

Wai

tA

dd

Dis

p

Inputs::c, tot_lt_s(bit)

Outputs:d, tot_ld, tot_clr (bit)

Wait

Disp

Init

d=0tot_clr=1

c’* tot_lt_s’

c’*tot_lt_s

d=1

c

tot_ld=1

c

d

tot_ld

tot_clr

tot_lt_s

Controller

Add




Step 1: Create a High-Level State Machine

• Let’s consider each step of the RTL design process in more detail

• Step 1– Soda dispenser example

– Not an FSM because:

• Multi-bit (data) inputs a and s

• Local register tot

• Data operations tot=0, tot<s, tot=tot+a.

– Useful high-level state machine:

• Data types beyond just bits

• Local registers

• Arithmetic equations/expressions

Inputs: c (bit), a (8 bits), s (8 bits)

Outputs: d (bit)

Local registers: tot (8 bits)

Wait

Disp

Init

d=0tot=0

c’ (tot<s)

d=1

c

tot=tot+a

c’(tot<s)’




Step 1: Create a High-Level State Machine

• Creating a high-level state machine is not the only possible extension to an FSM.

– Dozens of varieties of extended FSM exist. One example is ASM Charts U know? we will discuss later…

• That particular high-level state machine is sometime called

as FSM with Data or FSMD

• Conventions same as FSM

– Each transition is implicitly ANDed with raising clock edge

– Any bit output not explicitly assigned a value in a state is implicitly assigned a 0.

• This convention does not apply for multibit outputs




The End






Lecture-27

A.Amalin Prince





12-10-07




RTL Design Method

5th step may be required: Determine the clock frequency




Step 1 Example: Laser-Based Distance Measurer

• Example of how to create a high-level state machine to describe desired processor behavior

• Laser-based distance measurement – pulse laser, measure time T to sense reflection– Laser light travels at speed of light, 3*10

8m/sec

– Distance is thus D = T sec * 3*108

m/sec / 2

Object ofinterest

D

2D = T sec * 3*108 m/sec

sensor

laser

T (in seconds)





• Inputs/outputs

– B: bit input, from button to begin measurement

– L: bit output, activates laser

– S: bit input, senses laser reflection

– D: 16-bit output, displays computed distance

sensor

laser

T (in seconds)

Laser-based

distance

measurer16

from button

to displayS

L

D

Bto laser

from sensor





• Step 1: Create high-level state machine

• Begin by declaring inputs and outputs

• Create initial state, name it S0

– Initialize laser to off (L=0)

– Initialize displayed distance to 0 (D=0)

Laser-

baseddistancemeasurer16

from button

to displayS

L

D

Bto laser

from sensor

Inputs: B, S(1 bit each)Outputs: L (bit), D (16 bits)

S0 ?

L = 0 (laser off)D = 0 (distance = 0)





• Add another state, call S1, that waits for a button press

– B’ – stay in S1, keep waiting

– B – go to a new state S2

Inputs: B, S (1 bit each)Outputs: L (bit), D (16 bits)

S0

L = 0D = 0

S1 ?

B’ (button not pressed)

B(buttonpressed)

S0

Q: What should S2 do? A: Turn on the laser

Laser-


from button

to displayS

L

D

Bto laser

from sensor





• Add a state S2 that turns on the laser (L=1)

• Then turn off laser (L=0) in a state S3

S0 S1 S2

L = 0D = 0

L = 1(laser on)

S3

L = 0(laser off)

B’

B

Q: What do next? A: Start timer, wait to sense reflection

Laser-


from button

to displayS

L

D

Bto laser

from sensor

Inputs: B, S (1 bit each)Outputs: L (bit), D (16 bits)





• Stay in S3 until sense reflection (S)

• To measure time, count cycles for which we are in S3

– To count, declare local register Dctr

– Increment Dctr each cycle in S3

– Initialize Dctr to 0 in S1. S2 would have been O.K. too

Laser-baseddistancemeasurer16

from button

to displayS

L

D

Bto laser

from sensor

Local Registers: Dctr (16 bits)

S0 S1 S2 S3

L = 0D = 0

L = 1 L = 0Dctr = Dctr + 1(count cycles)

Dctr = 0(reset cycle

count)

B’

B

S’ (no reflection)

S (reflection)?

Inputs: B, S (1 bit each) Outputs: L (bit), D (16 bits)





• Once reflection detected (S), go to new state S4

– Calculate distance

– Assuming clock frequency is 3x108, Dctr holds number of meters, so

D=Dctr/2

• After S4, go back to S1 to wait for button again

Laser-baseddistancemeasurer16

from button

to displayS

L

D

Bto laser

from sensor

S0 S1 S2 S3

L = 0D = 0

L = 1 L=0Dctr = Dctr + 1

Dctr = 0

B’ S’

B SD = Dctr / 2

(calculate D)

S4

Local Registers: Dctr (16 bits)Inputs: B, S (1 bit each) Outputs: L (bit), D (16 bits)




Step 2: Create a Datapath

• Datapath must– Implement data storage

– Implement data computations

• Look at high-level state machine, do three substeps– (a) Make data inputs/outputs be datapath

inputs/outputs

– (b) Instantiate declared registers into the datapath (also instantiate a register for each data output)

– (c) Examine every state and transition, and instantiate datapath components and connections to implement any data computations

Instantiate: to

introduce a new

component into a

design.





(a) Make data inputs/outputs be datapathinputs/outputs

(b) Instantiate declared registers into the datapath (also instantiate a register for each data output)

(c) Examine every state and transition, and instantiate datapathcomponents and connections to implement any data computations

DatapathDreg_clr

Dctr_clr

Dctr_cnt

Dreg_ld


S0 S1 S2 S3

L = 0D = 0


Dctr = 0

B‘ S‘

B S

D = Dctr / 2(calculate D)

S4

load

Q

IDreg: 16-bit

register

Q

Dctr: 16-bitup-counter

16

D

clearclear

count






(c) (continued)

Examine every

state and

transition, and

instantiate

datapath

components and

connections to

implement any

data computations

clear

count

clear

load

Q Q

IDctr: 16-bitup-counter

Dreg: 16-bitregister

16

D

Datapath

Dreg_clr

Dctr_clr

Dctr_cnt

Dreg_ld16

16

>>1


S0 S1 S2 S3

L = 0D = 0


Dctr = 0

B‘ S‘

B S


S4





Step 2 Example Showing Mux Use

• Introduce mux when one component input can come from

more than one source

T0

T1

R = E + F

R = R + G

E,F, G, R (16 bits)

Localregisters:

(a)

E F G

A B+

R

add_A_s0

add_B_s02⋅ 1 2⋅ 1

(d)

××

E F G

A B+

R

(b)

E F G

A B+

R

(c)




Step 3: Connecting the Datapath to a Controller

• Laser-based distance measurer example

• Easy – just connect all control signals between controller and datapath300 MHz Clock

D

BL

S

16

to display

from buttonController

to laser

from sensor

Datapath

Dreg_clr

Dreg_ld

Dctr_clr

Dctr_cnt

clearcount

clear

load

Q Q



16

D

Datapath

Dreg_clr

Dctr_clrDctr_cnt

Dreg_ld 16

16

>>1




Step 4: Deriving the Controller’s FSM

• FSM has same structure as high-level state machine

– Inputs/outputs all bits now

– Replace data operations by bit operations using datapath

300 MHz Clock

D

BL

S

16

to display

from buttonController

to laser

from sensor

Datapath

Dreg_clr

Dreg_ld

Dctr_clr

Dctr_cnt

Inputs: B, SOutputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt

S0 S1 S2 S3

L = 0 L = 1 L = 0L = 0

B’ S’

B SS4

L = 0

Inputs: B, S (1 bit each) Outputs: L (bit), D (16 bits)Local Registers: Dctr (16 bits)

S0 S1 S2 S3

L = 0D = 0


Dctr = 0

B’ S’

B S


S4

Dreg_clr = 1

Dreg_ld = 0

Dctr_clr = 0

Dctr_cnt = 0

(laser off)

(clear D reg)

Dreg_clr = 0

Dreg_ld = 0

Dctr_clr = 1

Dctr_cnt = 0

(clear count)

Dreg_clr = 0

Dreg_ld = 0

Dctr_clr = 0

Dctr_cnt = 0

(laser on)

Dreg_clr = 0

Dreg_ld = 0

Dctr_clr = 0

Dctr_cnt = 1

(laser off)

(count up)

Dreg_clr = 0

Dreg_ld = 1

Dctr_clr = 0

Dctr_cnt = 0

(load D reg with Dctr/2)

(stop counting)




Step 4: Deriving the Controller’s FSM

• Using shorthand of outputs not assigned implicitly assigned 0

S0 S1 S2 S3

L = 0 L = 1 L = 0L = 0

B’ S’

B SS4

L = 0Dreg_clr = 1

Dreg_ld = 0

Dctr_clr = 0

Dctr_cnt = 0

(laser off)

(clear D reg)

Dreg_clr = 0

Dreg_ld = 0

Dctr_clr = 1

Dctr_cnt = 0

(clear count)

Dreg_clr = 0

Dreg_ld = 0

Dctr_clr = 0

Dctr_cnt = 0

(laser on)

Dreg_clr = 0

Dreg_ld = 0

Dctr_clr = 0

Dctr_cnt = 1

(laser off)

(count up)

Dreg_clr = 0

Dreg_ld = 1

Dctr_clr = 0

Dctr_cnt = 0


(stop counting)

S0 S1 S2 S3

L = 0 L = 1 L = 0

B’ S’

B S

(laser on)

S4

Inputs: B, S Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt

Dreg_clr = 1

(laser off)

(clear D reg)

Dctr_clr = 1

(clear count) Dctr_cnt = 1

(laser off)

(count up)

Dreg_ld = 1

Dctr_cnt = 0


(stop counting)




Step 4

• Implement FSM as state register and logic (Studied) to complete the design

300 MHz Clock

D

BL

S

16to display

from button

Contr

olle

r to laser

from sensor

Data

path

Dreg_clr

S0 S1 S2 S3

L = 0 L = 1 L = 0

B’ S’

B S

(laser on)

S4

Inputs: B, S Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt

Dreg_clr = 1

(laser off)

(clear D reg)

Dctr_clr = 1

(clear count) Dctr_cnt = 1

(laser off)

(count up)

Dreg_ld = 1

Dctr_cnt = 0


(stop counting)

Dreg_ld

Dctr_clr

Dctr_cnt

clearcount

clear

load

Q Q



16

D

Datapath

Dreg_clr

Dctr_clrDctr_cnt

Dreg_ld 16

16

>>1




RTL Design Examples and Issues

• We’ll use several more examples to illustrate RTL design

• Example: Bus interface– Master processor can read

register from any peripheral

• Each register has unique 4-bit address

• Assume 1 register/periph.

– Sets rd=1, A=address

– Appropriate peripheral places register data on 32-bit D lines

• Periph’s address provided on Faddr inputs (maybe from DIP switches, or another register)

32

4 A

rd

D

Per0 Per1 Per15

Masterprocessor

Faddr

4

ADrd

Bus interface

Main part

Peripheral

Q32

to/from processor bus

32 4




RTL Example: Bus Interface

• Step 1: Create high-level state machine– State WaitMyAddress

• Output “nothing” (“Z”) on D, store peripheral’s register value Q into local register Q1

• Wait until this peripheral’s address is seen (A=Faddr) and rd=1

– State SendData

• Output Q1 onto D, wait for rd=0 (meaning main processor is done reading the D lines)

WaitMyAddress

Inputs: rd (bit); Q (32 bits); A, Faddr (4 bits)Outputs: D (32 bits)Local register: Q1 (32 bits)

rd’ rd

SendData

D = “Z”Q1 = Q

(A = Faddr)and rd

((A = Faddr)and rd)’

D = Q1





W W

ZD Z ZQ1 Q1

W W WSD SD SD

clk

Inputs

State

Outputs

rd

WaitMyAddress


rd’ rd

SendData

D = “Z”Q1 = Q

(A = Faddr)and rd

((A = Faddr)and rd’)

D = Q1





WaitMyAddress


rd’ rd

SendData

D = “Z”Q1 = Q

(A = Faddr)and rd


D = Q1

• Step 2: Create a datapath(a) Datapath inputs/outputs

(b) Instantiate declared registers

(c) Instantiate datapath components and

connections

Datapath

Bus interface

Q1_ldld

Q1

F Qaddr

4 4 32

A

D_en

A_eq_Faddr

= (4-bit)32

32

D





• Step 3: Connect datapath to controller

• Step 4: Derive controller’s FSM

WaitMyAddress


rd’ rd

SendData

D = “Z”Q1 = Q

(A = Faddr)and rd


D = Q1

rd

Inputs: rd, A_eq_Faddr (bit)

Outputs: Q1_ld, D_en (bit)

WaitMyAddress

rd‘ rd

SendData

D_en = 0

Q1_ld = 1

D_en = 1

Q1_ld = 0

A_eq_Faddr

and rd

(A_eq_Faddr

and rd)‘

DatapathBus interface

Q1_ldld

Q1

Faddr Q

4 4 32

A

D_en

A_eq_Faddr

= (4-bit)32

32

D




RTL Example: Video Compression – Sum of Absolute Differences (SAD)

• Video is a series of frames (e.g., 30 per second)

• Most frames similar to previous frame

– Compression idea: just send difference from previous frame

Digitizedframe 2

1 Mbyte

Frame 2

Digitizedframe 1

Frame 1

1 Mbyte(a)

Digitizedframe 1

Frame 1

1 Mbyte(b)

Only difference: ball moving

Difference of2 from 1

0.01 Mbyte

Frame 2

Just send

difference





• Need to quickly determine whether two frames are similar enough to just send difference for second frame

– Compare corresponding 16x16 “blocks”

• Treat 16x16 block as 256-byte array

– Compute the absolute value of the difference of each array item

– Sum those differences – if above a threshold, send complete frame for second frame; if below, can use difference method (using another technique, not described)

Frame 2Frame 1

compareEach is a pixel, assume

represented as 1 byte

(actually, a color picture

might have 3 bytes per

pixel, for intensity of

red, green, and blue

components of pixel)





• Want fast sum-of-absolute-differences (SAD) component

– When go=1, sums the differences of element pairs in arrays A and B, outputs that sum

!(i<256)

B

A

go

SAD

sad

256-byte array

256-byte arrayinteger





• S0: wait for go

• S1: initialize sum and index

• S2: check if done (i>=256)

• S3: add difference to sum,

increment index

• S4: done, write to output

sad_reg

!(i<256)

B

A

go

SAD

sad

Inputs: A, B (256 byte memory); go (bit)Outputs: sad (32 bits)Local registers: sum, sad_reg (32 bits); i (9 bits)

!goS0

go

S1sum = 0i = 0

S3sum=sum+abs(A[i]-B[i])i=i+1

S4 sad_reg = sum

S2

i<256

(i<256)’





• Step 2: Create datapath

!(i<256)

!(i<256) (i_lt_256)

i_lt_256

i_inc

i_clr

sum_ld

sum_clr

sad_reg_ld

Datapath

sum

sad_reg

sad

AB_addr A_data B_data

<2569

32

8

8

8 8

3232

32

i –

+

abs

Inputs: A, B (256 byte memory); go (bit)Outputs: sad (32 bits)Local registers: sum, sad_reg (32 bits); i (9 bits)

!goS0

go

S1sum = 0i = 0


S4 sad_reg=sum

S2

i<256

(i<256)’





• Step 3: Connect to controller

• Step 4: Replace high-level state machine by FSM

!(i<256)

!(i<256) (i_lt_256)

S0

S1

S2

S3

S4

go’

go

go AB_rd

sum=0i=0

i<256

!(i<256) (i_lt_256)

?

sum=sum+abs(A[i]-B[i])

i=i+1

sad_reg=sum

Controller

i_lt_256

i_inc

i_clr

sum_ld

sum_clr

sad_reg_ld

sum

sad_reg

sad


<2569

32

8

8

8 8

3232

32

i –

+

abs

sum_ld=1; AB_rd=1

sad_reg_ld=1

i_inc=1

i_lt_256

i_clr=1sum_clr=1




RTL Example: Video Compression – Sum of Absolute Differences

• Comparing software and custom circuit SAD – Circuit: Two states (S2 & S3) for

each i, 256 i’s 512 clock cycles

– Software: Loop (for i = 1 to 256), but for each i, must move memory to local registers, subtract, compute absolute value, add to sum, increment i – say about 6 cycles per array item 256*6 = 1536 cycles

– Circuit is about 3 times (300%) faster

– Later, we’ll see how to build SAD circuit that is even faster

!(i<256)

!(i<256) (i_lt_256)


S2

i<256

(i<256)’




The End






Lecture-28

A.Amalin Prince





15-10-07




RTL Design Pitfalls and Good Practice

• Common pitfall: Assuming register is update in the state it’s written– Final value of Q?

– Final state?

– Answers may surprise you

• Value of Q unknown

• Final state is C, not D

– Why?

• State A: R=99 and Q=R

happen simultaneously

• State B: R not updated with R+1 until next clock cycle, simultaneously with state register being updated

A B

C

D

R>=100

R<100

R=R+1R=99Q=R

?

?

99

A

99

?

100

B

100

?

C

R<100

clk

R

Q

(a)

(b)

Local registers: R, Q (8 bits)





• Solutions

– Read register in following state (Q=R)

– Insert extra state so that conditions use updated value

– Other solutions are possible, depends on the example

BA B2

C

D

R>=100

R<100

R=R+1Q=R

R=99Q=R

?

?

99

A

99

?

100

B

100 100

99 99

B2 D

R<100 R>=100

clk

R

Q

(a)

(b)

Local registers: R, Q (8 bits)





• Common pitfall: Reading outputs

– Outputs can only be written

– Solution: Introduce additional register, which can be written and read

TS

P=P+BP=A

(a)

Inputs: A, B (8 bits)

Outputs: P (8 bits)

Inputs: A, B (8 bits)

Outputs: P (8 bits)

Local register: R (8 bits)

TS

P=R+BR=AP=A

(b)





• Good practice: Register all data outputs– In fig (a), output P would

show spurious values as addition computes

• Furthermore, longest register-to-register path, which determines clock period, is not known until that output is connected to another component

– In fig (b), spurious outputs reduced, and longest register-to-register path is clear

+

R

B

P

(a)

+

R

Preg

B

P(b)




Control vs. Data Dominated RTL Design

• Designs often categorized as control-dominated or data-dominated

– Control-dominated design – Controller contains most of the complexity

– Data-dominated design – Datapath contains most of the complexity

– General, descriptive terms – no hard rule that separates the two types of designs

– Laser-based distance measurer – control dominated

– Bus interface, SAD circuit – mix of control and data

– Now let’s do a data dominated design




Data Dominated RTL Design Example: FIR Filter

• Filter concept– Suppose X is data from a

temperature sensor, and particular input sequence is 180, 180, 181, 240, 180, 181 (one per clock cycle)

– That 240 is probably wrong!

• Could be electrical noise

– Filter should remove such noise in its output Y

– Simple filter: Output average of last N values

• Small N: less filtering

• Large N: more filtering, but less sharp output

1212

Y

clk

X

digital filter





• FIR filter– “Finite Impulse Response”

– Simply a configurable weighted sum of past input values

– y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)

• Above known as “3 tap”

• Tens of taps more common

• Very general filter – User sets the constants (c0, c1, c2) to define specific filter

– RTL design

• Step 1: Create high-level state machine

– But there really is none! Data dominated indeed.

• Go straight to step 2

1212

Y

clk

X

digital filter

y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)





• Step 2: Create datapath

– Begin by creating chain of xt registers to hold past values of X

1212

Y

clk

X

digital filter

xt0 xt1 xt2

12 12 12 12

x(t-2)x(t-1)x(t)

3-tap FIR filter

X Y

clk

y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)

180 180181 180181240

Suppose sequence is: 180, 181, 240





• Step 2: Create datapath(cont.)

– Instantiate registers for c0, c1, c2

– Instantiate multipliers to compute c*x values

y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)

xt0 xt1 xt2

x(t-2)x(t-1)x(t)

3-tap FIR filter

X

Y

clk

c1c0 c2

∗∗ ∗

1212

Y

clk

X

digital filter





• Step 2: Create datapath(cont.)

– Instantiate adders

y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)

xt0 xt1 xt2

x(t-2)x(t-1)x(t)

3-tap FIR filter

X

Y

clk

c0 c1 c2

∗ ∗ ∗

+ +

1212

Y

clk

X

digital filter





• Step 2: Create datapath (cont.)

– Add circuitry to allow loading of particular c register

y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)

1212

Y

clk

X

digital filter

xt0 xt1 xt2

x(t-2)x(t-1)x(t)

3-tap FIR filter

X

Y

clk

c0 c1 c2

* *

+

*

+

3210

2x4

yreg

e

Ca1

CL

C

Ca0





• Step 3 & 4: Connect to controller, Create FSM

– No controller needed

– Extreme data-dominated example

– (Example of an extreme control-dominated design – an FSM, with no datapath)

• Comparing the FIR circuit to a software implementation

– Circuit

• Assume adder has 2-gate delay, multiplier has 20-gate delay

• Longest past goes through one multiplier and two adders– 20 + 2 + 2 = 24-gate delay

• 100-tap filter, following design on previous slide, would have about a 34-gate delay: 1 multiplier and 7 adders on longest path

– Software

• 100-tap filter: 100 multiplications, 100 additions. Say 2 instructions per multiplication, 2 per addition. Say 10-gate delay per instruction.

• (100*2 + 100*2)*10 = 4000 gate delays

– Circuit is more than 100 times faster (10,000% faster). Wow.

y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)




Determining Clock Frequency

• Designers of digital circuits often want fastest performance– Means want high clock

frequency

• Frequency limited by longest register-to-register delay– Known as critical path

– If clock is any faster, incorrect data may be stored into register

– Longest path on right is 2 ns

• Ignoring wire delays, and register setup and hold times, for simplicity

a

+

b

c

2 nsdelay

clk




Critical Path

• Example shows four paths

– a to c through +: 2 ns

– a to d through + and *: 7 ns

– b to d through + and *: 7 ns

– b to d through *: 5 ns

• Longest path is thus 7 ns

• Fastest frequency

– 1 / 7 ns = 142 MHz

+ *

c d

7 ns7 ns

5 nsdelay

2 nsdelay

Max(2,7,7,5)

= 7 ns

a b

5 n

s

7 n

s

7 n

s

2 n

s




Critical Path Considering Wire Delays

• Real wires have delay too

– Must include in critical path

• Example shows two paths

– Each is 0.5 + 2 + 0.5 = 3 ns

• Trend

– 1980s/1990s: Wire delays were tiny compared to logic delays

– But wire delays not shrinking as fast as logic delays

• Wire delays may even be greater than logic delays!

• Must also consider register setup and hold times, also add to path

• Then add some time to the computed path, just to be safe

– e.g., if path is 3 ns, say 4 ns instead

a

+

b

c

2 ns

3 ns

3 n

s

0.5 ns0.5 ns

0.5 ns

clk

3 n

s




A Circuit May Have Numerous Paths

• Paths can exist

– In the datapath

– In the controller

– Between the

controller and

datapath

– May be

hundreds or

thousands of

paths

• Timing analysis tools that evaluate all possible paths automatically very helpful

Combinational logic

c

tot_lt_s

clk

n1

d

tot_ld

tot_lt_s

tot_clr

s0s1

n0

State register

s

8 8

8

8

a

ld

clr

tot

Datapath

8-bit

<

8-bit

adder

(c)

(b) (a)




The End






Lecture-29

A.Amalin Prince





17-10-07




RTL Design Optimizations and Tradeoffs

• While creating datapath during RTL design, there are several optimizations and tradeoffs, involving

– Pipelining

– Concurrency

– Component allocation

– Operator binding

– Operator scheduling




Pipelining

• Intuitive example: Washing dishes with a friend, you wash, friend dries

– You wash plate 1

– Then friend dries plate 1, while you wash plate 2

– Then friend dries plate 2, while you wash plate 3; and so on

– You don’t sit and watch friend dry; you start on the next plate

• Pipelining: Break task into stages,

each stage outputs data for next stage, all stages operate concurrently

(if they have data)

W1 W2 W3D1 D2 D3

Without pipelining:

With pipelining:

“Stage 1”

“Stage 2”

Time

W1

D1

W2

D2

W3

D3




Pipelining Example

• S = W+X+Y+Z

• Datapath on left has critical path of 4 ns, so fastest clock period is 4 ns

– Can read new data, add, and write result to S, every 4 ns

• Datapath on right has critical path of only 2 ns

– So can read new data every 2 ns – doubled performance (sort of...)

W X Y Z

2ns 2ns

2ns

+ +

+

S

clk

2ns 2ns

2ns

Longest pathis only 2 ns

stage 2

stage 1

clk

S S(0)

So minimum clockperiod is 2ns

S(1)

clk

S S(0)

So minimum clockperiod is 4ns

S(1)

Longest pathis 2+2 = 4 ns

W X Y Z

+ +

+

S

clk

2ns

pipelineregisters

Sta

ge 1

Sta

ge 2




Pipelining Example

• Pipelining requires refined definition of performance

– Latency: Time for new data to result in new output data (seconds)

– Throughput: Rate at which new data can be input (items / second)

– So pipelining above system

• Doubled the throughput, from 1 item / 4 ns, to 1 item / 2 ns

• Latency stayed the same: 4 ns

W X Y Z

2ns

2ns

2ns

+ +

+

S

clk

clk

S S(0)

So mininum clockperiod is4 ns

S(1)

Longest pathis 2+2 = 4 ns

W X Y Z

2n

s

2n

s

2ns

+ +

+

S

clk

clk

S S(0)

So mininum clockperiod is2 ns

S(1)

Longest pathis only 2 ns

pipelineregisters

stag

e 2

stag

e 1

(a) (b)




Recall: FIR Filter

xt0 xt1 xt2

x(t-2)x(t-1)x(t)

3-tap FIR filter

X

Y

clk

c0 c1 c2

* *

+

*

+

3210

2x4

yreg

e

Ca1

CL

C

Ca0




Pipeline Example: FIR Datapath

• 100-tap FIR filter: Row of 100 concurrent multipliers,

followed by tree of adders

– Assume 20 ns per multiplier

– 14 ns for entire adder tree

– Critical path of 20+14 = 34 ns

• Add pipeline registers

– Longest path now only 20 ns

– Clock frequency can be nearly doubled

• Great speedup with minimal

extra hardware

⋅ ⋅

+ +

+

multipliers

adder tree

xt registers

X

yreg

Y14 n

s20 n

s

stag

e 2

stag

e 1

pipeline

registers




Concurrency

• Concurrency: Divide task into subparts, execute subparts

simultaneously

– Dishwashing example: Divide stack into 3 substacks, give substacks to 3 neighbors, who work simultaneously -- 3 times speedup (ignoring time to move dishes to neighbors' homes)

– Concurrency does things side-by-side; pipelining instead uses stages (like a factory line)

– Already used concurrency in FIR filter -- concurrent multiplications

* * *

Task

Pipelining

Concurrency

Can do both, too




Concurrency Example: SAD Design Revisited

• Sum-of-absolute differences video compression example (Ch 5)

– Compute sum of absolute differences (SAD) of 256 pairs of pixels

– Original : Main loop did 1 sum per iteration, 256 iterations, 2 cycles per iter.

i_lt_256

i_inc

i_clr

sum_ld

sum_clr

sad_reg_ld

Datapath

sum

sad_reg

sad


<2569

32

8

8

8 8

3232

32

i –

+

abs

!goS0

go

S1sum = 0i = 0


S4 sad_reg=sum

S2

i<256

(i<256)’

-/abs/+ done in 1 cycle,

but done 256 times256 iters.*2 cycles/iter. = 512 cycles




Concurrency Example: SAD Design Revisited• More concurrent design

– Compute SAD for 16 pairs concurrently, do 16 times to compute all 16*16=256 SADs.

– Main loop does 16 sums per iteration, only 16 iters., still 2 cycles per iter.

go AB_rdAB_addr

AB_rd=1

S0

S1

S2

S4

!(i_lt_16)

go

!go

sum_clr=1i_clr=1

sum_ld=1

sad_reg_ld=1

i_inc=1

i_lt_16

Controller Datapath

sad

sad_reg

sum

i

<16i_lt_16

i_clr

sum_ld

sum_clr

sad_reg_ld

i_inc

A0 B0 A1 A14 A15B1 B14 B15

– – – –16 subtractors

abs abs abs abs16 absolute

values

+ +

+ +

Adder tree to sum 16 values

i_lt_1

6’

All -/abs/+’s shown done in 1 cycle, but done only 16 times

Orig: 256*2

= 5

12 c

yc

les

New

: 16*2

= 3

2 c

ycle

s




Concurrency Example: SAD Design Revisited

• Comparing the two designs

– Original: 256 iterations * 2 cycles/iter = 512 cycles

– More concurrent: 16 iterations * 2 cycles/iter = 32 cycles

– Speedup: 512/32 = 16x speedup

• Versus software

– Recall: Estimated about 6 microprocessor cycles per iteration

• 256 iterations * 6 cycles per iteration = 1536 cycles

• Original design speedup vs. software: 1536 / 512 = 3x

– (assuming cycle lengths are equal)

• Concurrent design’s speedup vs. software: 1536 / 32 = 48x

– 48x is very significant – quality of video may be much better

!(i_lt_16)




Component Allocation

• Another RTL tradeoff: Component allocation – Choosing a particular set of functional units to implement a set of operations

– e.g., given two states, each with multiplication

• Can use 2 multipliers (*)

• OR, can instead use 1 multiplier, and 2 muxes

• Smaller size, but slightly longer delay due to the mux delay

A B

t1 = t2*t3 t4 = t5*t6

∗∗∗∗

t2

t1

t3

∗∗∗∗

t5

t4

t6

(a)

FSM-A: (t1ld=1) B: (t4ld=1)

∗∗∗∗

2×1

t4t1(b)

2×1sl

t2 t5 t3 t6

sr

A: (sl=0; sr=0; t1ld=1)B: (sl=1; sr=1; t4ld=1)

(c)

2 mul

1 mul

delay




Operator Binding

• Another RTL tradeoff: Operator binding – Mapping a set of operations to a particular component allocation

– Note: operator/operation mean behavior (multiplication, addition), while component (aka functional unit) means hardware (multiplier, adder)

– Different bindings may yield different size or delay

Binding 2si

z

e

A B

t1 = t2* t3 t4 = t5* t6 t7 = t8* t3

C A B

t1 = t2* t3 t4 = t5* t6 t7 = t8* t3

C

MULA MULB

2x1

t7t4

2x1

t5t3t2 t8 t6 t3

sr

t1

sl 2x1

t2 t8 t3

sl

t6t5

t7t1 t4

MULBMULA2 multipliers allocated

Binding 1 Binding 2

Binding 1

delay

siz

e

2 muxes

vs.

1 mux

Component allocation

and Operator binding

are sometimes refered

to as Resource sharing




Operator Scheduling

• Yet another RTL tradeoff: Operator scheduling –Introducing or merging states, and assigning operations to

those states.

si

z

e

*

t3t2

*

t1

t6t5

*

t4

B2

(someoperations)

(someoperations)

t1 = t2* t3t4 = t5* t6

A B C

*t4 = t5 t6

3-state schedule

delay

siz

e

2x1

t4t1

2x1

t2 t5 t3 t6

srsl

4-state schedule

smaller(only 1 *)

but more delay due to

muxes

A B

(someoperations)

(someoperations)

t1 = t2*t3t4 = t5*t6

C




Think over it?

• Tasks of scheduling, allocation, and

binding are all interdependent

• Modern tools may combine the

tasks somewhat, and/or may iterate

among the tasks several times, in

search of good designs.




Operator Scheduling Example: Smaller FIR Filter

• 3-tap FIR filter design : Only one state – datapath computes new Y every cycle

– Used 3 multipliers and 2 adders; can we reduce the design’s size?

xt0 xt1 xt2

x(t-2)x(t-1)x(t)

3-tap FIR filter

X

Y

clk

c0 c1 c2

* *

+

*

+

3210

2x4

yreg

e

Ca1

CL

C

Ca0

y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)

Inputs: X (N bits)Outputs: Y (N bits)Local registers:

xt0, xt1, xt2 (N bits)

S1xt0 = Xxt1 = xt0xt2 = xt1Y = xt0*c0

+ xt1*c1+ xt2*c2





• Reduce the design’s size by re-scheduling the operations

– Do only one multiplication operation per state

y(t) = c0*x(t) + c1*x(t-1) + c2*x(t-2)


xt0, xt1, xt2 (N bits)

S1

(a)

xt0 = Xxt1 = xt0xt2 = xt1Y = xt0*c0

+ xt1*c1+ xt2*c2


xt0, xt1, xt2, sum (N bits)

S1

S2

S3

S4

S5

sum = sum + xt0 * c0

sum = 0xt0 = Nxt1 = xt0xt2 = xt1

sum = sum +xt1 * c1


Y = sum

(b)





• Reduce the design’s size by re-scheduling the operations

– Do only one multiplication (*) operation per state, along with sum (+)


xt0, xt1, xt2, sum (N bits)

S1

S2

S3

S4

S5


sum = 0xt0 = Xxt1 = xt0xt2 = xt1



Y = sum sum

*

+

yreg

c2c1c0xt0 xt1 xt2X

clk

x_ld

y_ld

Y

mul_s0

3x1 3x1

mul_s1

MAC

Multiply-

accumulate: a

common

datapath

component





• Many other options exist between fully-concurrent and

fully-serialized

– e.g., for 3-tap FIR, can use 1, 2, or 3 multipliers

– Can also choose fast array-style multipliers (which are concurrent internally) or slower shift-and-add multipliers (which are serialized internally)

– Each options represents compromises

concurrent FIR

compromises

serial

FIR

delay

siz

e




More on Optimizations and Tradeoffs• Serial vs. concurrent computation has been a common tradeoff

theme at all levels of design

– Serial: Perform tasks one at a time

– Concurrent: Perform multiple tasks simultaneously

• Combinational logic tradeoffs

– Concurrent: Two-level logic (fast but big)

– Serial: Multi-level logic (smaller but slower)

• abc + abd + ef (ab)(c+d) + ef – essentially computes ab first (serialized)

• Datapath component tradeoffs

– Serial: Carry-ripple adder (small but slow)

– Concurrent: Carry-lookahead adder (faster but bigger)

• Computes the carry-in bits concurrently

– Also multiplier: concurrent (array-style) vs. serial (shift-and-add)

• RTL design tradeoffs

– Concurrent: Schedule multiple operations in one state

– Serial: Schedule one operation per state




Higher vs. Lower Levels of Design

• Optimizations and tradeoffs at higher levels typically have greater impact than those at lower levels

– RTL decisions impact size/delay more than gate-level decisions

delay

size

(a) (b)

high-level changes

land

Spotlight analogy: The lower you are, the less solution landscape is illuminated (meaning possible)




Algorithm Selection

• Chosen algorithm can have big impact

– e.g., which filtering algorithm?• FIR is one type, but others require less computation at

expense of lower-quality filtering

• Example: Quickly find item’s address in 256-word memory

– One use: data compression. Many others.

– Algorithm 1: “Linear search”• Compare item with M[0], then M[1], M[2], ...

• 256 comparisons worst case

– Algorithm 2: “Binary search” (sort memory first)• Start considering entire memory range

– If M[mid]>item, consider lower half of M

– If M[mid]<item, consider upper half of M

– Repeat on new smaller range

– Dividing range by 2 each step; at most 8 such divisions

• Only 8 comparisons in worst case

• Choice of algorithm has tremendous impact

– Far more impact than say choice of comparator type

0x00000000

0x00000001

0x0000000F2:

96:

128:

255:

3:

1:

0:

0x000000FF

0x00000F0A

0x0000FFAA

0xFFFF0000

256x32 memory

128

96

64

Linear

search

Binary

search




Power Optimization

• Until now, we’ve focused on size and delay

• Power is another important design criteria

– Measured in Watts (energy/second)

• Rate at which energy is consumed

• Increasingly important as more transistors fit on a

chip

– Power not scaling down at same rate as size

• Means more heat per unit area – cooling is difficult

• Coupled with battery’s not improving at same rate

– Means battery can’t supply chip’s power for as long

– CMOS technology: Switching a wire from 0 to 1

consumes power (known as dynamic power)

• P = k * CV2f

– k: constant; C: capacitance of wires; V: voltage; f: switching

frequency

• Power reduction methods

– Reduce voltage: But slower, and there’s a limit

– What else?

energ

y (1

=valu

e in 2

001)

8

4

2

1

battery energydensity

energydemand

2001 03 05 07 09




Power Optimization using Clock Gating

• P = k * CV2f

• Much of a chip’s switching f (>30%)

due to clock signals

– After all, clock goes to every register

– Portion of FIR filter shown on right

• Notice clock signals n1, n2, n3, n4

• Solution: Disable clock switching to

registers unused in a particular state

– Achieve using AND gates

– FSM only sets 2nd input to AND gate to

1 in those states during which register

gets loaded

• Note: Advanced method, usually done

by tools, not designers

– Putting gates on clock wires creates

variations in clock signal (clock skew);

must be done with great care

yreg

c2c1c0xt0 xt1 xt2X

x_ld

y_ld

clk n2 n3 n4n1

yreg

c2c1c0xt0 xt1 xt2X

x_ld

y_ld

n2 n3 n4n1

clk

clk

n1, n2, n3

n4

Much switching on clock wires

clk

n1, n2, n3

n4

Greatly reduced

switching – less power

s1

s5




Power Optimization using Low-Power Gates on

Non-Critical Paths

• Another method: Use low-power gates

– Multiple versions of gates may exist

• Fast/high-power, and slow/low-power, versions

– Use slow/low-power gates on non-critical paths

• Reduces power, without increasing delay

gf

e

d

c

a

b

F1

26 transistors3 ns delay5 nanowatts power

1/1

1/1

1/1

1/1

1/1

nanowatts

nanoseconds gf

e

d

c

a

b

F1

26 transistors3 ns delay4 nanowatts power

2/0.5

1/1

2/0.5

1/1

1/1

high-power gates

low-power gateson noncritical path

low-powergates

delay

p

o

w

er

size




The End






Lecture-30

A.Amalin Prince




Objective : MEMORY COMPONENTS

19-10-07




Memory Components

• Register-transfer level design instantiates datapath

components to create

datapath, controlled by a controller

– A few more components are often used outside the controller and datapath

• MxN memory

– M words, N bits wide each

• Several varieties of memory,

which we now introduce

N-bits

wide each

M×N memory

M w

ord

s




Random Access Memory (RAM)

• RAM – Readable and writable memory

– “Random access memory”

• Strange name – Created several decades ago to

contrast with sequentially-accessed storage like

tape drives

– Logically same as register file – Memory with

address inputs, data inputs/outputs, and control

• RAM usually just one port; register file usually two

or more

– RAM vs. register file

• RAM typically larger than roughly 512 or 1024

words

• RAM typically stores bits using a bit storage

approach that is more efficient than a flip flop

• RAM typically implemented on a chip in a square

rather than rectangular shape – keeps longest

wires (hence delay) short

32

10data

addr

rw

en

1024× 32RAM

32

4

32

4

W_data

W_addr

W_en

R_data

R_addr

R_en16×32

register file

Register file

RAM block symbol




RAM Internal Structure

• Similar internal structure as register file

– Decoder enables appropriate word based on address inputs

– rw controls whether cell is written or read

32

10data

addr

rw

en

1024x32RAM

addr0addr1

addr(A-1)

clk

enrw

addr

Let A = log2M

to all cells

wdata(N-1)

rdata(N-1)

wdata(N-2)

rdata(N-2)

wdata0

rdata0

bit storageblock(aka “cell”)

word

word

RAM cell

wordenable

wordenable

rw

data cell

data

a0a1

d0

d1

d(M-1)

a(A-1)

e

AxMdecoder

enable




Dynamic RAM (DRAM)

• “Dynamic” RAM cell

– Relies on large capacitor to store bit

• Write: Transistor conducts, data voltage

level gets stored on top plate of capacitor

• Read: Just look at value of d

• Problem: Capacitor discharges over time

– Must “refresh” regularly, by reading d and

then writing it right back

addr0addr1

addr(A-1)

clk

enrw

ad

dr

Let A = log2 M

a0a1

d0

d1

d(M-1)

a(A-1)

e

A ⋅ Mdecoder

wordenable

to all cells

wdata(N-1)

rdata(N-1)

wdata(N-2)

rdata(N-2)

wdata0

rdata0

bit storageblock(aka cell )

word

,,,,

cell

wordenable

wordenable

rw

data

data

32

10data

addr

rw

en

1024x32RAM

Internal circuit of

memory is beyond

the scope of this

course. You will

do in later courses

courses




Comparing Memory Types

• Register file

– Fastest

– But biggest size

• SRAM

– Fast

– More compact than register file

• DRAM

– Slowest

• And refreshing takes time

– But very compact

• Use register file for small items, SRAM for large items, and DRAM for huge items

– Note: DRAM’s big capacitor requires a special chip design process, so DRAM is often a separate chip

MxN Memoryimplemented as a:

registerfile

SRAM

DRAM

Size comparison for same

number of bits (not to scale)




Reading and Writing a RAM

• Writing

– Put address on addr lines, data on data lines, set rw=1, en=1

• Reading

– Set addr and en lines, but put nothing (Z) on data lines, set rw=0

– Data will appear on data lines

• Don’t forget to obey setup and hold times

– In short – keep inputs stable before and after a clock edge

clk

addr

data

rw

en

1 2

9 913

999 Z 500500

3

1 means write

RAM[9]now equals 500

RAM[13]now equals 999

(b)

valid

valid

Z 500

accesstime

setuptime

holdtime

setuptime

clk

addr

data

rw




RAM Example: Digital Sound Recorder

• Behavior

– Record: Digitize sound, store as series of 4096 12-bit digital values in RAM

• We’ll use a 4096x16 RAM (12-bit wide RAM not common)

– Play back later

– Common behavior in telephone answering machine, toys, voice recorders

• To record, processor should read a-to-d, store read values into successive RAM words

– To play, processor should read successive RAM words and enable d-to-a

wire

speaker

microphone

wireanalog-to-

digitalconverter

digital-to-analog

converter

ad_ld da_ld

Rrw RenRa12

16

processor

ad_buf

dat

a

add

r

rw en

4096⋅ 16RAM





• RTL design of processor– Create high-level state

machine

– Begin with the record behavior

– Keep local register a

• Stores current address, ranges from 0 to 4095 (thus need 12 bits)

– Create state machine that counts from 0 to 4095 using a

• For each a

– Read analog-to-digital conv.

» ad_ld=1, ad_buf=1

– Write to RAM at address a

» Ra=a, Rrw=1, Ren=1

ad_ld=1ad_buf=1Ra=aRrw=1Ren=1

S

a=0

a=a+1

a=4095

a<4095

T

U

Local register: a (12 bits)

analog-to-digital

converter

digital-to-analog

converter

ad_ld da_ld

Rw RenRa12

16

processor

ad_buf

4096x16RAM

Record behavior





– Now create play behavior

– Use local register a again, create state machine that counts from 0 to 4095 again

• For each a

– Read RAM

– Write to digital-to-analog conv.

• Note: Must write d-to-a one cycle after reading RAM, when the read data is available on the data bus

– The record and play state machines would be parts of a larger state machine controlled by signals that determine when to record or play

da_ld=1

ad_buf=0Ra=aRrw=0Ren=1

V

a=0

a=a+1

a=4095

a<4095

W

X


Play behavior

data bus

analog-to-digital

converter

digital-to-analog

converter

ad_ld da_ld

Rw RenRa12

16

processor

ad_buf

4096x16RAM




Read-Only Memory – ROM

• Memory that can only be read from, not written to

– Data lines are output only

– No need for rw input

• Advantages over RAM

– Compact: May be smaller

– Nonvolatile: Saves bits even if power supply is turned off

– Speed: May be faster (especially than DRAM)

– Low power: Doesn’t need power supply to save bits, so can extend battery life

• Choose ROM over RAM if stored data won’t change (or won’t change often)

– For example, a table of Celsius to Fahrenheit conversions in a digital thermometer

32

10data

addr

rw

en

1024× 32RAM

RAM block symbol

32

10data

addr

en

1024x32ROM

ROM block symbol




Read-Only Memory – ROM

• Internal logical structure similar to RAM, without the data

input lines

32

10data

addr

en

1024x32ROM

ROM block symbol

ROM cell

addr0addr1

addr(A-1)

clk

en

addr

Let A = log2M

a0a1

d0

d1

d(M-1)

a(A-1)

e

AxMdecoder

wordenable

rdata(N-1) rdata(N-2) rdata0

bit storageblock(aka “cell”)

word

wordenable

wordenable

data

data




ROM Types

• If a ROM can only be read, how are the stored bits stored in the first place?– Storing bits in a ROM known as

programming

– Several methods

• Mask-programmed ROM– Bits are hardwired as 0s or 1s

during chip manufacturing

• 2-bit word on right stores “10”

• word enable (from decoder) simply passes the hardwired value through transistor

– Notice how compact, and fast, this memory would be

cell cell

wordenable

data line data line01

addr0addr1

addr(A-1)

en

add

r

Let A = log2 M

a0a1

d0

d1

d(M-1)

a(A-1)

e

A ⋅ Mdecoder

wordenable

data(N-1) data(N-2) data0

bit storageblock(a cell )

word

,,,,

cell

wordenable

wordenable

data

data




ROM Types

• Fuse-Based Programmable ROM

– Each cell has a fuse

– A special device, known as a programmer, blows certain fuses (using higher-than-normal voltage)

• Those cells will be read as 0s

(involving some special electronics)

• Cells with unblown fuses will be read

as 1s

• 2-bit word on right stores “10”

– Also known as One-Time Programmable (OTP) ROM

cell cell

wordenable

data line data line11

blown fusefuse

addr0addr1

addr(A-1)

en

add

r

Let A = log2 M

a0a1

d0

d1

d(M-1)

a(A-1)

e

A ⋅ Mdecoder

wordenable



word

,,,,

cell

wordenable

wordenable

data

data




ROM Types

• Erasable Programmable ROM (EPROM)

– Uses “floating-gate transistor” in each cell

– Special programmer device uses higher-

than-normal voltage to cause electrons to

tunnel into the gate

• Electrons become trapped in the gate

• Only done for cells that should store 0

• Other cells (without electrons trapped in

gate) will be 1

– 2-bit word on right stores “10”

• Details beyond our scope – just general

idea is necessary here

– To erase, shine ultraviolet light onto chip

• Gives trapped electrons energy to escape

• Requires chip package to have window

addr0addr1

addr(A-1)

en

add

r

Let A = log2 M

a0a1

d0

d1

d(M-1)

a(A-1)

e

A ⋅ Mdecoder

wordenable



word

,,,,

cell

wordenable

wordenable

data

data

cell cell

wordenable

data line data line

eÐeÐa

ting

g

a

t

e t

r

t

or

trapped electrons

01

flo

atin

g-g

ate

tran

sist

or




ROM Types

• Electronically-Erasable Programmable ROM (EEPROM)

– Similar to EPROM

• Uses floating-gate transistor, electronic programming to trap electrons in certain cells

– But erasing done electronically, not using UV light

– Erasing done one word at a time

• Flash memory

– Like EEPROM, but all words (or large blocks of words) can be erased simultaneously

– Become common relatively recently (late 1990s)

• Both types are in-system programmable

– Can be programmed with new stored bits while in the system in which the ROM operates

• Requires bi-directional data lines, and write control input

• Also need busy output to indicate that erasing is in progress – erasing takes some time

a

ting

g

a

t

e t

r

t

or

32

10data

addr

en

write

busy

1024x32EEPROM




ROM Example: Talking Doll

• Doll plays prerecorded message, trigger by vibration

– Message must be stored without power supply Use a ROM, not a RAM, because ROM is nonvolatile

• And because message will never change, use a mask-programmed ROM or OTP ROM

– Processor should wait for vibration (v=1), then read words 0 to 4095 from the ROM, writing each to the d-to-a

4096x16 ROM

processor

d

a

Ra

16

Ren

da_ld

digital-to-

analog

converter

v

speaker

vibration

sensor

“Hello there!”

“Hello there!” audio

divided into 4096

samples, stored

in ROM

“Hello

there!”




ROM Example: Talking Doll

• High-level state machine

– Create state machine that waits for v=1, and then counts from 0 to 4095 using a local register a

– For each a, read ROM, write to digital-to-analog converter

d

a

4096x16 ROM

processor

Ra

16

Ren

da_ld

digital-to-

analog

converter

v

Sa=0

da_ld=1

a=a+1a=4095

a<4095

T

U

Ra=a

Ren=1


v

v’




ROM Example: Digital Telephone Answering Machine

Using a Flash Memory• Want to record the outgoing

announcement

– When rec=1, record digitized sound in locations 0 to 4095

– When play=1, play those stored sounds to digital-to-analog converter

• What type of memory?

– Should store without power supply – ROM, not RAM

– Should be in-system programmable – EEPROM or Flash, not EPROM, OTP ROM, or mask-programmed ROM

– Will always erase entire memory when reprogramming – Flash better than EEPROM

analog-to-digital

converterdigital-to-

analogconverterad_ld

da_ld

Rrw Rener buRa12

16

processor

ad_buf

busy

4096x16 Flash

recplayrecord

microphone speaker

“We’re not home.”




ROM Example: Digital Telephone Answering Machine

Using a Flash Memory• High-level state machine

– Once rec=1, begin

erasing flash by setting

er=1

– Wait for flash to finish

erasing by waiting for

bu=0

– Execute loop that sets

local register a from 0 to

4095, reading analog-to-

digital converter and

writing to flash for each a

d

a

r

w

en

analog-to-digital

converterdigital-to-

analogconverterad_ld

da_ld

Rrw Ren er buRa12

16

processor

ad_buf

4096x16 Flash

recplayrecord

microphone speaker

T

er=0

bu

bu’

er=1

rec

S


a=4096

a<4096

U

V

ad_ld=1ad_buf=1Ra=aRrw=1Ren=1a=a+1

a=0




Blurring of Distinction Between ROM and RAM

• We said that

– RAM is readable and writable

– ROM is read-only

• But some ROMs act almost like RAMs

– EEPROM and Flash are in-system programmable

• Essentially means that writes are slow– Also, number of writes may be limited (perhaps a few million times)

• And, some RAMs act almost like ROMs

– Non-volatile RAMs: Can save their data without the power supply

• One type: Built-in battery, may work for up to 10 years

• Another type: Includes ROM backup for RAM – controller writes RAM contents to ROM before turning off

• New memory technologies evolving that merge RAM and ROM benefits

– e.g., MRAM

• Bottom line

– Lot of choices available to designer, must find best fit with design goals

EEPROM

ROM FlashNVRAM

RAM




Queues

• A queue is another component sometimes used during RTL design

• Queue: A list written to at the back, from read from the front– Like a list of waiting restaurant

customers

• Writing called a push, reading called a pop

• Because first item written into a queue will be the first item read out, also called a FIFO (first-in-first-out)

frontback

write itemsto the backof the queue

read (andremove) itemsfrom front ofthe queue




Queues

• Queue has addresses, and two pointers: rear and front

– Initially both point to 0

• Push (write)

– Item written to address pointed to by rear

– rear incremented

• Pop (read)

– Item read from address pointed to by front

– front incremented

• If front or rear reaches 7, next (incremented) value should be 0 (for a queue with addresses 0 to 7)

r f

01234567

fr

0

A

1234567

A

fr

0

AB

1234567

B

fr

0

B

1234567

A




Queues

• Treat memory as a circle

– If front or rear reaches 7, next (incremented) value should be 0 rather than 8 (for a queue with addresses 0 to 7)

• Two conditions of interest

– Full queue – no room for more items

• In 8-entry queue, means 8 items present

• No further pushes allowed until a pop occurs

• Causes front=rear

– Empty queue – no items

• No pops allowed until a push occurs

• Causes front=rear

– Both conditions have front=rear

• To detect whether front=rear means full or empty, need state machine that detects if previous operation was push or pop, sets full or empty output signal (respectively)

fr

0

B

1234567

A

B

1 7

2 6

3 5

4

0

f

r

r




Queue Implementation

• Can use register file for item storage

• Implement rear and frontusing up counters– rear used as register file’s

write address, front as read address

• Simple controller would set control lines for pushes and pops, and also detect full and empty situations– FSM for controller not

shown

8⋅ 16 register file

clr

3-bitup counter

3-bitup counter

inc

clr

inc

rear front

=

wr

rd

reset

wdata rdata16 16

33

wdata

waddr

wr

rdata

raddr

rd

eq

Contr

olle

r

full

empty8-word 16-bit queue




Common Uses of a Queue

• Computer keyboard

– Pushes pressed keys onto queue, meanwhile pops and sends to computer

• Digital video recorder

– Pushes captured frames, meanwhile pops frames, compresses them, and stores them

• Computer network routers

– Pushes incoming packets onto queue, meanwhile pops packets, processes destination information, and forwards each packet out over appropriate port




Queue Usage Example

• Example series of pushes and pops– Note how rear and front

pointers move

– Note that popping doesn’t really remove the data from the queue, but that data is no longer accessible

– Note how rear (and front) wraps around from address 7 to 0

• Note: pushing a full queue is an error– As is popping an empty queue

r f

01234567

fr

0123456

9585723

7

fr

01234567

f r

01234567

9585723

95857236

r f

01234567

data:9

full35857236

ERROR! Pushing a full queueresults in unknown state

Initially emptyqueue

1. After pushing9, 5, 8, 5, 7, 2, 3

2. After popping

3. After pushing 6

4. After pushing 3

5. After pushing 4




The End






Lecture-31

A.Amalin Prince




Objective : Programmable Logic Devices (PLDs)

22-10-07




Digital Logic Devices




Cost of Digital Logic




Field Programmable Logic Devices (FPLD)




Implementation Options for Digital Logic

• Assembly of SSI and MSI parts on PC boards.

– mostly obsolete; still useful when just a few parts needed

• Programmable Logic Devices (PLD)

– variety of types, with different size and performance characteristics; largest have over 106 gate “equivalents”

– CAD tools enable simulation and automate device programming

• Application Specific Integrated Circuits (ASIC)

– design methods similar to PLDs

• HDLs and simulation with synthesis using standard cell library

• plus physical design - placement of logic components and routing

– can augment with custom design of critical components

– higher performance, greater logic density

– custom IC fabrication -- suitable for high production volumes




Programmable Logic Devices• Simple logic arrays

– implement 2 level logic circuits (AND/OR)

– based on regular array structure

– several types

• Read Only Memories (ROMs and PROMs)

• Programmable Logic Array (PLA)

• Programmable Array Logic (PAL)

• Field Programmable Gate Arrays (FPGA)

– many copies of common building block

– each block can be configured for different logic functions and typically includes a

flip flop and a 4 input function generator

– programmable interconnect

– often includes SRAM blocks

– largest FPGAs have about 100K flip flops, 100K function generators and 10 Mb of

SRAM




Read Only Memory (ROM)

• “Permanent” binary information is stored

• Non-volatile memory

– Power off does not erase information stored

2k wordsN-bit per work

ROMROMN-bit Data Output

K-bit address lines

NK




32x8 ROM

32x8 ROM85

0

1

2

3

28

29

30

31

D7 D6 D5 D4 D3 D2 D1 D0

A4

A3

A2

A1

A0

5-to-32

Decoder

Each represents 32 wires

Fuse can beimplemented as

a diode or a pass transistor




Programming the 32x8 ROM

1000011111111

0110101001111

0000100010111

…………………………………

0000110101000

1101000110000

1010001100000

D0D1D2D3D4D5D6D7A0A1A2A3A4

012

293031

D7 D6 D5 D4 D3 D2 D1 D0

A4

A3

A2

A1

A0

5-to-32

Decoder




Example: Lookup Table

• Design a square lookup table for F(X) = XF(X) = X22 using ROM

497

366

255

164

93

42

11

00

F(X)=X2X

110001111

100100110

011001101

010000100

001001011

000100010

000001001

000000000

F(X)=X2X




Square Lookup Table using ROM

110001111

100100110

011001101

010000100

001001011

000100010

000001001

000000000

F(X)=X2X

0

1

2

3

F5 F4 F3 F2 F1 F0

X2

X1

X0

3-to-8

Decoder 4

5

6

7





110001111

100100110

011001101

010000100

001001011

000100010

000001001

000000000

F(X)=X2X

= X0= X0Not UsedNot Used

0

1

2

3

F5 F4 F3 F2 F1 F0

X2

X1

X0

3-to-8

Decoder 4

5

6

7





110001111

100100110

011001101

010000100

001001011

000100010

000001001

000000000

F(X)=X2X

0

1

2

3

F5 F4 F3 F2 F0

X2

X1

X0

3-to-8

Decoder 4

5

6

7

F1




Classifying Three Basic PLDs

Fixed AND planeFixed AND plane

(decoder)(decoder)Programmable Programmable

OR planeOR plane

Programmable

Connections

(Programmable) Read(Programmable) Read--Only Memory (ROM)Only Memory (ROM)

INPUT OUTPUT

Programmable Programmable

OR planeOR plane

Programmable

Connections

Programmable Logic Array (PLA)Programmable Logic Array (PLA)

ProgrammableProgrammable

AND planeAND planeINPUT OUTPUT

ProgrammableProgrammable

AND planeAND planeFixed Fixed

OR planeOR plane

Programmable Array Logic (PAL) DevicesProgrammable Array Logic (PAL) DevicesPAL: trademark of AMD, use PAL as an adjective orPAL: trademark of AMD, use PAL as an adjective or

expect to receive a letter from AMDexpect to receive a letter from AMD’’s lawyerss lawyers

INPUTOUTPUT

F/F




Programmable Logic Array (PLA)

C

B

A

C C B B A A

F2

Programmable AND Plane

Programmable

OR Plane




Regular k-map minimization




PLA minimization




PLA Example




Example using PLAPLA

∑

∑=

=

m(0,5,6,7)C)B,F2(A,

m(0,1,2,4) C)B,F1(A,

CBAACABF2

BCACABF1

CBCABAF1

++=

++=

++=




Example using PLAPLA

C

B

A

C C B B A A

CBAACABF2

BCACABF1

++=

++=

AB

AC

BC

A B C

F2F1




PAL Device

A

B

IO1

IO2

IO1 IO1B BA A IO1 IO2

Programmable

AND Plane

Fixed

OR Plane




PAL Device Design Example

A

B

IO1

IO2

IO1 IO1B BA A

DCBADCADCBACABIO2

DCBACABIO1

+++=

+=

D DC C

Not programmed




Example




Example (cont.)




The End






Lecture-32

A.Amalin Prince





24-10-07




Sequential Programmable Devices

• SPLD (Sequential or Simple Programmable Logic Device)

• CPLD (Complex Programmable Logic Device)

• FPGA (Field Programmable Logic Device)




SPLD

• Simple Programmable Logic Devices (SPLDs)

– Developed 1970s (thus, pre-dates FPGAs)

– Prefabricated IC with large AND-OR structure

– Connections can be "programmed" to create custom circuit

• Circuit shown can implement any

3-input function of up to 3 terms

– e.g., F = abc + a'c'

O1

PLD IC

I3I2I1

programmable nodes




Programmable Nodes in an SPLD• Fuse based – "blown" fuse removes

connection

• Memory based – 1 creates connection

1mem

Fuse

"unblown" fuse

0mem

"blown" fuse

programmable node

(a)

(b)

O1

PLD IC

I3I2I1

programmable nodes

Fuse based

Memory based




Example: Seat Belt Warning Light System

• Design circuit for warning light

• Sensors

– s=1: seat belt fastened

– k=1: key inserted

– p=1: person in seat

• Capture Boolean equation

– person in seat, and seat belt not fastened, and key inserted

• Convert equation to circuit

• Notice

– Boolean algebra enables easy capture as equation and conversion to circuit

• How design with switches?

• Of course, logic gates are built from switches, but we think at level of logic gates, not switches

w = p AND NOT(s) AND k

k

p

s

w

BeltWarn




PLD Drawings and PLD Implementation Example

• Common way of drawing PLD connections:

– Uses one wire to represent all inputs of an AND

– Uses "x" to represent connection

• Crossing wires are not

connected unless "x" is present

• Example: Seat belt warning

light using SPLDk

p

s

w

BeltWarn

Two ways to generate a 0 term

O1

PLD IC

I3I2I1

××

wired AND

I3∗I2'

××

×× ×× ××

×× ×

w

PLD IC

spk

kps'

0

0




PLD Extensions

I3I2I1

(a)

PLD IC

O1

O2

Two-output PLD




Sequential Programmable Logic Device




Basic Macrocell Logic

I3I2I1

(b)

PLD IC

O2

O1

FF

FF

2

⋅

1

2

⋅

1

programmable bit

clk

PLD with programmable registered outputs

Macrocell




Basic Macrocell Logic




More on PLDs

• Originally (1970s) known as Programmable Logic Array – PLA

– Had programmable AND and OR arrays

• AMD created "Programmable Array Logic" – "PAL" (trademark)

– Only AND array was programmable (fuse based)

• Lattice Semiconductor Corp. created "Generic Array Logic – "GAL" (trademark)

– Memory based

• As IC capacities increased, companies put multiple PLD structures on one

chip, interconnecting them

– Become known as Complex PLDs (CPLD), and older PLDs became known as

Simple PLDs (SPLD)

• GENERALLY SPEAKING, difference of SPLDs vs. CPLDs vs. FPGAs:

– SPLD: tens to hundreds of gates, and usually non-volatile (saves bits without

power)

– CPLD: thousands of gates, and usually non-volatile

– FPGA: tens of thousands of gates and more, and usually volatile (but no

reason why couldn't be non-volatile)




General CPLD




CPLD structure

PLD PLD PLD PLD

PLD PLD PLD PLD

Logic block

Interconnects

I/O block




Field Programmable Gate Arrays

• FPGAs can be used to construct more complex circuits.• Chip contains a large number (tens of thousands) of

configurable logic building blocks.– typically each block includes a 4 input function generator, a flip flop and

some “glue” logic– CAD tools map high level circuit to basic blocks, configuring function

generators & other configurable elements as needed

• Programmable interconnect used to wire logic blocks.– wire segments connected to logic blocks and to other wire segments by

configurable switches– CAD tools determine switch configuration needed to provide right

connectivity

• CAD tools perform mapping, placement, routing.– routing information used in timing analysis & simulation




Programmable IC Technology – FPGA

• Manufactured IC technologies require weeks to months to fabricate

– And have large (hundred thousand to million dollar) initial costs

• Programmable ICs are pre-manufactured

– Can implement circuit today

– Just download bits into device

– Slower/bigger/more-power than manufactured ICs

• But get it today, and no fabrication costs

• Popular programmable IC – FPGA

– "Field-programmable gate array"

• Developed late 1980s

• Though no "gate array" inside– Named when gate arrays were very popular in the 1980s

• Programmable in seconds




FPGA Internals: Lookup Tables (LUTs)

• Basic idea: Memory can implement combinational logic

– e.g., 2-address memory can implement 2-input logic

– 1-bit wide memory – 1 function; 2-bits wide – 2 functions

• Such memory in FPGA known as Lookup Table (LUT)

(b)(a) (d)

F = x'y' + xyG = xy'

x

0

0

1

1

y

0

1

0

1

F

1

0

0

1

G

0

0

1

0

F = x'y' + xy

x

0

0

1

1

y

0

1

0

1

F

1

0

0

1

4x1 Mem.

0

1

2

3

rd

a1a0

1

yx

D

F

4x1 Mem.

1

0

0

1

0

1

2

3

rd

a1a0

1

D

(c)

1

0

0

1

y=0

x=0

F=1

4x2 Mem.

10

00

01

10

0

1

2

3

rd

a1a0

1

xy D1 D0

F G(e)




Circuit for 2 input LUT

(a) Circuit for a two-input LUT

x 1

x 2

f

0/1

0/1

0/1

0/1

0

0

1

1

0

1

0

1

1

0

0

1

x 1

x 2

(b) f 1 x 1 x 2 x 1 x 2 + =

(c) Storage cell contents in the LUT

x 1

x 2

1

0

0

1

f 1

f 1





• Example: Seat-belt warning light (again)

k

p

s

w

BeltWarn

(a)

(b)

k

0

0

0

0

1

1

1

1

p

0

0

1

1

0

0

1

1

s

0

1

0

1

0

1

0

1

w

0

0

0

0

0

0

1

0

Programming(seconds)

Fab1-3 months

(c)

8x1 Mem.

0

0

0

0

0

0

1

0

D

w

IC

0

1

2

3

4

5

6

7

a2a1a0

kps





• Lookup tables become inefficient for more inputs

– 3 inputs only 8 words

– 8 inputs 256 words; 16 inputs 65,536 words!

• FPGAs thus have numerous small (3, 4, 5, or even 6-input) LUTs

– If circuit has more inputs, must partition circuit among LUTs

– Example: Extended seat-belt warning light system:

5-input circuit, but 3-

input LUTs available

Map to 3-input LUTs

k

p

s

t

d

w

BeltWarn

(a)

Partition circuit into

3-input sub-circuits

k

p

s

t

d

x w

BeltWarn

(b)

3 inputs1 outputx=kps'

3 inputs1 outputw=x+t+d

Sub-circuits have only 3-inputs each

8x1 Mem.

0

0

0

0

0

0

1

0

D

0

1

2

3

4

5

6

7

a2a1

a0

kp

s

kps'

x

dt

(c)

8x1 Mem.

0

1

1

1

1

1

1

1

D

w

0

1

2

3

4

5

6

7

a2a1

a0x+t+d

?





• Partitioning among smaller LUTs is more size efficient

– Example: 9-input circuit

a

cb

a

cb

d

fg

F

i

e

h

d

fe

g

ih

3x1

3x1 3x1

3x1

F

(a) (b) (c)

512x1 Mem.

8x1 Mem.

Original 9-input circuit Partitioned among

3x1 LUTs

Requires only 4

3-input LUTs

(8x1 memories) –

much smaller than

a 9-input LUT

(512x1 memory)




8x2 Mem.

D0D1

0

3

4

5

6

7

a2a1

a0

a

bc

(c)

(a)

(b)

8x2 Mem.

D0D1

0

1

2

3

4

5

a2a1

a0

a

cb

a

cb

d

d

e

e

F

F

t3

3

1

12

2


• LUT typically has 2 (or more) outputs, not just one

• Example: Partitioning a circuit among 3-input 2-output lookup tables

00

00

00

00

00

00

00

01

First column unused;

second column

implements AND

Fed

00

10

00

10

00

10

10

10

t

Second column unused;

first column implements

AND/OR sub-circuit

(Note: decomposed one 4-

input AND input two

smaller ANDs to enable

partitioning into 3-input

sub-circuits)

1

2

6

7





• Example: Mapping a 2x4 decoder to 3-input 2-output LUTs

8x2 Mem.

10

01

00

00

00

00

00

00

D0D1

0

1

2

3

4

5

6

7

a2a1

a0

i1 i0

(b)(a)

8x2 Mem.

00

00

10

01

00

00

00

00

D0D1

d1d0 d3d2

0

1

2

3

4

5

6

7

a2a1

a0

0

i1i0

0

d0

d1

d2

d3

Sub-c

ircu

it h

as 2

inputs

, 2 o

utp

uts

Sub-

circ

uit h

as 2

inpu

ts, 2

out

puts




The End






Lecture-33

A.Amalin Prince





26-10-07




Programmable IC Technology – FPGA

• Manufactured IC technologies require weeks to months to fabricate

– And have large (hundred thousand to million dollar) initial costs

• Programmable ICs are pre-manufactured

– Can implement circuit today

– Just download bits into device

– Slower/bigger/more-power than manufactured ICs

• But get it today, and no fabrication costs

• Popular programmable IC – FPGA

– "Field-programmable gate array"

• Developed late 1980s

• Though no "gate array" inside– Named when gate arrays were very popular in the 1980s

• Programmable in seconds





• Basic idea: Memory can implement combinational logic

– e.g., 2-address memory can implement 2-input logic

– 1-bit wide memory – 1 function; 2-bits wide – 2 functions

• Such memory in FPGA known as Lookup Table (LUT)

(b)(a) (d)

F = x'y' + xyG = xy'

x

0

0

1

1

y

0

1

0

1

F

1

0

0

1

G

0

0

1

0

F = x'y' + xy

x

0

0

1

1

y

0

1

0

1

F

1

0

0

1

4x1 Mem.

0

1

2

3

rd

a1a0

1

yx

D

F

4x1 Mem.

1

0

0

1

0

1

2

3

rd

a1a0

1

D

(c)

1

0

0

1

y=0

x=0

F=1

4x2 Mem.

10

00

01

10

0

1

2

3

rd

a1a0

1

xy D1 D0

F G(e)




Circuit for 2 input LUT

(a) Circuit for a two-input LUT

x 1

x 2

f

0/1

0/1

0/1

0/1

0

0

1

1

0

1

0

1

1

0

0

1

x 1

x 2

(b) f 1 x 1 x 2 x 1 x 2 + =

(c) Storage cell contents in the LUT

x 1

x 2

1

0

0

1

f 1

f 1





• Example: Seat-belt warning light (again)

k

p

s

w

BeltWarn

(a)

(b)

k

0

0

0

0

1

1

1

1

p

0

0

1

1

0

0

1

1

s

0

1

0

1

0

1

0

1

w

0

0

0

0

0

0

1

0

Programming(seconds)

Fab1-3 months

(c)

8x1 Mem.

0

0

0

0

0

0

1

0

D

w

IC

0

1

2

3

4

5

6

7

a2a1a0

kps





• Lookup tables become inefficient for more inputs

– 3 inputs only 8 words

– 8 inputs 256 words; 16 inputs 65,536 words!

• FPGAs thus have numerous small (3, 4, 5, or even 6-input) LUTs

– If circuit has more inputs, must partition circuit among LUTs

– Example: Extended seat-belt warning light system:

5-input circuit, but 3-

input LUTs available

Map to 3-input LUTs

k

p

s

t

d

w

BeltWarn

(a)

Partition circuit into

3-input sub-circuits

k

p

s

t

d

x w

BeltWarn

(b)

3 inputs1 outputx=kps'

3 inputs1 outputw=x+t+d

Sub-circuits have only 3-inputs each

8x1 Mem.

0

0

0

0

0

0

1

0

D

0

1

2

3

4

5

6

7

a2a1

a0

kp

s

kps'

x

dt

(c)

8x1 Mem.

0

1

1

1

1

1

1

1

D

w

0

1

2

3

4

5

6

7

a2a1

a0x+t+d





• Partitioning among smaller LUTs is more size efficient

– Example: 9-input circuit

a

cb

a

cb

d

fg

F

i

e

h

d

fe

g

ih

3x1

3x1 3x1

3x1

F

(a) (b) (c)

512x1 Mem.

8x1 Mem.

Original 9-input circuit Partitioned among

3x1 LUTs

Requires only 4

3-input LUTs

(8x1 memories) –

much smaller than

a 9-input LUT

(512x1 memory)




8x2 Mem.

D0D1

0

3

4

5

6

7

a2a1

a0

a

bc

(c)

(a)

(b)

8x2 Mem.

D0D1

0

1

2

3

4

5

a2a1

a0

a

cb

a

cb

d

d

e

e

F

F

t3

3

1

12

2


• LUT typically has 2 (or more) outputs, not just one

• Example: Partitioning a circuit among 3-input 2-output lookup tables

00

00

00

00

00

00

00

01

First column unused;

second column

implements AND

Fed

00

10

00

10

00

10

10

10

t

Second column unused;

first column implements

AND/OR sub-circuit

(Note: decomposed one 4-

input AND input two

smaller ANDs to enable

partitioning into 3-input

sub-circuits)

1

2

6

7





• Example: Mapping a 2x4 decoder to 3-input 2-output LUTs

8x2 Mem.

10

01

00

00

00

00

00

00

D0D1

0

1

2

3

4

5

6

7

a2a1

a0

i1 i0

(b)(a)

8x2 Mem.

00

00

10

01

00

00

00

00

D0D1

d1d0 d3d2

0

1

2

3

4

5

6

7

a2a1

a0

0

i1i0

0

d0

d1

d2

d3

Sub-c

ircu

it h

as 2

inputs

, 2 o

utp

uts

Sub-

circ

uit h

as 2

inpu

ts, 2

out

puts




8x2 Mem.

00

00

00

00

00

00

00

00

D0D1

0

1

2

3

4

5

6

7

a2a1

a0

P1

P0P6

P7

P8P9

P2P3

P5P4

(a)

8x2 Mem.

00

00

00

00

00

00

00

00

D0D1

0

1

2

3

4

5

6

7

a2a1

a0m0m1

o0o1

m2m3

Switchmatrix

FPGA (partial)

FPGA Internals: Switch Matrices • Previous slides had hardwired connections between LUTs

• Instead, want to program the connections too

• Use switch matrices (also known as programmable interconnect)

– Simple mux-based version – each output can be set to any of the four inputs just by programming its 2-bit configuration memory

(b)

m0

o0

o1

i0s0

d

s1

i1i2i3

m1m2m3

2-bitmemory

2-bitmemory

Switch matrix

4x1mux

i0s0

d

s1

i1i2i3

4x1mux




8x2 Mem.

10

01

00

00

00

00

00

00

D0D1

0

1

2

3

4

5

6

7

a2a1

a0

0

0d3

d2

d1d0

i1i0

i0i1

(a)

8x2 Mem.

00

00

10

01

00

00

00

00

D0D1

0

1

2

3

4

5

6

7

a2a1

a0m0m1

o0o1

m2m3

Switchmatrix

FPGA (partial)

10

11

10

11

FPGA Internals: Switch Matrices

• Mapping a 2x4 decoder onto an FPGA with a switch matrix

(b)

m0

o0

o1

i0s0

d

s1

i1i2i3

m1m2m3

Switch matrix

4x1mux

i0s0

d

s1

i1i2i3

4x1mux

Th

ese bits estab

lish th

e desired

conn

ection

s




FPGA Internals: Switch Matrices • Mapping the extended seatbelt warning light onto an

FPGA with a switch matrix

– Recall earlier example (let's ignore d input for simplicity)

8x2 Mem.

00

00

00

00

00

00

01

00

D0D1

0

1

2

3

4

5

6

7

a2a1

a0

k

0w

ps

0t

(a) (b)

8x2 Mem.

00

01

01

01

00

00

00

00

D0D1

0

1

2

3

4

5

6

7

a2a1

a0m0m1

o0o1

m2

m0

o0

o1

i0s0

d

s1

i1i2i3

m1m2m3

m3Switchmatrix

FPGA (partial)

00

10

Switch matrix

4x1mux

i0s0

d

s1

i1i2i3

4x1mux

00

10

k

p

s

t

d

x w

BeltWarn

x




FPGA Internals: Configurable Logic Blocks (CLBs)

• LUTs can only implement combinational logic

• Need flip-flops to implement sequential logic

• Add flip-flop to each LUT output

– Configurable Logic

Block (CLB)

• LUT + flip-flops

– Can program CLB

outputs to come

from flip-flops or

from LUTs directly

8x2 Mem.

00

00

00

00

00

00

00

00

D0D1

0

1

2

3

4

5

6

7

a2a1

a0

P1

P0

P2P3

P5P4

8x2 Mem.

00

00

00

00

00

00

00

00

D0D1

0

1

2

3

4

5

6

7

a2a1

a0m0m1

o0o1

m2m3

Switchmatrix

FPGA

00

00

CLB CLB

P6P7P8P9

flip-flopCLB output

00 2x12x1 00 2x12x1

1-bitCLB

outputconfiguration

memory

1 0 1 0 1 0 1 0




FPGA Internals: Sequential Circuit Example using CLBs

8x2 Mem.

11

10

01

00

00

00

00

00

D0D1

0

1

2

3

4

5

6

7

a2a1a0

0

0

ab

dc

8x2 Mem.

00

01

10

11

00

00

00

00

D0D1

0

1

2

3

4

5

6

7

a2a1a0m0

m1

o0o1

m2m3

Switchmatrix

FPGA

10

11

11 2 x12 x1 2 x12 x1

CLB CLB

zyxw

11

a b c d

w x y

(a)

(b)

(c)

z

a2

0

0

0

0

0

a1

a

0

0

1

1

a0

b

0

1

0

1

D1

w=a'

1

1

0

0

D0

x=b'

1

0

1

0

Left lookup table

below unused

1 0 1 0 1 0 1 0




FPGA Internals: Overall Architecture

• Consists of hundreds or thousands of CLBs and switch

matrices (SMs) arranged in regular pattern on a chip

CLB

SM SM

SM SM

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

Represents channel with

tens of wires

Connections for just one

CLB shown, but all

CLBs are obviously

connected to channels




FPGA Internals: Configuration memory

• The storage elements for the lookup table, the CLB output configuration, and the switch matrices, are collectively

known as an FPGA’s configuration memory, although that

“memory” is comprised of numerous smaller memories and even registers or flip-flops.

Programming an FPGA

?




FPGA Internals: Programming an FPGA

• All configuration

memory bits are connected as

one big shift register

– Known as scan chain

• Shift in "bit file" of desired circuit

8x2 Mem.

11

10

01

01

00

00

00

00

D0D1

0

1

2

3

4

5

6

7

a2a1a0

0

0

Pin

Pclk

ab

dc

Pin

Pclk

8x2 Mem.

01

00

11

10

00

00

00

00

D0D1

0

1

2

3

4

5

6

7

a2a1a0m0

m1

o0o1

m2m3

Switchmatrix

FPGA

10

11

11 2x12 x1 11 2 x12 x1

CLB CLB

zyxw

(c)

(b)

(a)

Conceptual view of configuration bit scan chainis that of a 40-bit shift register

Bit file contents for desired circuit: 1101101000000000111101100011010000000011

This isn't wrong. Although the bits appear as "10" above, note that the

scan chain passes through those bits from right to left – so "01" is correct

here.




FPGA Structure

Logic block

I/O block

Interconnects




Xilinx FPGA Organization

• CLBs can be connected to “passing” wires.• Wire segments connected by switch matrix.• Long wire segments used to connect distant CLBs.• Configuration information stored in SRAM bits that are loaded when power

turns on.

switch matrix

wire segments

configurable logic blocks (CLB)

IO blocks (IOB)




FPGA Programmability

• Floating gate transistor

– Used in EPROM and EEPROM

• SRAM-controlled switch Control

– Pass transistors

– Multiplexers (to determine how to route inputs)

• Antifuse

– Similar to fuse

– Originally an Open-Circuit

– One-Time Programmable (OTP)




S/R C

D

>

EC CLR

PRE

LUT4

LUT3

LUT4D

>

EC CLR

PRE

1

1

S/R C

YQ

XQ

Y

X

CLK EC

G1G2G3G4

F1F2F3F4

H1

DIN

S/R

Flip Flop

Xilinx Configurable Logic Block

MainFunctionGenerators

MainFunctionGenerators

Set/ResetControl

Clock EnableControl

Clock EdgeSelect




Implementing Serial Adder in CLB

• Second flip flop still available and LUT3 partially available.

S/R C

D

>

EC CLR

PRE

LUT4

LUT3

LUT4D

>

EC CLR

PRE

1

1

S/R C

XQ

X

CLK EC

Sum

SumFunction

A⊕B⊕Carry

Carry

AB0

(A⋅B+A⋅Carry+B⋅Carry)EN

CarryFunction

StateFlip Flop

EN

H1

DIN

S/R

0

1

00

1

0110100101101101

0000000000010111




How many gates does an FPGA Implement?

• A common method of indicating design size for a circuit approximate the number of 2-input NAND gates that would

be required to implement the circuit.

• FPGA have lookup tables and switch matrices inside, not

gates. FPGA size are therefore typically reported by

considering how large of a circuit made up of 2-input NAND gates could be implemented using the FPGA architecture.

• FPGA vendors may report FPGA size by saying a particular FPGA has

– Density of 100,000 system gates

– 100,000 typical gates But approximate




FPGA versus ASICs and Microprocessors

• FPGAs are less efficient than ASICs in terms of delay, size and power

• Despite the performance, size, and power overhead compared to ASICs, FPGAs are still much faster than

software on a microprocessor for many tasks, in part

FPGAs can effectively implement concurrency, pipelining, and bit-level operations.

• Thus FPGAs posses the programming flexibility of software on a microprocessor, yet approach the performance of an

ASIC, representing an excellent implementation option for many design.




The End

Company headquarters in Hillsboro.

Xilinx San Jose HQ Building at 2100 Logic

Drive

Altera headquarters in San

Jose

Mountain View, CA 94043-4655,

USA






Lecture-34

A.Amalin Prince




Objective : Algorithmic State Machines (ASM Chart)

29-10-07




The Algorithmic State Machine

Partitioning of a digital system.




The Algorithmic State Machine

Model of an algorithmic state machine




Algorithmic State Machine

Algorithmic State Machine –

representation of a Finite State Machine

suitable for FSMs with a larger number of inputs and outputs

compared to FSMs expressed using state diagrams and

state tables.




Timing of an algorithmic State Machine




Elements used in ASM charts: The state box




Elements used in ASM charts: The state box

• State box – represents a state.

Equivalent to a node in a state diagram or a row in

a state table.

Moore type outputs are listed inside of the box. It is

customary to write only the name of the signal that

has to be asserted in the given state, e.g., z

instead of z=1. Also, it might be useful to write an

action to be taken, e.g., Count = Count + 1, and

only later translate it to asserting a control signal

that causes a given action to take place.




Elements used in ASM charts: The decision box

(a) Symbol (b) Alternate symbol




Elements used in ASM charts: The decision box

• Decision box – indicates that a given condition is

to be tested and the exit path is to be chosen

accordingly

The condition expression consists of one or more

inputs to the FSM.




Elements used in ASM charts: The conditional Output box




Elements used in ASM charts: The conditional Output box

• Conditional output box – denotes output signals

that are of the Mealy type.

The condition that determines whether such

outputs are generated is specified in the decision

box.




Example of an ASM block and its link paths

1 1 2

2 1 2 3

3 1 3

4 1 2 3

5 1 3

Link path

L x x

L x x x

L x x

L x x x

L x x

=

=

=

=

=




Two equivalent ASM blocks





a) Using a single decision box (b) Using several decision boxes





(a) Parallel decision boxes

(b) Serial decision boxes




Invalid ASM block having nonunique next states

Two rules Rule-1

For any valid combination of values

to the decision - box variables, all

simultaneously selected link path

must lead to the same exit path.




Looping

(a) Incorrect (b) Correct

Rule-2

There is no closed loop that do not

contain at least one state box.




ASM Chart for a mod-8 binary counter




ASM Chart

for a mod-3

binary up-

down

counter




Relationship between state diagrams and ASM charts

Moore sequential network. (a) State diagram. (b) ASM chart.





Mealy sequential network. (a) State diagram. (b) ASM chart.




Register Transfer Level (RTL) Design using ASM chart




The End






Lecture-35

A.Amalin Prince




Objective : Algorithmic State Machines (ASM Chart)

07-11-07





Moore sequential network. (a) State diagram. (b) ASM chart.





Mealy sequential network. (a) State diagram. (b) ASM chart.




Sequence recognizer

(01, 01, 11, 00)




An ASM chart Binary multiplication

(a) Pencil-and-paper approach (b) Add-shift approach




Architecture for a binary multiplier




ASM Chart for a Binary multiplier




State Assignment




ASM Transition table




Assigned ASM transition table




Algebraic Representation of assigned Transition Tables




ASM Realizations using discrete gates with clocked D

Flip-Flop




ASM Realizations using Multiplexers with clocked D Flip-Flop




Register Transfer Level (RTL) Design using ASM chart




The End

12/11/2007 2

OBJECTIVE

Multiplication

Division

12/11/2007 3

MULTIPLICATION

More complicated than addition

Accomplished via shifting and addition

Multiplication of two N- bit binary integers results in

a product of up to 2N bits in length

12/11/2007 4

MULTIPLICATION OF UNSIGNED BINARY INTEGERS

12/11/2007 5

12/11/2007 6

12/11/2007 7

12/11/2007 8

12/11/2007 9

12/11/2007 10

12/11/2007 11

MULTIPLICATION OF SIGNED BINARY INTEGERS

Booth Algorithm

Generates a 2N bit product

Negative number is represented as in 2’s complement form

Sign bit is used to represent both the positive and negative numbers

Multiplier is scanned from right to left

If there is a bit change from 0 to 1 then -1 times the shifted multiplicand is selected

If there is a bit change from 1 to 0 then +1 times the shifted multiplicand is selected

12/11/2007 12

12/11/2007 13

12/11/2007 14

12/11/2007 15

DIVISION

Accomplished via shifting and addition / subtraction

More complicated

12/11/2007 16

Two methods

Restoration method

Non-Restoration method

12/11/2007 17

HARDWARE IMPLEMENTATION

12/11/2007 18

RESTORATION METHOD

Steps

1. Set A to zero

2. Shift A and Q left one binary position

3. Subtract M from A and place the answer back in A

4. If MSB of A is 1, set Q0 to 0 and add M back to A (restore A);

otherwise set Q0 to 1

5. Repeat steps 2,3 & 4 for N times

12/11/2007 19

Example:

12/11/2007 20

12/11/2007 21

NON-RESTORATION METHOD

Steps

1. Set A to zero

2. If MSB of A is 0, Shift A and Q left one binary position and Subtract

M from A ;otherwise, shift A and Q left and add M to A

3. Now, if MSB of A is 0 , set Q0 to 1 ; otherwise set Q0 to 0

4. Repeat steps 2 & 3 for N times

5. If MSB of A is 1, add M to A

12/11/2007 22






Lecture-37

A.Amalin Prince




Objective : Asynchronous Sequential Logic

14-11-07




Introduction

Block Diagram

of an

Asynchronous

Sequential

Circuit

Fundamental mode

?




Analysis Procedure

• Determine all feedback loops in the circuit

• Designate the output of each feedback loop with variable Yi,

and its corresponding input with yi for i=1,2,…,km where k is the number of feedback loops in the circuit.

• Derive the Boolean functions of all Y’s as a function of the

external inputs and the y’s.

• Plot each Y function in a map, using the y variable for the

rows and the external inputs for the columns.

• Combine all the maps into one table showing the value of

Y=Y1Y2…Yk inside each square.

• Circle those values of Y in each square that are equal to

the value of y=y1y2…yk in the same row.




Example1: Asynchronous Sequential Circuit

1 1 2'Y xy x y= +

2 1 2' 'Y xy x y= +




Example1: Maps and Transition Table

Total state=internal state + inputs




Example 1: State Table

1 1 1 01 1

0 0 1 01 0

1 1 0 10 1

0 0 0 10 0

x=0 x=1

Next StatePresent

State




Example1:Flow table

Primitive flow table

It has only one stable

state in each row.




Example 2: Implementation using Gates

Flow Table




Example 2:Transition table and Output map




Example 2: Logic diagram




Circuits with Latches




Analysis with latches

• Label each latch output with Yi and its external feedback path (if any) with yi for i=1,2,…,k.

• Derive the Boolean function for the Si and Ri inputs in each latch.

• Check whether SR=0 for each NOR latch or whether S’R’=0 for each NAND latch. If this condition is not satisfied, there is a possibility that the circuit may not operate properly.

• Evaluate Y=S+R’y for each NOR latch or Y=S’+Ry for each NAND latch.

• Construct a map with the y’s representing the rows and the x inputs representing the columns.

• Plot the value of Y=Y1Y2…,Yk in the map.

• Circle all stable states where Y=y. The resulting map is then the transition table.




Example 3: Circuit with SR NOR Latch

1 1 2 2 1 2

1 1 2 2 1 2' ' '

S x y S x x

R x y R x x

= =

= =

check whether

thecondition 0SR =

1 1 1 2 1 2

2 2 1 2 1 2

' '

'

S R x y x y

S R x x x x

=

=

0The result is




Example 2: Excitation function

1 1 1 1 1 2 1 2 1 1 2 1 1 2 1

2 2 2 2 1 2 2 1 2 1 2 2 2 1 2

' ( )

' ( ' ) '

Y S R y x y x x y x y x y x y

Y S R y x x x y y x x x y y y

= + = + + = + +

= + = + + = + +

'Y S R y= +




Example 3: Transition table

Flow

Table

?




Implementation Procedure

• Given a transition table that specifies the excitation function Y=Y1Y2…,Yk, derive a pair of maps for Si and Ri for each

i=1,2,…,k.

• Derive the simplified Boolean functions for each Si and Ri.

Care must be taken not to make Si and Ri equal to 1 in the

same minterm square.

• Draw the logic diagram using k latches together with the

gates required to generate the S and R Boolean functions. For NOR latches, use the S and R Boolean functions

obtained in step 2. For NAND latches, use the complemented values of those obtained in step-2




Example 4: Implementation using SR Latch

Flow table




Example 4: Transition Table and Map




Example 4: Circuit with NOR Latch




Example 4: Circuit with NAND Latch




The End






Lecture-38

A.Amalin Prince





16-11-07




Reduction of State and Flow Tables

• State table to be reduced

1 0a eg

0 0 c b f

1 0a de

1 0 a d d

0 1g fc

0 0 e a b

0 0d ba

x=0 x=1x=0 x=1

OutputNext State

Present

State




Implication Table

0 0 c a f

1 0 a d d

0 1d fc

0 0d aa

x=0 x=1x=0 x=1

OutputNext State

Present

State




Merging of the Flow Table

• Incompletely specified function

– Determine all compatible pairs by using the implication table.

– Find the maximal compatibles using merger diagram.

– Find a minimal collection of compatibles that covers all the states and is closed.




Step1: Compatible Pairs

( , ) ( , ) ( , ) ( , ) ( , ) ( , ) ( , )

Compatible pairs are

a b a c a d b e b f c d e f




Step2:Maximal Compatibles (Merger Diagram)




Example1: Step3:Closed Covering Condition

• A closed set of compatibles that covers all the state is called a closed covering.

• Consider the previous example

– If we remove (a,b), we are left with a set of two compatibles: (a,c,d) (b,e,f)

– All six states from the flow table are included in this set.

– This satisfies the covering condition.

– There are no implied states for (a,c); (a,d); (c,d); (b,e); (b,e); (b,f); and (e,f).

– So the closure condition is also satisfied.




Example2: Step3:Closed Covering Condition




The End






Lecture-39

A.Amalin Prince





19-11-07




Race Conditions

• A race is said to exist in an asynchronous sequential circuit when two or more binary state variables change value in

response to a change in an input variable.

• Race may cause the state variables to change in an

unpredictable manner.

• If the final stable state that the circuit reaches does not depend on the order in which the state variables change,

the race is called a noncritical race.

• If it is possible to end in two or more different stable states,

depending on the order in which the state variable change, then it is a critical race.

• For proper operation, critical race must be avoided.




Examples of Noncritical Races




Examples of Critical Races




Examples of Cycles

When a circuit goes through a unique sequence of

unstable states, it is said to have a cycle




Stability Considerations

1 2 1 2 1 2 2( ) ' ( ' ') ' 'Y x y x x y x x x x y= = + = +




Race-Free State AssignmentShared-Row Assignment




Race-Free State Assignment




Race-Free State AssignmentShared-Row Assignment





Multiple-Row Assignment




Reduce The Primitive Flow table




Exercise




The End






Lecture-40

A.Amalin Prince





21-11-07




Design Procedure

• Obtain the primitive flow tale from the given design specifications.

• Reduce the flow table by merging rows in the primitive floe table.

• Assign binary state variables to each row of the reduced

flow table to obtain the transition table.

• Assign output values to the dashes associated with the

unstable states to obtain the output maps.

• Simplify the Boolean functions of the excitation and output

variables and draw the logic diagram. The logic diagram can be drawn using S R latches.




Design Example1

• Design a gated latch circuit with two inputs, G (gate) and D (data), and one output, Q. Binary information present at the

D input is transformed to the Q output when G is equal to 1.

The Q output will follow the D input as long as G=1. When G goes to 0, the information that was present at the D input

at the time the transition occurred is retained at the Q output. The gated latch is a memory element that accept

the value of D when G=1 and retains this values after G goes to 0. Once G=0, a change in D does not change the

value of the output Q.




Example1:Primitive Flow Table




Example1:Reduction of the Primitive Flow Table




Example1:Transition Table and Output Map




Example1: Circuit with SR NAND Latch




Assigning Outputs to Unstable States




Assigning Outputs to Unstable States

• Assign a 0 to an output variable associated with an unstable state that is a transient state between two stable states that

have a 0 in the corresponding output variable.

• Assign a 1 to an output variable associated with an unstable

state that is a transient state between two stable states that have a 0 in the corresponding output variable.

• Assign a don't-care to an output variable associated with an

unstable state that is a transient state between two stable states that have different values (0 and 1 or 1 and 0) in the

corresponding output variable.




Design Example2

• Design a fundamental-mode asynchronous sequential network meeting the following requirement.

– There are two inputs x1 and x2 and a single output z.

– The inputs x1 and x2 never change simultaneously.

– The output is always to be 0 when x1=0, independent of the value of x2.

– The output is to become 1 if x2 changes while x1=1 and is to remain 1 until x1 becomes 0 again.




Design Example3

• Design a fundamental-mode asynchronous sequential network meeting the following requirements:

– There are two inputs x1 and x2 and a single output z.

– The inputs x1 and x2 never change or are 1 simultaneously.

– An output of z=1 is to occur only during the input state x1x2=01 is preceded by the input sequence x1x2=01,00,10,00,10,00.




The End






Lecture-41

A.Amalin Prince





23-11-07




Hazards

• Hazards are unwanted switching transients that may appear at the output of a circuit because different path exhibit different propagation delays.

• Hazards in Combinational circuit may cause a temporary false-output value.

• Hazards in asynchronous circuits may result in a transition to a wrong stable state.

• Hazards– Static Hazards

• Static 0 Hazard

• Static 1 Hazard

– Dynamic Hazards




Hazards In Combinational Circuits




Illustration of Static 1-Hazards




Illustration of Static 0-Hazards




Hazard-Free Circuit




Illustration of Dynamic Hazard

Consider inputs x1x2x3=000 and 100

Assume Delay of G1<G2<G4 and G3=G5=0




Hazards in Sequential Circuits




Essential Hazards

• An essential Hazard is caused by unequal delays along two or more paths that originate from the same input.




The End

Von Neumann architectureSingle bank of memory which processor accesses through a single set of address and data lines.

Processor core

Address bus

Memory

Data bus

Harvard ArchitectureThe Processor is connected to two independent memory banks via two independent set of buses.Program bank and Data bank

With modifications in Harvard Program bank will hold program instructions and data and other bank with data only.

Lots of devices on one bus leads to:Propagation delays

Long data paths mean that co-ordination of bus use can adversely affect performance

Most systems use multiple buses to overcome these problems

Complex Instruction Set ComputerIntel x86DEC VAX, PDP11Motorola 68kIBM 360, 370

Complex instructions bring the hardware closer to high-level languages

A CISC PROCESSOR

Larger instructions with variable formats(16-64 bits/ instruction)

Larger Addressing Modes(12- 24)

Few Registers

Most Microcoded with control Memory

Instruction Set ArchitectureMemory-to-registerLoad indexed

x = y[i];

Load indexed, post-incrementy = y[i++];

Load indexed, pre-decrementy = y[--i];

Memory-to-memorya = b

Block copymemcpy(d,s,n);

x86MOV AX,[BX]

MOV AX,[BP+SI]

LODSW

68k:

MOV.L D0,-(A2)

MOVSB

REP MOVSB

Instruction countUsually more than 256

Maximum number of 8-bit opcodesPowerful instructions

Many microcode stepsAdded some complexity to interrupt handling, page faulting, etc

Variable length, multiple formats1 to 10 bytes

Reduced Instruction Set Computer

LOAD- STORE ArchitectureFewer Addressing ModesFixed Length InstructionsMore RegistersDesigned for Pipeline EfficiencyHardwired Control Unit

Two steps:FetchExecute

Steps in Execution of an Instruction

CPU fetches instruction from Main Memory

CPU Decodes the Instruction Op-code

Depending on Op-code- Fetches another operand- Execute instruction via register to register transfer- Write the results in M- Write the results in I/O

Repeats the steps

Instruction and Address Formats:

Opcode + Operands

First Generation Computers

A3A2A1A0Opcode

- Because of sequential nature A3 not required

Two address Format

A1A0OPCODE

ADD AX, BX (8086)

One Address Format

A0OPCODE

ADD B (8085)

Zero address Machines:(Stack Machines)

ADD

Ex:

X = A*B + C*D

PUSHPOPADDSUBMULDIVHLT

LOADSTOREADDSUBMULDIVHLT

MOVEADDSUBMULDIVHLT

ADDSUBMULDIVHLT

0-adr m/c1-adr m/c2-adr m/c3-adr m/c

General Instructions available

3-ADR M/C

MUL T,A,BMUL X,C,DADD X,X,THLT

2 ADR M/C

MOVE T,AMUL T,BMOVE X,CMUL X,DADD X,THLT

1 ADR M/C

LOAD AMUL BSTORE TLOAD CMUL DADD TSTORE XHLT

0 ADR M/C

PUSH APUSH BMULPUSH CPUSH DMULADDPOP XHLT

A CISC PROCESSOR

Larger instructions with variable formats(16-64 bits/ instruction)

Larger Addressing Modes(12- 24)

Few Registers

Most Microcoded with control Memory

Designing a Processor

Given an instruction set how does one goabout designing the processor, how to arriveat different architectural blocks like execution unit controller etc.,

Microprocessor(Computer s central Processing Unit)Ex: Pentium, 68000 etc.

has two partsControl part says what to doData part does it

REG SET

ALU

CLU

CENTRAL PROCESSING UNIT

Clock Generator Bus Controller

Processor Controller

Execution Unit

A SINGLE CHIP MICROPROCESSOR

Control Part

Data Part

EXECUTION UNIT

Programmers Register set

Additional registers ( IR, PC , Temp Reg)

ALU and any special function units

Internal Data pathsAll connected through a interconnect networkUsually comprised of one/more buses

Register Set:

Program CounterPC PC + 1, PC Address part of the

branch Instruction

Instruction RegisterIR M [PC]

General Purpose Registers

ARITHMETIC LOGIC UNIT

F1 F2

MUX

A B

SEL LINES

CONTROLLINES

R

CONTROL PART

A Bus Controller to run the external bus cyclesto fetch instructions (or) operands from memory andto write results back to memory

A Controller that goes through control steps

A clock generator to generate timing signalsto decide the time durations of individual control steps

CONTROL LOGIC UNIT

-Directs all hardware activity inside

-Controls Fetch, Decode, Execute Cycle

Macro/Micro Instructions

Instruction set Summary

Instruction Formats

Operations

Addressing Modes

Programmers Registers

A TYPICAL INSTRUCTION

- ADD R1, D2(B2)

(R1, B2 - Registers ), D2- displacement

(R1) + (Memory) (R1) ; (B2) + D2 Memory

B2R15A D20 15 16 31

Steps for executing instruction

- Fetch the first instruction half-word

- Find ADD control sequence

- Fetch the remaining instruction half-word

- Calculate the operand address

- Fetch the operand

- Add

- Store the result

CPU Operations

Fetch a word from Memory

Store a word into memory

Reg Transfers

Performing an ALU function

Instruction Decoder

IR

PC

MAR

MDR

R0

Rn-1

Y

ALU

Z

Address Bus

Data Bus

A BControl Lines

Clear Y

Example Microinstructions:

Open/Close a gate from Reg to a bus

Transfer data along a bus

Send timing signals

Test bits within a register

Fetching a word from memory:

i. MAR (R1)

ii. Read Signal

iii. Wait for Memory-function-complete (MFC) signal

iv. R2 (MDR)

Storing a word into Memory:

i. MAR (R1)

ii. MDR (R2)

iii. Memory write signal

iv. Wait for MFC

Register Transfers:

R2 R1

To enable data transfer between various Blocks connected to common bus provide Input output gating.

R

Rin

Rout

ALU

Y

Z

Zout

Zin

Yin

Performing an Arithmetic or Logic Operation:

i. R1out, Yin

ii. R2out, Add, Zin

iii. Zout, R3in

MDRout, IRinIR MDRT3

Zout, PCin, Wait for MFCWaitT2

PCout, MARin, Clear Y, Set Carryin of ALU, ADD, Zin, READ

MAR PC; PC PC+1T1

Control SequenceRTLStep

Ex: Add contents of a memory location to register R1

- Instruction Fetch

Zout, R1in, ENDR1 ZT7

MDRout, ADD, ZinZ Y + M[MAR]T6

R1out, Yin, Wait for MFCY R1T5

Addr-field of IRout, MARin, READ

MAR IRT4


Ex: Add contents of a memory location to register R1




MAR PC; PC PC+1T1


Ex: Branch by an offset x

Zout, PCin, ENDPC ZT6

ADD, Zin Addr-field of IRoutZ Y + [x of IR]T5

PCout, YinY PCT4


Ex: Branch by an offset x

Ex: CALL absolute address

-Address fetched along with instruction

PCin, Addr-field of IRout, Wait for MFC, END

PC IRT7

MDRint, PCout, WRITEMDR PCT6

Zout, ,MARin,,SPin SP Z, MAR ZT5

Set Y, SPout, ADD, ZinZ SP-1T4




MAR PC; PC PC+1T1


Ex: CALL absolute address

Design of CLU

- Hard wired design

- Microprogrammed design

HARDWIRED CONTROL UNIT

Hard-wired Control Unit

-The opcode field of IR. This field is decoded to provide the encoder information about instruction being decoded

-Signals from status and condition

-Control step information( Step generator for T1, T2, .)

-External signals such as start, MFC, interrupts etc.

Control signal generator generatesIndividual control signals.

Ex:

Zin = T1 + T6.ADD + T5. BR + .

- IMPLEMENTED AS A COMBINATIONAL CIRCUIT.

Combinational design could be using PLDs.

Hard wired logic difficult to implement changes

Provides faster execution.

-Another approachMicroprogrammed control unit

Microprogrammed Unit

-Sequence of microinstructions corresponding to each instruction is stored in ROM called Control Memory

-Called Microprogram

-Provides flexibility of implementation

-Less hardware

Micro instruction word is the word whosebits represent control signals

Ex:

Y R1 ; R1out, Yin, Wait for MFC

Z Y + MDR ; MDRout, ADD, Zin

R1 Z ; Zout, R1in, END

Step :R1in R1out Yin Zin Zout MDRout ADD WMFC END

5 0 1 1 0 0 0 0 1 0

6 0 0 0 1 0 1 1 0 0

7 1 0 0 0 1 0 0 0 1

Microprogramming Types

Horizontal Microprogramming

Vertical Microprogramming

Horizontal Approach

-1 bit per control signal

-Many control signals generated concurrently

-Permitting very fast operation

-Requires large control memory area

Vertical Approach

- Most Micro instructions are mutually exclusive and never invoked simultaneously

- Possible to divide into groups and use few bitsto represent each group

- A Decoder then used to select a particularMicrooperation to be invoked

. . . . . . . . .

Decoder

Micro instruction

Control Lines

-Control Memory size reduced

-Additional hardware required

-Slows down the process

Nanomemory

-Third memory unit beside main memory andcontrol memory

-Appropriate when many microinstructionsoccur several time

Example:

Microprogram with k t-bit micro instructions

To store this k x t size control memory required

Assume only n distinct microinstructions are used where n k

Store these instructions in n-word, t-bit nanomemory

Original program replaced by address of nanomemory word

Reduction in memory size

For ex:

16, 384 x 128 is the original size

But has only 256 different microinstructions

Nanomemory size is 256 x 128

Control ROM size is 16,384 x 8

Size saved = (16,384 x 128)-(16,384x8) (256 x 128)= 1,933,312

Speed reduced because two levels of memory

CPU Memory Architectures &

Organization

Sunil Nanda

Agenda

• Memory Architecture Concepts– Caches

– Virtual Memory

– TLBs & Page Tables

• MP Memory Organization– MP Classification

– Cache Coherence

– Memory Consistency

Memory Architecture

Concepts

Caches – Principle of locality

• Temporal locality

– If an item is referenced, it will tend to be

referenced again soon

• Spatial locality

– If an item is referenced, nearby items will tend

to be referenced soon

Cache Performance

• Multiple level caches are the norm

– Upper caches are smaller and faster than lower

caches

– Inclusion principle is typically followed

• Miss rate is misleading

– Avg mem access time = Hit time + (Miss rate * Miss

penalty)

– Even better is the actual program execution time

Cache Block size

• Minimum unit of data that can either be present or not present in a cache

– Typical range 8 – 128 bytes

– Typically fixed for a design – though variable size designs have been done

Block size Block size

Miss penalty

Miss rate

Cache Associativity

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

Fully associativeBlock 12 can go anywhere

Direct MappedBlock 12 can go only into block 412 mod 8

2-way set associativeBlock 12 can go anywhere into set 012 mod 4

Block number Block number

Se

t 0

Se

t 1

Se

t 2

Se

t 3

Tag Index Block Offset

Portions of an address

Tag used to check all blocks in a set

Index used to select the set

Block offset is the address of the desired data within the block

Block Frame Address

Example Cache Design8KB cache, 2-way associative, 8 byte blocks

Tag <20> Index <9> Block Offset <3>

V <1> Tag <20> Data <64>

. . .

. . .

=?

=?

2:1 MUX

To CPU

Major Cache Design Issues

• Split/Unified

• Size & Number of levels

• Associativity

• Block size/sub-blocks

• Writeback v/s writethru

• Write-allocate

• Virtual or Physical tags

• Coherence Protocol

• Write buffers

• Victim caches

Virtual Memory Motivation

• Allow multiple processes to keep independent use of entire virtual address space

• Allow multiple processes to share same physical memory

• Allow processes which need more memory than available physical memory

• Prevent one process from accessing code or data of another process (unless explicitly allowed)

Virtual Memory basics

• Main memory acts as a “cache” for disk data

• Each process on each processor issues only virtual addresses

• Each process has a unique “context number” or “process id”

• The kernel sets up tables to map a [context, virtual-address] pair to a physical address. This mapping may not be unique for special cases.

• There is usually some hardware assist to do a fast lookup for the VA->PA mapping (e.g. TLB)

• IO devices usually work with physical addresses

Segmentation v/s Paging

Not always – small

segments may transfer only

a few bytes

Yes – page size adjusted to

balance access time and

transfer time

Efficient disk traffic

External fragmentation –

unused portions of main

memory

Internal fragmentation –

unused portion of a page

Memory use efficiency

Hard – must find contiguos,

variable size unused portion

of main memory

Trivial – all blocks are same

size

Replacing a block

May be visible to aplication

programmer

Invisible to application

programmer

Programmer visible

Two – Segment & offsetOneWords per address

SegmentationPaging

Virtual v/s Physical address

• Physical address is the address in main memory– Size depends on size of main memory e.g. 256MB needs 28-bits

of physical address

• Virtual address is the address issued by the processor. – Independent of the size of main memory – typically 32 bits

• Virtual address needs to be translated to physical address for every main memory access– Process called address translation

• Page size is common between virtual and physical addresses– Typically ranges from 4KB to 16KB– Some systems allow for a finite number of page sizes

Example VA/PA formats

• 1GB Main memory, 4K page size, 32-bit VA

Virtual Page Number <20> Page Offset <12>

Physical Page Number <18> Page Offset <12>

VA – 32 bits

PA – 30 bits

Address Translation

Conte

xt

ID

Page Tables

• Mapping for VA->PA organized in Page Tables– A collection of Page Table Entries (PTEs)

– Mapping of PA->VA organized in Inverted Page Tables

• PTE holds info for one page at a time– Primarily holds translation from one vritual-page-number to a

physical-page-number

• Typically holds additional info– Whether page is in memory, disk or unallocated

– Protection information (executable, read-only etc.)

– Whether page has been referenced or modified

– Kernel v/s User Page

Hierarchical Page Tables• Motivation

– Page tables can become pretty large– They may need to be paged themselves– Some architectures support multiple page sizes

• Introduce a Page Table Pointer (PTP)– Points to the base address of the next level of page table

<10> <10> Page offset <12>VA<16>ContextD

BaseAddress

PTEPTPPTP

Translation Lookaside Buffers (TLB)• TLB is nothing but a cache for PTEs

– Could be direct mapped, set associative or fully associative– Takes VA and context-id as input and returns PA and protection information

• A TLB-miss causes a Page Table search to find the approriate PTE– Called a Table Walk – lot of care taken in table organization to facilitate a walk– Much more expensive than a cache miss– Could be done in SW or HW– Replacement strategies similar to caches

• If new PTE indicates that the page is on disk – a Page-Fault occurs– OS must retrieve the page from disk– OS must allocate a physical page for it– OS must fix the PTE bits to indicate that it is now in memory

• If new PTE indicates that the page is unallocated (invalid)– OS must allocate a physical page for it– OS must fix the PTE bits to indicate that it is now allocated

• TLB coherence issues exist for MPs jus like cache coherence– Primary issue occurs when demapping a page– Stale entries may exist in other TLBs – need to be flushed

MP Memory Organization

Flynn Processor Classification

• SISD – Single Instruction Single Data– Classic uniprocessor Von-neumann architecture

• SIMD – Single Instruction Multiple Data– Array and Vector Processors– Same Operation performed at one time on multiple data

• MISD – Multiple Instruction Single Data– Systolic Processors

• MIMD – Multiple Instruction Multiple Data– Conventional MP architectures– Each processor executes different program with its own data

SISD Processors

Control

Unit

Processing

Unit

Memory

Unit

IS DS

IS

IS – Instruction Stream

DS – Data Stream

SIMD Processors

Control

Unit

Processing

Unit

Memory

Unit

IS

DS

IS Processing

Unit

Memory

Unit

DS

Processing

Unit

Memory

Unit

DS

DS

DS

DS

MISD Processors

Control

Unit

Processing

Unit

Memory

Unit

IS

DS

DS

ISControl

Unit

Processing

Unit

IS

DS

ISControl

Unit

Processing

Unit

IS

DS

IS

MIMD Processors

Control

Unit

Processing

Unit

Memory

Unit

IS DS

IS

Control

Unit

Processing

Unit

IS DS

IS

Control

Unit

Processing

Unit

IS DS

IS

MIMD Parallel Processors

Parallel Processors

SIMD MIMD

Shared Memory Message Passing

MISD

Classic MP MIMD Architectures

• Shared Memory– More natural transition from uniprocessors

– Easier on data partitioning & load balancing

– UMA, NUMA, COMA (Cache-only)

– Tightly coupled

• Message Passing– Scalable beyond shared-memory

– Loosely coupled – message passing for IPC

Symmetric v/s Asymmetric MPs

• Asymmetric– Master/slave configuration– Master monitors status & assigns work to slaves

– Slaves are a pool of resources to the master

– Master can be a bottleneck

• Symmetric– All processors are autonomous – treated equal– One copy of the kernel executed concurrently across

all processors

– Synchronized access to shared data structures• Multithreaded kernel

SMP Classification

Parallel Processors

SIMD MIMD


UMA NUMA COMA

MISD

UMA – Uniform Memory Architecture

P1 P2 Pn

Interconnect Network

(bus, xbar etc.)

SM1 SM2 SMn IO

• Single address space visible to all CPUs

• Memory access latency uniform for all processors

• Interconnect network could be a bus or a crossbar or switch

• Typically 8-16 nodes

NUMA – Non-Uniform Memory Architecture

P1

Inte

rconnect

Netw

ork

(bus,

xb

ar

etc

.)

LM1

P2 LM2

Pn LMn

• Single address space visible

to all CPUs

• Remote memory access

slower than local memory

• Compilers and OS need to be

careful about data placement

• Interconnect network could be

a bus or a crossbar or switch

• Theoretically scales better

than UMA

COMA – Cache-only Memory Architecture

P1

Interconnect Network

(bus, xbar etc.)

C1

D1

P2

C2

D2

Pn

Cn

Dn

• Single address space visible to all CPUs

• If collective cache size is big enough – dispense with main memory

• Memory access latency is not uniform

Cache coherency Problem

010Proc1 stores 0 to X3

111Proc2 reads X2

11Proc1 reads X1

10

Memlocation X

Proc2 cache

Proc1 cache

EventTime

Coherence v/s Consistency

• Coherence– What values are returned by a read operation

• Consistency– When will a written value be returned by a read

A memory system is coherent if a read of an item returns the most recently written value of that item. The system behaves as if there were no caches.

UMA MP Classification

Parallel Processors

SIMD MIMD


UMA NUMA COMA

Snoopy Directory based

MISD

Coherence Protocols

• Directory Based

– Sharing information about a cache block is kept in just

one location – the directory in main memory

– Requests sent only to relevant processors

• Snooping Based

– No centralized state information. Individual caches

keep sharing information on their cache blocks.

– Bandwidth hungry – doesn’t scale well

Snooping Protocol Types

Parallel Processors

SIMD MIMD


UMA NUMA COMA


Write-Invalidate Write-Update

MISD

Snooping Protocols

• Write Invalidate– On a write, all cached copies of the cache

block are invalidated except that of the writing processor.

– Writing Processor gains exclusive access to the cache block.

• Write Update (Write Broadcast)– All cached copies of the block are updated

when any processor writes to a location.

Coherence – Invalidation Protocol

000Cache miss for cache2Proc2 reads X

00Invalidation cycle for XProc1 writes 0 to X



1

Memlocation X

Proc2 cache

Proc1 cache

Bus activityProcessor activity

Invalidation Protocol – cache miss

• On a P1 cache miss, the required block may be

in another cache (P2) rather than memory

• P2 cancels P1’s read.

• P2 supplies the cache block to P1

• The cache block is also written to memory at the

same time.

Coherence – Update Protocol

000Cache hit for cache2Proc2 reads X

000Write broadcast for XProc1 writes 0 to X



1

Memlocation X

Proc2 cache

Proc1 cache

Bus activityProcessor activity

Coherence – Invalidate v/s Update

• Multiple writes to the same word without an

intermediate read

– Invalidate : Only one invalidate cycle

– Update : Multiple update cycles

• Multiword cache blocks

– Invalidate : Only first write to any word within the

cache block generates invalidate cycle

– Update : All writes to any word within cache block

generate update cycles

Common Snoop Protocols

Parallel Processors

SIMD MIMD


UMA NUMA COMA


Write-Invalidate Write-Update

MSI MESI MEI MOESI

MISD

Mainstream Processor Examples

• PowerPC755 : MEI protocol

• Pentium class: MESI protocol

• UltraSPARC: MOESI protocol

• AMD64 class: MOESI protocol

MESI Coherence Protocol

Block is invalid in this cache. It is not resident in this cache.I (Invalid)

Block is valid in this cache and at least one other cache. It is

consistent w.r.t. the main memory. Shared blocks are never

dirty.

S (Shared)

Block is valid in this cache only. It is also consistent w.r.t the

main memory – it is not dirty. This state may also be referred

to as Clean-Exclusive.

E (Exclusive)

Block is valid in this cache and only this cache. The block is

modified w.r.t. the main memory – it is dirty and has not been

written back. This state may also be referred to as Dirty-

Exclusive.

M (Modified)

DescriptionMESI States

MESI States contd.

Valid data

Cache A

MInvld data

Cache B

I

Invld data

Memory

Valid data

Cache A

EInvld data

Cache B

I

Valid data

Memory

Valid data

Cache A

SValid data

Cache B

S

Invld data

Memory

Invld data

Cache A

IDont care

Cache B

Dont care

Memory

MESI State changes

• Cache blocks change state on memory access events

• Event may be– Due to local processor activity

– Due to bus activity – snooping

• Each cache block changes its state only if its address matches the event address

MESI State transitions

• Modified/Exclusive/Shared/Invalid

• Upon loading, a line is marked E, subsequent read OK, write marks M

• If another's load is seen, mark S

• Write to an S, send I to all, mark M

• If another reads an M line, write it back, mark it S

• Read/write to an I misses

MESI State Diagram

RH = Read Hit

RMS = Read Miss, Shared

RME = Read Miss, Exclusive

WH = Write Hit

WM = Write Miss

SHR = Snoop Hit, Read Operation

SHW = Snoop Hit, Write Operation

MESI – Local Read Hit

• Line must be in one of MES

• This must be correct local value (if M it must have been modified locally)

• Simply return value

• No state change

MESI Local Read Miss (1)

• No other copy in caches– Processor makes bus request to memory

– Value read to local cache, marked E

• One cache has E copy– Processor makes bus request to memory

– Snooping cache puts copy value on the bus

– Memory access is abandoned

– Local processor caches value

– Both lines set to S


• Several caches have S copy

– Processor makes bus request to memory

– One cache puts copy value on the bus

(arbitrated)



– Local copy set to S

– Other copies remain S


• One cache has M copy

– Processor makes bus request to memory

– Snooping cache puts copy value on the bus



– Local copy tagged S

– Source (M) value copied back to memory

– Source value M -> S

MESI Local Write Hit (1)

Line must be one of MES

• M– line is exclusive and already ‘dirty’

– Update local cache value

– no state change

• E– Update local cache value

– State E -> M

MESI Local Write Hit (2)

• S

– Processor broadcasts an invalidate on bus

– Snooping processors with S copy change S->I

– Local cache value is updated

– Local state change S->M

MESI Local Write Miss (1)

Detailed action depends on copies in other processors

• No other copies

– Value read from memory to local cache

– Value updated

– Local copy state set to M


• Other copies, either one in state E or more in state S

– Value read from memory to local cache - bus

transaction marked RWITM (read with intent

to modify)

– Snooping processors see this and set their

copy state to I

– Local copy updated & state set to M


Another copy in state M

• Processor issues bus transaction marked RWITM

• Snooping processor sees this– Blocks RWITM request

– Takes control of bus

– Writes back its copy to memory

– Sets its copy state to I


Another copy in state M (continued)

• Original local processor re-issues RWITM request

• Is now simple no-copy case

– Value read from memory to local cache

– Local copy value updated

– Local copy state set to M

MOESI Protocol

• MESI does not distinguish between Shared-Clean and Shared-Modified

• MOESI adds an Owned (O) state to signify Shared-Modified while the S state gets redefined as Shared-Clean

• Caches with O state update each others blocks but do not write back to main memory

Memory consistency problem

• Processes running on different processors

• A and B cached in both processors with initial value of 0

• If memory always consistent – impossible for both L1 and L2 to be TRUE

• What if write invalidates have some delay?

• Possible that both P1 and P2 have not seen invalidations for A & B

• How consistent a picture of memory must both processors see?

P1: A = 0;

……

A = 1;

L1: if (B == 0)

.…..

P2: B = 0;

……

B = 1;

L2: if (A == 0)

.…..

Another Memory Consistency Example

P1: A = data1;

……

B = data2;

flag = 1

.…..

P2: while (flag==0) ;

……

varA = A;

varB = B;

……

• Processes running on different processors

• Flag is cached in both processors with initial value of 0

• Expectation is that P2 will see data1 and data2 for A and B respectively after it gets through the wait loop on flag

Memory Consistency Models

Strict ConsistencyRead always see the value of last write

Sequential ConsistencyInterleaving of different processors in

strict program order

Processor ConsistencyEach Processor’s writes in program order but

different processors’ writes may not be

Weak ConsistencyUse of explict synchronization instructions

to enforce sequential consistency

Release Consistency

Weak consistency with two sync operators

Release and Acquire

Sequential consistency

• Result of any execution is the same as if– The accesses of each processor were kept in order and

– The accesses among different processors were arbitrarily interleaved

• Implies that a processor delay any memory access till all invalidations required by previous writes are completed

• Presents a simple programming paradigm

• Reduces potential performance– Speculative execution w/ repair is a problem

– Write buffers are potential problems

– Reordered memory operations is another issue

Weak (Relaxed) consistency

• Observation : Sequential consistency not always needed in MPs.

• A special “barrier” or “fence” instruction explicitly serializes memory operations when it matters– Stop all instructions from executing till all previous ones have

completed– Empty write buffers into memory

• Potentially higher performance but the burden of synchronization shifted to the programmer

• Used in IA-32 architecture





1

Orientation

A.Amalin Prince



Objective : Orientation

2

03-08-07



Instructor-in-charge:

Mr. A.AMALIN PRINCE



Team of Instructors:

Prof. Jagmohan Singh

Dr.Iven Jose

Mr.M.T.Abhilash

Mr.D.B.Singh

Mr.Abhihjeet Khadke

Ms.Sushmita Wils.K

Mr.Nitin Sharma

Mrs.Chaya Devi



Consultation Hours

10.00 to 11.00TuesdayChaya Devi

10.00 to 11.00SaturdayAbhihjeet Khadke

10.00 to 11.00SaturdayD.B.Singh

12.00 to 01.00WednesdayJagmohan Singh

10.00 to 11.00MondayNitin Sharma

10.00 to11.00TuesdayIven Jose

04.00 to 05.00ThursdaySushmita Wils.K

11.00 to 12.00TuesdayM.T.Abhilash

11.00 to 12.00ThursdayA.Amalin Prince

TimeDayInstructor



Course Description:

This course covers the topics on logic circuits

and minimization, Combinational and

sequential logic circuits, Programmable Logic

devices, State table and state diagrams,

Digital ICs, Arithmetic operations and

algorithms, Introduction to Computer

organization, Algorithmic State Machines and

Verilog HDL.



Scope and Objective:

The objective of the course is to impart

knowledge of the basic tools for the design of

digital circuits and to provide methods and

procedures suitable for a variety of digital

design applications. The course also

introduces fundamental concepts of computer

organization. The course also provides

laboratory practice using MSI devices, Xilinx

ISE software tools and FPGA



Text Books



T1:

M.Moris Mano,

“ Digital Design”, PHI, 3rd Edition,

2002



T2:

G Raghurama, TSB Sudharshan , “ Introduction to Computer Organization”, EDD notes 1997



T3: Laboratory References

Digital Electronics and

Computer Organization

course team , “Laboratory

Manual”, EDD notes BITS-

Pilani Goa Campus 2007.

Data Books available in the laboratory



R1:

Palnitkar.S ,

“Verilog HDL”

Pearson Education Pvt.

Ltd., 2004



R2:

Donald D. Givone ,

“Digital Principles and

Design” TMH, 2003



R3:

Robert K.Dueck ,

“Digital Design

with CPLD

Applications and

VHDL” ,

Thomson, 2002.



Course Plan:

4.7 to 4.10Comparators, Decoders, Encoders,

MUXs, DEMUXs

MSI Components10-11

4.1 - 4-6Adders, Subtracters MultipliersCombinational Logic,

Arithmetic circuits

7-9

3.9Hardware Description

Language

Simulation and synthesis

basics

6

3.1 to 3.3, 3.5 to 3.8K-Maps (4,5 variables),

QM Method

Simplification of Boolean

functions

3-5

1.2-7, 2.4-2.8; Boolean functions Canonical forms,

number systems and codes

Boolean algebra and logic

gates, Codes number systems

2.

1.1; 1.9; 2.3, 10.1,2Digital Systems, Digital ICs Introduction to Digital

Systems and Characteristics

of Digital ICs.

1

Reference to Text

Book

Topics to be covered Learning ObjectivesLect.

No.



6.1 to 6.5Shift registers, Synchronous &

Asynchronous counters

Registers & Counters23-24

5.4, 5.6Analysis of clocked sequential

circuits, state diagram and

reduction

Clocked Sequential

Circuits

21-22

5.1 to 5.3Flip-Flops & Characteristic

tables, Latches.

Sequential Logic19-20

7.1, 7.5 to 7.7RAM, ROM, PLA, PALMemory and PLDs16-18

10.3, 10.5, 10.7 to

10.10

TTL, MOS Logic families and

their characteristics

Digital Integrated Circuits13-15

4.11HDL for Combinational LogicSimulation of

Combinational Logic

Functions.

12

Reference to Text Book

Topics to be coveredLearning Objectives Lect. No.



T2: Ch 6Memory Hierarchy & different

types of memories

Memory Organization39-40

9.1 – 9.7Asynchronous Sequential LogicDesign of Asynchronous

Circuits.

35-38

R2. Chapter 8Algorithmic State MachinesDesign of Digital Systems32-34

8.1,8.2, 8.4 to 8.7RTL, HDL descriptionModular approach for CPU

Design

28-31

T2: Appendix AMultiplication & Division

algorithms

Analysis of arithmetic

units

26-27

5.5, 6.6HDL for Sequential Logic, HDL

for registers and counters

Simulation of Sequential

Logic Functions.

25

Reference to Text

Book

Topics to be coveredLearning Objectives Lect.

No.



Evaluation Scheme:

CBTo be announced40To be announcedLab test & Viva

OBRegularly40_____Practicals:

Regularity, Lab reports

& Assignment

CB01-12-07 (AN)1203 HrsComprehensive

Examination

OB01-11-07 5060 MinTest II

CB20-09-07 5060 MinTest I

RemarksDateMaximum

Marks

DurationComponent



Practical (From T3)

Implementation Of Mealy And Moore Machine In FPGA12.

Sequential Circuits11. IV

Shift Registers10.

Implementation Of Sequential Logic In FPGA9.

Operation Of 4 – Bit Counter8.III

Latches & Flip-flops7.

Implementation Of Combinational Logic In FPGA6.

Comparators & Arithmetic Logic Unit 5. II

Decoders, Multiplexers And Encoders 4.

Adders And Subtractors3.

Implementation Of Boolean Functions Using Logic Gates2. I

Familiarization Of Bench Equipments1.

CycleName of the experimentEx. No:



Assignment: To be announced in the class Notices: will be displayed on FTP & EEE/INSTR

notice board Only

Make-up Policy:-Prior Permission of the Instructor-in-Charge is required to take a make-up for a test/lab. - Make-up applications must be given to the Instructor-in-charge personally.- A make-up test/lab shall be granted only in genuine cases where - in the Instructor’s judgment -the student would be physically unable to appear for the test.



How to get good Score???



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