altera ciclon 2

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Preliminary Information101 Innovation DriveSan Jose, CA 95134(408) 544-7000http://www.altera.com

Cyclone Device Handbook, Volume 2

C5V2-1.0
http://www.altera.com/http://www.altera.com/http://www.altera.com/http://www.altera.com/http://www.altera.com/


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Copyright 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks andservice marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al-tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrantsperformance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to makechanges to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap-plication or use of any information, product, or service described herein except as expressly agreed to in writing by AlteraCorporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in-formation and before placing orders for products or services .

Printed on recycled paper

ii Altera CorporationPreliminary


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Altera Corporation iii

Contents

Chapter Revision Dates ........................................................................... v

About this Handbook ............................................................................. xiiiHow to Find Information ..................................................................................................................... xiiiHow to Contact Altera .......................................................................................................................... xiiiTypographic Conventions ........................................................................................................ ............ xiv

Part I. PCB Layout GuidelinesRevision History ............................................................................................................................ Part I1

Chapter 1. Cyclone EP1C3T100 Device Pin InformationIntroduction ................................................................................................................... ......................... 11Pin List .....................................................................................................................................................12Pin Definitions ................................................................................................................ ........................17PLL & Bank Diagram ............................................................................................................. ............. 110

Chapter 2. Cyclone EP1C3T144 Device Pin InformationIntroduction ................................................................................................................... ......................... 21Pin List .....................................................................................................................................................22Pin Definitions ................................................................................................................ ........................29PLL & Bank Diagram ............................................................................................................. ............. 213

Chapter 3. Cyclone EP1C6 Device Pin InformationIntroduction ................................................................................................................... ......................... 31Pin List .....................................................................................................................................................32Pin Definitions ................................................................................................................ ......................316PLL & Bank Diagram ............................................................................................................. ............. 320

Chapter 4. Cyclone EP1C12 Device Pin InformationIntroduction ................................................................................................................... ......................... 41Pin List .....................................................................................................................................................42Pin Definitions ................................................................................................................ ......................420PLL & Bank Diagram ............................................................................................................. ............. 424

Chapter 5. Cyclone EP1C20 Device Pin InformationIntroduction ................................................................................................................... ......................... 51Pin List .....................................................................................................................................................52


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iv Altera Corporation


Pin Definitions ................................................................................................................ ......................522PLL & Bank Diagram ............................................................................................................. ............. 526

Chapter 6. Package Information for Cyclone DevicesIntroduction ................................................................................................................... ......................... 61

Device & Package Cross Reference ..................................................................................................... 61Thermal Resistance ............................................................................................................. ................... 62Package Outlines ............................................................................................................... .................... 62

100-Pin Plastic Thin Quad Flat Pack (TQFP) ................................................................................ 63144-Pin Plastic Thin Quad Flat Pack (TQFP) ................................................................................ 65240-Pin Plastic Quad Flat Pack (PQFP) ......................................................................................... 67256-Pin Non-Thermally Enhanced FineLine Ball-Grid Array ................................................... 69324-Pin Non-Thermally Enhanced FineLine Ball-Grid Array ................................................. 611400-Pin Non-Thermally Enhanced FineLine Ball-Grid Array ................................................. 613

Chapter 7. Designing with FineLine BGA Packages

Introduction ................................................................................................................... ......................... 71Overview of BGA Packages ................................................................................................................. 71PCB Layout Terminology ......................................................................................................... ............ 72

Escape Routing ................................................................................................................. ................72Multi-Layer PCBs ............................................................................................................... ..............72Vias .....................................................................................................................................................72Via Capture Pad ................................................................................................................ ............... 74Surface Land Pad ............................................................................................................... ............... 74Stringer ...............................................................................................................................................75

PCB Layout for FineLine BGA Packages ........................................................................................... 76Surface Land Pad Dimension ..................................................................................................... .... 76Via Capture Pad Layout & Dimension ......................................................................................... 77Signal Line Space & Trace Width ................................................................................................. 710Number of PCB Layers .................................................................................................................. 711

Conclusion ............................................................................................................................................ 712


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Altera Corporation vPreliminary

Chapter Revision Dates

The chapters in this book, Cyclone Device Handbook, Volume 2, were revised on the following dates.Where chapters or groups of chapters are available separately, part numbers are listed.

Chapter 1. Cyclone EP1C3T100 Device Pin InformationRevised: May 2003Part number: C52001-1.0

Chapter 2. Cyclone EP1C3T144 Device Pin InformationRevised: May 2003Part number: C52002-1.0

Chapter 3. Cyclone EP1C6 Device Pin InformationRevised: May 2003Part number: C52003-1.0

Chapter 4. Cyclone EP1C12 Device Pin InformationRevised: May 2003Part number: C52004-1.0

Chapter 5. Cyclone EP1C20 Device Pin InformationRevised: May 2003

Part number: C52005-1.0

Chapter 6. Package Information for Cyclone DevicesRevised: May 2003Part number: C52006-1.0

Chapter 7. Designing with FineLine BGA PackagesRevised: May 2003Part number: C52007-1.0
http://../datasheets/stratix/dsstratix_intro.pdfhttp://../datasheets/stratix/dsstratix_intro.pdfhttp://../datasheets/stratix/dsstratix_intro.pdfhttp://../datasheets/stratix/dsstratix_intro.pdf


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vi Altera CorporationPreliminary



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Altera Corporation xiiiPreliminary

About this Handbook

This handbook provides comprehensive information about the Altera Cyclone family of devices.

How to FindInformation

You can find more information in the following ways:

The Adobe Acrobat Find feature, which searches the text of a PDFdocument. Click the binoculars toolbar icon to open the Find dialog box.

Acrobat bookmarks, which serve as an additional table of contents inPDF documents.

Thumbnail icons, which provide miniature previews of each page,provide a link to the pages.

Numerous links, shown in green text, which allow you to jump torelated information.

How to Contact

Altera

For the most up-to-date information about Altera products, go to theAltera world-wide web site at www.altera.com . For technical support on

this product, go to www.altera.com/mysupport . For additionalinformation about Altera products, consult the sources shown below.

Information Type USA & Canada All Other Locations

Technical support www.altera.com/mysupport/ altera.com/mysupport/

(800) 800-EPLD (3753)(7:00 a.m. to 5:00 p.m. Pacific Time)

(408) 544-7000 (1) (7:00 a.m. to 5:00 p.m. Pacific Time)

Product literature www.altera.com www.altera.com

Altera literature services [email protected] (1) [email protected] (1)

Non-technical customerservice

(800) 767-3753 (408) 544-7000(7:30 a.m. to 5:30 p.m. Pacific Time)

FTP site ftp.altera.com ftp.altera.com

Note to table:(1) You can also contact your local Altera sales office or sales representative.
http://www.altera.com/mysupporthttp://www.altera.com/mysupport/http://www.altera.com/mysupport/http://www.altera.com/http://www.altera.com/mailto:[email protected]:[email protected]://ftp.altera.com/ftp://ftp.altera.com/ftp://ftp.altera.com/http://www.altera.com/mysupportftp://ftp.altera.com/ftp://ftp.altera.com/mailto:[email protected]:[email protected]://www.altera.com/http://www.altera.com/http://www.altera.com/mysupport/http://www.altera.com/mysupport/


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xiv Altera CorporationPreliminary


TypographicConventions

This document uses the typographic conventions shown below.

Visual Cue Meaning

Bold Type with InitialCapital Letters

Command names, dialog box titles, checkbox options, and dialog box options areshown in bold, initial capital letters. Example: Save As dialog box.

bold type External timing parameters, directory names, project names, disk drive names,filenames, filename extensions, and software utility names are shown in boldtype. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.

Italic Type with Initial CapitalLetters

Document titles are shown in italic type with initial capital letters. Example: AN75: High-Speed Board Design.

Italic type Internal timing parameters and variables are shown in italic type.Examples: t PIA, n + 1.

Variable names are enclosed in angle brackets (< >) and shown in italic type.Example: , .pof file.

Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples:Delete key, the Options menu.

Subheading Title References to sections within a document and titles of on-line help topics areshown in quotation marks. Example: Typographic Conventions.

Courier type Signal and port names are shown in lowercase Courier type. Examples: data1 ,tdi , input. Active-low signals are denoted by suffix n , e.g., resetn .

Anything that must be typed exactly as it appears is shown in Courier type. Forexample: c:\qdesigns\tutorial\chiptrip.gdf . Also, sections of anactual file, such as a Report File, references to parts of files (e.g., the AHDLkeyword SUBDESIGN ), as well as logic function names (e.g., TRI ) are shown inCourier.

1., 2., 3., anda., b., c., etc.

Numbered steps are used in a list of items when the sequence of the items isimportant, such as the steps listed in a procedure.

Bullets are used in a list of items when the sequence of the items is not important.

v The checkmark indicates a procedure that consists of one step only.

1 The hand points to information that requires special attention.

r The angled arrow indicates you should press the Enter key.

f The feet direct you to more information on a particular topic.


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Altera Corporation Section I1Preliminary

Section I. PCB LayoutGuidelines

This section provides information for board layout designers tosuccessfully layout their boards for Cyclone devices. It contains therequired PCB layout guidelines, device pin tables, and packagespecifications.

This section includes the following chapters:

Chapter 1. Cyclone EP1C3T100 Device Pin Information

Chapter 2. Cyclone EP1C3T144 Device Pin Information

Chapter 3. Cyclone EP1C6 Device Pin Information



Chapter 6. Package Information for Cyclone Devices

Chapter 7. Designing with FineLine BGA Packages

Revision History The table below shows the revision history for Chapter 7 .

Chapter(s) Date / Version Changes Made

12 May 2003v1.0

Updated Table 76 .

v1.03 Updated the PCB Layout for FineLine BGAPackages section and Table 76 .

v1.02 Minor updates.

v1.01 Updated Table 76 .


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Altera Corporation 11May 2003 Preliminary

1. Cyclone EP1C3T100Device Pin Information

Introduction The following tables contain pin information for the Cyclone EP1C3T100device, organized into the following sections:

Section Page

Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17PLL & Bank Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

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Pin List Table 11 shows the complete pin list for the Cyclone EP1C3T100 device:

Table 11. Pin List for the Cyclone EP1C3T100 Device (Part 1 of 5)

Device Pack

Pin Name /Function

OptionalFunction(s)

ConfigurationFunction Bank Number VREF Bank

100-Pin TFlat

IO INIT_DONE B1 VREF0B1 1

IO B1 VREF0B1 2

IO CLKUSR B1 VREF0B1 3

IO VREF0B1 B1 VREF0B1 4

VCCIO1 B1 VREF0B1

GND B1 VREF0B1


IO nCSO B1 VREF1B1 6

DATA0 DATA0 B1 VREF1B1 7

nCONFIG nCONFIG B1 VREF1B1 8

VCCA_PLL1 VREF1B1 9

CLK0 B1 VREF1B1 10

GNDA_PLL1 VREF1B1 11

nCEO nCEO B1 VREF1B1 12

nCE nCE B1 VREF1B1 13

MSEL0 MSEL0 B1 VREF1B1 14


DCLK DCLK B1 VREF1B1 16

IO ASDO B1 VREF1B1 17

VCCIO1 B1 VREF2B1 18

GND B1 VREF2B1 19


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IO B1 VREF2B1 21

IO B1 VREF2B1 22

IO B1 VREF2B1 23

IO B1 VREF2B1 24

IO B1 VREF2B1 25

IO B4 VREF2B4 26

IO B4 VREF2B4 27

IO B4 VREF2B4 28

IO B4 VREF2B4 29

GND B4 VREF2B4 30


GND VREF2B4 32

VCCINT VREF2B4 33

IO DPCLK7 B4 VREF2B4 34


IO B4 VREF2B4 36

IO B4 VREF1B4 37


IO B4 VREF1B4 39

IO B4 VREF1B4 40




Device Pack

Pin Name /Function

OptionalFunction(s)


100-Pin TFlat


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GND VREF0B4 43

VCCINT VREF0B4 44

GND B4 VREF0B4 45


IO B4 VREF0B4 47

IO B4 VREF0B4 48

IO B4 VREF0B4 49

IO B4 VREF0B4 50

IO B3 VREF2B3 51

IO B3 VREF2B3 52

IO B3 VREF2B3 53

IO B3 VREF2B3 54

IO B3 VREF2B3 55

IO B3 VREF2B3 56


GND B3 VREF2B3 58


CONF_DONE CONF_DONE B3 VREF1B3 60

nSTATUS nSTATUS B3 VREF1B3 61

TCK TCK B3 VREF1B3 62

TMS TMS B3 VREF1B3 63

TDO TDO B3 VREF1B3 64

IO B3 VREF1B3 65


Device Pack

Pin Name /Function

OptionalFunction(s)


100-Pin TFlat


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CLK2 B3 VREF1B3 66

TDI TDI B3 VREF1B3 67


IO B3 VREF0B3 69

IO B3 VREF0B3 70

IO B3 VREF0B3 71


GND B3 VREF0B3

VCCIO3 B3 VREF0B3


IO B3 VREF0B3 74

IO B3 VREF0B3 75

IO B2 VREF0B2 76

IO B2 VREF0B2 77

IO B2 VREF0B2 78

IO B2 VREF0B2 79


GND B2 VREF0B2 81

VCCINT VREF0B2 82

GND VREF0B2 83



IO B2 VREF1B2 86


Device Pack

Pin Name /Function

OptionalFunction(s)


100-Pin TFlat


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IO B2 VREF1B2 87


IO B2 VREF1B2 89

IO B2 VREF2B2 90



VCCINT VREF2B2 93

GND VREF2B2 94


GND B2 VREF2B2 96

IO B2 VREF2B2 97

IO B2 VREF2B2 98

IO DEV_OE B2 VREF2B2 99

IO DEV_CLRn B2 VREF2B2 100


Device Pack

Pin Name /Function

OptionalFunction(s)


100-Pin TFlat


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Pin Definitions Table 12 shows pin definitions for the EP1C3T100 device.

Table 12. Pin Definitions for the Cyclone EP1C3T100 Device (Part 1 of 3)

Pin Name Pin Type (1st, 2nd, & 3rd

Function)Pin Description

Supply and Reference Pins

VCCIO[1..4] Power These are I/O supply voltage pins for banks 1 through 4. Eachdifferent voltage level. VCCIO supplies power to the outpustandards. VCCIO also supplies power to the input buffers LVCMOS, 1.5-V, 1.8-V, 2.5-V, and 3.3-V PCI I/O standards

VCCINT Power These are internal logic array voltage supply pins. VCCINT athe input buffers used for the LVDS, SSTL2, and SSTL3 I/

VREF[0..2]B[1..4] I/O, Input Input reference voltage for banks 1-4. If a bank uses a voltagestandard, then these pins are used as the voltage-reference pvoltage reference I/O standards are not used in the bank, thavailable as user I/O pins.

VCCA_PLL[1..2] Power Analog power for PLLs[1..2]. The designer must connect thisthe PLL is not used.

GNDA_PLL[1..2] Ground Analog ground for PLLs[1..2]. The designer can connect thison the board.

Configuration and JTAG Pins

CONF_DONE Bidirectional (open-drain) This is a dedicated configuration status pin; it is not available a

nSTATUS Bidirectional (open-drain) This is a dedicated configuration status pin; it is not available a

nCONFIG Input Dedicated configuration control input. A low transition reset

low-to-high transition begins configuration. All I/O pins tridriven low.

DCLK Input (PS mode), Output(AS mode)

In passive serial configuration mode, DCLK is a clock inpuconfiguration data from an external source into the Cycloneconfiguration mode, DCLK is a clock output from the Cycldevice acts as master in this mode). This is a dedicated pin

DATA0 Input Dedicated configuration data input pin.


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nCE Input Active-low chip enable. Dedicated chip enable input used toactive in a chain of devices. When nCE is low, the device is high, the device is disabled.

nCEO Output Output that drives low when device configuration is completconfiguration, this pin feeds a subsequent devices nCE pin

ASDO I/O, Output Active serial data output from the Cyclone device. This outpuactive serial configuration mode. The Cyclone device contrdrives address and control information out on ASDO. In paconfiguration, this pin is available as a user I/O pin.

nCSO I/O, Output Chip select output that enables/disables a serial configurationis utilized during active serial configuration mode. The Cyconfiguration and enables the serial configuration device bpassive serial configuration, this pin is available as a user I/

INIT_DONE I/O, Output (open-drain) This is a dual-purpose pin and can be used as an I/O pin whenINIT_DONE. When enabled, the pin indicates when the demode. This pin can be used as a user I/O pin after configur

CLKUSR I/O, Input Optional user-supplied clock input. Synchronizes the initialidevices. This pin can be used as a user I/O pin after configu

DEV_CLRn I/O, Input Dual-purpose pin that can override all clears on all device regis driven low, all registers are cleared; when this pin is drivbehave as defined in the design.

DEV_OE I/O, Input Dual-purpose pin that can override all tri-states on the devicedriven low, all I/O pins are tri-stated; when this pin is driven as defined in the design.

MSEL[1..0] Input Dedicated mode select control pins that set the configuration

TMS Input This is a dedicated JTAG input pin.

TDI Input This is a dedicated JTAG input pin.

TCK Input This is a dedicated JTAG input pin.

TDO Output This is a dedicated JTAG output pin.


Pin Name Pin Type (1st, 2nd, & 3rdFunction) Pin Description


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Clock and PLL Pins

CLK0 Input Dedicated global clock input. The dual-function of CLK0 isused for differential input to PLL1.

CLK2 Input Dedicated global clock input. The dual-function of CLK2 isused for differential input to PLL2.

DPCLK[7..0] I/O Dual-purpose clock pins that can connect to the global clockcan be used for high fan-out control signals, such as clocks, or DQS signals. These pins are also available as user I/O p

Dual-Purpose External Memory Interface Pins

DQS[0..1][L,R,T,B] I/O Optional data strobe signal for use in external memory interfafunction as DPCLK pins; therefore, the DQS signals can con

network. A programmable delay chain is used to shift the Ddegrees.

DQ[0..7][L,R,T,B] I/O Optional data signal for use in external memory interfacing.

DM[0..1][L,R,T,B] I/O Optional data mask output signal for use in external memor




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PLL & BankDiagram

Figure 11 shows the PLL and Bank locations for the EP1C3T100 device.

Figure 11. PLL and Bank Diagram (1) , (2)

Notes for Figure 11 :(1) This is a top view of the silicon die.

(2) This is a pictoral representation only to get an idea of placement on the device. Refer to the pin-list and

V R E B 2 B 3

B4VREF2B4 VREF1B4 VREF0B4

B 3

V R E F 0 B 3

V R E F 1 B 3

VREF2B2 VREF1B2 VREF0B2

B2

V R E F 0 B 1

B 1

V R E F 1 B 1

PLL1

V R E B 2 B 1


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2. Cyclone EP1C3T144Device Pin Information

Introduction The following tables contain pin information for the Cyclone EP1C3T144device, organized into the following sections:

Section Page

Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29PLL & Bank Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

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Pin List Table 21 shows the complete pin list for the Cyclone EP1C3T144 device:


Device Pack

Pin Name/Function

OptionalFunction(s)


144-Pin TFlat

IO LVDS4p INIT_DONE B1 VREF0B1 1

IO LVDS4n B1 VREF0B1 2

IO LVDS3p CLKUSR B1 VREF0B1 3



IO LVDS2p B1 VREF0B1 6


VCCIO1 B1 VREF0B1 8

GND B1 VREF0B1 9



IO nCSO B1 VREF1B1 12

DATA0 DATA0 B1 VREF1B1 13

nCONFIG nCONFIG B1 VREF1B1 14

VCCA_PLL1 VREF1B1 15

CLK0 LVDSCLK1p B1 VREF1B1 16

CLK1 LVDSCLK1n B1 VREF1B1 17

GNDA_PLL1 VREF1B1 18

GNDG_PLL1 VREF1B1 19

nCEO nCEO B1 VREF1B1 20

nCE nCE B1 VREF1B1 21


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DCLK DCLK B1 VREF1B1 24

IO ASDO B1 VREF1B1 25

IO PLL1_OUTp B1 VREF1B1 26

IO PLL1_OUTn B1 VREF1B1 27



GND B1 VREF2B1 30


IO B1 VREF2B1 32











GND B4 VREF2B4 43



Device Pack

Pin Name/Function

OptionalFunction(s)


144-Pin TFlat


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GND VREF2B4 45

VCCINT VREF2B4 46



IO B4 VREF2B4 49














GND VREF0B4 63

VCCINT VREF0B4 64

GND B4 VREF0B4 65




Device Pack

Pin Name/Function

OptionalFunction(s)


144-Pin TFlat


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GND B3 VREF2B3 80





IO B3 VREF2B3 85

CONF_DONE CONF_DONE B3 VREF1B3 86

nSTATUS nSTATUS B3 VREF1B3 87

TCK TCK B3 VREF1B3 88

TMS TMS B3 VREF1B3 89

TDO TDO B3 VREF1B3 90


Device Pack

Pin Name/Function

OptionalFunction(s)


144-Pin TFlat


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IO B3 VREF1B3 91

CLK3 LVDSCLK2n B3 VREF1B3 92

CLK2 LVDSCLK2p B3 VREF1B3 93

IO B3 VREF1B3 94

TDI TDI B3 VREF1B3 95


IO B3 VREF0B3 97




GND B3 VREF0B3 101


IO B3 VREF0B3 103












Device Pack

Pin Name/Function

OptionalFunction(s)


144-Pin TFlat


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GND B2 VREF0B2 116

VCCINT VREF0B2 117

GND VREF0B2 118














IO B2 VREF2B2 132



VCCINT VREF2B2 135

GND VREF2B2 136


Device Pack

Pin Name/Function

OptionalFunction(s)


144-Pin TFlat


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GND B2 VREF2B2 138





IO LVDS5n DEV_OE B2 VREF2B2 143

IO LVDS5p DEV_CLRn B2 VREF2B2 144


Device Pack

Pin Name/Function

OptionalFunction(s)


144-Pin TFlat


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Pin Definitions Table 22 shows pin definitions for the EP1C3T144 device.

Table 22. Pin Definitions for the EP1C3T144 Device (Part 1 of 4)

Pin Name Pin Type (1st, 2nd, & 3rd

Function)Pin Description


VCCIO[1..4] Power These are I/O supply voltage pins for banks 1 through 4. Each bankdifferent voltage level. VCCIO supplies power to the output buffeVCCIO also supplies power to the input buffers used for the LVTTLV, 2.5-V, and 3.3-V PCI I/O standards.

VCCINT Power These are internal logic array voltage supply pins. VCCINT also suinput buffers used for the LVDS, SSTL2, and SSTL3 I/O standard

VREF[0..2]B[1..4] I/O, Input Input reference voltage for banks 1-4. If a bank uses a voltage-referethen these pins are used as the voltage-reference pins for the bankI/O standards are not used in the bank, the VREF pins are availab

VCCA_PLL[1..2] Power Analog power for PLLs[1..2]. The designer must connect this pin to is not used.

GNDA_PLL[1..2] Ground Analog ground for PLLs[1..2]. The designer can connect this pin to thboard.

GNDG_PLL[1..2] Ground Guard ring ground for PLLs[1..2]. The designer can connect this pin tthe board.


CONF_DONE Bidirectional (open-drain) This is a dedicated configuration status pin; it is not available as a user

nSTATUS Bidirectional (open-drain) This is a dedicated configuration status pin; it is not available as a use

nCONFIG Input Dedicated configuration control input. A low transition resets the tahigh transition begins configuration. All I/O pins tri-state when nC

DCLK Input (PS mode), Output (ASmode)

In passive serial configuration mode, DCLK is a clock input used data from an external source into the Cyclone device. In active seriaDCLK is a clock output from the Cyclone device (the Cyclone dethis mode). This is a dedicated pin used for configuration.


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nCE Input Active-low chip enable. Dedicated chip enable input used to detect win a chain of devices. When nCE is low, the device is enabled. Whdevice is disabled.

nCEO Output Output that drives low when device configuration is complete. Duriconfiguration, this pin feeds a subsequent devices nCE pin.

ASDO I/O, Output Active serial data output from the Cyclone device. This output pin isserial configuration mode. The Cyclone device controls configuratand control information out on ASDO. In passive serial configuratas a user I/O pin.

nCSO I/O, Output Chip select output that enables/disables a serial configuration deviceutilized during active serial configuration mode. The Cyclone deconfiguration and enables the serial configuration device by drivingserial configuration, this pin is available as a user I/O pin.

INIT_DONE I/O, Output (open-drain) This is a dual-purpose pin and can be used as an I/O pin when not enaINIT_DONE. When enabled, the pin indicates when the device haThis pin can be used as a user I/O pin after configuration.

CLKUSR I/O, Input Optional user-supplied clock input. Synchronizes the initialization ofThis pin can be used as a user I/O pin after configuration.

DEV_CLRn I/O, Input Dual-purpose pin that can override all clears on all device registers.driven low, all registers are cleared; when this pin is driven high, adefined in the design.

DEV_OE I/O, Input Dual-purpose pin that can override all tri-states on the device. Whenall I/O pins are tri-stated; when this pin is driven high, all I/O pinsthe design.

MSEL[1..0] Input Dedicated mode select control pins that set the configuration mode







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Clock and PLL PinsCLK0 Input, LVDS Input Dedicated global clock input. The dual-function of CLK0 is LVDSC

for differential input to PLL1.

CLK1 Input, LVDS Input Dedicated global clock input. The dual-function of CLK1 is LVDSCfor differential input to PLL1. The EP1C3T100 does not support t

CLK2 Input, LVDS Input Dedicated global clock input. The dual-function of CLK2 is LVDSCfor differential input to PLL2.

CLK3 Input, LVDS Input Dedicated global clock input. The dual-function of CLK3 is LVDSCfor differential input to PLL2. The EP1C3T100 does not support t

DPCLK[7..0] I/O Dual-purpose clock pins that can connect to the global clock networ

used for high fan-out control signals, such as clocks, clears, IRDY, signals. These pins are also available as user I/O pins.

PLL1_OUTp I/O, Output External clock output from PLL 1. This pin can be used with differeI/O standards. If clock output from PLL1 is not used, this pin is avaThe EP1C3T100 does not support this output pin.

PLL1_OUTn I/O, Output Negative terminal for external clock output from PLL1. If the clock othis pin is available as a user I/O pin. The EP1C3T100 does not su




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Dual-Purpose LVDS & External Memory Interface Pins

LVDS[0..33]p I/O, LVDS RX or TX Dual-purpose LVDS I/O channels 0 to 33. These channels can be ustransmitting LVDS compatible signals. Pins with a "p" suffix carrthe differential channel. If not used for LVDS interfacing, these pinI/O pins. The EP1C3T100 does not support LVDS I/O interfacin

LVDS[0..33]n I/O, LVDS RX or TX Dual-purpose LVDS I/O channels 0 to 33. These channels can be ustransmitting LVDS compatible signals. Pins with an "n" suffix carrthe differential channel. If not used for LVDS interfacing, these pinI/O pins. The EP1C3T100 does not support LVDS I/O interfacin

LVDSCLK1p Input, LVDS Input Dual-purpose LVDS clock input to PLL1. If differential input to PLpin is available as the CLK0 input pin.

LVDSCLK1n Input, LVDS Input Dual-purpose LVDS clock input to PLL1. If differential input to PL

pin is available as the CLK1 input pin. The EP1C3T100 does not LVDSCLK2p Input, LVDS Input Dual-purpose LVDS clock input to PLL2. If differential input to PL

pin is available as the CLK2 input pin.

LVDSCLK2n Input, LVDS Input Dual-purpose LVDS clock input to PLL2. If differential input to PLpin is available as the CLK3 input pin. The EP1C3T100 does not

DQS[0..1][L,R,T,B] I/O Optional data strobe signal for use in external memory interfacing.function as DPCLK pins; therefore, the DQS signals can connect network. A programmable delay chain is used to shift the DQS sigdegrees.

DQ[0..7][L,R,T,B] I/O Optional data signal for use in external memory interfacing.

DM[0..1][L,R,T,B] I/O Optional data mask output signal for use in external memory interf




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PLL & Bank Diagram

PLL & BankDiagram

Figure 21 shows the PLL and Bank locations for the EP1C3T144 device.


Notes for Figure 21 :(1) This is a top view of the silicon die.


B2

V R E F 0 B 1

B 1

V R E F 1 B 1

PLL1

V R E B 2 B 1


V R E B 2 B 3


B 3

V R E F 0 B 3

V R E F 1 B 3


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3. Cyclone EP1C6 DevicePin Information

Introduction The following tables contain pin information for the Cyclone EP1C6device, organized into the following sections:

Section Page

Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316PLL & Bank Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

C52003-1.0


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Pin List Table 31 shows the complete pin list for the device Cyclone EP1C6 device:

Table 31. Pin List for the Cyclone EP1C6 Device (Part 1 of 14)

Device Package

DQS for X8in 144-PinTQFP

Pin Name /Function

OptionalFunction(s)

ConfigurationFunction

BankNumber VREF Bank

144-Pin

TQFP

240-Pin

PQFP

256-PinFineLine BGA

IO LVDS14p INIT_DONE B1 VREF0B1 1 1 D4 DM1L

IO LVDS14n B1 VREF0B1 2 2 C3 DQ1L0

IO LVDS13p CLKUSR B1 VREF0B1 3 3 C2 DQ1L1

IO LVDS13n B1 VREF0B1 4 4 B1

IO VREF0B1 B1 VREF0B1 5 5 G5

IO B1 VREF0B1 6 6 F4 DQ1L2

IO LVDS12p B1 VREF0B1 7 7 D3 DQ1L3 D

IO LVDS12n B1 VREF0B1 8 E4 D

VCCIO1 B1 VREF0B1 8 9

GND B1 VREF0B1 9 10

IO DPCLK1 B1 VREF0B1 10 11 F5 D

IO LVDS11p B1 VREF0B1 12 E3 D

IO LVDS11n B1 VREF0B1 13 D2 D

IO LVDS10p B1 VREF0B1 14 E2

IO LVDS10n B1 VREF0B1 15 D1

IO LVDS9p B1 VREF0B1 16 F3

IO LVDS9n B1 VREF0B1 17 G3


IO LVDS8n B1 VREF0B1 19 E1

IO LVDS7p B1 VREF0B1 20 G2


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IO LVDS7n B1 VREF0B1 21 F1 D


IO VREF1B1 B1 VREF1B1 11 23 H5

IO nCSO B1 VREF1B1 12 24 G4

DATA0 DATA0 B1 VREF1B1 13 25 H2

nCONFIG nCONFIG B1 VREF1B1 14 26 H3

VCCA_PLL1 VREF1B1 15 27 H6

CLK0 LVDSCLK1p B1 VREF1B1 16 28 G1

CLK1 LVDSCLK1n B1 VREF1B1 17 29 H1GNDA_PLL1 VREF1B1 18 30 J6

GNDG_PLL1 VREF1B1 19 31 J5

nCEO nCEO B1 VREF1B1 20 32 H4

nCE nCE B1 VREF1B1 21 33 J4

MSEL0 MSEL0 B1 VREF1B1 22 34 J3

MSEL1 MSEL1 B1 VREF1B1 23 35 J2

DCLK DCLK B1 VREF1B1 24 36 K4

IO ASDO B1 VREF1B1 25 37 K3

IO PLL1_OUTp B1 VREF1B1 26 38 J1IO PLL1_OUTn B1 VREF1B1 27 39 K2

GND B1 VREF2B1 40

IO B1 VREF2B1 41 L3

IO LVDS6p B1 VREF2B1 42 K1


Device PackageDQS for X8in 144-Pin

TQFPPin Name /

FunctionOptional

Function(s)Configuration

FunctionBank

Number VREF Bank144-Pin

TQFP

240-Pin

PQFP

256-PinFineLine BGA


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IO LVDS6n B1 VREF2B1 43 L1

IO LVDS5p B1 VREF2B1 44 L2

IO LVDS5n B1 VREF2B1 45 M1

IO LVDS4p B1 VREF2B1 46 N1


IO LVDS3p B1 VREF2B1 48 N2 D


IO DPCLK0 B1 VREF2B1 28 50 L5 DQS1L

VCCIO1 B1 VREF2B1 29 51GND B1 VREF2B1 30 52

IO LVDS2p B1 VREF2B1 53 M4

IO LVDS2n B1 VREF2B1 54 N3 D

IO VREF2B1 B1 VREF2B1 31 55 K5

IO B1 VREF2B1 32 56 L4 DQ1L4

IO LVDS1p B1 VREF2B1 33 57 R1 DQ1L5

IO LVDS1n B1 VREF2B1 34 58 P2 DQ1L6

IO LVDS0p B1 VREF2B1 35 59 P3 DQ1L7

IO LVDS0n B1 VREF2B1 36 60 N4IO LVDS71p B4 VREF2B4 37 61 R2

IO LVDS71n B4 VREF2B4 38 62 T2

IO LVDS70p B4 VREF2B4 63 R3

IO LVDS70n B4 VREF2B4 64 P4



TQFPPin Name /

FunctionOptional


FunctionBank


TQFP

240-Pin

PQFP

256-PinFineLine BGA


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IO LVDS69p B4 VREF2B4 39 65 R4 DQ1B7

IO LVDS69n B4 VREF2B4 40 66 T4 DQ1B6

IO LVDS68p B4 VREF2B4 41 67 R5 DQ1B5 D

IO LVDS68n B4 VREF2B4 42 68 P5 DQ1B4 D

GND B4 VREF2B4 43 69


GND VREF2B4 45 71

VCCINT VREF2B4 46 72

IO DPCLK7 B4 VREF2B4 47 73 M5 DQS1B DIO VREF2B4 B4 VREF2B4 48 74 M6

IO LVDS67p B4 VREF2B4 49 75 N5

IO LVDS67n B4 VREF2B4 76 N6 D

IO LVDS66p B4 VREF2B4 77 P6 D

IO LVDS66n B4 VREF2B4 78 R6

IO B4 VREF2B4 79 M7

IO LVDS65p B4 VREF2B4 80 T6

IO LVDS65n B4 VREF2B4 81 R7

IO LVDS64p B4 VREF2B4 82 P7IO LVDS64n B4 VREF2B4 83 N7

IO LVDS63p B4 VREF2B4 50 84 R8


IO LVDS62p B4 VREF1B4 52 86 N8



TQFPPin Name /

FunctionOptional


FunctionBank


TQFP

240-Pin

PQFP

256-PinFineLine BGA


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IO LVDS62n B4 VREF1B4 53 87 P8

IO B4 VREF1B4 88 M8

GND VREF1B4 54 89


GND B4 VREF1B4 91


IO VREF1B4 B4 VREF1B4 56 93 M10

IO LVDS61p B4 VREF1B4 57 94 R9 DM1B D

IO LVDS61n B4 VREF1B4 58 95 T9IO LVDS60p B4 VREF1B4 96 P9

IO LVDS60n B4 VREF1B4 97 N9



IO LVDS58p B4 VREF1B4 100 N10




IO LVDS56p B4 VREF0B4 104 N11IO LVDS56n B4 VREF0B4 105 N12

IO B4 VREF0B4 60 106 M9

IO VREF0B4 B4 VREF0B4 61 107 M11

IO DPCLK6 B4 VREF0B4 62 108 M12



TQFPPin Name /

FunctionOptional


FunctionBank


TQFP

240-Pin

PQFP

256-PinFineLine BGA


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GND VREF0B4 63 109




IO LVDS55p B4 VREF0B4 67 113 P12 DQ1B3 DQ

IO LVDS55n B4 VREF0B4 68 114 R12 DQ1B2 DQ

IO LVDS54p B4 VREF0B4 69 115 T13 DQ1B1 DQ

IO LVDS54n B4 VREF0B4 70 116 R13 DQ1B0 DQ

IO LVDS53p B4 VREF0B4 117 R14IO LVDS53n B4 VREF0B4 118 P13

IO LVDS52p B4 VREF0B4 71 119 T15

IO LVDS52n B4 VREF0B4 72 120 R15

IO LVDS51n B3 VREF2B3 73 121 N13

IO LVDS51p B3 VREF2B3 74 122 P14

IO LVDS50n B3 VREF2B3 75 123 P15

IO LVDS50p B3 VREF2B3 76 124 R16

IO LVDS49n B3 VREF2B3 77 125 N15 DQ1R7 DQ

IO LVDS49p B3 VREF2B3 78 126 N16 DQ1R6IO VREF2B3 B3 VREF2B3 79 127 K12

IO B3 VREF2B3 128 K14





TQFPPin Name /

FunctionOptional


FunctionBank


TQFP

240-Pin

PQFP

256-PinFineLine BGA


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IO DPCLK5 B3 VREF2B3 82 131 L12 DQS1R D

IO LVDS48n B3 VREF2B3 83 132 N14 DQ1R5 DQ

IO LVDS48p B3 VREF2B3 84 133 M13 DQ1R4 DQ

IO LVDS47n B3 VREF2B3 85 134 M14 DM1R

IO LVDS47p B3 VREF2B3 135 L13


IO LVDS46p B3 VREF2B3 137 M16

IO LVDS45n B3 VREF2B3 138 L14

IO LVDS45p B3 VREF2B3 139 L15IO LVDS44n B3 VREF2B3 140 L16

IO LVDS44p B3 VREF2B3 141 K16

GND B3 VREF2B3 142

IO PLL2_OUTn B3 VREF1B3 143 K15

IO PLL2_OUTp B3 VREF1B3 144 J16

CONF_DONE

CONF_DONE

B3 VREF1B3 86 145 K13

nSTATUS nSTATUS B3 VREF1B3 87 146 J13

TCK TCK B3 VREF1B3 88 147 J14TMS TMS B3 VREF1B3 89 148 J15

TDO TDO B3 VREF1B3 90 149 H15

GNDG_PLL2 VREF1B3 91 150 J12

GNDA_PLL2 VREF1B3 151 J11

CLK3 LVDSCLK2n B3 VREF1B3 92 152 H16



TQFPPin Name /

FunctionOptional


FunctionBank


TQFP

240-Pin

PQFP

256-PinFineLine BGA


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CLK2 LVDSCLK2p B3 VREF1B3 93 153 G16

VCCA_PLL2 VREF1B3 94 154 H11

TDI TDI B3 VREF1B3 95 155 H14

IO VREF1B3 B3 VREF1B3 96 156 H12


IO LVDS43n B3 VREF0B3 158 G14 D

IO LVDS43p B3 VREF0B3 159 G13

IO LVDS42n B3 VREF0B3 160 G15

IO LVDS42p B3 VREF0B3 161 F16IO LVDS41n B3 VREF0B3 162 F14


IO LVDS40n B3 VREF0B3 164 F15

IO LVDS40p B3 VREF0B3 165 E16

IO LVDS39n B3 VREF0B3 166 E15

IO LVDS39p B3 VREF0B3 97 167 D16 DQ1R3

IO LVDS38n B3 VREF0B3 98 168 D15 DQ1R2

IO LVDS38p B3 VREF0B3 99 169 E14 DQ1R1 DQ

IO DPCLK4 B3 VREF0B3 100 170 F12GND B3 VREF0B3 101 171


IO LVDS37n B3 VREF0B3 173 E13 D

IO LVDS37p B3 VREF0B3 174 D14 D



TQFPPin Name /

FunctionOptional


FunctionBank


TQFP

240-Pin

PQFP

256-PinFineLine BGA


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IO B3 VREF0B3 103 175 H13 DQ1R0 D

IO VREF0B3 B3 VREF0B3 104 176 G12


IO LVDS36p B3 VREF0B3 106 178 C15

IO LVDS35n B3 VREF0B3 107 179 C14

IO LVDS35p B3 VREF0B3 108 180 D13


IO LVDS34p B2 VREF0B2 110 182 A15

IO LVDS33n B2 VREF0B2 183 B14IO LVDS33p B2 VREF0B2 184 C13

IO LVDS32n B2 VREF0B2 111 185 B13 DQ0T0 DQ

IO LVDS32p B2 VREF0B2 112 186 A13 DQ0T1 DQ

IO LVDS31n B2 VREF0B2 113 187 B12 DQ0T2 DQ

IO LVDS31p B2 VREF0B2 114 188 C12 DQ0T3 DQ




GND VREF0B2 118 192IO DPCLK3 B2 VREF0B2 119 193 E12 DQS0T DQ

IO VREF0B2 B2 VREF0B2 120 194 E11

IO B2 VREF0B2 121 195 E9




TQFPPin Name /

FunctionOptional


FunctionBank


TQFP

240-Pin

PQFP

256-PinFineLine BGA


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IO LVDS30p B2 VREF0B2 197 D11

IO LVDS29n B2 VREF0B2 198 C11

IO LVDS29p B2 VREF0B2 199 B11

IO LVDS28n B2 VREF1B2 200 A11


IO LVDS27n B2 VREF1B2 122 202 C10

IO LVDS27p B2 VREF1B2 203 D10

IO LVDS26n B2 VREF1B2 204 A9

IO LVDS26p B2 VREF1B2 205 B9IO LVDS25n B2 VREF1B2 123 206 D9 DM0T D

IO LVDS25p B2 VREF1B2 124 207 C9

IO VREF1B2 B2 VREF1B2 125 208 E10


GND B2 VREF1B2 210


GND VREF1B2 127 212

IO B2 VREF1B2 213 E8

IO LVDS24n B2 VREF1B2 128 214 C8IO LVDS24p B2 VREF1B2 129 215 D8

IO LVDS23n B2 VREF2B2 130 216 A8

IO LVDS23p B2 VREF2B2 131 217 B8




TQFPPin Name /

FunctionOptional


FunctionBank


TQFP

240-Pin

PQFP

256-PinFineLine BGA


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IO LVDS22p B2 VREF2B2 219 C7

IO LVDS21n B2 VREF2B2 220 B7

IO LVDS21p B2 VREF2B2 221 A6

IO B2 VREF2B2 222 E7

IO LVDS20n B2 VREF2B2 223 B6

IO LVDS20p B2 VREF2B2 224 C6


IO LVDS19p B2 VREF2B2 132 226 D5

IO VREF2B2 B2 VREF2B2 133 227 E6IO DPCLK2 B2 VREF2B2 134 228 E5


GND VREF2B2 136 230



IO LVDS18n B2 VREF2B2 139 233 C5 DQ0T4 DQ

IO LVDS18p B2 VREF2B2 140 234 B5 DQ0T5 DQ

IO LVDS17n B2 VREF2B2 141 235 A4 DQ0T6 D

IO LVDS17p B2 VREF2B2 142 236 B4 DQ0T7 DQIO LVDS16n B2 VREF2B2 237 C4


IO LVDS15n DEV_OE B2 VREF2B2 143 239 A2

IO LVDS15p DEV_CLRn B2 VREF2B2 144 240 B2



TQFPPin Name /

FunctionOptional


FunctionBank


TQFP

240-Pin

PQFP

256-PinFineLine BGA


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VCCINT A7

VCCINT A10

VCCINT G8

VCCINT G10

VCCINT H7

VCCINT H9

VCCINT J8

VCCINT J10

VCCINT K7VCCINT K9

VCCINT T7

VCCINT T10

VCCIO1 C1

VCCIO1 G6

VCCIO1 P1

VCCIO4 T3

VCCIO4 L7

VCCIO4 L10VCCIO4 T14

VCCIO3 P16

VCCIO3 K11

VCCIO3 C16



TQFPPin Name /

FunctionOptional


FunctionBank


TQFP

240-Pin

PQFP

256-PinFineLine BGA


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VCCIO2 A14

VCCIO2 F10

VCCIO2 F7

VCCIO2 A3

GND A1

GND A16

GND A5

GND A12

GND F6GND F8

GND F9

GND F11

GND G7

GND G9

GND G11

GND H8

GND H10

GND J7GND J9

GND K6

GND K8

GND K10



TQFPPin Name /

FunctionOptional


FunctionBank


TQFP

240-Pin

PQFP

256-PinFineLine BGA


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GND L6

GND L8

GND L9

GND L11

GND T1

GND T5

GND T12

GND T16



TQFPPin Name /

FunctionOptional


FunctionBank


TQFP

240-Pin

PQFP

256-PinFineLine BGA


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Pin Definitions Table 32 shows pin definitions for the EP1C6 device.

Table 32. Pin Definitions for the EP1C6 Device (Part 1 of 4)

Pin Name Pin Type (1st, 2nd, & 3rd Function) Pin Description


VCCIO[1..4] Power These are I/O supply voltage pins for banks 1 through 4. Eaca different voltage level. VCCIO supplies power to the outstandards. VCCIO also supplies power to the input buffersLVCMOS, 1.5-V, 1.8-V, 2.5-V, and 3.3-V PCI I/O standards

VCCINT Power These are internal logic array voltage supply pins. VCCINTthe input buffers used for the LVDS, SSTL2, and SSTL3 I

VREF[0..2]B[1..4] I/O, Input Input reference voltage for banks 1-4. If a bank uses a voltagstandard, then these pins are used as the voltage-referencevoltage reference I/O standards are not used in the bank, thavailable as user I/O pins.

VCCA_PLL[1..2] Power Analog power for PLLs[1..2]. The designer must connect thithe PLL is not used.

GNDA_PLL[1..2] Ground Analog ground for PLLs[1..2]. The designer can connect thison the board.

GNDG_PLL[1..2] Ground Guard ring ground for PLLs[1..2]. The designer can connectplane on the board.


CONF_DONE Bidirectional (open-drain) This is a dedicated configuration status pin; it is not available a

nSTATUS Bidirectional (open-drain) This is a dedicated configuration status pin; it is not available a

nCONFIG Input Dedicated configuration control input. A low transition reselow-to-high transition begins configuration. All I/O pins trdriven low.

DCLK Input (PS mode), Output (AS mode) In passive serial configuration mode, DCLK is a clock input useconfiguration data from an external source into the Cycloneconfiguration mode, DCLK is a clock output from the Cycldevice acts as master in this mode). This is a dedicated pin


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nCE Input Active-low chip enable. Dedicated chip enable input used to

is active in a chain of devices. When nCE is low, the deviceis high, the device is disabled.

nCEO Output Output that drives low when device configuration is completconfiguration, this pin feeds a subsequent devices nCE pin

ASDO I/O, Output Active serial data output from the Cyclone device. This outpuactive serial configuration mode. The Cyclone device contdrives address and control information out on ASDO. In pconfiguration, this pin is available as a user I/O pin.

nCSO I/O, Output Chip select output that enables/disables a serial configurationis utilized during active serial configuration mode. The Cconfiguration and enables the serial configuration device bpassive serial configuration, this pin is available as a user I

INIT_DONE I/O, Output (open-drain) This is a dual-purpose pin and can be used as an I/O pin whenINIT_DONE. When enabled, the pin indicates when the dmode. This pin can be used as a user I/O pin after configur

CLKUSR I/O, Input Optional user-supplied clock input. Synchronizes the initialdevices. This pin can be used as a user I/O pin after config

DEV_CLRn I/O, Input Dual-purpose pin that can override all clears on all device regis driven low, all registers are cleared; when this pin is drivbehave as defined in the design.

DEV_OE I/O, Input Dual-purpose pin that can override all tri-states on the devicdriven low, all I/O pins are tri-stated; when this pin is drivbehave as defined in the design.

MSEL[1..0] Input Dedicated mode select control pins that set the configuration








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Clock and PLL Pins

CLK0 Input, LVDS Input Dedicated global clock input. The dual-function of CLK0 isused for differential input to PLL1.




DPCLK[7..0] I/O Dual-purpose clock pins that can connect to the global clockcan be used for high fan-out control signals, such as clocks,or DQS signals. These pins are also available as user I/O

PLL1_OUTp I/O, Output External clock output from PLL 1. This pin can be used withended I/O standards. If clock output from PLL1 is not useda user I/O pin.

PLL1_OUTn I/O, Output Negative terminal for external clock output from PLL1. If theended, this pin is available as a user I/O pin.

PLL2_OUTp I/O, Output External clock output from PLL 2. This pin can be used withended I/O standards. If clock output from PLL2 is not useda user I/O pin. The EP1C6T144 does not support this outp

PLL2_OUTn I/O, Output Negative terminal for external clock output from PLL2. If theended, this pin is available as a user I/O pin. The EP1C6Tthis output pin.

Dual-Purpose LVDS & External Memory Interface PinsLVDS[0..71]p I/O, LVDS RX or TX Dual-purpose LVDS I/O channels 0 to 71. These channels ca

receiving or transmitting LVDS compatible signals. Pins wpositive signal for the differential channel. If not used for Lpins are available as user I/O pins.




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LVDS[0..71]n I/O, LVDS RX or TX Dual-purpose LVDS I/O channels 0 to 71. These channels careceiving or transmitting LVDS compatible signals. Pins winegative signal for the differential channel. If not used for pins are available as user I/O pins.

LVDSCLK1p Input, LVDS Input Dual-purpose LVDS clock input to PLL1. If differential inprequired, this pin is available as the CLK0 input pin.

LVDSCLK1n Input, LVDS Input Dual-purpose LVDS clock input to PLL1. If differential inprequired, this pin is available as the CLK1 input pin.

LVDSCLK2p Input, LVDS Input Dual-purpose LVDS clock input to PLL2. If differential inprequired, this pin is available as the CLK2 input pin.

LVDSCLK2n Input, LVDS Input Dual-purpose LVDS clock input to PLL2. If differential inprequired, this pin is available as the CLK3 input pin.

DQS[0..1][L,R,T,B] I/O Optional data strobe signal for use in external memory interfa

function as DPCLK pins; therefore, the DQS signals can cclock network. A programmable delay chain is used to shiftor 72 degrees.

DQ[0..7][L,R,T,B] I/O Optional data signal for use in external memory interfacing

DM[0..1][L,R,T,B] I/O Optional data mask output signal for use in external memor




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PLL & BankDiagram

Figure shows the PLL and Bank locations for the EP1C6 device.


Notes for Figure:(1) This is a top view of the silicon die.


B2

V R E F 0 B 1

B 1

V R E F 1 B 1

PLL1 PLL2

V R E B 2 B 1


V R E B 2 B 3


B 3

V R E F 0 B 3

V R E F 1 B 3


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4. Cyclone EP1C12 DevicePin Information

Introduction The following tables contain pin information for the Cyclone EP1C12device, organized into the following sections:

Section Page

Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420PLL & Bank Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

C52004-1.0


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Pin List Table 41 shows the complete pin list for the device Cyclone EP1C12 device:


Device Package DQS for

X8 in240-Pin

PQFP

Pin Name /Function

OptionalFunction(s)


BankNum.

VREFBank

240-Pin

PQFP

256-PinFineLine BGA

324-PinFineLine BGA

IO LVDS23p INIT_DONE B1 VREF0B1 1 D4 C3

IO LVDS23n B1 VREF0B1 2 C3 C2

IO LVDS22p CLKUSR B1 VREF0B1 3 C2 D3

IO LVDS22n B1 VREF0B1 4 B1 D2

IO VREF0B1 B1 VREF0B1 5 G5 D4

IO B1 VREF0B1 6 F4 D1

IO LVDS21p B1 VREF0B1 7 D3 E3 DQ0L0 DQ

IO LVDS21n B1 VREF0B1 8 E4 E2 DQ0L1 DQ

VCCIO1 B1 VREF0B1 9

GND B1 VREF0B1 10

IO DPCLK1 B1 VREF0B1 11 F5 F1 DQS0L DQ

IO LVDS20p B1 VREF0B1 12 E3 E4 DQ0L2 DQ

IO LVDS20n B1 VREF0B1 13 D2 E5 DQ0L3 DQ

IO LVDS19p B1 VREF0B1 14 E2 F2

IO LVDS19n B1 VREF0B1 15 D1 F3

IO LVDS18p B1 VREF0B1 16 F3 F4

IO LVDS18n B1 VREF0B1 17 G3 F5

IO LVDS17p B1 VREF0B1 18 F2 G1

IO LVDS17n B1 VREF0B1 19 E1 G2

IO LVDS16p B1 VREF0B1 20 G2 F6


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IO LVDS16n B1 VREF0B1 21 F1 F7 DM0L DM

IO LVDS15p B1 VREF0B1 G3

IO LVDS15n B1 VREF0B1 G4



IO B1 VREF0B1 H1


GND B1 VREF0B1

IO LVDS13p B1 VREF1B1 H2

IO LVDS13n B1 VREF1B1 H3



IO VREF1B1 B1 VREF1B1 23 H5 H6

IO nCSO B1 VREF1B1 24 G4 J1

DATA0 DATA0 B1 VREF1B1 25 H2 H7

nCONFIG nCONFIG B1 VREF1B1 26 H3 J2

VCCA_PLL1 VREF1B1 27 H6 J5

CLK0 LVDSCLK1p B1 VREF1B1 28 G1 J3

CLK1 LVDSCLK1n B1 VREF1B1 29 H1 J4

GNDA_PLL1 VREF1B1 30 J6 K1

GNDG_PLL1 VREF1B1 31 J5 J6

nCEO nCEO B1 VREF1B1 32 H4 K2


Device Package DQS forX8 in240-Pin

PQFP

Pin Name /Function

OptionalFunction(s)


BankNum.

VREFBank

240-Pin

PQFP

256-PinFineLine BGA

324-PinFineLine BGA


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nCE nCE B1 VREF1B1 33 J4 J7

MSEL0 MSEL0 B1 VREF1B1 34 J3 K3

MSEL1 MSEL1 B1 VREF1B1 35 J2 K7

DCLK DCLK B1 VREF1B1 36 K4 L1

IO ASDO B1 VREF1B1 37 K3 K6

IO PLL1_OUTp B1 VREF1B1 38 J1 K4

IO PLL1_OUTn B1 VREF1B1 39 K2 K5

IO LVDS11p B1 VREF1B1 L7

IO LVDS11n B1 VREF1B1 L6





VCCIO1 B1 VREF2B1

GND B1 VREF2B1 40

IO B1 VREF2B1 M1

IO LVDS8p B1 VREF2B1 M3

IO LVDS8n B1 VREF2B1 M2


IO LVDS7n B1 VREF2B1 41 L3 M4

IO LVDS6p B1 VREF2B1 42 K1 N1

IO LVDS6n B1 VREF2B1 43 L1 N2



PQFP

Pin Name /Function

OptionalFunction(s)


BankNum.

VREFBank

240-Pin

PQFP

256-PinFineLine BGA

324-PinFineLine BGA


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IO LVDS5p B1 VREF2B1 44 L2 M6

IO LVDS5n B1 VREF2B1 45 M1 N7

IO LVDS4p B1 VREF2B1 46 N1 N5


IO LVDS3p B1 VREF2B1 48 N2 N3 DQ0L4 DQ

IO LVDS3n B1 VREF2B1 49 M3 N4 DQ0L5 DQ

IO DPCLK0 B1 VREF2B1 50 L5 P5


GND B1 VREF2B1 52

IO LVDS2p B1 VREF2B1 53 M4 P2 DQ0L6 DQ

IO LVDS2n B1 VREF2B1 54 N3 P3 DQ0L7 DQ

IO VREF2B1 B1 VREF2B1 55 K5 R1

IO B1 VREF2B1 56 L4 P4

IO LVDS1p B1 VREF2B1 57 R1 R2

IO LVDS1n B1 VREF2B1 58 P2 R3

IO LVDS0p B1 VREF2B1 59 P3 T2

IO LVDS0n B1 VREF2B1 60 N4 T3

IO LVDS102p B4 VREF2B4 61 R2 U3

IO LVDS102n B4 VREF2B4 62 T2 V4

IO LVDS101p B4 VREF2B4 63 R3 M8

IO LVDS101n B4 VREF2B4 64 P4 N8

IO LVDS100p B4 VREF2B4 65 R4 T4



PQFP

Pin Name /Function

OptionalFunction(s)


BankNum.

VREFBank

240-Pin

PQFP

256-PinFineLine BGA

324-PinFineLine BGA


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IO LVDS100n B4 VREF2B4 66 T4 U4

IO LVDS99p B4 VREF2B4 67 R5 T5 DQ1B7 DQ

IO LVDS99n B4 VREF2B4 68 P5 U5 DQ1B6 DQ

GND B4 VREF2B4 69


GND VREF2B4 71

VCCINT VREF2B4 72

IO DPCLK7 B4 VREF2B4 73 M5 R4 DQS1B DQ

IO VREF2B4 B4 VREF2B4 74 M6 R5

IO LVDS98p B4 VREF2B4 75 N5 V6

IO LVDS98n B4 VREF2B4 76 N6 U6 DQ1B5 DQ

IO LVDS97p B4 VREF2B4 77 P6 P6 DQ1B4 DQ

IO LVDS97n B4 VREF2B4 78 R6 P7

IO LVDS96p B4 VREF2B4 79 M7 T6

IO LVDS96n B4 VREF2B4 R6

GND VREF2B4 80

VCCINT VREF2B4 81

IO LVDS95p B4 VREF2B4 82 T6 U7

IO LVDS95n B4 VREF2B4 83 R7 V7


IO LVDS94n B4 VREF2B4 85 N7 R7




PQFP

Pin Name /Function

OptionalFunction(s)


BankNum.

VREFBank

240-Pin

PQFP

256-PinFineLine BGA

324-PinFineLine BGA


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IO LVDS92p B4 VREF1B4 88 M8 T8


GND VREF1B4 89

VCCINT VREF1B4 90

GND B4 VREF1B4 91


IO LVDS91p B4 VREF1B4 U9

IO LVDS91n B4 VREF1B4 V9

IO LVDS90p B4 VREF1B4 N8 R9

IO LVDS90n B4 VREF1B4 P8 T9


IO LVDS89n B4 VREF1B4 N9

IO VREF1B4 B4 VREF1B4 93 M10 P9

IO LVDS88p B4 VREF1B4 U10

IO LVDS88n B4 VREF1B4 V10

IO LVDS87p B4 VREF1B4 94 R9 T10 DM1B DM

IO LVDS87n B4 VREF1B4 95 T9 R10

GND VREF1B4 96

VCCINT VREF1B4 97

IO B4 VREF1B4 P10

IO LVDS86p B4 VREF1B4 98 P9 R11



PQFP

Pin Name /Function

OptionalFunction(s)


BankNum.

VREFBank

240-Pin

PQFP

256-PinFineLine BGA

324-PinFineLine BGA


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GND B4 VREF1B4

VCCIO4 B4 VREF1B4

IO LVDS84p B4 VREF1B4 N10 V12

IO LVDS84n B4 VREF1B4 P10 U12

GND VREF0B4 102

VCCINT VREF0B4 103

IO LVDS83p B4 VREF0B4 R11 T12

IO LVDS83n B4 VREF0B4 P11 R12

IO LVDS82p B4 VREF0B4 V13

IO LVDS82n B4 VREF0B4 U13

IO LVDS81p B4 VREF0B4 T13


IO LVDS80p B4 VREF0B4 104 N11 N10

IO LVDS80n B4 VREF0B4 105 N12 M10

IO B4 VREF0B4 106 M9 P12

IO VREF0B4 B4 VREF0B4 107 M11 P13

IO DPCLK6 B4 VREF0B4 108 M12 U14

GND VREF0B4 109

VCCINT VREF0B4 110



PQFP

Pin Name /Function

OptionalFunction(s)


BankNum.

VREFBank

240-Pin

PQFP

256-PinFineLine BGA

324-PinFineLine BGA


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GND B4 VREF0B4 111


IO LVDS79p B4 VREF0B4 113 P12 T14 DQ1B3 DQ

IO LVDS79n B4 VREF0B4 114 R12 R14 DQ1B2 DQ

IO LVDS78p B4 VREF0B4 115 T13 V15 DQ1B1 DQ

IO LVDS78n B4 VREF0B4 116 R13 U15 DQ1B0 DQ

IO LVDS77p B4 VREF0B4 117 R14 N11

IO LVDS77n B4 VREF0B4 118 P13 M11

IO LVDS76p B4 VREF0B4 119 T15 U16

IO LVDS76n B4 VREF0B4 120 R15 T15



IO LVDS74n B3 VREF2B3 123 P15 R17

IO LVDS74p B3 VREF2B3 124 R16 R18

IO LVDS73n B3 VREF2B3 125 N15 R15 DQ1R7 DQ

IO LVDS73p B3 VREF2B3 126 N16 R16

IO VREF2B3 B3 VREF2B3 127 K12 P16

IO B3 VREF2B3 128 K14 P17 DQ1R6 DQ

GND B3 VREF2B3 129


IO DPCLK5 B3 VREF2B3 131 L12 P15 DQS1R DQ

IO LVDS72n B3 VREF2B3 132 N14 P14 DQ1R5 DQ



PQFP

Pin Name /Function

OptionalFunction(s)


BankNum.

VREFBank

240-Pin

PQFP

256-PinFineLine BGA

324-PinFineLine BGA


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IO LVDS72p B3 VREF2B3 133 M13 N14 DQ1R4 DQ


IO LVDS71p B3 VREF2B3 135 L13 N17


IO LVDS70p B3 VREF2B3 137 M16 N12

IO LVDS69n B3 VREF2B3 138 L14 N16

IO LVDS69p B3 VREF2B3 139 L15 N15

IO LVDS68n B3 VREF2B3 140 L16 M18

IO LVDS68p B3 VREF2B3 141 K16 M17



IO B3 VREF2B3 M16

GND B3 VREF2B3 142

VCCIO3 B3 VREF2B3







IO B3 VREF1B3 L14

IO PLL2_OUTn B3 VREF1B3 143 K15 K16



PQFP

Pin Name /Function

OptionalFunction(s)


BankNum.

VREFBank

240-Pin

PQFP

256-PinFineLine BGA

324-PinFineLine BGA


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IO PLL2_OUTp B3 VREF1B3 144 J16 K15

CONF_DONE CONF_DONE B3 VREF1B3 145 K13 K17

nSTATUS nSTATUS B3 VREF1B3 146 J13 L12

TCK TCK B3 VREF1B3 147 J14 K18

TMS TMS B3 VREF1B3 148 J15 K14

TDO TDO B3 VREF1B3 149 H15 K13

GNDG_PLL2 VREF1B3 150 J12 J18

GNDA_PLL2 VREF1B3 151 J11 K12

CLK3 LVDSCLK2n B3 VREF1B3 152 H16 J16

CLK2 LVDSCLK2p B3 VREF1B3 153 G16 J15

VCCA_PLL2 VREF1B3 154 H11 J12

TDI TDI B3 VREF1B3 155 H14 J17

IO VREF1B3 B3 VREF1B3 156 H12 J14

IO LVDS63n B3 VREF1B3 J13






GND B3 VREF0B3


IO B3 VREF0B3 H18



PQFP

Pin Name /Function

OptionalFunction(s)


BankNum.

VREFBank

240-Pin

PQFP

256-PinFineLine BGA

324-PinFineLine BGA


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IO LVDS59n B3 VREF0B3 158 G14 G13 DM1R DM

IO LVDS59p B3 VREF0B3 159 G13 G14

IO LVDS58n B3 VREF0B3 160 G15 G15

IO LVDS58p B3 VREF0B3 161 F16 G16

IO LVDS57n B3 VREF0B3 162 F14 G12

IO LVDS57p B3 VREF0B3 163 F13 F12

IO LVDS56n B3 VREF0B3 164 F15 F18

IO LVDS56p B3 VREF0B3 165 E16 F17

IO LVDS55n B3 VREF0B3 166 E15 F13

IO LVDS55p B3 VREF0B3 167 D16 F14

IO LVDS54n B3 VREF0B3 168 D15 F16

IO LVDS54p B3 VREF0B3 169 E14 F15 DQ1R3 DQ

IO DPCLK4 B3 VREF0B3 170 F12 E17

GND B3 VREF0B3 171


IO LVDS53n B3 VREF0B3 173 E13 E16 DQ1R2 DQ

IO LVDS53p B3 VREF0B3 174 D14 E15 DQ1R1 DQ

IO B3 VREF0B3 175 H13 D18 DQ1R0 DQ

IO VREF0B3 B3 VREF0B3 176 G12 E14

IO LVDS52n B3 VREF0B3 177 B16 D16



PQFP

Pin Name /Function

OptionalFunction(s)


BankNum.

VREFBank

240-Pin

PQFP

256-PinFineLine BGA

324-PinFineLine BGA


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IO LVDS52p B3 VREF0B3 178 C15 D15

IO LVDS51n B3 VREF0B3 179 C14 C17

IO LVDS51p B3 VREF0B3 180 D13 D17

IO LVDS50n B2 VREF0B2 181 B15 C16

IO LVDS50p B2 VREF0B2 182 A15 B16

IO LVDS49n B2 VREF0B2 183 B14 G11

IO LVDS49p B2 VREF0B2 184 C13 F11

IO LVDS48n B2 VREF0B2 185 B13 B15 DQ0T0 DQ

IO LVDS48p B2 VREF0B2 186 A13 A15 DQ0T1 DQ

IO LVDS47n B2 VREF0B2 187 B12 C15 DQ0T2 DQ

IO LVDS47p B2 VREF0B2 188 C12 D14 DQ0T3 DQ


GND B2 VREF0B2 190

VCCINT VREF0B2 191

GND VREF0B2 192

IO DPCLK3 B2 VREF0B2 193 E12 B14 DQS0T DQ

IO VREF0B2 B2 VREF0B2 194 E11 C14

IO B2 VREF0B2 195 E9 E13

IO LVDS46n B2 VREF0B2 196 D12 G10

IO LVDS46p B2 VREF0B2 197 D11 F10

IO LVDS45n B2 VREF0B2 B13

IO LVDS45p B2 VREF0B2 A13



PQFP

Pin Name /Function

OptionalFunction(s)


BankNum.

VREFBank

240-Pin

PQFP

256-PinFineLine BGA

324-PinFineLine BGA


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IO LVDS37p B2 VREF1B2 F9

IO LVDS36n B2 VREF1B2 C8 D9

IO LVDS36p B2 VREF1B2 D8 C9

IO LVDS35n B2 VREF1B2 A9

IO LVDS35p B2 VREF1B2 B9


GND B2 VREF1B2 210

VCCINT VREF1B2 211

GND VREF1B2 212

IO LVDS34n B2 VREF1B2 D8

IO LVDS34p B

altera ciclon 2

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