advanced(laboratory(tes1ng(methods( · pdf fileadvanced(laboratory(tes1ng(methods ... outside...

NREL is a na*onal laboratory of the U.S. Department of Energy, Office of Energy Efficiency and Renewable Energy, operated by the Alliance for Sustainable Energy, LLC.

Advanced Laboratory Tes1ng Methods Use Case: PHIL An*-‐islanding Tes*ng

DERlab/SIRFN Workshop

19 March 2015

Blake Lundstrom, P.E. Research Electrical Engineer Power Systems Engineering Center Na*onal Renewable Energy Laboratory (NREL) Golden, CO, USA

2

Outline

•  Introduc1on to PHIL-‐based Uninten1onal Islanding Tes1ng

•  NREL Experimental Implementa1on and Capabili1es o  AC/DC amplifiers (NREL and U.S.) o  Lab power ra*ng / grid level o  Real-‐*me systems available o  Interoperability (technical/communica*on/interface)

•  PHIL UI Test Results •  PHIL co-‐simula1on

3

Introduc1on – IEEE 1547 and UI

��

� ��

�

Figure 2.4: Unintentional islanding test circuit (Simplified version of Figure 2 of IEEE Std1547.1 [39])

IEEE Std 1547.2-2008 [30] fills that gap by providing very detailed information as to the

interpretation, background, and impact of each requirement in IEEE Std 1547-2003 as well

as application guidance, tips, techniques, and rules of thumb to aide implementation of each

requirement. For example, IEEE Std 1547-2003 provides only a simple statement regarding

the requirement regarding voltage regulation: “The DR shall not actively regulate the voltage

at the PCC. The DR shall not cause the Area EPS service voltage at other Local EPSs to go

outside the requirements of ANSI C84.1-1995, Range A” [18]. However, IEEE Std 1547.2-

2008 provides much greater detail, such as that regarding interpretation: “there is a subtle

di↵erence between actively regulating and fulfilling an area EPS request to supply or absorb

reactive power” [30]; background on voltage regulation, typical utilization equipment, voltage

limits from ANSI C84.1 Range A [40], etc.; the potential impacts of DR on utility voltage

regulation schemes; and rules of thumb as to when to expect voltage regulation issues due

to DRs. Overall, IEEE Std 1547.2-2008 is an extremely valuable resource for understanding

IEEE Std 1547 and interconnection issues in general.

2.5 IEEE Std 1547.3

IEEE Std 1547 provides specific interconnection requirements that describe how a specific

DR or group of DRs must interact with the area EPS at a single PCC. However, the success-

24

Uninten1onal Islanding Requirement •  For an uninten*onal island in which the DR energizes a

por*on of the Area EPS through the PCC, the DR interconnec*on system shall detect the island and cease to energize the Area EPS within two seconds of the forma*on of an island.

4

B usCirc uits

B us

Substat ion Feeds

Step-Dn Transfe rs

L

C irc uit Isla nd

N. C.

N.C.

N.C .

L L

Adja cent C ircuit

N .O. (c losed for adjacent

circuit island)

(open for circuit island)

Open for lateral island

CB2

© IEEE 1547.4-‐2011

Circuit Island

5

Introduc1on – Tradi1onal UI Test

5

Prac1cal Limita1ons: •  RLC load bank overall (and step size) power level •  Discrete elements in RLC load bank •  Execu*on *me for large number of cases

6

Introduc1on – PHIL-‐based UI Test

6

Advantages: •  Specialized RLC load bank no

longer needed (though power amplifier and RTS required)

•  Tuning of RLC load bank much more precise with modeled elements instead of discrete elements

•  Execu*on *me for a single test is much faster and tests can be automated

7

Introduc1on – Components Required for PHIL

•  AC Power Amplifier (and possibly a dump load) of appropriate specifica1ons

•  Real-‐1me Simulator (RTS) and RT model •  AC Current Sensors •  Stabiliza1on network (if applicable)

7

8

Outline




9

PV

Energy Storage

Diesel / NG Generators

AC Loads

Aux / DC Loads

GS

Local Controller

Power Conditioningand Conversion

DC REDB AC REDB

Grid ModelDC Device Models

Bi-directionalProgrammable DC Supply

Bi-directionalGrid Simulator

M M

Local Hardwareat ESIF

ESIFEquipment

Distribution PMUWeather

Real-Time Data User Interface and Visualization

Real-TimeSimulator

LocalUser Interface

Ipv Id Rp

Rs

V

I

Market Pricing

Local UtilityConnection

GSAC Device Models

System Controller PCC

27

10

PV

Energy Storage


AC Loads

Aux / DC Loads

GS

Local Controller


DC REDB AC REDB




M M


ESIFEquipment



Real-TimeSimulator

LocalUser Interface

Ipv Id Rp

Rs

V

I

Market Pricing


GSAC Device Models


Real-‐*me PMU Measurements

27

11

PV

Energy Storage


AC Loads

Aux / DC Loads

GS

Local Controller


DC REDB AC REDB




M M


ESIFEquipment



Real-TimeSimulator

LocalUser Interface

Ipv Id Rp

Rs

V

I

Market Pricing


GSAC Device Models


Real-‐*me Solar Irradiance Measurements

27

12

PV

Energy Storage


AC Loads

Aux / DC Loads

GS

Local Controller


DC REDB AC REDB




M M


ESIFEquipment



Real-TimeSimulator

LocalUser Interface

Ipv Id Rp

Rs

V

I

Market Pricing


GSAC Device Models


1.08 MVA Grid Simulator

27

13

1.08 MVA Grid Simulator Basic Specifica+ons (RS270) •  Voltage: 0 – 400 Vl-‐n or 400 Vdc •  Frequency:

o  DC or 16 – 819 Hz (Sourcing) o  DC or 16 – 500 Hz (Sinking)

•  Current: 375 A (1500 A total) •  Power Flow: Bi-‐direc*onal •  Phase Control: Independent

phase control •  PHIL Interface: Analog input

corresponding to instantaneous voltage waveform command

•  Input Current THD: o  Source Mode: ~ 3% o  Sink Mode: ~ 5%

•  Sobware Interface: o  Transient List Editor o  Arbitrary Waveform

Genera*on •  Cooling: Air-‐cooled

Manufacturer and Base Model Ametek RS90 (90 kVA)

Modularity Four RS270 “Quads” capable of independent or parallel opera*on

14

1.0 MVA Grid Simulator – Addtl. Specs

Architecture •  Topology: Three Single-‐Phase H-‐Bridges •  Device Type: PFC = IGBT, Inverter = MOSFET •  Inverter Switching Frequency: 60 kHz, interleaved to 240 kHz effec*ve Output Specifica+ons •  Voltage Accuracy: ±0.3 V AC, ±1 V DC •  Frequency Accuracy: ±0.01% •  Phase Angle Accuracy: < 1.5° @ 16 – 100 Hz; < 2° @100 – 500 Hz •  THD at full load

o  Sourcing: < 0.5% @ 16 – 66 Hz; < 1% @ 66 – 500 Hz; < 1.25% up to 819 Hz o  Sinking: < 1% @45 – 66 Hz; < 2% @ 66 – 500 Hz

•  Load Regula1on: 0.25% FS @ DC – 100 Hz; 0.5% FS @ > 100 Hz •  DC Offset Voltage: < 20 mV •  Slew Rate: 200 µs for 20% -‐ 90% output change into resis*ve load, > 0.5 V/µs •  Sedling Time: < 0.5 µs •  -‐3dB Bandwidth: 4 kHz (but fundamental component limited to 1 kHz due to

output snubber power limita*ons)

15

Summary of MW-‐scale Power Amplifiers (U.S. Facili1es)

1.08 MVA (+1.08 MVA future) 480 V

6

� Installed at NWTC test site—November 2012 � Commissioning and characterization testing—end of 2013 � Row 4/turbine bus connection—FY14 � Energy storage site connection—end of 2014

NWTC’s 7-MVA CGI

Photo from Mark McDade, NREL

7 MVA (39 MVA short-‐circuit) 3.3 kV (13.2 kV)

NREL ESIF – Golden, CO NREL NWTC – Boulder, CO

• Su erconductivit and Cr o enics Labs

FSU-CAPS Lab Capabilities • Integrated 5 MW HIL Testbed

– 5 MW variable voltage/frequency converter

– 5 MW dynamometers – 5 MW MVDC converters (MMC)

• Real-time Digital Simulators RTDS & OPAL-RT using typical time step sizes from 2 µs to 50 µs Cyber-physical test bed

• Superconductivity and Cryogenics Labsy y gp – AC Loss and Quench Stability Lab – Cryo-dielectrics High Voltage Lab – Cryo-cooled Systems Lab

• Low Power and Smart Grid Labs • Extensive non-RT simulation tools and

expertise – PSCAD, PSS/E, Matlab, PLECS, OpenDSS, etc. – COMSOL, Magnet, etc.

4

15 MVA (20 MVA) 4.16 kV (23.9 kV)

5 MVA 4.16 kV

Clemson/DOE – N. Charleston, SC Florida State Univ. CAPS – Tallahassee, FL

See Proceedings of Second Interna*onal Workshop on Grid Simulator Tes*ng of Wind Turbine Drivetrains: htp://www.nrel.gov/electricity/transmission/grid-‐simulator-‐workshop-‐2.html

M. Steurer, FSU CAPS J.C. Fox, Clemson University

16

PV

Energy Storage


AC Loads

Aux / DC Loads

GS

Local Controller


DC REDB AC REDB




M M


ESIFEquipment



Real-TimeSimulator

LocalUser Interface

Ipv Id Rp

Rs

V

I

Market Pricing


GSAC Device Models


1 MVA RLC Load

27

17

1 MVA Load Bank Manufacturer and Base Model LoadTec OSW4c 390 kW/kVARL/kVARC RLC Load Banks

Modularity Four modules can be operated independently or in parallel

Basic Specifica+ons •  Voltage: 0 – 346 Vl-‐n / 600 Vl-‐l •  Frequency:

o  L and C: 45 – 65 Hz o  R: DC – 400 Hz

•  Power: o  390 kW/kVAR @ 346/600 V 3ɸ o  250 kW/kVAR @ 277/480 V 3ɸ o  47 kW/kVAR @ 120/208 V 3ɸ o  47 kW/kVAR @ 120 V 1ɸ

•  Resolu1on o  234 W/VAR @ 346/600 V 3ɸ o  150 W/VAR @ 277/480 V 3ɸ o  28 W/VAR @ 120/208 V 3ɸ o  10 W/VAR @ 120 V 1ɸ

•  Phase Configura1on: o  Balanced or Unbalanced 3ɸ o  Single Phase o  Split-‐Phase

•  PHIL Interface: Digital kW/kVAR commands

•  Sobware Interface: o  Load Profile Entry

•  Cooling: Air-‐cooled

18

PV

Energy Storage


AC Loads

Aux / DC Loads

GS

Local Controller


DC REDB AC REDB




M M


ESIFEquipment



Real-TimeSimulator

LocalUser Interface

Ipv Id Rp

Rs

V

I

Market Pricing


GSAC Device Models


1.5 MW PV Simulator

27

19

1.5 MW PV Simulator Basic Specifica+ons (MTD1000-‐250) •  Voltage: 25 – 1000 V (up to 4000 V) •  Current: 250 A (up to 1500 A) •  Power Flow: Supply Only •  PHIL Interface: Analog input corresponding

to instantaneous voltage / current waveform command

•  Bandwidth: o  Voltage: 60 Hz o  Current: 45 Hz

•  Slew Rate: o  Voltage: 4 ms for 0 – 63% step o  Current: 8 ms for 0 – 63% step

•  Load Transient Response: 10 ms to recover to within ± 1% of regulated output with a 50 – 100% or 100 – 50% load step

•  Load Regula1on: o  Voltage: ±0.01% of full scale o  Current: ±0.04% of full scale

•  Sobware Interface: o  PV IV Curve Emula*on o  Profile Genera*on

•  Cooling: Air-‐cooled

Manufacturer and Base Model Magna-‐Power MTD1000-‐250 (250 kW)

Modularity Six Modules capable of independent, parallel, or series opera*on (up to 4000 V)

20

PV

Energy Storage


AC Loads

Aux / DC Loads

GS

Local Controller


DC REDB AC REDB




M M


ESIFEquipment



Real-TimeSimulator

LocalUser Interface

Ipv Id Rp

Rs

V

I

Market Pricing


GSAC Device Models


660 kW DC Supply 27

21

660 kW Badery/PV Simulator Basic Specifica+ons (AC2660P) •  Voltage: 264 – 1000 V (up to 2000 V) •  Current: 2500 A (up to 5000 A) •  Power Flow: Bi-‐direc*onal •  PHIL Interface: Digital voltage,

current, irradiance, and/or temperature commands

•  Bandwidth: •  Slew Rate: •  Load Regula1on:

o  Steady-‐state: ±0.5% o  Transient: ±3%

•  Load Transient Response: < 10 ms for 10 – 90% or 90 – 10% load step

•  Bandwidth: o  Voltage Control: 180 Hz (500 Hz) o  Current Control: 2.0 kHz (2.5 kHz)

•  Sobware Interface: o  PV IV Curve Emula*on o  Batery Emula*on o  Profile Genera*on

•  Cooling: Liquid-‐cooled

Manufacturer and Base Model Anderson Electric Controls AC2660P (660 kW)

Modularity Currently one module, future two modules capable of independent, parallel or series opera*on

22

Addi1onal Equipment •  PV Simulators

–  100 kW Ametek TerraSAS •  DC Supplies

–  250 kW AeroVironment AV-‐900 •  Load Banks

–  100 kW R-‐L (portable) –  100 kW R (portable)

•  Small grid simulators –  (3) 45 kW Ametek MX45 –  (4) 50 kW Pacific Power –  15 kW Elgar

•  Diesel generators –  125kVA and 80 kVA Onan/Cummins –  300kVA Caterpillar

•  Hydrogen Systems –  Electrolyzers: 50kW, 10kW –  Storage tanks –  Fuel cells

•  Real-‐Time Digital Simulators –  Opal-‐RT (3 racks) –  RTDS (1 rack)

23

ESIF Laboratories

High Performance Compu1ng, Data Analysis, and Visualiza1on

16.  ESIF Control Room 17.  Energy Integra*on Visualiza*on 18.  Secure Data Center 19.  High Performance Compu*ng

Data Center 20.  Insight Center Visualiza*on 21.  Insight Center Collabora*on

Fuel Systems Laboratories 9.  Energy Systems Fabrica*on 10.  Manufacturing 11.  Materials Characteriza*on 12.  Electrochemical

Characteriza*on 13.  Energy Systems Sensor 14.  Fuel Cell Development &

Test 15.  Energy Systems High

Pressure Test

Thermal Systems Laboratories 6.  Thermal Storage Process and

Components 7.  Thermal Storage Materials 8.  Op*cal Characteriza*on

Electrical Systems Laboratories 1.  Power Systems Integra*on 2.  Smart Power 3.  Energy Storage 4.  Electrical Characteriza*on 5.  Energy Systems Integra*on

24

ESIF Research Infrastructure Research Electrical Distribu*on Bus – REDB (AC 3ph, 600V, 1600A and DC +/-‐500V, 1600A) Thermal Distribu*on Bus Fuel Distribu*on Bus Supervisory Control and Data Acquisi*on (SCADA)

25

Research Electrical Distribu1on Bus (REDB)

AC • 4-wire plus ground

• Floating or grounded neutral

• 600 Vac

• 16 Hz to 400 Hz

• 250A and 1600A installed

• 250A and 2500A planned (future)

• 4-pole switches

• Connects PSIL, SPL, ESL, GSE, LBE, LVOTA, MVOTA, ESIL

DC • 3-wire plus ground

• Any pole may be grounded

• ±500Vdc or 1000Vdc

• 250A and 1600A installed

• 250A and 2500A planned (future)

• Experiment connection via cart contactor/fuse or direct (main lug only)

• Connects PSIL, SPL, ESL, PVE, LVOTA, MVOTA, ESIL

26

Example Racetrack and Lab Sec1on

PSIL Lateral A PSIL Lateral B PSIL Ladder Tie Switch

PSIL Ladder B Switch PSIL Ring Bus Switch

PSIL Ring Bus Switch

PSIL Ladder A Switch

PSIL Ladder Rung

UC Ring Bus Switch

Neighboring Ring Bus Switch for the UC

UC Lateral

Ring-‐*e Ring-‐*e

27

REDB Switchgear Room (AC)

27

28

Busway Connec1ons in PSIL

29

Outline




30

Discrete Hardware UI Test

30

Prac1cal Limita1ons: •  RLC load bank overall (and step size) power level •  Discrete elements in RLC load bank •  Execu*on *me for large number of cases

31

PHIL-‐based UI Test

31

Advantages: •  Specialized RLC load bank no

longer needed (though power amplifier and RTS required)

•  Tuning of RLC load bank much more precise with modeled elements instead of discrete elements

•  Execu*on *me for a single test is much faster and tests can be automated

32

Results (1-‐ph) – qf = 1

32

breaker in the hardware test does not always occur on a zero crossing, but always does

in the PHIL case (the reason for phase o↵set in the results of the first two cases),

variance of trip time within a cycle or two is to be expected. All three cases are very

closely matched time-wise between the hardware and PHIL tests; the first two are

within one cycle and the third is nearly matched.

−0.2 −0.15 −0.1 −0.05 0 0.05 0.1 0.15 0.2−20

−15

−10

−5

0

5

10

15

20

Time (s)

Cur

rent

(A

)

Inverter Current versus Grid Current

hw−iinv

phil−iinv

hw−igrid

phil−igrid

−0.2 −0.15 −0.1 −0.05 0 0.05 0.1 0.15 0.2−400

−300

−200

−100

0

100

200

300

400

Time (s)

Vol

tage

(V

)

Vpcc Voltage

hw−v

phil−v

Figure 5.9: Results from the task 1 unintentional islanding test for qf = 1.04

One will notice that the grid current (igrid) for the discrete hardware and PHIL tests

does not match perfectly. This is because the EPS model used in the two cases was not the

same; in the discrete hardware case, the EPS was the hardware power amplifier, while, in the

PHIL case, the EPS model was just an ideal voltage source. In any case, what really matters

108

1. B. Lundstrom, B. Mather, M. Shirazi, and M. Coddington, “Methods and Implementa*on of Advanced Uninten*onal Islanding Tes*ng using Power Hardware-‐in-‐the-‐Loop (PHIL),” in IEEE PVSC, 2013. 2. B. Lundstrom, M. Shirazi, M. Coddington, and B. Kroposki, “An Advanced Plazorm for Development and Evalua*on of Grid Interconnec*on Systems using Hardware-‐in-‐the-‐Loop: Part III–Grid Interconnec*on System Evaluator,” in IEEE Green Technologies Conference, Denver, CO, April 2013.

33

Results (1-‐ph) – qf = 2.84

33

−0.2 −0.15 −0.1 −0.05 0 0.05 0.1 0.15 0.2−20

−15

−10

−5

0

5

10

15

20

Time (s)

Cur

rent

(A

)


hw−iinv

phil−iinv

hw−igrid

phil−igrid

−0.2 −0.15 −0.1 −0.05 0 0.05 0.1 0.15 0.2−400

−300

−200

−100

0

100

200

300

400

Time (s)

Vol

tage

(V

)

Vpcc Voltage

hw−v

phil−v


109


34

Results (1-‐ph) – qf = 4.35

34

−0.2 −0.15 −0.1 −0.05 0 0.05 0.1 0.15 0.2−20

−15

−10

−5

0

5

10

15

20

Time (s)

Cur

rent

(A

)


hw−iinv

phil−iinv

hw−igrid

phil−igrid

−0.2 −0.15 −0.1 −0.05 0 0.05 0.1 0.15 0.2−400

−300

−200

−100

0

100

200

300

400

Time (s)

Vol

tage

(V

)

Vpcc Voltage

hw−vphil−v


110


35

Results (1-‐ph) – repe11on of qf = 2.84 case

35

is that the inverter’s response matches in both hardware and PHIL tests. This was the case,

so no emphasis was placed on trying to use the same EPS model in both cases to get better

matching between the grid currents of the two tests. In terms of repeatability, the results of

five runs of the same test case (qf = 2.84) using the PHIL method are shown in Figure 5.12.

It can be seen that the PHIL is very repeatable. Again, a small variance (1-2 cycles) in trip

times is expected due to the variance in the inverter’s anti-islanding algorithms. In all, these

results show very clearly that the PHIL and discrete hardware methods match very closely

and that the PHIL technique is repeatable, validating the PHIL approach.

−0.1 −0.05 0 0.05 0.1 0.15 0.2−20

−15

−10

−5

0

5

10

15

20Currents

1

2

3

4

5

−0.1 −0.05 0 0.05 0.1 0.15 0.2−400

−300

−200

−100

0

100

200

300

400Voltages

1

2

3

4

5

Figure 5.12: Inverter current and voltage from repeated tests of the task 1 unintentionalislanding test for qf = 2.84

111

Consistency of Results

36

Results (1-‐ph) – repe11on of qf = 2.84 case

36

Precision of Circuit Model (Tuning) in PHIL

%%)%&* %%)%&*' %%)%&+ %%)%&+' %%)%&, %%)%&,' %%)"

-%$

$

%$

�� (�

��-��

��

Figure 5.13: Results from the task 2 unintentional islanding test for qf ⇠= 1 with a poorly-tuned RLC load (igrid1 ⇠= 0.02 · iinv,FL)

113

qf = 1 (discrete HW tuning) Trip in 0.156s

��

��

�

��

(��

Figure 5.14: Results from the task 2 unintentional islanding test for qf ⇠= 1 with a well-tunedRLC load (igrid1 ⇠= 0.002 · iinv,FL)

114

qf = 1 (well tuned in SW) Trip in 1.08s

limit of IEEE Std 1547-2003 [18]. When repeating the same test, but for a quality factor

of 5, the inverter never detected the island condition and continued to operate indefinitely.

These results confirm that the variable RLC load PHIL approach is e↵ective for achieving

conditions di�cult to replicate with discrete hardware and that the technique is applicable

over a wide range of quality factors.

�� !" �� !# ��$ ��$!% ��$! ��$!" ��$!# ��" ��"!% ��"! ��"!"

&�'

'

�'

��

Figure 5.15: Results from the task 2 unintentional islanding test for qf ⇠= 3 with a well-tunedRLC load (igrid1 ⇠= 0.002 · iinv,FL)

115

qf = 3 (well tuned in SW) Trip in 1.8s

qf = 5 (well tuned in SW) Ran indefinitely

37

Hardware: •  (EUT) Advanced Energy 500TX 500 kW PV Inverter

•  810 kVA Grid Simulator with analog control

•  1.5 MW PV Simulator •  1 MVA (150 VA) RLC Load Bank

•  LEM current and voltage transducers

Real-‐1me Modeling: •  Opal-‐RT eMegaSim RTS •  Real-‐*me model developed in SimPowerSystems (no co-‐simula*on)

•  ITM interface •  Phase compensa*on •  HW feedback filtering •  33 μs < Ts < 66 μs

PV Simulator

AC RLC Load BankInverterLocal PCC Model

Grid Simulator

M

Local Controller

Grid Model

DC R

EDB

M

AC REDB

VpccIinv

Vpcc

Vpcc

Iinv

StaticPV Array

Uninten1onal Islanding PHIL: Test Setup

38

Uninten1onal Islanding PHIL: Test Setup

39

Results (3-‐ph) – Best Comparison Example

40

Preliminary Results (3-‐ph) – Spread

0 100 200 300 400 500 600 700

PHIL-‐UF

PHIL-‐OF

HW-‐UF

HW-‐OF

Trip Time (ms) for same RLC Load Condi*on

Also see: M. Steurer et. al., “Progress on PHIL based An*-‐Islanding Tes*ng of PV Converters”. Proceedings of Second Interna8onal Workshop on Grid Simulator Tes8ng of Wind Turbine Drivetrains. Available: htp://www.nrel.gov/electricity/transmission/grid-‐simulator-‐workshop-‐2.html for similar results on smaller converter

41

Outline




42

PHIL Co-‐simula1on: Mo1va1on

•  Leverage benefits of PHIL: o  Examine system-‐level and mul*-‐device impacts o  Repeatability of complex scenarios o  Flexible, modular

•  But add: o  Simplify model conversion o  Allow use of more complex, mul*-‐discipline system models without simplifica*on or abstrac*on

o  Connec*on/link of mul*ple sites into a single PHIL simula*on

•  Within limita1ons

43

A Testbed for Distributed Integra1on

•  Arbitrary Grid o  Loca*on o  Topology & Equipment

•  Any scenario o  Rou*ne o  Con*ngency

•  Actual Hardware o  No (proprietary) model required

•  Co-‐simula1on o  U*lize exis*ng off-‐the-‐shelf so|ware with no model conversion required

25

Grid Interconnec*on Hardware Simula8on

Power System Simula*on

Computer Model

Device(s) Under Test

Device Under Test Device(s) Under Test

Co-‐Simula*on

PHIL Simula*on

44

GridLAB-D Electric Distribution System ModelRunning in Real-Time Mode

PV Inverter 1

PV Simulator 1

Phase A

Phase C

Phase BN

Load Bank 1

Grid Simulator

ControlSet points

Measurements

NREL

PNNL

Weather Data

InverterCurrents

PCC Voltages

PV Inverter 2

PV Simulator 2

Load Bank 2

InverterCurrent

7200V Primary 3-phase

75 kVASplit-phase

Center-tappedTransformers

Triplex Nodes

HomesInverter 2Inverter 1 Homes

VPCC1 VPCC2

IEEE 8500 Node Feeder with Building Loads Phase A Phase C

Triplex Line

Hardware under Test (HUT)

FPGA-based I/O

JSON-Link UDP/IP Communication over Ethernet

Grid PCC Model Weather Model

Real-Time Simulator

VPN Tunnel

PV Model

200

400

600

800

1000

1200IEEE8500 Inverter 2 Time Series

PO

A Ir

radi

ance

(W/m

2 )

20

30

40

50

60

70

80

Rea

l Pow

er(k

W)

−50

−40

−30

−20

−10

0

10

Rea

ctiv

e P

ower

(kV

Ar)

12:47 12:48 12:49 12:50 12:51 12:52240

245

250

255

260

265

270P

CC

Vol

tage

(V

)

Time (MDT)

No Solar PF=1 PF=0.81 absorbing Volt/VAR Control

28

45

27

Test Case # 3: Three-phase Inverter • IEEE 8500-node test feeder

- One 7 kVA real-inverter output scaled up to 140 kVA in GridLAB-D simulation

- This hardware inverter was operating in VVC

- Added a large number small UPF inverters; combined output of 800 kW

• Cloud transient was implemented based on historical weather data

• The hardware inverter with VVC was capable of maintaining constant voltage on the secondary

12:35 12:40 12:45122

123

124

125

126

127

128

|V| m

ax

Maximum voltage magnitude on secondary system

no solar base case

distributed PF=1.0 solar

distributed PF=1.0 solar and VVC solar

0

500

1000

1500

Irra

dia

nce

(W/m

2)

10

20

30

40

50

Ph

ase

A R

eal

Po

wer

(kW

)

-40

-20

0

20

Ph

ase

A R

eact

ive

Po

wer

(kV

Ar)

12:35 12:40 12:45275

280

285

290

Ph

ase

A |V

| at

PC

C(V

)

base PF=1.0 PF=0.81

Figure 4 shows power generation and |V| at the inverter PCC over a 10-minute period with a cloud transient. As in the case of the single-phase inverters, voltage increases as compared to the no-solar base case when the inverter is operated with PF = 1.0. Unlike in the single-phase inverter case described above, the PF = 0.81 case is not well-tuned to control voltage with this combination of inverter output and PCC location. This demonstrates how operating in a fixed-PF mode, while it has the benefits of simplicity, will not result in optimal behavior. The impact to the distribution feeder’s voltage profile will differ depending on the interaction of the PV output under changing irradiance conditions, the inverter size, and the characteristics of the feeder at the PCC. B.2 Hardware inverter with additional modeled solar

The voltage on the secondary system can be studied under different PV penetration scenarios. In systems without distributed generation (DG), power flow is unidirectional, and voltage may drop up to 3V from the transformer to the meter due to the impedance of the triplex cable [12]. In systems with DG, there may be local reverse power flow in the triplex line, potentially leading to over-voltage problems. ANSI C84.1 defines acceptable operating envelope for steady-state voltage levels as 95-105% of nominal voltage [19], which may be violated when there is reverse power flow [20].

Because the simulated electrical distribution systems modeled in GridLAB-D include detailed models of secondary service transformers and triplex cables, the PHIL test platform described here is well-suited to study how new modes of inverter control affect voltages on the secondary system.

Figure 5 shows the maximum voltage at any point in the secondary system. The modeled system is the IEEE 8500-node test feeder. Three cases are considered. 1. Base case. In the base case (black trace), no solar PV is added to the system, and the voltage is well within acceptable limits and almost constant over a 10-minute period. 2. Modeled distributed solar PV. High levels of modeled distributed solar PV generation are added to the base case (blue trace), with inverters operating at PF = 1.0. Each residential load is given a solar PV array of 15-30% of its total square footage, leading to a net feeder real power demand of near 0W during the 10-minute time period shown. The voltage on the backbone is held to normal levels by the action of the voltage regulators. The maximum voltage on the secondary system rises to over 125.2V and at the cloud transient shortly after 12:40, the maximum voltage tracks the irradiance levels. 3. Modeled distributed solar PV and hardware inverter. Case 2 is used as the model distribution system for a PHIL test case (red trace), where the three-phase hardware inverter is operated in VVC mode, modifying Q in response to |V| at the PCC. The distributed PV at unity PF have a combined power output of 800kVA; the hardware PV contribution is scaled up in software to a maximum power of 140kVA. The action of the hardware inverter in VVC mode has the effect of maintaining the maximum voltage on the secondary system at

a constant level through the cloud transient, mitigating some of the effects of the unity power factor solar PV.

IV. ADDITIONAL APPLICATIONS OF PHIL PLATFORM

In addition to the examples discussed above, there are many system-level quantities and phenomena that may be studied with this type of PHIL test platform. Two additional examples are briefly described in this section: the effect of an inverter’s control mode on actions of other voltage control devices throughout the feeder and the feeder-wide voltage profile.

A. Effect of Solar PV on Voltage Control Devices

The impact of high-penetration levels of solar PV on the actions of voltage control devices is of concern to utilities. High-penetration levels of solar PV may cause increased tap changes or switching operations, resulting in higher maintenance costs and decreased equipment lifetimes. Quasi-static time-series simulations have been used to study this effect [21], and show a range of impacts depending on feeder characteristics, solar PV size and placement, and inverter control mode. Changes in tap counts are highly sensitive to these parameters, making it important to use accurate representation of advanced inverter control modes in conjunction with detailed voltage control device and feeder power flow models. In situations where adequate models may not exist, as in the case of newly developed control modes, a PHIL test platform can provide the necessary accuracy, and has the additional advantage of being able to test a wide array of electric distribution system configurations.

In the test cases described in Section III, the output of the hardware inverters does not change in response to a cloud transient sufficiently to cause additional tap changes.

12:35 12:40 12:45122

123

124

125

126

127

128

|V| m

ax

Maximum voltage magnitude on secondary system

no solar base case

distributed PF=1.0 solar

distributed PF=1.0 solar and VVC solar

Figure 5: Maximum voltage magnitude at any point in the secondary system, for three different solar PV penetration scenarios.

29

46

Distributed Control of Energy Storage •  NREL integrated Power Hardware in the Loop (PHIL)

simula1on of energy storage + PV with residen1al inverter •  ±10kW badery + 10kW PV •  123 node grid simula1on

© CYME International, June 2011

CYME QA Validation Tests CasesLoad Flow -Unbalanced - IEEE 123 Node Test Feeder

CYME Power Engineering Software

A self-contained study file (.sxst) to use with this document is provided. The explanations below are based on the use of that file.

n Highlights

x Comparison between CYME Load flow analysis voltage drop unbalanced method results against those published in the document “IEEE 123 node test feeder” by IEEE Distribution system analysis subcommittee.

x Simulation includes comparison of results obtained with the method of voltage drop unbalanced: line currents and bus voltages.

x 123 bus system with overhead and underground line segments with various phasing , unbalanced loading with all combinations of load types (PQ, constant I, constant Z), four step-type voltage regulators, shunt capacitor banks and switching to provide alternate paths of power-flow.

o Load Flow Analysis

1. Open the IEEE_123_node_test_feeder.sxst self-contained study file. To do so, go to the the dialog box displayed using the Help > Validation Cases menu option. Select the “Load Flow - Unbalanced” option in the List of test cases and enable the check box next to the file name. Click on the Start Case button.

2. Select the Analysis > Load Flow menu option. Ensure that the Calculation Method is Voltage Drop – Unbalanced. Leave all the other parameters intact.

3. Click on to Run the analysis.

IEEE 123 Node Feeder Model

47

28

Panorama of Complete Hardware Setup

Three-phase Setup

Real-time System (Opal-RT)

Grid Simulator

Single-phase Setup

30

48

Thank you

Blake Lundstrom [email protected]

33

advanced(laboratory(tes1ng(methods( · pdf fileadvanced(laboratory(tes1ng(methods ... outside...

Documents