Advanced Operating Systems - Spring 2009Lecture 17 – March 16, 2009Dan C. Marinescu

Email: dcm@cs.ucf.eduOffice: HEC 439 B. Office hours: M, Wd 3 – 4:30 PM.

TA: Chen YuEmail: yuchen@cs.ucf.eduOffice: HEC 354. Office hours: M, Wd 1.00 – 3:00 PM.

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Last, Current, Next Lecture Last time:

M/M/m systems Scheduling Algorithms

Today Memory management

Next time: Caching and Virtual Memory

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Scheduling algorithms

A scheduling problems is defined by : The machine environment A set of side constrains and characteristics The optimality criterion

Machine environments: 1 One-machine. P Parallel identical machines Q Parallel machines of different speeds R Parallel unrelated machines O Open shop. m specialized machines; a job requires a

number of operations each demanding processing by a specific machine

F Floor shop

)()(

)(

),,(

One-machine environment

n jobs 1,2,….n. pj amount of time required by job j.

rj the release time of job j, the time when job j is available for processing.

wj the weight of job j.

dj due time of job j; time job j should be completed.

A schedule S specifies for each job j which pj units of time are used to process the job.

CSj the completion time of job j under schedule S.

The makespan of S is: CSmax = max CS

j The average completion time is

n

j

SjCn 1

1

One-machine environment (cont’d)

Average weighted completion time:Optimality criteria minimize:

the makespan CSmax

the average completion time :The average weighted completion time:

the lateness of job j maximum lateness of any

job under schedule S. Another optimality criteria, minimize maximum lateness.

n

j

SjjCw

1

n

j

SjC

1

n

j

SjjCw

1

Sj

nj LL 1max max j

Sjj dCL

Priority rules for one machine environmentTheorem: scheduling jobs according to SPT – shortest

processing time is optimal for

Theorem: scheduling jobs in non-decreasing order of is optimal for

jjCw||1 j

j

p

w

jC||1

Earliest deadline first (EDF)Dynamic scheduling algorithm for real-time OS. When a scheduling event occurs (task finishes, new

task released, etc.) the priority queue will be searched for the process closest to its deadline. This process will then be scheduled for execution next.

EDF is an optimal scheduling preemptive algorithm for uniprocessors, in the following sense: if a collection of independent jobs, each characterized by an arrival time, an execution requirement, and a deadline, can be scheduled (by any algorithm) such that all the jobs complete by their deadlines, the EDF will schedule this collection of jobs such that they all complete by their deadlines.

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EDF

8

11

n

j jp

djU

Process Execution Time Period

P1 1 8

P2 2 5

P3 4 10

The schedulability test for EDF is:

In this case U = 1/8 +2/5 + 4/10 = 0.925 = 92.5%

It has been proved that the problem of deciding if it is possible to schedule a set of periodic processes is NP-hard if the periodic processes use semaphores to enforce mutual exclusion.

Priority InversionA high priority process is blocked by a lower

priority one.Example: J1 and J3 share a data structure

guarded by a binary semaphore S.prty(J1) > prty(J2) > prty(J3).J1 in initiated while J3 is in its critical sectionWhen J1 attempts to enter the critical section it is

blocked.The duration of this blocking cannot be determined

as because J3 can be preempted by a higher priority job J2. prty

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Memory ManagementArchitectural backgroundSwapping Contiguous memory allocationPagingSegmentationCase studies:

The Intel PentiumLinux

Multistep Processing of a User Program

Architectural background

Program must be brought (from disk) into memory and placed within a process for it to be run

CPU can access directly only Main memory and registers.

Register access in one CPU clock (or less)Main memory can take many cyclesCache sits between main memory and CPU

registers

Base and limit Registers delimit logical address space Base register start of logical address space

Limit register end of logical address space

Address binding of instructions and data to memory addresses

Absolute code Object code in a form suitable for direct execution. Relocatable code Object code that can be run from any memory

location. Compile time If memory location known a priori, absolute

code can be generated; must recompile code if starting location changes

Load time Must generate relocatable code if memory location is not known at compile time

Execution time Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limit registers)

Logical vs. Physical Address SpaceAddress space a range of discrete addresses; may

correspond to a physical or virtual memory register, a network host, disk sector or other logical or physical entity.

Virtualization of addressingLogical (virtual) address generated by the CPUPhysical address address seen by the memory unit

A user program deals with logical addresses; it never sees the real physical addresses.

Logical and physical addresses are the same in compile-time and load-time address-binding

schemes differ in execution-time address-binding scheme

Memory-Management Unit (MMU)Hardware device that maps virtual to

physical address

In MMU scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory

Dynamic relocation with a relocation register

Dynamic Loading

Routine is not loaded until it is calledBetter memory-space utilization; unused routine is

never loadedUseful when large amounts of code are needed to

handle infrequently occurring casesNo special support from the operating system

required; implemented through program design

Dynamic linking

Linking postponed until execution time. A stub is used to locate the appropriate memory-resident library routine. Particularly useful for libraries; also known as shared libraries

Stub replaces itself with the address of the routine, and executes the routine

Operating system needed to check if routine is in processes’ memory address.

SwappingBacking store fast disk providing direct access to

copies of all memory images for all processes in the system. Swap out A process moved temporarily out of memory to

a backing store. Swap in The process is brought into memory for

continued execution.Roll out, roll in swapping variant used for priority-based

scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed.

Swap time time to transfer the process, proportional to amount of memory swapped.

Ready queue queue of processes which have memory images on disk and are ready to run. Maintained by the operating system.

Versions of swapping found in UNIX, Linux, and Windows.

Swapping

Contiguous AllocationMain memory usually into two partitions:

Resident operating system, usually held in low memory with interrupt vector

User processes then held in high memory

Relocation registers used to protect user processes from each other, and from changing operating-system code and data

Base register contains value of smallest physical address

Limit register contains range of logical addresses – each logical address must be less than the limit register

MMU maps logical address dynamically

HW address protection with base and limit registers

Multiple-partition contiguous allocationHole block of available memory; holes of

various size are scattered throughout memoryWhen a process is loaded it is allocated

memory from a hole large enough to accommodate it

Operating system maintains information about:a) allocated partitions b) free partitions (hole)

OS

process 5

process 8

process 2

OS

process 5

process 2

OS

process 5

process 2

OS

process 5

process 9

process 2

process 9

process 10

Dynamic storage allocation

First-fit Allocate the first hole that is big enoughBest-fit Allocate the smallest hole that is big

enough; must search entire list, unless ordered by size. Produces the smallest leftover hole

Worst-fit Allocate the largest hole; must also search entire list . Produces the largest leftover hole

How to satisfy a request of size n from a list of free holes

First-fit and best-fit better than worst-fit in terms of speed and storage utilization

Fragmentation

External Fragmentation total memory space exists to satisfy a request, but it is not contiguous

Internal Fragmentation allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used

Compaction Reduces external fragmentation: How it shuffle memory contents to place all free memory

together in one large block Limits possible only if relocation is dynamic, done at

execution time I/O problem

Latch job in memory while it is involved in I/O Do I/O only into OS buffers

Noncontiguous logical address space Paging

Frames blocks of physical memory of fixed-size (512 - 8,192 bytes)

Pages blocks of logical memory of same size.What the memory management must do:

Keep track of all free frames To run a program of n pages find n free frames and load

program Set up a page table to translate logical to physical addresses Address internal fragmentation

Dynamic address translation (DAT)Address generated by CPU is divided into:

Page number (p) – used as an index into a page table which contains base address of each page in physical memory

Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit.

For given logical address space 2m and page size 2n

page number page offset

p d

m - n n

Paging Hardware

Mapping logical to physical memory

Example

32-byte memory and 4-byte pages

Free Frames

Before allocation After allocation

Page Table

Page table is kept in main memory.Page-table base register (PTBR) points to the page tablePage-table length register (PRLR) indicates size of the

page table In this scheme every data/instruction access requires two

memory accesses. One for the page table and one for the data/instruction.

Translation look-aside buffers (TLBs) special fast-lookup hardware cache called associative memory. Helps solve the two memory access problem can be solved by the use of a or

Some TLBs store address-space identifiers (ASIDs) in each TLB entry – uniquely identifies each process to provide address-space protection for that process.

Associative Memory Associative memory – parallel search

Address translation (p, d)If p is in associative register, get frame #

outOtherwise get frame # from page table in

memory

Page # Frame #

Dynamic address translation with TLB

Effective Access Time

Associative Lookup = time unit Assume memory cycle time is 1 microsecond Hit ratio percentage of times that a page is found

in TLB Hit ratio = Effective Access Time (EAT)

EAT = (1 + ) + (2 + )(1 – )= 2 + –

Memory ProtectionMemory protection protection bit for each frameValid-invalid bit attached to each entry in the page

table:valid legal page; the page is in the process’ logical

address space. invalid the page is not in the process’ logical address

space

Shared PagesShared code

One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems).

Shared code must appear in same location in the logical address space of all processes

Private code and data Each process keeps a separate copy of the code and dataThe pages for the private code and data can appear

anywhere in the logical address space

Example

Structure of the Page Table

Hierarchical PagingHashed Page TablesInverted Page Tables

Hierarchical Page TablesBreak up the logical address space into multiple

page tablesA simple technique is a two-level page table

Example

A logical address (on 32-bit machine with 1K page size) is divided into: a page number consisting of 22 bits a page offset consisting of 10 bits

Since the page table is paged, the page number is further divided into: a 12-bit page number a 10-bit page offset

Thus, a logical address is as follows:

where pi is an index into the outer page table, and p2 is the displacement within the page of the outer page table

page number page offset

pi p2 d

12 10 10

DAT with a two level page table scheme

Three-level Paging Scheme

Hashed Page TablesCommon when logical address spaces > 32 bitsThe virtual page number is hashed into a page table. This page

table contains a chain of elements hashing to the same location.Virtual page numbers are compared in this chain searching for

a match. If a match is found, the corresponding physical frame is extracted.

Inverted Page Table

One entry for each real page of memoryEntry consists of the virtual address of the page

stored in that real memory location and the process that owns that page.

Decreases memory needed to store each page table. Increases time needed to search the table.

Use hash table to limit the search to one — or at most a few — page-table entries

Inverted Page Table

Segmentation Memory-management scheme that supports user view of

memory. Program collection of segments. Segment logical unit such as:

main program, procedure,

function, method, object, local variables,

global variables, common block, stack, symbol table,

arrays

Logical View of Segmentation

1

3

2

4

1

4

2

3

user space physical memory space

Segmentation Architecture Logical address <segment-number, offset>, Segment table maps two-dimensional

physical addresses; each table entry has: base the starting physical address of the

segment limit the length of the segment

Segment-table base register (STBR) points to the segment table’s location in memory

Segment-table length register (STLR) the number of segments used by a program; segment number s is legal if s < STLR

Protection for segmentation

ProtectionWith each entry in segment table associate:

validation bit = 0 illegal segment read/write/execute privileges

Protection bits associated with segments; code sharing occurs at segment level

Since segments vary in length, memory allocation is a dynamic storage-allocation problem

A segmentation example is shown in the following diagram

Segmentation Hardware

Example

Case study: Intel PentiumSupports

segmentation and segmentation with paging

CPU generates logical address passed on to the segmentation unit which produces linear addresses passed on to paging unit which generates physical address in main memory.

Intel Pentium Segmentation

Pentium Paging Architecture

Linear Address in LinuxBroken into four parts:

Three-level Paging in Linux