advanced logic design techniques in asynchronous ... logic design techniques in asynchronous...
TRANSCRIPT
Advanced Logic Design Techniques
in
Asynchronous Sequential Circuit Synthesis
Charles R. Bondhttp://www.crbond.com
c©1990 – 2013, All rights reserved.
Contents
I Synthesis Methods 4
1 Development of Methods and Techniques 71.1 Derivation and Construction of a ‘T’ Flip-Flop . . . . . . . . . . 7
1.1.1 The Flow Table . . . . . . . . . . . . . . . . . . . . . . . . 71.1.2 The Secondary Equations . . . . . . . . . . . . . . . . . . 91.1.3 Implementing the ‘T’ Flip-Flop . . . . . . . . . . . . . . . 10
1.2 ‘D’ Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.2.1 The Flow Table . . . . . . . . . . . . . . . . . . . . . . . . 121.2.2 The Circuit Equations . . . . . . . . . . . . . . . . . . . . 141.2.3 A Digression on Hazards . . . . . . . . . . . . . . . . . . . 151.2.4 Location and Identification of Signals . . . . . . . . . . . 211.2.5 Asynchronous Set and Clear . . . . . . . . . . . . . . . . . 21
1.3 Negative Pulse Generator . . . . . . . . . . . . . . . . . . . . . . 231.3.1 The Flow Table . . . . . . . . . . . . . . . . . . . . . . . . 231.3.2 Equations and Implementation . . . . . . . . . . . . . . . 241.3.3 Analysis of Implementation . . . . . . . . . . . . . . . . . 24
1.4 Up-Down Counter Controller . . . . . . . . . . . . . . . . . . . . 251.4.1 The Flow Table . . . . . . . . . . . . . . . . . . . . . . . . 251.4.2 Equations and Implementation . . . . . . . . . . . . . . . 27
1.5 A Phase/Frequency Detector . . . . . . . . . . . . . . . . . . . . 291.5.1 The Flow Table . . . . . . . . . . . . . . . . . . . . . . . . 291.5.2 The Equations . . . . . . . . . . . . . . . . . . . . . . . . 32
2 The Complete Synthesis Method 37
3 Miscellaneous Problems and Solutions 403.1 Clock Stream Switch . . . . . . . . . . . . . . . . . . . . . . . . . 403.2 Two-Phase Clock Generator . . . . . . . . . . . . . . . . . . . . . 423.3 Glitch Suppressor . . . . . . . . . . . . . . . . . . . . . . . . . . . 443.4 Digital Single Shot . . . . . . . . . . . . . . . . . . . . . . . . . . 453.5 Master/Slave J-K Flip-Flop . . . . . . . . . . . . . . . . . . . . . 47
3.5.1 The Flow Table . . . . . . . . . . . . . . . . . . . . . . . . 473.5.2 The J-K Flip-Flop Circuit Equations . . . . . . . . . . . . 49
3.6 Edge-Triggered J-K Flip-Flop . . . . . . . . . . . . . . . . . . . . 53
1
3.6.1 The Flow Table . . . . . . . . . . . . . . . . . . . . . . . . 533.6.2 Edge-Triggered J-K Flip-Flop Flow Table . . . . . . . . . 533.6.3 The Circuit Equations . . . . . . . . . . . . . . . . . . . . 543.6.4 The Implementation . . . . . . . . . . . . . . . . . . . . . 55
II Analysis Methods 58
4 Sequential Circuit Analysis 594.1 Fundamental Properties of Secondary Variables . . . . . . . . . . 594.2 An Outline of the Analysis Method . . . . . . . . . . . . . . . . . 614.3 A Simple Example . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.3.1 Labeling the Circuit Elements . . . . . . . . . . . . . . . . 614.3.2 Writing the Raw Circuit Equations . . . . . . . . . . . . . 614.3.3 Reducing the Equations . . . . . . . . . . . . . . . . . . . 624.3.4 Constructing the Flow Table . . . . . . . . . . . . . . . . 634.3.5 The Circuit Description . . . . . . . . . . . . . . . . . . . 64
4.4 Another Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 644.4.1 The Circuit Equations . . . . . . . . . . . . . . . . . . . . 644.4.2 The Flow Table . . . . . . . . . . . . . . . . . . . . . . . . 65
4.5 Caveats and Cautions . . . . . . . . . . . . . . . . . . . . . . . . 66
2
List of Figures
1.1 NAND Implementation of Y1 . . . . . . . . . . . . . . . . . . . . 101.2 Partial Construction of “T” Flip-Flop . . . . . . . . . . . . . . . 111.3 Construction of ‘T’ Flip-Flop . . . . . . . . . . . . . . . . . . . . 121.4 Implementation of ‘T’ Flip-Flop with Hazard Suppression . . . . 131.5 Implementation of ‘D’ Flip-Flop . . . . . . . . . . . . . . . . . . 151.6 Combining a Signal with its Inverse . . . . . . . . . . . . . . . . 161.7 Suppressing a Hazard by Cancellation . . . . . . . . . . . . . . . 161.8 Combinational Circuit with Undesired Transient . . . . . . . . . 171.9 Combinational Circuit with Subscripted Signal . . . . . . . . . . 181.10 Circuit Solution Providing Hazard Suppression . . . . . . . . . . 181.11 Hazard-free Implementation of ‘D’ Flip-Flop . . . . . . . . . . . . 201.12 Complete Implementation of ‘D’ Flip-Flop with Set and Clear . . 231.13 Negative Pulse Generator . . . . . . . . . . . . . . . . . . . . . . 251.14 Up-Down Counter Controller . . . . . . . . . . . . . . . . . . . . 281.15 Partial Implementation of Phase/Frequency Detector . . . . . . . 341.16 Complete Implementation of Phase/Frequency Detector . . . . . 35
3.1 Clock Stream Switch . . . . . . . . . . . . . . . . . . . . . . . . . 423.2 Timing Diagram for Two-Phase Clock Generator . . . . . . . . . 423.3 Two-Phase Clock Generator . . . . . . . . . . . . . . . . . . . . . 443.4 Positive Glitch Suppressor . . . . . . . . . . . . . . . . . . . . . . 453.5 Timing Diagram for Digital Single Shot . . . . . . . . . . . . . . 453.6 Digital Single-Shot . . . . . . . . . . . . . . . . . . . . . . . . . . 463.7 Implementation of Y1 . . . . . . . . . . . . . . . . . . . . . . . . 493.8 Box Model of Logic Circuit . . . . . . . . . . . . . . . . . . . . . 503.9 Box Model of J-K Flip-Flop . . . . . . . . . . . . . . . . . . . . . 513.10 Partial Implementation of Y2 . . . . . . . . . . . . . . . . . . . . 523.11 Master/Slave J-K Flip-Flop . . . . . . . . . . . . . . . . . . . . . 533.12 1st Partial Implementation of Y2 . . . . . . . . . . . . . . . . . . 553.13 2nd Partial Implementation of Y2 . . . . . . . . . . . . . . . . . . 563.14 Edge-Triggered J-K Flip-Flop . . . . . . . . . . . . . . . . . . . . 57
4.1 Cross-Coupled Flip-Flop (Latch) . . . . . . . . . . . . . . . . . . 604.2 Unknown Circuit with Labels . . . . . . . . . . . . . . . . . . . . 624.3 2nd Example Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 65
3
Part I
Synthesis Methods
4
Introductory Notes
In this paper a number of advanced techniques for solving sequential logic cir-cuit design problems are developed. Special methods are presented for takinga problem from its initial statement to a fully implemented solution. The ob-jective is to find practical solutions for a variety of typical sequential circuitproblems. Each problem begins with a problem statement and proceeds witha flow table description of the desired behavior, the derivation of the circuitequations, and the implementation of those equations using standard logic de-vices. A typical solution will be constructed from some family of logic gatesand inverters. See [Huff 54, Cald 58] for complete information on the flow tablemethod of synthesis. Many of the problems posed here yield solutions whichwill be familiar to the reader. The emphasis is more on ‘how to get there’ thanon whether anyone has been there before. Some complex problems with novelsolutions are also treated, however, and others can be readily developed.
It is assumed that the reader is already familiar with combinational logicproblems and solutions using Boolean algebra and with the use of Karnaughmaps. See [Karn 53] for details. A thorough understanding of DeMorgan’stheorem and its application to logic devices is also assumed.
Some experience with state machines would be helpful, but not necessary, aswe will exclusively use flow tables to specify sequential circuit behavior. Thus,any previous experience in generating flow table descriptions of logic blocks willaid materially in getting through the various exercises. Other synthesis methodscan be found in [Moore 54, Maley 63, Mealey 55].
The reader should be advised that this paper deals with design at the low-est logic level; i.e., we will be designing logic circuits using NAND gates, NORgates, etc. We will not address the higher level problem of building countersfrom flip-flops or state machines from counters. Nor will we deal with the lowerlevel (analog) problem of designing NAND or NOR gates using discrete compo-nents. Typical problems will be the design of flip-flops, arbitraters, synchronousswitches and a variety of other sequential circuit blocks which are used in com-plex digital systems. Treatments of synthesis using higher level logic blocks canbe found in many digital design texts and in [Maley 63, Marc 62, Cald 58].
The terms synchronous and asynchronous are used in a context sensitivemanner. In general, the terms are used to distinguish between logic circuitswhich only change external states following changes in a particular input (clockedor ‘synchronous’ behavior) from those whose external states may change follow-ing changes in any or all inputs (‘asynchronous’ behavior). The circuits wewill design are ‘input driven’, which means that the internal states will changefollowing changes in inputs, and output states may or may not change. Anexternal clock will not be required to trigger state changes, although there isnothing to prevent us from designating one of the circuit inputs as a clock.When designing circuits intended for use in synchronous (clocked) systems, wewill often take one of the inputs as the ‘synchronizer’ (clock) and develop thebehavioral description accordingly.
5
For example, the ‘D’ flip-flop is a standard logic storage element in syn-chronous systems where one input is designated as a clock input. Even thoughthe internals of the flip-flop are asynchronous, the outputs are synchronous withthe clock. However, in the discussions of the flip-flop set and clear signals, wewill refer to those inputs as asynchronous, since they drive the output directly,independent of the clock. In reality, these inputs are neither more nor less asyn-chronous than any other part of the circuit. It is purely a matter of convenienceat a higher level that we create these distinctions.1
One caution should be mentioned. There are no detailed discussions in thispaper about device timing requirements. Specifications for gate delays, rise andfall times, setup and hold time, etc. are beyond the scope of this paper. Infact, such timing issues are crucial in any sequential circuit and it is not alwayspossible to guarantee performance when multiple input changes occur at orabout the same time. Specific timing requirements are entirely implementationdependent and are best determined on completion of the design. No functionalproblems should arise if all gates have approximately the same delay or, as aminimum condition, if the longest gate delay through a single gate is less thanthe shortest delay through two gates. For the most part, the only restriction onrise and fall times is that they should be less than the shortest gate delay.
Plan to review the circuits after they are finished to determine the minimumsetup and hold time requirements for each input. Optimization techniques forlogic minimization and layer reduction should be considered, as well.
Most of the designs have been implemented with NAND gates. There isno requirement for this, except that it often simplifies the descriptions of theimplementation techniques. In some cases, there will be good reasons to makeuse of other logic blocks, and in those cases we will not hesitate to do so.
Although the primary objective of this paper is to develop design methods,in Part II a method for analyzing existing circuits is presented. The techniquesused to derive circuit equations from existing sequential circuits are not generallycovered in existing texts and appear to be unknown to many designers. For somereaders this section will provide a useful complement to the core material.
I wish to thank Frank Brown for his many suggestions which have resultedin a materially improved paper.
1Perhaps the term non-sequential would be better than asynchronous.
6
Chapter 1
Development of Methodsand Techniques
1.1 Derivation and Construction of a ‘T’ Flip-Flop
The ‘T’ (toggle) flip-flop has a single input, T , and a single output, Q. Itserves as a divide-by-two circuit in counter and control applications and can beconstructed from simple gates, as will be shown in the following paragraphs.
1.1.1 The Flow Table
For this device, the output changes state, or toggles, each time the input goespositive. A flow table, which provides a concise description of its behavior, is inTable 1.1. The flow table is organized with the input (externally controlled) sig-
T0 1 Q
(1) 2 03 (2) 1
(3) 4 11 (4) 0
Table 1.1: Flow Table for ‘T’ Flip-Flop
nals labeling the columns. Responses are indicated by providing rows associatedwith critical output signals.
To see that this table provides a complete circuit description, begin by con-sidering state (1). Stable states are represented by bold numbers surrounded
7
by parentheses, and unstable or transitional states are represented by ordinarynumbers. Notice that in state (1), the input, T , is zero and the output, Q, isalso zero. When T changes state to a one, the circuit enters the transitionalstate indicated with a ‘2’ and then drops into stable state 2 in the next row.The required value of Q is now one. When T changes back to a zero, the circuitresponds by moving to state 3, with no change in Q. The next change of T(to a one) causes Q to go to zero with the circuit entering state (4). Finally,another change of T returns the circuit to its original state. Note that changesof the input variable cause movement from column to column, and internal statechanges cause movement along the rows. See [Huff 54].
For most flow tables the next step would be to attempt a state reduction,but in this case no reduction is possible because none of the rows in the tablecan be ‘merged’ with any of the others. (Other examples in this paper will dealwith state reduction.)
After constructing the flow table, we associate each row with an internalstate which can be identified with some combination of internal variables. Sincethere are four rows in the table, two binary symbols will be required.1 Thereis considerable freedom in assigning the internal (secondary) variables, and it iscustomary to do so in a way which will simplify the derived equations. We willset the values of the secondaries in the first row to zero, and use a gray code forsubsequent rows to assure that only one internal variable will change when thecircuit moves from any row to an adjacent row. See Table 1.2.
Ty1 y2 0 1 Q00 (1) 2 001 3 (2) 111 (3) 4 110 1 (4) 0
Table 1.2: Flow Table with Secondary Variable Assignments
Note that with the secondary variable assignments we have chosen, the valueof y2 follows the output, Q. When we construct the gate which generates y2,which will be labeled Y2, we can equate it with Q.
A stable state is defined as a state in which the secondary variables havesettled; i.e., no transitions are occurring internally. To make use of the table,we replace the state numbers with their Boolean equivalent row assignments.For example, the stable state cell in row 1, with secondary assignment 00 willcontain 00. The unstable state in row 1, which leads to row 2, will contain theassignment 01. Continuing in this manner, we arrive at Figure 1.3. For thetable, we are not concerned with which cells represent stable states and which
1Since the symbols are binary, we use: ceil(log2 number of states) = number of variables.
8
do not. We are only concerned with deriving a truth table from which we canextract the equations for the secondary (internal) circuit elements.
Ty1 y2 0 1 Q00 00 01 001 11 01 111 11 10 110 00 10 0
Table 1.3: Flow Table with Boolean State Entries
The leftmost entries of each cell in Figure 1.3 represent the truth table fory1 and the rightmost entries represent y2. To simplify the derivation of thecorresponding equations, we will split the table into two separate tables, one foreach element. This done in Table 1.4.
Ty1 y2 0 100 0 001 1 011 1 110 0 1
Y1
Ty1 y2 0 100 0 101 1 111 1 010 0 0
Y2
Table 1.4: Split Internal State Tables
1.1.2 The Secondary Equations
There is now a truth table for each internal element. These elements are capableof distinguishing between internal states by providing unique codes for each rowin the state table. We are now able to write the circuit equations, which can betaken directly from the tables.2
Y1 = Ty2 + y1y2 + Ty1 (1.1)
Y2 = Ty2 + y1y2 + Ty1 (1.2)
A note about the symbols used in forming circuit equations is in order. Itis customary to label the logic elements used to implement the equations with
2The redundancy in these expressions will be taken up later.
9
upper case letters, e.g. Y1, Y2. These elements (gates) can also by regardedas synonymous with their output function or signal, i.e. y1, y2, since there isa one-to-one correspondence here. The standard practice is to use the uppercase label on the left side of circuit equations to emphasize the fact that weare connecting devices together to implement our solutions. Some caution is inorder in adopting these conventions, because the equations are then not strictlyreciprocal mathematical relations, but are more like process flow statements orcause and effect relations. In general, no problems should arise from mixingdevice labels with circuit function, but keep in mind that Y1 is not strictlyidentical with y1. Where circuit feedback exists, be sure to verify the signalflow.
Part of the challenge in the implementation phase of the design is in carefullyselecting and including redundant terms. Generally, it is advisable to includethe terms which tie row elements together even if they are already included invertical tie sets. We have done this with the y1y2 term in the equation for Y1and the y1y2 term in the equation for Y2. The intent is to eliminate criticalhazards associated with column movement in the resulting circuit.3
The next challenge is to group the terms in each equation for easy assignmentto standard logic devices. We will choose NAND gates and group the mintermswith them in mind. By grouping the terms of the equation as the sum of twoproducts, an application of DeMorgan’s theorem will produce the input termsrequired for a two input gate.
Y1 = y2(T + y1) + Ty1 (1.3)
Y2 = y2(T + y1) + Ty1 (1.4)
1.1.3 Implementing the ‘T’ Flip-Flop
Now we are in a position to construct the circuit. Figure 1.1 shows Y1 with itsoutput and two input equations labeled.
�T+ y1
y2 +Ty1y1Y1
Figure 1.1: NAND Implementation of Y1
The upper input is a part of the memory (feedback) loop for Y1 and issatisfied by the configuration in Figure 1.1, in which we have also begun theconstruction of the Y2 element. The memory loop for this variable is completelyspecified by the first term on the right side of Equation 1.4. We can assign Y2
3There are situations in which this redundancy can be avoided without causing problems,so each design should be treated as unique and the implemented circuit should be analyzedcarefully.
10
to a two-input NAND gate and generate the feedback term, y2(T + y2), withanother two-input NAND.
�
�
�
�
•
•
•Y1
Y2
y1
y2
T
T+ y1
y2 +Ty1
T+ y1
Figure 1.2: Partial Construction of “T” Flip-Flop
Before proceeding with the rest of the construction, some potential problemswith our design approach should be mentioned. First, there is some risk inassuming that signal inverted twice can be treated the same as the originalsignal. The inversions generate delays which may (and often will) affect thecircuit behavior. All assumed equivalences should be carefully verified. Second,some of the signals we create will be formed by the cancellation of literals, e.g.when we combine a signal with its inverse. This can produce glitches (races,hazards, etc.) caused by timing differences between switching of the signal andthe corresponding change of state of its inverse. This subject will be taken upin detail later.
With these cautions in mind, we proceed as shown in Figure 1.2. Here wefind that the upper input to Y2 can be obtained by combining the existing signalsT(T + y1) to form Ty1 and inverting the result.
To confirm the circuit behavior we must consider the problems cited previ-ously with the implementation method and examine any potentially troublesomedetails. Note that the gate marked with ‘*’ in Figure 1.2 is responsible for astatic hazard. The hazard is generated whenever y1 is high and the input Tgoes positive. But, from the flow table in Table 1.2, the circuit must then be instate 3 with y2 also positive. Under these conditions, there will be a transitionto state 4, whether the hazard occurs or not. A detailed timing analysis willshow that the flip-flop does behave as expected, given reasonable assumptionsabout the elements used.4
It may be a small comfort that in this case the hazard does not cause amalfunction, so for this and more serious cases we will provide a method foreliminating the hazard entirely. Although the method is not discussed untillater, a version of the ‘T’ flip-flop with hazard suppression is shown in Figure1.3.
4The usual assumptions are that the longest gate delay is less than twice the shortest gatedelay, and that rise and fall times are less than a gate delay.
11
�
�
�
�
�
�
•
•
•
••
•
T
*
Y1
Y2
y1
y2 = Q
T+ y1
T+ y1
y2 +Ty1
Figure 1.3: Construction of ‘T’ Flip-Flop
1.2 ‘D’ Flip-Flop
In this section we will derive equations for an edge-triggered ‘D’ type flip-flop. We will also develop the method mentioned earlier for eliminating hazardscaused by cancellation of literals. To complete the section, we will show how toimplement asynchronous set and clear lines in an otherwise synchronous device.
1.2.1 The Flow Table
We start with a flow table representing the desired circuit behavior. Now, thereare some more or less standard conventions used in constructing the table whichdeserve comment. First, we will adopt the rule that only one input to a circuitmay change at a time. This rule is not always necessary or desirable, but it canresult in simplification by permitting the use of don’t care entries (designated byhyphens) in the table. Second, we will attempt to ‘merge’ rows in the resultingtable to reduce the number of secondary state assignments required to specifyeach unique internal state. Both of these rules will be invoked in the treatmentof the ‘D’ flip-flop. Note that there are situations in which these simplifyingassumptions are not appropriate and we will forego them when necessary.
The following two tables show the initial (primitive) and merged versions ofthe flow table for a ‘D’ flip-flop, Tables 1.5 and 1.6, respectively.
Merging rows is facilitated using the method described by Mealey,[Mealey 55].Briefly, we can merge two internal states (rows) if there are no conflicting statesin the cells, if they have the same output value, and if all possible next statesfor each of them have the same output value. Don’t cares (hyphens) will beoverridden by any numbered entry after merging. Merging can be repeated un-til it is no longer possible. Using this method, the original (primitive) flow table
12
�
�
�
�
�
��
�
�@
@
@
�@
•
•
•
•
•
•
•
•
T
Y1
Y2 Q
Q
Figure 1.4: Implementation of ‘T’ Flip-Flop with Hazard Suppression
can be reduced from eight rows to four. Consequently, the number of internalsecondary variables is reduced from three to two.
Once the table has been reduced, the row assignments can be made. For thistable the gray-coded secondary assignments in Table 1.6 are suitable. Note thatour assignment selection allows us to identify the secondary labeled y1 with therequired Q output. This identification will simplify the circuit implementation.
Using Table 1.6 we now can develop the state maps for the required secon-daries. Table 1.7 shows the combined map with all secondary variables entered.
Table 1.8 shows the same information in two individual maps — one for eachsecondary.
DC00 01 11 10 Q(1) 2 – 4 01 (2) 3 – 0– 2 (3) 4 01 – 7 (4) 0
(5) 2 – 8 15 (6) 7 – 1– 6 (7) 8 15 – 7 (8) 1
Table 1.5: Primitive Flow Table for ‘D’ Flip-Flop
13
DCy1y2 00 01 11 10 Q00 (1) (2) (3) 4 001 1 – 7 (4) 011 5 (6) (7) (8) 110 (5) 2 – 8 1
Table 1.6: Merged Flow Table with Secondary Assignments
DCy1 y2 00 01 11 10 Q00 00 00 00 01 001 00 – 11 01 011 10 11 11 11 110 10 00 – 11 1
Table 1.7: Completed Composite Flow Table for ‘D’ Flip-Flop
1.2.2 The Circuit Equations
The equations corresponding to the maps in Table 1.8 are:
Y1 = y1y2 + y2C + y1C (1.5)
Y2 = y2C + y2D + DC (1.6)
The following regrouping eases the implementation problem:
Y1 = y1(y2 + C) + y2C (1.7)
DCy1 y2 00 01 11 10 Q00 0 0 0 0 001 0 – 1 0 011 1 1 1 1 110 1 0 – 1 1
Y1
DCy1 y2 00 01 11 10 Q00 0 0 0 1 001 0 – 1 1 011 0 1 1 1 110 0 0 – 1 1
Y2
Table 1.8: Completed Maps for ‘D’ Flip-Flop Secondaries
14
Y2 = D(y2 + C) + y2C (1.8)
As in the earlier treatment of the ‘T’ flip-flop, we will construct our circuitstarting from the explicit secondary gates. Since we will be using this exampleto develop methods for the elimination of hazards as well as for implementingasynchronous set and clear control modes, the step by step creation of the ‘D’flip-flop is left to the reader. No new techniques beyond those shown alreadyare needed. Some ingenuity, however, will always be required. Our result isshown in Figure 1.5 with the internal gates numbered for reference.
�
�
�
�
�
��
@
@
@
�@
•
•
•
•
•
•
C
D
G1
G2
G3
G4
Y2 Y1 Q
Q
Figure 1.5: Implementation of ‘D’ Flip-Flop
1.2.3 A Digression on Hazards
The circuit implementation in Figure 1.5 harbors a serious hazard which wewould like to eliminate. The hazard, as in the previous ‘T’ flip-flop implementa-tion, is caused by attempting to cancel terms which do not occur simultaneously.The consequence is incomplete cancellation and spurious transient excursions ofthe affected signal line. See [Huff 55, Ung 59] for a full treatment of static anddynamic hazards.
A logic diagram and timeline representation of the problem is shown inFigure 1.6. In this figure, a signal and it (derived) inverse are combined at theinput of an AND gate. Note that the result expected from the raw equations5
does not suggest the glitch which actually occurs. Part of the reason for thisdiscrepancy is that the raw equations do not have provisions for keeping trackof time delays, i.e. they are intrinsically static. Rather than developing a more
5In Boolean algebra, a + a = 1 and a · a = 0.
15
elaborate algebra to include time explicitly we will simply make use of heuristicmethods to eliminate the problem.
�
�
••A A
A ·A
Logic Diagram
CC �
�
�� C
C
�� CC
A
A
A ·A
Timing Diagram
Figure 1.6: Combining a Signal with its Inverse
The method uses the fact that the undesired glitch noted above can besuppressed by combining a further delayed version of the original signal (orits equivalent). We can illustrate the concepts in detail by using subscriptedvariables to show time placement, as in Figure 1.7.
All this may seem like an exercise in futility, since in this example we haveonly succeeded in creating a signal which never changes. But the point of thisdiscussion is not to find ways to cancel the only term in an expression, it is tofind some way to completely cancel one of the unwanted terms in an SOP (SumOf Products) expression, without disrupting the others.
� �
�
A0 A1 A2
A0 ·A1 ·A2
• •
CC �
�
�� C
C
CC �
�
A0
A1
A2
A0 ·A1 ·A2
Logic Diagram Timing Diagram
Figure 1.7: Suppressing a Hazard by Cancellation
In the next section, these concepts will be applied to a more complex circuit,which illustrates their use in real, non-trivial problems.
Example of Hazard Suppression
Suppose we are given three input signals, A, B, and C. We require a signalC + A · B, which must be free of transients when A changes state. As stated,this example is basically a combinational problem with dynamic behavior con-straints.
16
Consequently, we take the following approach. First, note that the behaviorof the signal of interest is only important during the time that A switches. Thismeans that the inputs B and C can be considered static during the analysis.Second, if we keep track of propagating signals by using subscripts for timeintervals, only the signal A needs to be subscripted.
Here is one candidate solution to the combinational part of the problem withthe desired signal appearing at the output of Q3.
�
�
�A
B
C
Q1
Q2
Q3
•A+B
A+B
C +A ·B
Figure 1.8: Combinational Circuit with Undesired Transient
Of course, the signal C +A ·B, could be generated by other choices of gateswithout creating the transient problem we are called upon to solve. But we cansuppose that the other signals from Q1 and Q2 are already needed for otherpurposes and are therefore available for use without additional hardware.
The glitch appears at the output of Q2 when B is high and A goes from lowto high. It is caused by the attempt to produce A ·B at the input side of Q2 bycanceling the A term in A+ B. It propagates through Q3 when C is high anddisturbs the target signal.
We now use subscripts to identify the time periods (delays) as a change ofstate of A propagates through the circuit. Since B and C are static during thetime interval under consideration, there is neither any benefit nor motive forsubscripting them.
Since the transient begins at the input of Q2, we turn our attention toeliminating it here. We hoped to create a serviceable version ofA·B at this point.Instead, we created A0A1+A0 ·B. From the previous discussion, we are temptedto look for another signal approximating AB, but with later delays. The outputof Q3 contains such a signal and might serve to eliminate the spurious A0 ·A1.If a third input is added to Q2 the expression for the combined input thenbecomes,
A0 · (C +A2 ·A3 +A2 ·B) · (A1 +B).
This expands to,
A0A1C +A0A1A2A3 +A0A1A2B +A0BC +A0A2A3B +A0A2B
17
�
�
�A0
B
C
Q1
Q2
Q3
•A1 +B
A1 +A2 ·B
C +A2 ·A3 +A2 ·B
Figure 1.9: Combinational Circuit with Subscripted Signal
where we have omitted the AND dot multipliers for compactness.
Examination of the above expressions reveals that, 1) the second and thirdterms, are completely eliminated by the previous results, 2) the last two termscan be combined into a single term.6 Rearranging the surviving terms yields,
C(A0A1 +A0B) +A0A2B.
We have now arrived at the following result: When the signal C is low, notransient can propagate through Q3 because the gate is disabled. When C ishigh (true), C is low, so the only term which survives to propagate through Q2
is A0 · A2 · B. This signal is a slightly trimmed version of our intended A · Band solves the problem posed. The circuit is shown below.
�
�
�
�@
A0
B
C
Q1
Q2
Q3•
•A1 +B
A1 +A2 ·B
C +A2 ·A3 +A2 ·B
Figure 1.10: Circuit Solution Providing Hazard Suppression
Having presented the method, we must report that analysis by subscripting
6A0A2A3B + A0A2B = A0A2B(1 + A3) = A0A2B.
18
is error-prone and often prohibitively difficult. It is best suited for automated orcomputer driven solvers. Fortunately, there are simpler techniques for solvingsimilar problems with pencil and paper. These will be developed in followingparagraphs.
Suppressing the ‘D’ Flip-Flop Hazard
Let’s examine our implementation of the ‘D’ flip-flop more closely. The hazardoccurs at the output of gate G3 when Y2 is positive and the C input rises. Thegate is implementing the term Cy2 on the input side to produce C + y2 at itsoutput. Cy2 is constructed from the combination C(y2+C), and the cancellationof C is the cause of the problem.
We need to locate (or generate) another signal which contains the term Cy2where the C term is delayed. That signal may contain other terms summed withthis term if certain cautions are observed. On searching through the existingsignal set we find, at the output of G2 the signal D + Cy2. This signal satisfiesthose requirements which have been articulated so far.7
The requirement is that the candidate signal must be false at the time thehazard would occur and must be true when a legitimate Cy2 signal appears atthe input of G3. Our choice meets this requirement. There are several ways toverify our modification. One way is to construct a detailed timing chart for thecircuit, or submit it to a computerized simulation. Another is to examine thecircuit Karnaugh maps.
How do we use the maps to analyze hazards? We start with the following:
1. Each stable state represents a specific combination of Primary and Sec-ondary variables,
2. No circuit action takes place until an input (Primary) variable changes,
3. The stable state entries in the merged flow table represent the definedcircuit behavior; the other (unstable) entries define the transitory behaviorfrom the time a Primary changes until the circuit settles into a stable state.
From the maps we can identify those stable states for which C is false and Y2is true. Since y2 is true,8 the term Cy2 should remain false during changes ofthe Primary, C. The skeletal flow tables in Table 1.9 are maps of the indicatedexpressions using the form of the merged flow table and show that there areonly two stable states where C is false and y2 is true — in the rightmost columnof the table. It is here that we need to maintain the zero state of Cy2 when theC input rises.
It is clear that our chosen hazard suppression signal will be zero at this time,and that it will prevent any other signals from activating the gate G3. Whatmay not be clear is that the gate will still be properly functional at other critical
7Note that Cy2 · (D + Cy2) = Cy2.8The potential ambiguity between Y2 and y2 doesn’t occur in the stable states.
19
DCy1y2 00 01 11 10 Q00 (0) (1) (1) 001 – (0) 011 (0) (0) (0) 110 (0) – 1
Cy2
DCy1y2 00 01 11 10 Q00 (1) (1) (1) 001 – (0) 011 (1) (0) (0) 110 (1) – 1
D + Cy2
Table 1.9: Skeletal Flow Tables
times. To prove this, we only need to establish that when the term Cy2 goespositive, the auxiliary signal D + Cy2 is true. Why is this sufficient? Becausewe only need the effect of the delayed Cy2 at the time of the hazard; we needto disable that line when the driving version of C sets Cy2 to one. It happensthat Cy2 is driven true only from the two stable states in the leftmost columnof the table. In these states, our chosen signal is true and no inhibition of therequired signals will take place.
The conclusion? To complete the properly functions ‘D’ flip-flop we simplyneed to connect a wire from G2 to G3. That’s it! The result is shown in Figure1.11
�
�
�
�
�
��
@
@
�
@
�@
•
•
•
•
• •
•
C
D
G1
G2
G3
G4
Y2 Y1 Q
Q
Figure 1.11: Hazard-free Implementation of ‘D’ Flip-Flop
20
1.2.4 Location and Identification of Signals
We will now make further use of skeletal flow tables to show how we were ableto identify the Q signal labeled in the schematic of Figure 1.11. The techniqueis generally useful for locating or generating a signal with predetermined prop-erties. To develop Q populate the stable cells of our circuit flow table with therequired signal values. This is done in Table 1.10.
DCy1y2 00 01 11 10 Q00 (1) (1) (1) 001 – (1) 011 (0) (0) (0) 110 (0) – 1
Table 1.10: Skeletal Map for Q
Recall that only the stable states are required to define the external behaviorof the circuit. Any signal with the stable state values in Table 1.10 matches ourrequirement. The gate labeled G4, for example, implements the Boolean func-tion y1+Cy2, but its truth values in the stable states are the same as Q. We arethus justified in labeling it as we did. The only differences between the desiredand actual signals occur during transitional states, and since those transitionsare gray-coded the net effect is simply that some edges of our derived Q occurearlier or later than those of an ‘ideal’ Q. Incidentally, it is a characteristic ofmemory devices (latches, R-S flip-flops, etc.) that the circuit equations for Qdo not represent strict Boolean inverses.
1.2.5 Asynchronous Set and Clear
The completed ‘D’ flip-flop can be seen to consist of an output latch and somecontrol logic. The state of the output latch does not affect the control logic inany way, and may be in any initial state at power up. It is desirable to havesome way to force the output into a pre-determined state independent of thecurrent state of the output and input variables; i.e., to introduce set (or preset)and clear (or reset) signal lines into the circuit.
This is best accomplished by referring to the equations for the circuit sec-ondary variables Y1 and Y2. Since our requirement is to force a known outputstate regardless of the input combination, we must alter the states of some ofthe secondaries. The equations for these are repeated below.
Y1 = y1(y2 + C) + y2C (1.9)
Y2 = D(y2 + C) + y2C (1.10)
21
We also need the merged flow table to identify the stable state entries forour altered functions. We begin by examining the flow table.
DCy1y2 00 01 11 10 Q00 (1) (2) (3) 4 001 1 – 7 (4) 011 5 (6) (7) (8) 110 (5) 2 – 8 1
Table 1.11: Flow Table for ‘D’ Flip-Flop
According to the table, if we can force both y1 and y2 to the true statemomentarily (third row of table), Q will go true and remain that way untilsome other signal occurs. The circuit will be in state 5, 6, 7, or 8, This is theaction needed for an asynchronous set. Similarly, an asynchronous clear can beaccomplished by forcing both y1 and y2 low (false). The resulting set or clearis independent of the current states of Q or any of the inputs.
Another, possibly better, way to derive the set and clear conditions is byinspecting the right sides of (1.9) and (1.10). From (1.9) we can see that to setY1 (on the left) true, we must force both y1 and y2 (on the right) true. This doesnot guarantee that Y2 will remain true, but it does guarantee that Q will be set.Why? Because Y2 can only revert to false if C is false. But in this case, Y1 (Q)will remain set because of the presence of the term y2C. By the same token,forcing y1 and y2 low will clear Q. Here, the state of Y2 is also indeterminate,but it can only revert to true if C is false, in which case Y1 will stay clear.
The complete ‘D’ flip-flop solution is shown in Figure 1.12. To implementthe enhancements we simply added additional inputs to the gates for Y1 and Y2to handle the asynchronous set function. These are tied together and broughtout as S. To create an asynchronous clear we need to provide similar inputs toG1 and G4 to force Y1 low, and an input to G2 to force Y2 low. These are tiedtogether and brought out as R.
22
�
�
�
�
�
��@
@
�@
@�
•
•
• •
•
•
•
•
•
•
Q
Q
S
C
D
R
G1
G2
G3
G4
Y1 Y2
Figure 1.12: Complete Implementation of ‘D’ Flip-Flop with Set and Clear
1.3 Negative Pulse Generator
1.3.1 The Flow Table
This exercise will illustrate some of the power of the flow table as a circuitdescription tool. We will be using the table in unusual ways and developingsome special design techniques which will be used later.
The problem posed in this section is to devise a circuit with a single input,P , and a single output, Q, which produces a short negative pulse whenever theinput goes positive. This sort of circuit is encountered frequently, and manylogic designers have met it and solved it one way or another — usually by usinga single-shot or some sort of logic delay line. Our solution is clearly not theonly one possible, but it does have a certain elegance, and offers a vehicle forintroducing new design methods.
Our circuit description only provides for a single stable output value — withQ positive. The negative pulse is generated on the rising edge of the input, andwill automatically complete before stability returns. So how do we describe thisbehavior with a flow table? Table 1.12 shows a technique for doing this.
Note that we have identified four states, but only two of them are stable.In the table, we have explicitly provided transitional rows to control the circuitbehavior during unstable operation. We will decode the secondary combinationswhich correspond to the unstable rows and use the decoded signal to satisfy theproblem statement. In a sense, we have expanded the flow table by the additionof these rows. Contrast this with the previous problem where we found it
23
P0 1 Q
(1) 2 1– 3 0– 4 01 (4) 1
Table 1.12: Flow Table for Negative Pulse Generator
convenient to merge rows. Also note that we have placed don’t cares in thoseplaces where the circuit behavior is not specified. Generally, this practice cansimplify the design, but always confirm the operation of the completed circuitto assure that no unwanted behavior occurs.
The selection of secondary assignments is closely linked with the problemstatement. We have two secondary variables, one of which we would like toequate with Q. Our choice is shown in Table 1.13.
Py1 y2 0 1 Q10 10 00 100 – 01 001 – 11 011 10 11 1
Table 1.13: Secondary Assignments for Negative Pulse Generator
1.3.2 Equations and Implementation
The equations for the circuit are:
Y1 = P + y2 (1.11)
Y2 = y1 + Py2 (1.12)
These equations are implemented in the rather surprising configuration in Figure1.13.
1.3.3 Analysis of Implementation
If this paper carries any consistent message, it is that every circuit implemen-tation should be reviewed carefully. The assumptions and simplifications madeduring the design may cause unwanted behavior.
24
�
�
�
•
••
P
Q
Y2
Y1
Figure 1.13: Negative Pulse Generator
In the current design, we placed don’t care entries in some of the cells in col-umn one. As expected, this decision simplified the logic equations by acceptinga default transition to state (1). The practical consequence is that if the inputgoes positive and then returns to negative before the output pulse completes,the output pulse will be forced to complete early.
Engineering judgment comes into play here. It may be acceptable to placea hold time restriction on the input to the circuit such that the input mustremain positive until the output completes automatically. It is also possible tolatch the input so that no such requirement is needed, with the penalty thatthe circuit implementation will be more complex. Review the individual circuitrequirements carefully.
1.4 Up-Down Counter Controller
1.4.1 The Flow Table
The next circuit solves another common problem — that of controlling the actionof an up-down counter which has separate count-up and count-down inputs. Thecontroller is needed to deal with the case in which the count-up and count-downsignals arrive simultaneously. When this occurs, such counters often drop acount (or add a count) because one the inputs gets lost. In applications whereup-down counters are used to control a FIFO or cyclic buffer, this fault is fatal.Because the controller assures that count-up and count-down signals occurringat arbitrary times are properly ordered, it is sometimes called a derandomizer.
Our objective is to devise a control circuit which is able to properly arbitratewhen the commands occur at or near the same instant.
Development of the flow table follows from these requirements:
1. The up-down counter has separate count-up and count-down pins,
2. The count action occurs on the leading edge of a negative going pulse atthe appropriate pin,
25
3. Pulses on the count-up and count-down pins must be separated by at leastone gate delay to guarantee proper operation of the counter.
For this application, we will assume external count-up and count-down com-mands consisting of positive-going signals of arbitrary duration; i.e., the signalsmay coincide or overlap in time.
This will be our first exposure to incompletely specified functions, and wewill develop our solution in carefully contained stages. The first step will beto create a partial flow table documenting what we know from the problemstatement. This table is shown in Figure 1.14.
Cu Cd
00 01 11 10 Qu Qd
(1) – 111 (2) – 11– 2 (3) 4 111 – (4) 11
Table 1.14: Partial Flow Table for Counter Controller
In this table we have only provided rows for the stable states. Those statetransitions which do not involve output signals are shown, but the other tran-sitions are left blank for the moment. What can we learn from this partialtable?
1. We will have expand the table to provide unstable rows, such as we didfor the pulse generator,
2. If the output variables are equated with specific secondaries, two addi-tional secondaries will be required to guarantee unique row assignments.
A fully expanded, partially filled, table is reproduced in Table 1.15. In thistable we have replaced the stable state numbers with their secondary assignmentequivalents and have added the transition requirements for the unstable states.We have also retained the stable state indicators (parentheses, bold type) foreasy comparison with Table 1.14. The secondaries y1 and y2 have been identifiedwith with Qu and Qd, respectively.
Note the use of blanks instead of hyphens in some table entries. In ourmethod there is an important distinction between the two. The blank meansthat the circuit behavior has not been specified. It doesn’t necessarily meanthe action can’t happen or won’t matter, it only means we have not chosen torestrict it at this time. If we truly do not care, we will place hyphens in thecell. Otherwise, we may specify some or all of the variables in the cell at a latertime.
A case in point concerns the blank cells in the rows where y1 and y2 equal zero(first four rows). From the circuit description, this is a forbidden combination;
26
Cu Cd
y1 · · · y4 00 01 11 10 Qu Qd
00000001001100100110 [1110] 1110 010111 1111 010101 0111 010100 [0110] 0110 011100 (1100) 1000 - -00 0100 111101 1100 (1101) 0101 111111 1101 (1111) 1110 111110 1100 1010 (1110) 111010 1011 101011 1111 101001 1101 [1101] 101000 1001 [1001] 10
Table 1.15: Partially Filled Flow Table
i.e., at least one of these secondaries should be true at all times. Hence, thecells in these rows can be used to simplify the equations for Y1 and Y2.
A more problematic situation occurs in the row labeled 1100 in column11. Here we have the opportunity to specify what happens when both countcommands occur at the same time. But we expect the circuit to ‘decide’ whichcount pulse to output first, so we choose not to select the next state identifiersfor y1 and y2.9 On the other hand, we also expect the circuit to immediatelyoutput one or the other pulse so we need to assure that the next state is outsidethe four stable rows. We can do this by specifying the secondaries y3 and y4 asshown.
1.4.2 Equations and Implementation
The circuit equations are:
Y1 = Cu + y3 + y2 (1.13)
Y2 = Cd + y4 + y1 (1.14)
Y3 = y1 + y3Cu (1.15)
Y4 = y2 + y4Cd (1.16)
9These secondaries are identified with Qu and Qd, respectively.
27
The first two equations borrow heavily from the unspecified portions of thetable for simplifications and redundancy. In this implementation Y3 and Y4 wereconstructed first, and the others followed. See Figure 1.14.
�
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�
�
�
�
@�
•
•
•
•
•
•
Cu
Cd
Qu
Qd
Y3
Y1
Y2
Y4
Figure 1.14: Up-Down Counter Controller
This circuit has several aspects which deserve comment. First, the latchconsisting of Y1 and Y2 operates as a ‘turnstile’ which passes a signal through oneside or the other, but which prohibits simultaneous passage of both. It arbitratesbetween coincident requests by latching in one of two states. Whichever signalis honored first will produce an appropriate output pulse, after which the otherwill be allowed to pass. Second, with ‘real-world’ devices the possibility ofmetastable behavior exists. That is, there may be a short period time duringwhich the latching process produces uncertain outputs on Y1 and Y2. This canoccur if the input signals arrive within a very small time interval; e.g., lessthan a gate delay. But even if this does occur, the duration of the uncertaintywill be very short and its effects can be controlled with glitch suppression logic(described later), or an ‘exclusive-latch’ which consists of an input latch drivingan output latch.
It is worth recalling that metastability can be managed and, in general,the potential for its appearance does not necessarily suggest circuit failure.10
It is a constant companion in digital environments and even lurks inside thecommon ‘D’ flip-flop. Since it can only occur during changes of state, such
10Metastability has been the subject of many analytic studies using statistical models andvarious plausible device timing distributions. But the likelihood of an extended metastablecondition is vanishingly small.
28
as when inputs change, it can be managed by imposing proper setup and holdtime requirements. In situations where the inputs are unrestricted, such ashere, additional logic may be considered. But the author has implemented thisconfiguration in TTL logic and driven it with a reference clock consisting of a 1MHz sine-wave modulated reference clock over a period of several days withoutany miscounts.
1.5 A Phase/Frequency Detector
This section calls upon techniques already developed and introduces the conceptof ‘strong’ and ‘weak’ secondaries. It also provides a last example before wecomplete the development method and summarize it in its entirety.
We are to implement a phase/frequency detector which generates negativepulses to drive the charge pumps associated with a phase-locked loop (PLL).The circuit action is controlled by two inputs — one is the variable clock signalderived from the PLL oscillator, φpll , and the other is the incoming referencesignal, φref , with which phase lock is desired. In the following exposition, thesesignals will be designated as C and R, resectively. The input logic is driven bythe negative edges of these two input signals and will activate (or deactivate)one of two pump signals, pump up or pump down, according as the referencesignal is ahead of or behind the PLL clock. The active level of the pump signalsis negative, and their normal state is high.
Phase lock is achieved when both signals are coincident at their negativetransitions. In this condition, both pump signals remain high, although we willaccept small glitches on both outputs on the assumption that they will haveno net effect on the total charge driving the phase locked oscillator (PLO). Byactivating the pump up output when the reference signal is early, and clearingall pumps when the PLL clock arrives, we can develop a driving signal thatis proportional to the time difference between the two. Similarly, if the clocksignal is early, we activate the pump down signal and clear all pumps when thereference arrives.
The circuit is insensitive to duty cycle because of the edge triggering. It isalso immune to spurious lock-up on harmonics because it forces a one-to-onecorrespondence between clock edges and reference signal edges. Hence, it is aphase/frequency detector as opposed to a phase detector only.
1.5.1 The Flow Table
A suitable flow table description of the desired behavior is shown in Table;1.16, where R is the reference signal and C is the PLL clock. This table canbe constructed easily from the observation that the circuit can only have threedifferent output states, and can have any combination of inputs for each possibleoutput. For this problem, it will be expedient to merge the table and thenexpand it. The reason for this unusual approach is that the output requirementscannot be met with any direct secondary variables. Decoding of secondaries
29
RC00 01 11 10 PU PD
(1) 4 – 10 11(2) 5 – 11 01(3) 6 – 12 103 (4) 7 – 111 (5) 8 – 013 (6) 9 – 10– 5 (7) 12 11– 5 (8) 10 01– 4 (9) 12 102 – 7 (10) 112 – 8 (11) 011 – 9 (12) 10
Table 1.16: Raw Flow Table
would be required to produce the outputs unless the table is expanded to includea greater number of secondaries, as was done in the previous example. But anexpansion at this point would create an unnecessarily, if not prohibitively, largeflow table. Our solution is to first reduce the table by merging, and then expandthe merged table to equate some secondaries to the output variables.
Merging presents no unusual problems and the merged table is shown inTable 1.17.
Before expanding the table, we will reorder the rows. Why? Because ourtable construction process has left us with a scrambled list of output states andwe would like to gray-code them before proceeding. Recall that the reorderingof flow table rows is essentially dealing with the row assignment problem, and
RC00 01 11 10 PU PD
(1) 4 – 10 11(2) 5 8 (11) 01(3) (6) 9 12 103 (4) 7 – 111 (5) (8) 10 01– 5 (7) 12 111 4 (9) (12) 102 – 7 (10) 11
Table 1.17: Merged Flow Table
30
by taking some action to order the outputs at this time, we may be able tosimplify the row assignments later. The sorted table is shown in Table 1.18.
RC00 01 11 10 PU PD
(2) 5 8 (11) 011 (5) (8) 10 01
(1) 4 – 10 113 (4) 7 – 11– 5 (7) 12 112 – 7 (10) 111 4 (9) (12) 10
(3) (6) 9 12 10
Table 1.18: Sorted Flow Table
A glance at the output column shows why an expansion of the table is calledfor. If we reserve a pair of secondary variables to provide the Pu and Pd signals,we need two more to distinguish between the four rows whose outputs are 11.Because of the symmetry in the circuit description and the table as developedso far, we will try and preserve symmetry in the additional secondaries. Ourexpanded table is shown in Table 1.19 with the state entries already replacedby their corresponding row designations.
A few words are in order concerning constructing the expanded flow table.The strategy used to create a satisfactory table is intended to deal with someof the ‘real world’ problems that complicate some designs. For one thing, weare at all times attempting to produce a flow table which permits easy move-ment between states without critical races. This means we try to assure thatmovement from row to row will involve the change of one variable only. We nor-mally gray-code the secondaries to facilitate this task and will sometimes needto expand the table to increase the number of state transition options available.
If often happens that there is no way to move from one unstable state toa stable one without multiple secondary changes. In those cases, we will oftentake advantage of any available don’t care cells as ‘stepping stones’; i.e., we willmake a gray coded move to an auxiliary cell and then another gray coded moveto the final state. We may even have to make several such steps to get to thetarget state. If there are any blank cells in the table, we can use those, too.
Another way to approach this problem is to avoid ‘overspecifying’ the sec-ondaries. If we only really care about a few of the secondaries, we can specifythem and leave the others in don’t care conditions wherever possible. We havedone this in the previous example, and do it again here in Table 1.19 in twocells in row 0111, columns 00 and 10, as well as in row 1011, columns 00 and01. Each of these cells would require multiple steps to get to the target state.We have chosen to only specify those secondaries whose values concern us, andnot the others.
31
RCy1 · · · y4 00 01 11 10 PU PD
00000001001100100110 (0110) 0111 0111 (0110) 010111 11- - (0111) (0111) 11- - 01010101001100 (1100) 1101 - - - - 1110 111101 1001 (1101) 1111 - - - - 111111 - - - - 0111 (1111) 1011 111110 0110 - - - - 1111 (1110) 1110101011 11- - 11- - (1011) (1011) 101001 (1001) (1001) 1011 1011 101000
Table 1.19: Expanded Flow Table
1.5.2 The Equations
Before deriving the equations for this circuit we will introduce the concepts ofexternal and internal secondaries. Heretofore we have regarded all secondariesas ‘internal’ in the sense that they were implicit in the problem statement. Wenow find it convenient to qualify certain secondaries depending on whether theysatisfy any of the given signal requirements. External secondaries are thosewhich can be immediately identified with a required output signal, and whosevalues may be partly or completely fixed by the problem statement. Inter-nal secondaries are those which are merely required to complete the internalrow identification requirements, and whose implementation details are uncon-strained beyond that.
The reason for making such a distinction follows from the many degrees offreedom available in implementing a set of Boolean equations. We are, of course,always interested in economy. We can solve the implementation problem in morethan one way, but an optimal or quasi-optimal solution is not easily pulled fromthe raw equations without imposing external constraints. In fact, more thanone set of equations can represent the same circuit.11
With this in mind, we begin the equation development by taking a first cutat the equations for the external secondaries, Y1 and Y2.
11Consider that fact that some boolean terms are technically redundant, and do not alterthe truth values of the equations. We add or remove redundant terms when it serves ourpurpose to do so — particularly to eliminate hazards.
32
Y1 = y1R + y3 + y3y4(y2 · R + y1 · C) (1.17)
Y2 = y2C + y4 + y3y4(y2 · R + y1 · C) (1.18)
With all the blank map space we have used, there is a real danger of incom-pletely specifying the circuit equations. Indeed, an example of such an error isrevealed in equations (1.19) and (1.20) where we have partially completed theequations for the internal secondaries, Y3 and Y4. Note that if either of theseterms ever becomes true, the secondary will ‘latch up’ because there is no wayto set it false.12
Y3 = y1R + y3 (1.19)
Y4 = y2C + y4 (1.20)
Clearly there should be some zeros in the y3 positions of cells in rows ofthe map where the y3 row identifier is one. Similarly for y4. Why? Becausethose zeros would prevent us from collecting all the rows where y3 is true intoour equation. The problem has occurred because of careless and over-optimistictreatment of blanks and don’t cares. Some of the y3 terms need to be qualifiedby some other variable which, when false, will unlatch Y3. We intend to correctthis oversight in the course of completing the design, but for the moment wewill simply note the problem and put it aside to concentrate on the externalsecondaries.
When confronted with potentially conflicting design objectives, such as thenegotiable desire for economy with the absolute need for correctness, we mayfind it necessary to re-examine the design space in which we are working. Here,for example, we have ‘opened up’ the flow table to make the external secondariesreflect the required circuit outputs. Now we need to place restrictions on thesecondaries to assure that they are not underspecified. We hope to do this in away that reduces the number of auxiliary signals we need to generate. This willhelp assure that the final implementation is, in some sense, minimized.
To begin, note that the last term in the equations for Y1 and Y2 are thesame. Since this term, or an equivalent, will be implemented in our design, itis worth examining it closely to determine whether it can be constructed fromterms which are usable in Y3 and Y4. This heuristic part of the design processsimply tries to minimize the total number of logic terms required by makingbest use of common terms, if possible.
Relabeling the term under consideration as F1 and applying DeMorgan’stheorem to obtain its inverse, F 1, we have:
F1 = y3y4(y2 · R + y1 · C) (1.21)
F 1 = y3 + y4 + y1y2 + y1R + y2C + RC (1.22)
12Recall Einstein’s admonition to make everything as simple as possible, but no simpler.Here, in our zeal to maximize blank space, we have ‘overshot’ the mark.
33
It can be shown, by the use of skeletal flow tables, for example, that theBoolean function in (1.22) can be ‘AND’ed with the y3 in (1.19) to eliminatethe problem of underspecification.13 In other words, replacing the simple y3with a qualified version give by the term: F 1 · y3, manages to capture all therequired true states in the flow table without the risk of latch-up. We can usethe same function to correct (1.20). Thus, to complete the specification for Y3and Y4 we need only ‘AND’ the term F 1 with y3 and y4, respectively.
Now, we still may be able to simplify the logic if we can further reduce (1.22).However, reductions in the expression for F 1 must be done with careful regardfor its impact on Y1 and Y2, as there are no obvious constraints available fromY3 and Y4.
A partial implementation of the circuit is shown in Figure 1.15.
�
�
�
�
�
� �
�
�@
@�
•
•
•
•
•
•
• •
R
(φref )
C
(φpll)
Pu
Pd
F1
Y1
Y2Y4
Y3
Figure 1.15: Partial Implementation of Phase/Frequency Detector
Note that we have already generated terms for Ry1 and Cy2 and we wouldlike to know if we really need the terms y1y2 and RC. After all, these enteredinto our equations for Y1 and Y2 following a very loose grouping of their maps.We will always strive to eliminate unnecessary terms. To determine whetherwe can simplify F 1 we can withhold the questionable terms, apply DeMorgan’stheorem, and inspect the maps to see if we have introduced any damaging zerosinto the true equations.
The new values for F 1 and its inverse, now called F 2 and F2, are shown in
13This isn’t too surprising since y3 covered true, blank or unspecified cells only.
34
(1.23) and (1.24).
F2 = y3 + y4 + y1R + y2C (1.23)
F2 = y3y4(y1y2 + y1C + y2R + RC) (1.24)
We can now examine the changes to F1 embodied in F2 to verify them. Acareful comparison of the skeletal maps with the Expanded Flow Table of Table1.19 reveals that they do not invalidate our earlier implementation of Y1 andY2, so we can accept them and proceed.
The revised circuit equations are listed in (1.25) through (1.28) for referenceand the completed circuit diagram is shown in Figure 1.16.
Y1 = y1R + y3 + y3y4(y1 + R)(y2 + C) (1.25)
Y2 = y2C + y4 + y3y4(y1 + R)(y2 + C) (1.26)
Y3 = y1R + y3(y4 + y2C) (1.27)
Y4 = y2C + y4(y3 + y1R) (1.28)
�
�
�
�
�
� �
�
��@
@�
•
•
•
•
•
•
•
•
•
•
•
•R
(φref )
C
(φpll)
Pu
Pd
F2
Y1
Y2Y4
Y3
Figure 1.16: Complete Implementation of Phase/Frequency Detector
Dealing with incompletely specified functions can be very confusing, andeach case must be examined closely. In this case we have expanded the raw flowtable to allow us to identify certain secondary variables (external secondaries)
35
with the circuit outputs. In doing so we introduced new rows in the table whichserve as ‘wild cards’ in gathering truth values from the resulting Karnaughmaps. Handling the entries in these rows is part of the specification and designproblem. We may insert values in specific cells when it is necessary or desirableto do so, or we may determine that we can leave blank and cells which representdon’t care conditions. Hence, we should be prepared to place 1s or 0s in emptycells representing transient states if there a reason for it.
We have accepted one slight departure from the strict original circuit specifi-cation in this exercise. When both inputs go negative simultaneously, e.g. whenthe PLL is in lock, there should be no corrective pump signals from Pu or Pd.But in our circuit there will be coincident short glitches on both pump outputs.These glitches can be eliminated with glitch suppression logic (discussed later)or by redesigning the circuit to control the transient behavior under these con-ditions. We have not bothered with either of these steps because, by the natureof the problem, such glitches will not adversely affect the performance of thePLL. This is because the PLL responds to the total time the pump up or downoutputs are active, and short glitches or spikes will have negligible impact.
36
Chapter 2
The Complete SynthesisMethod
We are now in a position to pull together the techniques developed in the pre-vious sections and generalize the entire process.
A summary is shown in the outline below.
1. Develop Circuit Description This should completely define the be-havior of the identified output signals in terms of the inputs.
2. Derive the Raw Flow Table There are many ways to do this depend-ing on the ‘fine print’ in the circuit description. Different raw flow tablescan describe the same circuit. If you have problems here, there may beproblems with the specification itself.
3. Expand or Merge Flow Table This step may not be necessary ordesirable in many cases. But if there is some problem in equations outputsto unique rows in the raw flow table, we can assume additional secondariesand expand the table accordingly.
4. Sort Flow Table If there is a desire to equate output signals withspecific secondary variables, the rows should be sorted so that the outputsare in gray coded order.
5. Make Secondary Assignments Having created a suitable flow table,we can now assign a unique combination of secondary variables to eachrow. The most direct way of doing this is to simply number the rowsin binary counting order. But because we are concerned with controllingmovement from row to row, we will use gray-coding exclusively. Note thatit is not necessary to start the assignments with the first row equal tozero. The starting count is a matter of convenience and consistency withthe output.
37
6. Make the Cell Assignments This is a multi-step process. Use thefollowing order:
(a) Fill those entries which represent stable states with their correspond-ing row assignment numbers. This is a mandatory step.
(b) Fill the cells whose Hamming distance from their stable rows equalsone. In other words, if a change of input (column movement) placesthe circuit on a transient (unstable) cell, and if there is only one bitwhich is different in the present and next states, then fill the cell withthe next stable state value.
(c) Use stepping stone rows if the Hamming distance between the presentunstable state and target state exceeds one. Be advised that some-times this will not be possible, and sometimes is won’t be worth theeffort. If there is only one stable state in the column, we may notcare how the secondaries get there. It is often possible to specify afew of the secondaries to avoid undesired movement and leave therest unspecified. If more than one stable state exists in the column,great care should taken to assure that the circuit always ends up inthe right one.
(d) Fill in any remaining necessary or desirable consrtaints. This is whereany blank cells are given 1s or 0s to force secondary movement intoor out of certain rows or blocks of rows in the table. We also usethis step to identify or eliminate potential problems associated withunderspecified secondaries.
7. Split the Completed Flow Table Note that this step of purely me-chanical and does not involve any decision making. We have not shownthe split tables for all our examples, because they can be easily deducedfrom the complete table.
8. Derive First Cut Secondary Equations In this step we considerthe simplest forms for each of the secondaries. Decisions about whetherto incorporate redundant terms in an equation are made at this point.Problems with underspecification in expanded tables will also appear here,hence we refer to this step as a ‘first cut’.
9. Partially Implement the External Secondaries If the circuit equa-tions permit a complete solution at this point, we can implement all thesecondaries and complete the design process. Otherwise, we should moveahead interactively constucting portions of the circuit as condistions per-mit. While we have not yet discussed the exploitation of symmetry inthe defining equations, there are opportunities here to do so. (See the J-Kflip-flops later in this paper.) Complex terms which include blank areas onthe maps are targets for reduction and should be identified at this point.
10. Partially Implement the Internal Secondaries If these secondariesallow a simple, unambiguous solution we can inspect the terms generated
38
in the solution process to see if any are useful in completing the externalsecondaries. Otherwise consider the implementation as tentative.
11. Apply DeMorgan’s Theorem to External Secondaries Actually,we only need to look at those terms which are condidates for reduction.Some of the terms in the secondary equations will be straightforward andeasily constructed. The other terms need to be inverted so that the inputrequirements to the selected gate can be examined.1 We are looking forexisting signals or easily obtained signals to satisfy the requirements forthis term. We are also looking for ways to simplify or reduce the termwithout invalidating the secondary equations.
12. Perform any Reductions If it is possible to simplify the input equa-tions to the secondary under consideration, do so at this point.
13. Refine the Secondary Equations Having developed a new set ofequations which satisfy the derived maps and which are simpler to im-plement, apply them to the affected secondaries.
14. Loop over Previous Five Steps This interactive reduction shouldcontinue until the equations and implementation are satisfactory.
It should be emphasized that logic synthesis is as much an art and a devel-oped skill as it is a science. No completely mechanical process for deriving circuitsolutions will render the conscientious, experienced designer obsolete. Do notthink of these procedures as substitutes for thought, but rather as tools. Theywill not work if used carelessly. Many of the most important constraints in logicdesign are imposed by considerations which are external to the problem speci-fication. Make sure you understand the problem, the context, the constraints,and the design space before attempting a solution.
In the hands of a thoughtful engineer, the methods presented here can helpdevelop solutions to many complex and difficult synthesis problems. They canalso aid in finding simpler solutions to problems normally solved at higher sys-tem levels. This is important when available power or silicon real estate is at apremium or when constructing custom cell libraries.
1In all the designs here we use an inverting gate as the source of the secondary signal. Thisisn’t absolutely necessary, but this choice carries a great deal of simplification power with it.
39
Chapter 3
Miscellaneous Problemsand Solutions
Here is a collection of sequential logic synthesis problems with solutions. Othersolutions to these same problems are possible, so these shouldn’t be taken asdefinitive or necessarily optimal. Nevertheless, it is believed that they representgood solutions which are in some sense minimal.
The solution process follows the outline in the previous section. No funda-mentally new issues will arise, but each problem may have some unique aspectwhich may require explanation. Considerations of symmetry in the implemen-tation phase of the development will be given in some cases, and the handlingof exceptions to the general procedure will also be treated.
3.1 Clock Stream Switch
The circuit required here is to act as a clock stream multiplexer. It will have aclock input C, an enable E, and two outputs C1 and C2. The clock input is tobe routed through the circuit to one of the two outputs, depending on the stateof the enable line. The enable input, E is asynchronous with the clock streamand may switch at any time. The outputs, however, should complete the clockcycle in process before they switch so that only full clock periods are presentedto the driven circuits. The output lines should be low when they are ‘off’ (noclock stream is being passed through) and should follow the clock in the samepolarity when they are ‘on’.1
A suitable flow table is shown in Table 3.1. After merging and sorting therows we have Table 3.2. Note that this table has one completely unspecifiedrow already. This is because we were able to merge the original table into threerows, but three rows require two secondary variables. Thus an additional uniquecombination of secondary variables is unused and available.
1A fixed delay from the source clock to the output clock is acceptable.
40
CE00 01 11 10 C1 C2
(1) 3 – 2 001 – 6 (2) 011 (3) 4 – 00– 3 (4) 5 101 – 4 (5) 10– 3 (6) 2 01
Table 3.1: Flow Table for Clock Stream Switch
CE00 01 11 10 C1 C2
(1) (3) 4 2 001 3 (6) (2) 01– – – – –1 3 (4) (5) 10
Table 3.2: Merged, Sorted Flow Table for Clock Stream Switch
Having sorted the rows, the secondary assignments follow easily. C1 and C2
are identified with Y1 and Y2, respectively. Secondary assignments are indicatedin Table 3.3 with the composite map entries.
The equations for the circuit are shown (3.1) and (3.2), and are implementedin the final circuit shown in Figure 3.1.
Y1 = y1C + CEy2 (3.1)
Y2 = y2C + CEy1 (3.2)
CEy1 y2 00 01 11 10 C1 C2
00 00 00 10 01 0001 00 00 01 01 0111 – – – – –10 00 00 10 10 10
Table 3.3: Secondary Assignments for Clock Stream Switch
41
�
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�
�� �@
•
•
•
•
•• •
•
Y1
Y2
C
E
CE
CE
Figure 3.1: Clock Stream Switch
3.2 Two-Phase Clock Generator
This circuit can best be described by referring to Figure 3.2. It has a singleinput, C, and two outputs, φ1 and φ2. The input is an externally providedclock signal which is to be separated into a phase-one and phase-two portion.For this reason, the circuit is sometimes referred to as a clock separator or an‘underlapped’ clock generator.
Input Clock - C
Phase One - φ1
Phase Two - φ2
Figure 3.2: Timing Diagram for Two-Phase Clock Generator
The flow table is shown in Table 3.4. Note that this flow table is the sameas the table for the ‘T’ flip-flop except for the output assignments. Because theoutputs are not unique for two of the rows (row 1 and row 3), we cannot directlyassign secondary variables to them.
From our previous experience with the designs in this paper, we might betempted to try expanding the table. This would, of course, lead us to a so-lution. But we have a different approach in mind. Because of the similarity
42
C0 1 φ1 φ2
(1) 2 112 (3) 01
(3) 4 111 (4) 10
Table 3.4: Flow Table for Two-Phase Clock Generator
of the flow table with that of the ‘T’ flip-flop, we choose to examine our pre-vious implementation of the ‘T’ flip-flop to look for already decoded variableswhich might correspond to φ1 and/or φ2. Remember that we typically assignsecondary variables to outputs so that decoding is not necessary, but such as-signment decisions are purely for convenience and may not always be possibleor yield the simplest circuit.
The effort required to examine the ‘T’ flip-flop is easily worth the cost.Skeletal flow tables from that device but with stable state entries correspondingto the truth table values for φ1 and φ2 are shown in Table 3.5. We can derive theequations for those outputs from this table, assuming the same row assignmentsas were used for the ‘T’ flip-flop (not shown in these maps).
C0 1 φ1 φ2
(1) 11(0) 01
(1) 11(1) 10
φ1
C0 1 φ1 φ2
(1) 11(1) 01
(1) 11(0) 10
φ2
Table 3.5: Skeletal Maps for φ1 and φ2
On these assumptions, the decode values for φ1 and φ2 are:
φ1 = C + y1 (3.3)
φ2 = C + y1 (3.4)
Except for the change of input variable from T to C these same signals areavailable already. (See Figure 1.2 for the locations of these pre-existing signals.)Therefore, we do not need to separately implement this circuit — we merelyredraw our implementation of the ‘T’ flip-flop to identify the required outputs.This is done in Figure 3.3.
43
�
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��
�
�@
@
@
�@
•
•
•
•
•
••
•
C
Y1
Y2
φ1
φ2
Figure 3.3: Two-Phase Clock Generator
3.3 Glitch Suppressor
In a sense, this glitch suppressor is the counterpart of the Negative Pulse Gen-erator designed earlier. The relation is so close, in fact, that the same circuitprovides both functions. We will pose the problem statement in such a way asto show this.
We require a circuit which will suppress narrow positive spikes on a signalline. The output of the circuit will be an inverted and slightly delayed versionof the input — minus the spikes.
An appropriate flow table is shown in Table 3.6. The only change from theflow table for the pulse generator is in the output requirements. Here we haveused the second row to accomplish the suppression.
Xy1 y2 0 1 Z10 (1) 2 100 – 3 101 – 4 011 1 (4) 0
Table 3.6: Flow Table for Glitch Suppressor
For example, if the circuit is momentarily taken from stable state 1 to state2 by a change at the input from low to high, the output will, at first, remainhigh. If the input signal which caused this action suddenly reverts to low, the
44
circuit will return to state 1 with no change in the output. If, on the otherhand, the input remains high long enough for the circuit to reach state 4, theoutput will go low.
We could have increased the suppression span by demanding that the outputbe high in row three, but by accepting the shorter value we can identify theoutput with y2 or its equivalent. In the implemented circuit (see Figure 3.4) wehave found that X + y2 meets our requirements.
�
�
�••
•
X
Z
Y2
Y1
Figure 3.4: Positive Glitch Suppressor
3.4 Digital Single Shot
The digital single-shot is a circuit which picks out a single, full-sized clock pulsefrom a regular clock signal stream for transmission to the output. The clockinput, C, and the control line, E, are the only inputs. Q is the only output. Wewill require that the output pulse be negative for positive clock pulses and thatthe control (enable) line be active true. A timing diagram is shown in Figure3.5.
������������������
Clock - C
Enable - E
Output - Q
Figure 3.5: Timing Diagram for Digital Single Shot
The merged flow table is shown in Table 3.7 and the equations derived fromit are in (3.5) and (3.6).
Y1 = Cy2 + Ey1 (3.5)
45
EC00 01 11 10 Q(1) (2) (8) 3 11 – 4 (3) 11 (5) (4) 6 01 2 (7) (6) 1
Table 3.7: Merged Flow Table for Digital Single Shot
Y2 = Cy2 + ECy1 (3.6)
The completed circuit is shown in Figure 3.6.
�
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��
•
•
•
• Y1
Y2
Q
E
C
Figure 3.6: Digital Single-Shot
Caveats and Cautions — A Potential Problem
This circuit contains a potential problem. It occurs if the rising edges of E andC are simultaneous, or nearly so. In this case a malfunction may occur in whicha brief glitch or oscillation appears on the output. The reason this situationarose is that we chose to designate that cell in the primitive flow table as a‘don’t care’. If the positive edges are separated by at least three gate delays,the circuit will operate as advertised.
Now, in most of the previous circuits we have treated simultaneous inputchanges in two or more inputs as ’don’t cares’. Typically, this simplifies themerging process and also simplifies the resulting circuit. In many cases the onlypenalty is uncertainty over which final stable state the circuit will choose. Inthis circuit, malfunction can occur, so the edge separation is required.
If the user’s application can accept this limitation, no further action is indi-cated. But if the application requires predictable behavior for coincident pos-
46
itive edges, a redesign is necessary. This is why we have frequently cautionedthe designer to examine circuits for unanticipated behavior.
Recall that we solved this kind of problem in the Up/Down Counter Con-troller for simultaneous negative going inputs. We dealt with it again in thePhase/Frequency Detector where simultaneous positive edges is the normal op-erating condition. Similar techniques can be used to solve the problem for thiscircuit. Redesign is left to the reader.
3.5 Master/Slave J-K Flip-Flop
3.5.1 The Flow Table
This device illustrates an interesting aspect of logic design — the compromiseof performance requirements vs. circuit complexity. For the ‘D’ flip-flop theproblem statement implied edge triggering and the resulting circuit is morecomplex than, say, a simple ‘R-S’ flip-flop or latch. In the problem statementfor the J-K flip-flop, we will accept a constraint on the inputs which simplifiesthe flow table and the corresponding circuit. The limitation is that the ‘J’ and‘K’ inputs must not change when the clock is high. This concession allows us toincrease the number of don’t care entries in the flow table, which will reduce thenumber of terms required in the circuit equations. The circuit outputs changeswhen the clock goes low.
Most of the popular Master/Slave flip-flops place this constraint on changingthe ‘J’ and ‘K’ inputs at the positive level of the clock, leading to the descriptivename ‘ones catcher’ for this device. The derivation presented here will show whythis is so.2 As will be seen later, the inverted sense of the clock is just as easyto implement.
Before deriving the flow table, we should look at the truth table descriptionof the desired circuit behavior. This is shown in Table 3.8.
J K Qn+1
0 0 Qn
0 1 01 0 1
1 1 Qn
Table 3.8: Truth Table for Master/Slave J-K Flip-Flop
This type of description is valuable for specifying the external behavior ofthe circuit and in constructing the flow table, but it does not have any meansof identifying input constraints or distinguishing between edge-triggered andlevel-sensitive operation. Nor does it indicate the clock polarity.
2The choice of logic levels for the clock is largely arbitrary, but we have chosen the negativeclock to comply with standard convention.
47
It is instructive to examine the full, unmerged flow table for this flip-flop.Such a table is shown in Table 3.9.
CJK000 001 011 010 110 111 101 100 Q(1) 2 – 4 – – – 8 01 (2) 3 – – – 7 – 0– 2 (3) 4 – 6 – – 01 – 3 (4) 5 – – – 0– – – 12 (5) – – – 0– – 11 – – (6) – – 0– 2 – – – – (7) – 01 – – – – – – (8) 0
(9) 10 – 12 – – – 16 19 (10) 11 – – – 15 – 1– 10 (11) 12 – 14 – – 19 – 11 (12) 13 – – – 1– – – 12 (13) – – – 1– – 3 – – (14) – – 1– 2 – – – – (15) – 19 – – – – – – (16) 1
Table 3.9: Flow Table for Master/Slave J-K Flip-Flop
The don’t care entries are due to the external restrictions on the ‘J’ and‘K’ input changes and the general restriction on multiple simultaneous inputchanges we have used before. We have used C = 1 on the right half of the tablewhere the restriction on input changes is in force.
Merging will reduce the number of rows from sixteen to four, as shown inTable 3.10. Because of the large number of initial don’t care entries, we stillhave some present in the merged table.
CJK000 001 011 010 110 111 101 100 Q(1) (2) (3) (4) 5 6 (7) (8) 0– – 11 12 (5) (6) – – 0
(9) (10) (11) (12) (13) 14 15 (16) 1– 2 3 – – (14) (15) – 1
Table 3.10: Merged Flow Table for J-K Flip-Flop
The secondary assignments derived from the merged flow table are shown inTable 3.11.
48
CJKy1 y2 000 001 011 010 110 111 101 10000 00 00 00 00 01 01 00 0001 – – 11 11 01 01 – –11 11 11 11 11 11 10 10 1110 – 00 00 – – 10 10 –
Table 3.11: Secondary Assignments for J-K Flip-Flop
3.5.2 The J-K Flip-Flop Circuit Equations
The equations for the secondaries are:
Y1 = y1C + y1y2 + y2C (3.7)
Y2 = y2K + y1y2 + y2C + CJy1 (3.8)
Implementing Y1 is straightforward, but the redundant term y1y2 must beincluded to prevent hazards from occurring during transitions between stablestates 12 and 13 in the merged flow table. Our grouping of the three terms isintended to exploit the obvious symmetry in the problem statement.
Y1 is, by our definition, an external secondary. It is directly identified withthe output, Q, and is easily implemented as shown in Figure 3.7.
�
��@
•
•
y2 +C
y2 +C
Q
Q
Y1
Figure 3.7: Implementation of Y1
Considerations of Circuit Symmetry
Suppose that some logic circuit can be represented by a box, as in Figure 3.8.The inputs are on the left, and the outputs are on the right. Internal feedbackis concealed within the box, so that external inputs and outputs are all that arevisible.
There may be an arbitrary number of inputs and outputs, but in order forthe circuit to qualify as a candidate for symmetric treatment the following rulesmust apply:
49
Input Output
Logic
Circuit
Axis of
Symmetry
Figure 3.8: Box Model of Logic Circuit
• Output lines will occur in related pairs; e.g., each Y will have a corre-sponding Y . It isn’t necessary that the problem statement require suchpairs, but only the circuit can be put in this form.
• Input lines will be of two types:
1. Clock or Trigger inputs, which will usually be single-ended in theproblem statement,
2. Other inputs which can be arranged in pairs with corresponding func-tions.
If the circuit specification is such that the box representation rules can beapplied, we should consider a fully symmetrical implementation.
There are several benefits in exploiting symmetry in a design. For one thing,it assures that corresponding inputs will have similar delay paths through thenetwork. Propagation delays which are equal for symmetric inputs have obviousadvantages to the user. For another, the logic implementation process has somany degrees of freedom that it may be largely undirected unless we adopt‘meta’ rules to restrict choices. Many different circuit arrangements can meeta given requirement, but some of the designs decisions will be more or lessarbitrary. Imposing external constraints allows us to meet other objectivesat the price of reducing the number of arbitrary decisions. Symmetry, likeminimization, is an aid in directing the design process.
The J-K flip-flop can be put in symmetric form, as shown in Figure 3.9.We have already implemented the external secondary, Y1, in a symmetrical
arrangement. Now we want to look more closely at the internals of the logic boxto see what rules are applicable to the rest of the circuit. We find the following:
• For every gate that exists on one side of the axis of symmetry, there willbe an identical gate in the mirror image position on the other side axis.
• All secondaries will exist in true and complemented forms (this followsfrom the previous item).
50
J
C
K
Q
Q
Figure 3.9: Box Model of J-K Flip-Flop
• Each gate input which comes from a secondary will have a mirror imageinput which uses the complemented secondary.
• Each gate which uses a single-ended or clock signal will have a correspond-ing mirror image input which uses the same signal.
• Each gate input which uses one of the paired input lines will have a mirrorimage counterpart using the other member of the pair.
A close examination of Figure 3.7 in light of these rules will help to clarifytheir usage. First, notice that Y1 does exist in true and complemented formalready as an R-S latch. Again, this was not part of the original problemstatement, but the circuit readily fits the symmetric template and the two signalsarose naturally in the implementation. But note that a different grouping of theterms in the equation for Y1 might have obscured the potential for symmetryrather than bringing it to the surface. Second, note that the input terms aresymmetric by our definition. The clock input is single-ended. Logic expressionswhich include the secondary, y2, will be implemented so that one of the mirrorimage inputs uses the true version and the other uses the complement.
Implementing Y2 provides a good opportunity to employ a design techniquewhich can reduce the effort in deriving gate input requirements from the outputequations. It is particularly useful in designs using NOR gates and AND-OR-INVERT blocks, but is not restricted to those devices. Instead of picking up the1s from a Karnaugh map to determine the locally true expression for a variable,we can pick up the 0s and invert the entire expression. This approach directlygives a Sum Of Products form for the inputs to the gate and relieves us fromhaving to apply DeMorgan’s theorem to determine what the inputs should be.On the other hand, it gives the input equation in a form which is not well-suitedfor NAND gate usage. NAND gate input requirements are better expressed in aProduct Of Sums form where each input line corresponds to one of the productterms.
The equation for Y2 using this technique is:
Y2 = y1y2 + Cy2 + y2J + y1CK (3.9)
51
Factoring out y2 so that only two inputs are required gives (on the inputside of the gate):
Y2 = y2(y1 + C + J) + y1CK (3.10)
The question, “Can this expression be implemented symmetrically?” is an-swered in the affirmative. To see this, consider the terms in (3.10). First,the equations defines, as many secondaries do, a cross-coupled latch or mem-ory element. Such equations, which are expressed in terms of one of the twolatch outputs (or its input), contain terms for both of the gates forming thelatch. Thus, (3.10) consists of two major terms. One, which is written: y1CK,represents a direct input line to the gate Y2, and the other, which is written:y2(y1 + C + J), represents the output of the other gate of the pair. We see thatthe direct term defines one input to Y2. The other term defines the other inputto Y2 and, since this signal comes from the other member of the latch, its in-verse defines the inputs required for the other gate. Thus, if we invert the secondterm, the resulting unimplemented inputs should satisfy our symmetry rules. Apartial implementation of Y2 is shown in Figure 3.10, where the symmetry canbe easily seen.
@�
•
•Y2
y1CK
y1CJ
Figure 3.10: Partial Implementation of Y2
The completed circuit is shown in Figure 3.11.Before leaving this design a few comments are in order. First, the circuit
as shown expects C as an clock input, rather than C. In our original problemstatement we made the decision to use negative clocking and built the flowtable to reflect that choice. But, since the circuit uses both the input clockand its inverse, we could accept either as an input and provide the other withan inverter. If the logic devices have equivalent delays, no critical races shouldoccur.
Second, our implementation of the external secondary, Y1, could have usedAND and NOR gates rather than NANDs. This is a ‘dealer’s choice’ issue.Other implementation choices could have been made as well.
Third, the Master/Slave J-K flip-flop represents a simple problem in design-ing by symmetry rules. The Edge-Triggered J-K flip-flop in the next section ismore complex, and some of the subtle difficulties in dealing with symmetry aretaken up there.
Finally, this is a good example of a circuit type which calls out for asyn-chronous set and clear imputs. Because of their symmetric role, they can also
52
�
�
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�
�
�� @��@
•
•
•
•
••
K
C
J
Q
Q
Y1
Y2
Figure 3.11: Master/Slave J-K Flip-Flop
be retrofitted symmetrically. The solution to this design challenge is left to thereader.
3.6 Edge-Triggered J-K Flip-Flop
The best way to avoid having to impose restrictions on changing the inputs toa J-K flip-flop when the clock is high (or low) is to require that the flip-flop beedge triggered. The design will be more involved in this case, but the addedcomplexity may be worth the added difficulty.
3.6.1 The Flow Table
For the edge-triggered J-K flip-flop the flow table must account for input changeswhen the clock is in either state. Only at the time of a clock change will thevalues of the ‘J’ and ‘K’ inputs matter. We will build the flow table for positiveedge triggering, but otherwise the circuit behavior is completely described bya truth table which is similar to the previous Master/Slave J-K version, ex-cept that here we will use positive edge-triggering rather than negative leveltriggering.
3.6.2 Edge-Triggered J-K Flip-Flop Flow Table
The full flow table is shown in Table 3.12.Merging is straightforward, except that there are fewer don’t cares than there
were in the Master/Slave flip-flop. The merged table is shown in Table 3.13Secondary assignments present no difficulties, largely because of the care we
have taken in constructing the flow table. The result is shown in Table 3.14.
53
CJK000 001 011 010 110 111 101 100 Q(1) 2 – 4 – – – 8 01 (2) 3 – – – 7 – 0– 2 (3) 4 – 14 – – 01 – 3 (4) 13 – – – 0– – – 4 (5) 6 – 8 0– – 3 – 5 (6) 7 – 0– 2 – – – 6 (7) 8 01 – – – 5 – 7 (8) 0
(9) 10 – 12 – – – 16 19 (10) 11 – – – 7 – 1– 10 (11) 12 – 6 – – 19 – 11 (12) 13 – – – 1– – – 12 (13) 14 – 16 1– – 11 – 13 (14) 15 – 1– 10 – – – 14 (15) 16 19 – – – 13 – 15 (16) 1
Table 3.12: Flow Table for Positive Edge-Triggered J-K Flip-Flop
3.6.3 The Circuit Equations
The equation for Y1 is:
Y1 = y1C + y1y2 + y2C (3.11)
Note that this is the same as the equation for Y1 of the Master/Slave device.Rather than dwell on the implementation, we can just take it from the previousdesign. See Figure 3.7.
The implementation of Y2 is more of a challenge. We begin by writing theequation for Y 2 in order to deal directly with the input side of a NOR latch.Equation (3.12) contains all the zeros and only the zeros from the Karnaugh
CJK000 001 011 010 110 111 101 100 Q(1) (2) 3 4 (5) (6) (7) (8) 01 2 (3) (4) 13 14 – – 0
(9) 10 11 (12) (13) (14) (15) (16) 19 (10) (11) 12 – 6 7 – 1
Table 3.13: Merged Flow Table for Edge-Triggered J-K Flip-Flop
54
CJKy1 y2 000 001 011 010 110 111 101 10000 00 00 01 01 00 00 00 0001 00 00 01 01 11 11 – –11 11 10 10 11 11 11 11 1110 11 10 10 11 – 00 00 –
Table 3.14: Secondary Assignments for Edge-Triggered J-K Flip-Flop
map for Y2. We have included redundant terms or tie sets covering those statesbetween which transitions can occur.
Y2 = CJy1 + CKy1 + Cy1y2 + Ky1y2 + Jy1y2 (3.12)
Since we wish to avail ourselves of readily available signals we will group theterms of (3.12) as in Equation 3.13. This provides us with a starting point forour design by symmetry.
Y2 = Ky1(C + y2) + y1(CJ + Cy2 + Jy2) (3.13)
3.6.4 The Implementation
�
�
�
�
Y2
y1
y2 +CK
y1
Figure 3.12: 1st Partial Implementation of Y2
A partial implementation of Y2 provides clues which will carry us forward tothe complete circuit. See Figure 3.12. We can see from the terms in (3.13) thattwo AND gates will be required at the input of Y2, hence the mirror image gate,which we expect to identify with y2, also has two AND gates. The symmetric
55
signal requirements are spelled out in Figure 3.13, in accordance with the rulesgiven previously.
�
�
�
�
•
•
Y2
y1
y2 +CK
y1
Jy2 +C
y1(y1 + J + Cy2)
Figure 3.13: 2nd Partial Implementation of Y2
The schematic diagram in Figure 3.13 can be derived from the partial schematicin Figure 3.12 by appealing to the rules of symmetry. Now we should assessour progress by looking at the partially developed output of the mirror imagegate, and comparing it with the remaining requirements for the input to Y2.Naturally, we would like to cross couple the gates as soon as we are certain thatthe equation for Y2 is satisfied.
We see from (3.13) that we need to provide CJ + y2C + Jy2 at the unusedinput to the upper AND gate of Y2. The output of the mirror image gate willproduce this if it is ANDed with the existing signal C + y2. We must verify,however, that connecting the lines suggested by symmetry does not invalidatethe equation. This validation and the assurance that cancellation of literals doesnot introduce new problems is left as exercises. The complete circuit is shownin Figure 3.14.
A Comment on the Concept of Edge-Triggering
The term ‘edge-triggering’ is used rather loosely in logic hardware literature. Itsmeaning must be determined from the context, because there are two distinctsenses in which the term is used. One, to mean event driven and two, to meanedge sensitive (as opposed to level sensitive).
An event driven device3 may be designed to perform its function on therising or falling edge of some input, but may not be immune to changing in-put conditions at other times. On the other hand, an edge sensitive device is,presumably, unaffected by input changes at any time except near the rising or
3We may consider state transitions or edges to represent events. When all transients havecompleted, we are in a steady state.
56
��
��
�
�
�
���@@��@@
•
•
•
•
•
••
•
•
•
•
Y1
Y2K
J
C
Q
Q
Figure 3.14: Edge-Triggered J-K Flip-Flop
falling edge of some specific input. The term pulse triggered is also sometimesuse to refer to clocked devices which are designed to respond to a relativelynarrow input clock.
Data sheets for many J-K flip-flop implementations refer to them as edge-triggered when, by our definition, they are not. Specifically, we define an edge-triggered device to be one which is driven by the stated edge of its input line,and whose next state is determined solely by the conditions that exist at or nearthe time of the triggering event. Input changes that occur at other times have noeffect on the operation of the device. Of course, practical circuit implementationconsiderations will affect the specific timing limits for any circuit. These shouldbe identified in the set up and hold time specifications.
For example, the Master/Slave J-K flip-flop is intended to perform its func-tion when the appropriate clock occurs and it is the leading edge of the clockwhich drives the output changes. Nevertheless, when the clock is high, changesin the ‘J’ or ‘K’ inputs can change the intended future state.4
It is important to read the fine print in the data sheets to determine whetherthere are any constraints on the inputs during either state of the clock for aspecific device. Don’t depend on ambiguous terminology in selecting a devicefor your application.
4This property leads to the ‘ones-catching’ behavior sometimes noted in the literature.
57
Part II
Analysis Methods
58
Chapter 4
Sequential Circuit Analysis
Synthesis is the major problem in digital circuit design. Analysis, although itenjoys wide coverage in the analog domain, and even in digital signal processing,is poorly represented in the digital logic domain. Nevertheless, analytic toolsare powerful aids in solving the synthesis problem and in understanding orverifying the performance of existing digital circuits. We need a good analyticmethod if we are to be able to examine the schematic for a given logic circuitand answer the questions: What does it do? How can we use it? Will it meetcertain requirements? In other words, the analysis problem we are addressingis behavior analysis, not timing analysis.
In this chapter, we present a method for analyzing sequential circuits whichcomplements the synthesis procedures given earlier. The process is almost ex-actly the reverse of that for circuit synthesis. With few exceptions,1 it canbe used to derive the governing Boolean equations for a given circuit, and toreconstruct the flow tables and high level behavioral descriptions.
4.1 Fundamental Properties of Secondary Vari-ables
Before presenting the analysis method, we should gain a clear understandingof what a secondary (internal) variable is, and what its role is in satisfying theoverall sequential circuit requirements.
In the literature it is shown that secondary variables are associated withinternal states of a sequential state machine, i.e., a machine whose currentoutput depends on previous outputs as well as present inputs.2 These internalstates can be numbered and identified, for example, with some kind of binary
1Some logic circuits are designed to exploit special properties of the devices used to imple-ment them, and their behavior cannot be completely specified by a formal method.
2For purely combinational circuits, no secondary variables are required because the outputvalues are completely determined by the current input values.
59
counter which has a sufficient number of stages to uniquely determine them.Thus, we expect approximately log2(n) latches for every n states.
We further expect that in examining the equations for a sequential machinewe will find equations for memory or storage elements which cannot be reducedto purely combinational form. The difference between combinational equationsand sequential equations is of fundamental importance, leading us to considerthe question of what that difference is, and how to identify it.
There is no better way to understand the algebra of memory than to examinethe simplest memory element: the cross-coupled latch. In Figure 4.1 we showan R-S flip-flop whose boolean equation can be written:3
Q = S + qR (4.1)
�
��@
•
•
Q qS
R
Figure 4.1: Cross-Coupled Flip-Flop (Latch)
The memory feature of this circuit is found in the presence of the Q term inboth the input and output of the circuit equation. From an analog perspective,this is feedback with greater than unity gain. If the S and R lines are set to 1,then the circuit equation reduces to Q = q, which is an identity. Thus, if q was1 then Q will be 1. Similarly, if q was 0 then Q will be 0. When we speak ofmemory in a digital circuit context, this behavior is what we mean.
Notice that the only way to prevent the latch from remaining forever in thesame state is to active S or R. (Of course, we are assuming that power to thecircuit is always available.) S is the means to force a 1 state and R is the meansto force 0. In general we will find that memory elements, or secondaries, will bedefined by equations of the form,
Y = f(xi, yj) + y · g(xm, yn) (4.2)
where f(xi, yj) and g(xm, yn) are functions of the inputs, Xp and outputs, Yq.The variable y can be forced to either state by appropriate manipulation of theprimaries and secondaries, and will serve as a memory element when f(xi, yj)is false and g(xm, yn) is true. Corresponding equations for NOR latches orcombinations of gates can be developed as long as the elements have gain, delay,and can be connected so as to satisfy the memory requirements.
3R and S stand for Reset and Set, respectively.
60
4.2 An Outline of the Analysis Method
Our analysis strategy will be to develop the circuit equations for the given circuitfrom the schematic diagram and to construct the flow table from the equations.We will then determine the stable state behavior from the flow table, giving usthe information needed to generate a high level description.
The procedure will follow a simple set of elementary steps:
• Label each of the input signals,
• Label all gates with arbitrary names or symbols,
• Write the equations for each gate in terms of the labeled gates and theinput signals,
• Reduce the equation set by the elimination of unnecessary internal vari-ables,
• Construct the flow table from the remaining equations,
• Identify the stable states,
• Formulate a circuit description.
We will step through the solution of several example problems to illustrateand clarify the procedure.
4.3 A Simple Example
Although we have chosen the Negative Pulse Generator for this example, wewill assume no prior knowledge of the circuit behavior. The circuit design isprovided to us with no description and only the unlabeled schematic.
4.3.1 Labeling the Circuit Elements
First, we must label the inputs and gates. This is shown in Figure 4.2.We are using upper case alphabetic characters to identify the gates, and lower
case letters to identify the output signals from those gates. This is essentially amnemonic device and could be replaced by some other labeling scheme.
4.3.2 Writing the Raw Circuit Equations
We may write the equations directly from the labeled schematic.
A = X + c (4.3)
B = X + a (4.4)
C = a+ b (4.5)
(4.6)
61
�
�
�
•
••
X
b
AC
B
Figure 4.2: Unknown Circuit with Labels
We have placed the gate label, possibly representing a secondary variable, onthe left side of each equation and the terms of the required equation on the right.This is also a convenient strategy, but it reminds us that the Boolean equationsin a sequential circuit are not true equalities — they are flow statements. Weunderstand them to mean that the conditions on the right side of the equation(true or false) determine the condition on the left.4
Clearly the memory capability (if any) of the circuit is hidden among theequations which describe the relations between the variables, and some stepsmust be taken to uncover memory elements. This is the heart of the analysisprocedure.
4.3.3 Reducing the Equations
For a combinational circuit we can label gates and write equations as we havedone for the circuit we are presently examining. But we can also describeeach output solely in terms of the inputs. Thus, for the output of each gate,we can substitute the controlling expression (possible inverted) for its input,and eliminate the unnecessary label it used. By successive eliminations we caneventually represent all outputs in terms of the inputs.
For a sequential circuit, the substitution process will terminate differently.We will eventually arrive at a minimum set of equations involving inputs andmemory elements beyond which no further reduction is possible. In some caseswe will have irreducible equations which indicate essential secondaries, and re-ducible equations which represent circuit outputs. We will retain the latter,even if they are reducible, but our objective is not to eliminate gates from theequations set, but only to eliminate unnecessary labels. The remaining labelswill be used in the expanded flow table.
The process of reduction begins by examining the circuit to identify any out-put signals which, for convenience, we wish to identify with secondary variables.Clearly B, in the present example, is an obvious choice for a secondary and we
4It actually would have been better to use arrows instead of equal signs, but we prefer tosubmit to convention rather than unnecessarily disturbing it.
62
will proceed with this in mind. Turning to the equation for A, we see that allinstances of a in the other equations can be replaced by X + c. By making thisreplacement, we find that no secondary called A is actually needed. Hence wecan reduce the equation set to,
B = X + Xc (4.7)
C = b+ Xc. (4.8)
Now, the equation for C is clearly that of a memory element, and cannot beeliminated because it contains itself as a term. We could attempt to eliminateB, but that would be absurd because it is the generator for the circuit outputsignal. At this point we have a set of equations which describe a sequentialcircuit constructed from an expanded flow table.
One further simplification of the equations is possible. The X term in theequation for B is redundant. We can therefore simplify B to,
B = X + c. (4.9)
4.3.4 Constructing the Flow Table
Having derived equations for the circuit, we can now construct the truth tablefrom which the flow table is derived. This truth table has the same structureas the Karnaugh map for the circuit variables. Because of this identificationbetween the map and flow table, we need not be too rigorous in our terminol-ogy. The main difference between the map and flow table is that the table isconcerned with state changes and the map facilitates term grouping.
First, we determine the number of rows and columns from the number ofinputs and secondaries. An appropriate skeletal table is shown in Table 4.1.
Xb c 0 1 B00 001 011 110 1
Table 4.1: Skeletal Flow Table (map) for Example Circuit
Now we simply fill in the truth values derived from the equations. That is,B is true whenever X is false or C is true. We but the ones in the table for allthese cells, and put zeros in the remaining cells. Since we have two secondariesto consider, we can double up and put the truth values for both B and C in themap at once. We have done this in Table 4.2. On completion of the map, we
63
can identify those cells which represent stable states as those cells whose entriesagree with their row assignments. These are already identified in the table.
Xb c 0 1 B00 11 01 001 11 11 011 10 (11) 110 (10) 00 1
Table 4.2: Karnaugh Map for Example Circuit
Although it is not necessary, we can convert this to the same form as wasused in the Negative Pulse Generator. The conversion simply consists of re-labeling the input and secondaries, coupled with re-ordering of the rows anddecimal numbering of the stable and unstable states. None of these operationsalters the circuit behavior.
4.3.5 The Circuit Description
The stable state change that occurs when the input X falls does not produceany output response. This is seen by simply tracing the behavior from thestable state cell labeled ‘11’ to the adjacent cell and then into the row with thecorresponding entry. On the other hand, when X rises, the circuit produces thenegative pulse for which it was originally designed. Our analysis has successfullyretained and identified the performance feature of interest and provided us witha complete description.
4.4 Another Example
Given the circuit in Figure 4.3, derive the circuit equations, generate a flowtable, and provide a description of its function.
4.4.1 The Circuit Equations
Using the labels we have placed on the gates, we write the following equations,
A = X1 + X2 (4.10)
B = X1 + d (4.11)
C = X2 + d (4.12)
D = a+ b+ c. (4.13)
64
�
�
�
��•
•
••
A
B
C
D
X1
X2c
Figure 4.3: 2nd Example Circuit
We will retain C because it is a required output signal, and retain D becausewe can see that it is part of an internal latch. B or D could be retained, aseither one could be identified with the memory element.
Eliminating A and B by substitution, we have,
C = X2 + d (4.14)
D = X1X2 + X1d+ c. (4.15)
4.4.2 The Flow Table
We can now construct the truth table. There are two inputs and two secondariesof interest. A table with the truth values derived from the equations is shownin Table 4.3. We have also identified the stable states in the table.
X1 X2
c d 00 01 11 10 C00 11 11 11 11 001 11 (01) (01) 11 011 10 00 01 (11) 110 (10) (10) (10) 11 1
Table 4.3: Karnaugh Map for 2nd Example
At this point we will move on to the construction of a flow table. We dothis by numbering the stable states as shown in Table 4.4, where the unstablestates with a Hamming distance of unity are also shown.
To create the primitive flow table we need only build a table with one rowfor each stable state and fill in the unstable cells from the merged table in Table4.4. Note that stable states 3 and 4 are the only stable states in their respective
65
X1 X2
00 01 11 10 C–
(1) (2) 3 04 – 2 (3) 1
(4) (5) (6) 3 1
Table 4.4: Partial Flow Table for 2nd Example
columns, so it is reasonable to fill the remaining cells in those columns with thesame number, although we could also leave them initially blank.
In fact, we do not really need the expanded table to determine the circuitbehavior. From inspection of the merged table we can see that there are twopossible output levels. The output zero level is associated with stable states 1and 2, and can only be entered following state 3. The only way to return theoutput to the one level is by moving to state 3 or 4.
States 2 and 3 represent a cycle or loop. When in one of these states thecircuit moves to the other following a change in X2. Thus, X2 is passed invertedto C in this mode. Before entry to this mode, or after exit via state 4, the output,C, stays high.
The circuit is a synchronous clock enable. Inspection of the flow table showsthat it is designed to pass (inverted) the first full length positive pulse whichoccurs on X2 (clock) after X1 (enable) is raised, and to pass all subsequentpulses until X1 is lowered, permitting the last pulse to complete before raisingthe output line. It is similar to our earlier Clock Stream Switch, and was takenfrom a partial schematic for a 74120 pulse synchronizer.
4.5 Caveats and Cautions
As mentioned in an earlier footnote, this analysis procedure will not necessarilyreverse the synthesis procedure used to to create every device. Some designsdepend for their operation on special properties of the components used in theimplementation. For those cases, part of the logic description is implicit in theelements used, and may not be amenable to the analytic procedure describedhere.
Finally, since the synthesis procedure often involves arbitrary decisions andcreative adjustments, the analysis procedure may not be entirely straightfor-ward. Be prepared to consider any analysis problem from a fresh point of view.
In spite of these limitations, the analysis procedure will work on all thedesigns presented in this paper, and most of the designs one is likely to encounterin practice.
66
Bibliography
[Cald 58] S. H. Caldwell, Switching Circuits and Logical Design, John Wiley& Sons, 1958.
[Huff 54] D. A. Huffman, The Synthesis of Sequential Switching Circuit, J. ofFranklin Institute, pp. 275–303, March and April 1954.
[Huff 55] D. A. Huffman, The Design of Hazard-Free Switching Networks,M.I.T. Press, Cambridge, Mass., 1955.
[Karn 53] M. Karnaugh, The Map Method for the Synthesis of CombinatorialLogic Circuits, Comm. and Electronics, No. 9, 1953.
[Maley 63] G. A. Maley, The Logic Design of Transistor Digital Circuits,Prentice-Hall Inc., Englewood Cliffs, N.J., 1963.
[Marc 62] Mitchell P. Marcus, Switching Circuits for Engineers, Prentice-HallInc.,Englewood Cliffs, N.J., 1962.
[Mealey 55] George H. Mealey, A Method for Synthesizing Sequential Circuits,Bell System Technical Journal, September 1955.
[Moore 54] E. F. Moore, Gedanken-Experiments in Sequential Machines, Au-tomata Studies, Princeton University Press, 1954.
[Ung 59] S. H. Unger, Hazards and Delays in Asynchronous SequentialSwitching Circuits, IRE Trans. Circuit Theory, Vol. CT-6, pp. 12–25,March 1959.
67
Index
analysismethod, 61
asynchronous, 5
Boolean, 8, 21algebra, 5equation, 32, 59, 60, 62function, 21
charge pump, 29circuit
analysis, 59reduction, 62sequential, 5, 6, 40, 59, 62, 63synthesis, 40
circuit symmetry, 49clear, 6, 21, 22clock stream switch, 40–41counter controller, 25–29
DeMorgan’s theorem, 5, 10, 33, 34, 51don’t care, 25, 31
edge-triggered, 12edge-triggering, 56equation
circuit, 5, 9, 10, 14, 21, 27, 33, 35,49, 54, 60, 61, 64
secondary, 9
flip-flopD, 6, 12–22edge-triggered, 53–56J-K, 47–56master/slave, 47–53R-S, 60T, 7–11, 15, 43
flow table, 5, 7, 12, 22, 23, 26, 29, 40,42, 44, 45, 47, 53, 63, 65
expanded, 31merged, 13, 19, 30, 53skeletal, 19, 34, 63
glitch suppressor, 44–45
hazardcritical, 10, 11, 15, 49dynamic, 15static, 15suppresion, 17suppression, 11, 15, 16, 19
Karnaugh map, 5, 19, 65
latch, 21, 28, 60logic
combinational, 5
merge, 12, 12metastable, 28
phase-locked loop, 29phase/frequency detector, 29–36pulse generator, 23–25
race condition, 11
secondarystrong, 29weak, 29
set, 6, 21, 22signal
clear, 21identification, 21inversion, 11
68
location, 21preset, 21
single shot, 45–46stable state, 21state
stable, 7, 8, 19transitional, 7, 23
state machine, 5, 59synchronous, 5synthesis, 37
truth table, 9, 63two-phase clock, 42–43
up-down counter, 25
variableprimary, 19secondary, 8, 13, 19, 21, 31, 40, 59
69