advanced io wizard v1.0 pg320 (v1.0) july 14, 2020 · and tools, contact your local xilinx sales...

Advanced IO Wizard v1.0

LogiCORE IP Product Guide

PG320 (v1.0) December 15, 2020

https://www.xilinx.com

Table of ContentsChapter 1: Introduction.............................................................................................. 4

Features........................................................................................................................................4IP Facts..........................................................................................................................................5

Chapter 2: Overview......................................................................................................6Navigating Content by Design Process.................................................................................... 6Core Overview..............................................................................................................................6Applications..................................................................................................................................7Unsupported Features................................................................................................................7Licensing and Ordering.............................................................................................................. 7

Chapter 3: Product Specification........................................................................... 9Performance.............................................................................................................................. 10Port Descriptions.......................................................................................................................10

Chapter 4: Designing with the Core................................................................... 15Clocking...................................................................................................................................... 15Resets..........................................................................................................................................18Asynchronous Mode Support (Beta Support)....................................................................... 18Bi-Directional Mode Support................................................................................................... 19Use the Example Design...........................................................................................................20TCL XDC Flow in Advanced IO Wizard.....................................................................................21

Chapter 5: Design Flow Steps.................................................................................22Customizing and Generating the Core...................................................................................22Constraining the Core...............................................................................................................36Simulation.................................................................................................................................. 36Synthesis and Implementation................................................................................................37I/O Planning for Versal Advanced IO Wizard.........................................................................37

Chapter 6: Example Design..................................................................................... 49

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Chapter 7: Test Bench.................................................................................................50

Chapter 8: Advanced IO Wizard Tutorial......................................................... 51Design Description....................................................................................................................51Create a Project......................................................................................................................... 52Create and Configure the Advanced IO Wizard.................................................................... 53Create and Configure the Clocking Wizard IP....................................................................... 54Create Constant IP, and Connect the IPs............................................................................... 57Close the Block Diagram, and Generate the RTL Wrapper.................................................. 59Elaborate the Design, and Assign I/O Package Pins.............................................................59Review XDC Constraints, and Run Implementation..............................................................63Summary.................................................................................................................................... 64

Appendix A: Debugging............................................................................................ 65Migration....................................................................................................................................65Finding Help on Xilinx.com...................................................................................................... 66Debug Tools............................................................................................................................... 67

Appendix B: Additional Resources and Legal Notices............................. 68Xilinx Resources.........................................................................................................................68Documentation Navigator and Design Hubs.........................................................................68References..................................................................................................................................68Revision History......................................................................................................................... 69Please Read: Important Legal Notices................................................................................... 69




Chapter 1

IntroductionThe Xilinx® LogiCORE™ Advanced IO Wizard simplifies the integration of SelectIO™ technologyinto high-speed system designs for Versal™ devices. The Advanced IO Wizard creates a wrapperfile that instantiates and configures IO and clocking logic such as XPHY_NIBBLE and XPLL blockspresent in the physical-side interface (PHY) architecture. The Advanced IO Wizard also providesan optimized default pin placement for the interface with pre-defined grouping of pins. TheAdvanced IO Wizard supports a wide range of interfaces, particularly high performanceinterfaces.

Features• Supports source synchronous and asynchronous I/O interfaces using high performance XPHYprimitives.

• Supports user selectable interface types such as TX, RX, BIDIR or a mix of all bus directions.

• Provides Advanced TCL mode for customization features that are not found in wizard GUI,and allows overriding of all SelectIO supported attributes of XPHY.

• For RX and BiDir interface, the clock/strobe to data relationship is selectable based on theprotocol setting.

• Serialization factor of 8-bit, 4-bit, and 2-bit is supported.

• Range of the user selectable XPLL input clock frequencies for a given data speed.

• Optional register interface unit (RIU) interface and bitslip logic.

• Provides optimized pin planning solution through automation with pins grouped into pre-defined sets, and can customize after autoplace for specific pin locations.

Chapter 1: Introduction




IP FactsLogiCORE™ IP Facts Table

Core Specifics

Supported Device Family1 Versal™ ACAP

Supported User Interfaces RIU

Provided with Core

Design Files RTL

Example Design Verilog

Test Bench Verilog

Constraints File Xilinx® Design Constraints (XDC)

Simulation Model Yes

Supported S/W Driver2 N/A

Tested Design Flows2

Design Entry Vivado® Design Suite

Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.

Synthesis Vivado Synthesis

Support

All Vivado IP Change Logs Master Vivado IP Change Logs: 72775

Xilinx Support web page

Notes:1. For a complete list of supported devices, see the Vivado® IP catalog.2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.

Chapter 1: Introduction


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Chapter 2

Overview

Navigating Content by Design ProcessXilinx® documentation is organized around a set of standard design processes to help you findrelevant content for your current development task. This document covers the following designprocesses:

• Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardwareplatform, creating PL kernels, subsystem functional simulation, and evaluating the Vivado®

timing, resource use, and power closure. Also involves developing the hardware platform forsystem integration. Topics in this document that apply to this design process include:

• Port Descriptions

• Clocking and Resets

• Customizing and Generating the Core

• Chapter 6: Example Design

Core OverviewThe Advanced IO Wizard core provides the source HDL wrapper for the high performance XPHYnibble primitives. It also generates optimum pin placement for the user-defined interface pins.

The wizard configures bus direction, clock to data alignment, interface speed, XPLL clock source,XPLL input clock frequency, and IO standard selection for the interface. The wizard builds acomplex high speed I/O interface through XPHY parameter settings, clock setup, clock routing,and forwarding that allows simple I/O user input for complex applications. Additionally, bitslipcan be enabled for RX/BiDir pins.

The wizard also configures pin/bus selection, bus direction, signal type, data/strobe, and signalname. It allows you to choose the TX/RX/BiDir bus direction for the signals in the interface. EachIO bank contains 54 pins that can be configured as TX/RX/BiDir. The wizard provides thefollowing features:

Chapter 2: Overview




• TX/RX/BiDir

• Single ended/Differential

• Data/Strobe/Input clock/Clock forward/WrClk/RdClk

• Customizable bus signal name

ApplicationsThe Advanced IO Wizard core is used in applications that need SelectIO technology that issource synchronous or asynchronous in nature for data speeds supported by XPHY. Refer to thedatasheet for information on speeds.

IMPORTANT! The Advanced IO Wizard is the only way to access XPHY outside of NoC MemoryController or Soft Memory Controller.

Unsupported FeaturesThe following features are not supported in the core. See Versal ACAP SelectIO ResourcesArchitecture Manual (AM010) for additional details :

• IDDR, ODDR, IFD, and OFD IO primitives are not supported in the Advanced I/O wizard.These primitives can be used outside the wizard.

• Block automation in the Vivado® Design Suite IP integrator is not supported.

• Example design is not supported for a TX design with no clk_fwd pins.

• There are corner cases for designs with a large number of TX pins that do not have a feasibleexample design.

• Reference clock to XPLL acting as a strobe for RX design is not supported.

Licensing and OrderingThis Xilinx® LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado®

Design Suite under the terms of the Xilinx End User License.

Note: To verify that you need a license, check the License column of the IP Catalog. Included means that alicense is included with the Vivado® Design Suite; Purchase means that you have to purchase a license touse the core.

Chapter 2: Overview


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Information about other Xilinx® LogiCORE™ IP modules is available at the Xilinx IntellectualProperty page. For information about pricing and availability of other Xilinx LogiCORE IP modulesand tools, contact your local Xilinx sales representative.

Chapter 2: Overview


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Chapter 3

Product SpecificationThe functional block diagram of the core is shown in the following figure.

Figure 1: Core Block Diagram

X21860-110918

IBUF

IBUF

IBUF

PLL0

PLL1

PLL2

IO Buffers

Bank 0

IO Buffers

Bank 1

Bank 2IO Buffers

Reset Logic

Bank0_pll_clkoutphy

Bank1_pll_clkoutphy

Bank2_pll_clkoutphy

Core_top

Note: PLL0, PLL1, PLL2 are the XPLL blocks.

Each I/O bank in Versal™ devices contains 54 pins (9 nibbles) that can be used for input andoutput. The Advanced IO Wizard provides various options to generate a wrapper using XPHYprimitive for the user selected configuration of the XPHY features of high performance banks.This wizard also configures clocking circuitry using XPLL that is needed to support theseconfigurations. The reset and initialization sequence is also provided in the HDL wrapper.

Chapter 3: Product Specification




PerformanceThe Advanced IO Wizard performance is measured by the data speed it supports, which in turn isthe capability realized in the selected I/Os of the device. For more information, see Versal ACAPSelectIO Resources Architecture Manual (AM010).

Port DescriptionsThe following tables describe the input and output ports of the Advanced IO Wizard. Availabilityof ports is controlled by the user selection.

Ports Connected to FPGA I/OTable 1: Ports Connected to FPGA I/O

Port Direction Clock Domain DescriptionGlobal Ports

<input_clock_name> Input NA Differential/Single Ended clock input connected to XPLL.The port is available only when an XPLL is instantiated inthe core.

rst Input ctrl_clk Global reset pin. CTRL_CLK Free Running Requiremetn,assertion of the reset is asynchronous. De-assertion issynchronous with respect to the CTRL_CLK. Minimumpulse width should be 5 ns.

<port_name> Input/Output/Inout

NA Data/Input Clock/Strobe/Clk forward/WrClk/RdClk portsconnected to I/O pins. Port name of the wizard IP isuser-specified through the Vivado® Integrated DesignEnvironment (IDE).

Ports Connected to FPGA General Interconnect LogicTable 2: Ports Connected to FPGA General Interconnect Logic

Port Direction Clock Domain DescriptionData Ports

data_from_fabric_<sig_name>[sf*num_pins -1:0]

Input app_clk Parallel data input from the interconnect logic to TX NIBBLESLICE.<sig_name> is the signal name configured for TX bus directionduring customization. sf is the serialization factor. num_pins is thenumber of pins associated with the signal.

data_to_fabric_<sig_name>[sf*num_pins-1:0]

Output app_clk Parallel data output to general interconnect logic from RXNIBBLESLICE. <sig_name> is the signal name configured for RXbus direction during customization. sf is the serialization factor.num_pins is the number of pins associated with the signal.






Table 2: Ports Connected to FPGA General Interconnect Logic (cont'd)

Port Direction Clock Domain DescriptionClock Ports

bank<x>_pll_clkout0 Output NA The frequency of this is data speed divided by the serializationfactor. This clock can be used as a clock for the generalinterconnect logic. x: bank number 0 to 2.

bank<x>_pll_clkin Input NA Enabled when the Input Clock to XPLL is through a Clock capablepin and XPLL in Core option is chosen. Only one Input Clock pinneeds to be chosen for the entire multi bank interface x: banknumber 0 to 2.

bank<x>_pll_rst_pll Input NA Reset input to XPLL x: bank number 0 to 2.

bank<x>pll_clkout1 Output NA The frequency of this can be set in Vivado IDE from a list ofsupported frequencies for the data speed chosen. x: bank number0 to 2.

bank<x>_pll_clkout2 Output NA Frequency of XPLL_CLKOUT2 = data_speed/serialization factor.Serialization factor = the greater of TX and RX serialization factorsx: bank number 0 to 2.

bank<x>_pll_clkout3 Output NA Frequency of XPLL_CLKOUT3 = data_speed/serialization factor.Serialization factor = the lesser of TX and RX serialization factors x:bank number 0 to 2.

bank<x>_pll_clkoutphy

Output Not applicable This port is available when you choose to instantiate the XPLL inthe core. The pll_clkoutphy signal from the master core is theoutput to the slave core. x: bank number 0 to 2. For moreinformation, see Clocking section.

RIU Ports

riu_addr Input ctrl_clk Address of the RIU register. Width of this bus is[num_banks*72-1:0] when SIMPLE_RIU parameter is disabled.When this parameter is enabled the width is [7:0]

ctrl_clk Input NA System clock from the general interconnect. CTRL_CLK must befree running.

riu_nibble_sel[num_banks*8:0]

Input ctrl_clk Width of this bus is [num_banks*9-1:0] when SIMPLE_RIUparameter is disabled. Each bit in the riu_nibble_sel corespondentto each nibble in the bank. Enable the bits to use the RIU Interfaceof particular nibble. To broadcast the writes, all bits can be set to"1".

riu_wr_data Input ctrl_clk Input write data to the register. Width of this bus is[num_banks*144-1:0] when SIMPLE_RIU parameter is disabled.When this parameter is enabled width is [15:0]

riu_wr_en Input ctrl_clk Register write enable active-High. Width of this bus is[num_banks*144-1:0] when SIMPLE_RIU parameter is disabled.When this parameter is enabled widthis [15:0]

riu_rd_data[num_banks*14:0]

Output ctrl_clk Output read data to the controller .Width of this bus is[num_banks*9-1:0] when SIMPLE_RIU parameter is disabled.When this parameter is enabled width is 1

riu_valid[num_banks*8:0]

Output ctrl_clk Output read valid to the controller .Width of this bus is[num_banks*9-1:0] when SIMPLE_RIU parameter is disabled.When this parameter is enabled width is 1 There can be apossibility of collision between BISC and PL where valid plays acrucial role in determining the validity of RIU.

Note: RIU ports are available only when ENABLE_RIU_INTERFACEparameter is selected.






Port Direction Clock Domain DescriptionStatus/Control

bank<x>_pll_locked Output NA Logic High indicates XPLL is locked to the desired clock frequency.x: indicates the bank number 0 to 2.

en_vtc Input ctrl_clk Assert to enable VTC for all interfaces.

intf_rdy Output ctrl_clk It indicates that the reset sequence of the interface is done.

rxtx_cntvaluein_<<port_name>>

Input ctrl_clk This port would be enabled when delay control ports or enable allports parameters are enabled. Width would be 9*buswidth. Referto Versal ACAP SelectIO Resources Architecture Manual (AM010) formore details on the port.

rxtx_cntvalueout_<<port_name>>

Output ctrl_clk This port would be enabled when delay control ports or enable allports parameters are enabled. Width would be 9*buswidth. Referto Versal ACAP SelectIO Resources Architecture Manual (AM010) formore details on the port.

rxtx_ce_<<port_name>>

Input ctrl_clk

This port would be enabled when delay control ports or enable allports parameters are enabled. Refer to Versal ACAP SelectIOResources Architecture Manual (AM010) for more details on theport.

rxtx_inc_<<port_name>>

Input ctrl_clk

rxtx_ld_<<port_name>>

Input ctrl_clk

rxtx_sel_<<port_name>>

Input ctrl_clk

rxen_vtc_<<port_name>>

Input ctrl_clk

txen_vtc_<<port_name>>

Input ctrl_clk

fifo_empty[num_banks*9-1 :0]

Output app_clk Aggregated FIFO empty flag from each nibble which containsRX/TX/BiDir Pins.

Note: Do not rely on FIFO_EMPTY asserting every eightFIFO_WR_CLK cycles for bit and word alignment. The firstdeassertion of FIFO_EMPTY must be used for controllingFIFO_RDEN.

Note: The width of the port is 27 by default. WhenREDUCE_CONTROL_SIG_EN parameter is enabled, the port width isreduced to 1. All ports together give a single bit output using the"OR" operation. This feature reduces the number of ports exposedto the customers.

fifo_rd_en[num_banks*9-1 :0]

Input app_clk FIFO read enable for each bit slice.<i> is the pin number on whichthe RX is selected.


fifo_rd_clk Input app_clk FIFO read clock for the interface.

fifo_wr_clk Output fifo_wr_clk FIFO write clock for the interface. SelectPLL_FIFO_WRITE_CLK_EN parameter to enable this clock.









Port Direction Clock Domain Descriptionstart_bitslip Input Not applicable Reset for the bitslip logic. Active-Low. When the top level reset pin

is asserted, start_bitslip should be driven Low. The start_bitslipport should be deasserted only when the Transmit partner of theserial line is transmitting the bitslip training pattern.

bitslip_error_<sig_name>[num_pins-1 :0]

Output fifo_rd_clk Error output for bitslip. When eight bitslips are performed for 8-bitserialization or four bitslips are performed for 4-bit serialization,this output is pulsed high.

bitslip_sync_done Output fifo_rd_clk Indicates that the bitslip training pattern is received at all RX pinsin the design.

shared_bank<x>_pll_clkoutphy_in

Input Not applicable This port is available when you choose to instantiate the XPLL inthe example design. The pll_clkoutphy signal from the master coreis given as an input to the slave core.

shared_bank<x>_pll_locked_in

Input Not applicable This port is available when you choose to instantiate the XPLL inthe example design. The pll_locked signal from the master core isgiven as an input to the slave core.

shared_bank<x>_pll_clkoutphyen_out

Output Not applicable This port is available when you choose not to instantiate the XPLLin the core. The pll_clkoutphy_en signal from the slave core isgiven as an input to the master core.

tx_app_clk Input Not Applicable This is the clock used to drive the fabric side ports related to TXpins. Available for asynchronous applications.

rx_app_clk Input Not Applicable This is the clock used to drive the fabric side ports related to RXpins. Available for asynchronous applications.

gearbox_clk Input Not Applicable This clock drives gearbox for asynchronous interfaces.

parallel_clk Input Not Applicable This port is available when PLL in outside core and Enable BLI istrue. This is the clock on which user sends the data_from_fabric.Advanced IO Wizard needs this clock to synchronize thedata_from_fabric and place n BLI for timing closure.

dly_rdy[num_banks*9-1 :0]

Output Async dly_rdy from XPHY is given as output. Indicates that delay linevalues can be changed


phy_rdy[num_banks*9-1 :0]

Output Async phy_rdy from XPHY is given as output. Indicates that the PHY isready for voltage and temperature compensation (VTC)


phy_rden[num_banks*36-1 :0]

Input app_clk This port is input to XPHY. Port width would be 36*Number ofbanks. These are nibble level pins, each nibble instantiated wouldcontribute to four pins. Used to control the gate on the receiver

phy_wren[num_banks*36-1 :0]

Input app_clk This port is input to XPHY. Port width would be 36*Number ofbanks. These are nibble level pins, each nibble instantiated wouldcontribute to four pins. Used to control the gate on thetransmitter. Can also be used to control tristating when it's set toserialized.






Port Direction Clock Domain DescriptionPhy_rdcs0[num_banks*36-1 :0]

Input app_clk This port would be available when ENABLE_ALL_PORTS parameteris enabled.

Phy_rdcs1[num_banks*36-1 :0]


Phy_wrcs0[num_banks*36-1 :0]


Phy_wrcs1[num_banks*36-1 :0]


GT_status[num_banks*9-1 :0]

Output Async This port would be available when ENABLE_ALL_PORTS parameteris enabled.

Notes:1. For more details on ports related to XPHY, refer to the XPHY Primitive Ports section in the Versal ACAP SelectIO

Resources Architecture Manual (AM010).






Chapter 4

Designing with the CoreThis chapter includes guidelines and additional information to facilitate designing with the core.

General Design Guidelines

This Advanced IO Wizard core is for high-speed Versal™ architecture designs and can beconfigured over wide range of Interface speeds for Source sync and Async configurations.

Refer to the Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956) and VersalAI Core Series Data Sheet: DC and AC Switching Characteristics (DS957) for supported frequenciesin Source synchronous Interfaces.

You are expected to have the interface requirements of your application before generating theAdvanced IO Wizard specific to your designs — details such as interface speed, clock to datarelationship, and system clocking structure. For example, what the source of the XPLL input clockshould be.

Once the wizard generates the HDL wrapper, you should run synthesis and perform pin planningusing the Advanced I/O Planner tools. For more information, see I/O Planning for VersalAdvanced IO Wizard section.

ClockingThe XPLLs associated with each bank are the primary source for clocking the SelectIO resourcesin the bank. You can select the source of the input reference clock to XPLL. The source can be aclock from the global clock pin (GC) or from the global clock network through BUFG. You canalso select the input clock frequency from Vivado IDE, which lists all the supported clocks for agiven device.

XPLL InstantiationYou are given the option in Vivado IDE to instantiate the XPLL in the core or the example design.This provides ease of use to share the XPLL across multiple interfaces in a single bank. The corethat has the XPLL instantiated inside is called the master. Other instances of the wizard that donot have the XPLL instance inside the core are called slaves. The interface between the masterand slave cores is shown in the following figure.

Chapter 4: Designing with the Core


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https://www.xilinx.com/cgi-bin/docs/ndoc?t=data_sheets;d=ds957-versal-ai-core.pdf



Note: When generating the master and slave cores, the interface speed and other XPLL parameters shouldremain the same. Both cores must reside within a single XPIO bank.

Since the wizard supports up to three banks, three XPLLs are instantiated in the clk_scheme.vmodule. Based on the selection, the clk_scheme.v signal is instantiated in the core or exampledesign.

Figure 2: XPLL Sharing

Master Core

Slave Core

Shared_pII0_clkoutphyXPLL0

Shared_pII0_lockedShared_pII0_clkout0





X21893-111218

CTRL ClockCTRL clock is mandatory for a design. The reset state machine and XPHY nibble modules operateon the CTRL clock. It can be provided through the ctrl_clk input port. This clock can besourced from a valid clock source that is internal or external to the FPGA. clkout1 output of PLLcan be used as ctrl_clk. Use ENABLE_PLLCLKOUT1 parameter to enable this clock.

Clocking of TXData is transmitted on the serial lines along with the associated clock or strobe. The clockforwarding option in the wizard can be enabled on any pin in a given bank. It is mandatory thatthe number of Clock Forward pins are less than or equal to the number of TX pins in thedesign. The phase of the forwarded clock with respect to the data can be set in Vivado IDE. TheClock Forward pin acts as a Strobe/Clock for RX. The clock/strobe can be edge-aligned orcenter-aligned with the data. Clock/Strobe is generated similar to the data by applying a01010101 pattern at the D[7:0] input of XPHY nibble. Alignment can be determined on the TXor RX side from an XPHY perspective (TX_OUTPUT_PHASE_# vs RX_CLK_PHASE_P/N).





Clocking of RXThere are two modes used to capture data in the XPHY initiated by an attribute (SERIAL_MODE= TRUE/FALSE).

• When the attribute SERIAL_MODE is set to TRUE, the received data is captured usingCLKOUTPHY from XPLL. This corresponds to the asynchronous option shown in Vivado IDEfor clock to data alignment. The receive data capture clock and receive data are eitherasynchronous or synchronous phase unknown. These types of applications require specializedextra logic designs to handle data recovery which is called CDR logic. The CDR logic neededfor data capture is built into the wizard.

• When the attribute SERIAL_MODE is set to FALSE, the received data is captured using a clockor strobe that is forwarded with the data. This corresponds to the Edge DDR/Center DDRoptions shown in Vivado IDE for Clock to Data Alignment.

Edge DDR

In this mode, the RX data is captured using the incoming strobe. The strobe input is present onthe pin 0 of a XPHY nibble present in a bank. The wizard supports up to eight strobes in a givenbank. The propagation of strobes to RX data pins follows the inter-byte and inter-nibble clockingrules as mentioned in the Clocking section of the Versal ACAP SelectIO Resources ArchitectureManual (AM010).

The strobe pin nearest to an RX data pin is chosen as the associated strobe for the data pin.Special care needs to be taken while pin planning to ensure that the appropriate strobe and datapin positions are chosen. By default, the wizard chooses an ideal location for the clocks, whichXilinx recommends to use the default configuration.

Figure 3: Edge DDR

Transmitted/Received Clock

Transmitted/Received Data

X15065-110918

Center DDR

Center aligned mode.

Figure 4: Center DDR

Transmitted/Received Clock

Transmitted/Received Data

X15066-110918






ResetsThe wizard generates a reset module that is built in the wrapper. This module runs on the Ctrlclock. The input is an asynchronous reset that triggers resets to all XPHY modules in the design.

When any pin is enabled as Clock Forward, it is mandatory to hold the counterpart design(RX) in reset until the TX is out of reset and intf_rdy of TX is asserted. This ensures a reliableclock to the RX.

Asynchronous Mode Support (Beta Support)In an Asynchronous (Beta) mode of an operation, there is no incoming clock/strobe associateddata. The CDR module is provided in the wizard generated wrapper to enable the data capture.Data_Out is the actual data from the Async mode design, and Data_Valid is the signal that wouldindicate that Data_Out is Valid when Dataout_Valid is High.

IMPORTANT! In an asynchronous mode of operation, the I/O pins are required to be differential.





Figure 5: Asynchronous Mode Structure

Reset State Machine

XPHY CDR

Clocking Module

Gearbox

PLL lock, DLY_RDY_ALL

All EN_VTC signals, All RST_PHY signals

Bitslice [Y+1]8-bit data

Bitslice [Y]8-bit data

CNTVALUEIN

CNTVALUEOUT

LD

PHY_RDEN

FIFO_RDEN

FIFO_EMPTY

CTRL_CLK FIFO_CLK

wr_clk rd_clk

RX_DATA(8-bit data)

DATA_VALID

fifo_rst_done

CTRL_CLK(from clocking module)

External Reset

reset_done

Data_out

Dataout_valid

Rx serialinput data

Rx serialinput data

BitSlice[Y+1]

BitSlice[Y]

intrf_rdy

CTRL_CLK FIFO_RD_CLK

Receiver side

X23342-100919

Bi-Directional Mode SupportBidirectional feature is supported by the Wizard. There are 3 different BIDIR Modes that theWizard supports.

1. Independent WrClk and RdClk

In this scenario, a user has 2 separate pins each for WrClk and RdClk. Data I is bidirectionalbut the clocks are uni-directional and continuous. RdClk must follow the placement rules ofstrobe and must always be placed in Nibbleslice0. WrClk can be placed at any Nibbleslice.

2. Single Continuous Clock

Data and Clock associated with the Data are bidirectional, and the clock associated with theData is always continuous.

3. Single Strobe

Data and Clock associated with the Data are bidirectional, and the clock associated with thedata is not continuous.





When an IO is configured as BIDIR, make sure that when using the bidirectional data path totristate the buffer or gate the data paths to prevent data loss. The following points must beenforced.

• User cannot use TRI_SELECT as Serialized in Independent WrClk and RdClk mode in thebelow condition. If BIDIR and WrClk pins share same nibble and WrClk is not placed inNIbbleSlice-1 position. In this scenario we recommend to use TRISTATE to Combinatorial.

• When the BIDIR Interface is ready to receive data, assert PHY_RDEN (can keep high forever).FIFO_RDEN should follow the FIFO_EMPTY.

• When the BIDIR Interface is ready to write data, assert PHY_WREN to write data. De-assertPHY_WREN when the write is complete.

Note: For alignment of the data across the Nibble, bitslip pattern must be enabled with a fixed trainingpattern. Pattern can be mentioned in IP GUI.

• RIU Interface must be enabled when using BiDir data to enable proper turnaround frombetween TX and RX without any data loss.

• Turn Around Process when TRI_STATE is Serialized

○ After the write is complete, de-assert PHY_WREN.

○ Issue BS_RESET_TRI, BS_RESET and CLR_GATE before asserting PHY_RDEN to bringpointers to known position.

○ Use the RIU register BS_RESET_CTRL (RIU_ADDR 0x03) with RIU_WR_DATA = 0x0007for eight RIU clock periods before de-asserting the resets with RIU_WR_DATA = 0x0000.

○ No need to assert clear gate or BS_RESET again after PHY_RDEN de-assertion.

○ FIFO_RDEN should follow FIFO_EMPTY. Bitslip is required in the beginning of read acrossbank.

Note: PHY_WREN and PHY_RDEN have a latency of 3 clock cycles, they have synchronizes added to takecare of cross clock domain.

Note: The turn around time in BIDIR mode must be handled by the user, as the XPHY needs specific timefor the transition between TX and RX. In the example design, it is handled in simple case by providing sometime gap in the conversion.

Use the Example DesignEach instance of the Advanced IO Wizard core created by the Vivado design tool is deliveredwith an example design that can be implemented in a device and then simulated. This design canbe used as a starting point for your own design or can be used to sanity-check your application inthe event of difficulty. See the Example Design content for information about using andcustomizing the example designs for the core.





TCL XDC Flow in Advanced IO WizardAdvanced IO Wizard core allows you to override XPHY parameters through Tcl flow. When yourIP is synthesized, perform the following to update the XPHY parameter values:

1. Open your synthesized design.

2. Locate the XPHY to update its parameters. Use show_objects -name find_1[get_cells -hierarchical -filter { PRIMITIVE_TYPE == I/O.PHY.XPHY } ] command to get the list of XPHYs used in the design.

3. Use set_property <<PARAMETER_NAME>> <<PARAMETER_VALUE>> [get_cells<<inst_path>>] command to change the property value of an XPHY in an instance.

4. Use Save_constraints command to save constraints.

5. Use Implement_xphy_cores command to regenerate the XPHY instances with newproperties or run implementation.





Chapter 5

Design Flow StepsThis section describes customizing and generating the core, constraining the core, and thesimulation, synthesis, and implementation steps that are specific to this IP core. More detailedinformation about the standard Vivado® design flows and the IP integrator can be found in thefollowing Vivado Design Suite user guides:

• Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)

• Vivado Design Suite User Guide: Designing with IP (UG896)

• Vivado Design Suite User Guide: Getting Started (UG910)

• Vivado Design Suite User Guide: Logic Simulation (UG900)

Customizing and Generating the CoreThis section includes information about using Xilinx® tools to customize and generate the core inthe Vivado® Design Suite.

If you are customizing and generating the core in the Vivado IP integrator, see the Vivado DesignSuite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IPintegrator might auto-compute certain configuration values when validating or generating thedesign. To check whether the values do change, see the description of the parameter in thischapter. To view the parameter value, run the validate_bd_design command in the Tclconsole.

You can customize the IP for use in your design by specifying values for the various parametersassociated with the IP core using the following steps:

1. Select the IP from the IP catalog.

2. Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the VivadoDesign Suite User Guide: Getting Started (UG910).

Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might varyfrom the current version.

Chapter 5: Design Flow Steps


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General Vivado IDE Settings

Basic Tab

Basic tab is shown in the following figure:

Figure 6: Basic Tab

See Customizing and Generating the Core for more information.

• Component Name: Component name is user defined. Component names must not containany reserved words in Verilog.

• Application:

• Source Synchronous: Indicates that the data capture clock is present along with the dataon the serial lines.

• Asynchronous: Indicates that there is no data capture clock on the serial lines for RX buses.

• Bus Direction: Indicates the direction of the pins in the user design





• TX ONLY: Indicates that the user design contains only TX pins.

• RX ONLY: Indicates that the user design contains only RX pins.

• TX +RX: Indicates that the user design contains TX and RX pins.

• BiDir (Beta): Indicates that the user design contains BiDir Pins

• BiDir+Tx_Rx (Beta): Indicates that the user design contains a mix of TX, RX and BiDir pins

• Clocking:

• Interface Speed (Mb/s): Sets the interface speed for the configuration. The interface speedhas different limits, defined by the device and speed grade selected. For more information,see Versal Architecture and Product Data Sheet: Overview (DS950)

• PLL Clock Source

The clock is sent to the XPLL through the buffer set in this option.

○ GC Pin: Choose this option if the input clock is available on the GC pin. In this case theinput clock goes to XPLL via IBUF (for single-ended clock) or IBUFDS (for differentialclock) instantiated by the wizard.

○ Fabric (Driven by BUFG): Choose this option if the clock is sent from the generalinterconnect. The wizard connects the input clock port (clk) directly to the XPLL. Youneed to ensure that a BUFG is instantiated in the interconnect.

• XPLL Input Clk Frequency (MHz): Sets the input clock frequency for the XPLL. Dependingon the data speed selected, a range of supported input clock frequencies are listed.

• Forwarded Clock Phase (Tx Signal Type = Clk Fwd): Available only for the TX pins. Sets thephase between clock forward and TX data. Supported values are 0 and 90.

• Clock Data Relation: Indicates the alignment of external clock to data. This is applicable forRX and BiDir pins.

• ASYNC/NONE: Refer to Clocking section for detailed information.

• Center DDR: Applicable to RX pins. Refer to Clocking in Chapter 4 for detailedinformation.

• EDGE DDR: Applicable to RX pins. Refer to Clocking in Chapter 4 for detailedinformation.

• Data and Control:

• TX/RX Serialization Factor: Defines the serialization factor for parallel data input/outputwidth from/to the general interconnect. Legal values are 2, 4, and 8. The serialization factoris set to 8 by default. These parameters are disabled when Bus Direction is BiDir/BiDir+Rx+Tx



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• Serialization Factor: Defines the serialization factor for parallel data input/output widthfrom/to the general interconnect. Legal values are 2, 4, and 8. The serialization factor is setto 8 by default. These parameters are available only when Bus Direction is BiDir/BiDir+Rx+Tx. The same value is reflected for both Rx and Tx Serialization factors.

• 3-State

Sets the tristate control for TX pins.

○ Combinatorial: Uses the T pin of the XPHY. The T input from the general interconnectlogic directly goes to XPHY nibble which controls the 3-state of the Tx and BiDir pins.

○ Serialized: PHY_WREN port is used to 3-state the Tx and BiDir pins.

• Enable Bitslip

For bus direction RX, and BiDir bitslip logic can be enabled to byte alignment. This option isnot available for Serialization factor 2.

• Enable Data Bitslip

Enables the XPHY RX output to be presented, even before the bitslip is completed.

• Bitslip Training Pattern

For Bitslip logic to achieve sync, a pre-defined training pattern (in HEX format) should bereceived. The training pattern should be unique and defined by the higher level protocol.The start_bitslip port (active-Low) holds the bitslip logic in reset. The start_bitslip portshould be driven High only when the transmitter has started driving the valid bitsliptraining pattern. The transmitter is expected to send the training pattern continuously untilthe bitslip_sync_done is asserted.

Note: Bitslip Detector cannot detect continuous 1's or 0's. So avoid "F" and "0" in any nibble of theBitslip pattern.

• Enable RIU Interface

Enables Register Interface Unit (RIU) for all nibbles to access internal registers. Every delayelement tap setting can be read with the RIU. Various features, such as clock gating andVoltage Temperature tracking, can be disabled. It enables the RIU access, but does not addadditional logic for RIU access.

• Include PLL In Core

Enabling this option includes XPLL inside the core. It generates all the clocks required bythe user. Number of XPLLs are instantiated based on the Number of banks requested.

Advanced Tab

Advanced tab is shown in the following figure:





Figure 7: Advanced Tab

• Optional Ports:

• ENABLE XPLL CLKOUT1: Setting this enables the CLKOUT1 port of XPLL0 to be broughtas the output port of the wrapper.

• PLL_CLKOUT1_FREQ: Select the required frequency from this drop-down menu.

• Enable FIFO Write Clock: Setting this exposes the fifo_wr_clk output port of theinterface.

Note: Other XPLL outputs are provided by default. No need to enable them. For more infomration,see Port Descriptions.

• Reduce Control Signals: When enabled, a single set of control signals (fifo_wrclk,dly_rdy, phy_rdy, fifo_empty, fifo_rden) of the XPHY nibble are presented to theuser. It is an aggregation of the status signals from multiple nibbles.

• ENABLE ALL PORTS OF XPHY: When enabled, all the control ports, RIU signals and otherXPHY signals that a user needs is available at the top level of the wizard.





• Enable Delay Control Signals: When enabled, all XPHY ports related to delay controlappear at the top level of the Wizard. LD, CE, INC, CNTVALUEIN, CNTVALUEOUT, TX ENVTC and RX EN VTC ports with respect to each bus are available to control delays on theIOs.

• Enable BLI logic: When enabled, BLI registers between fabric and XPHY can be used tohelp with timing closure.

Note: Enabling this parameter adds latency of one clock cycle in the data path. It is recommended toenable this parameter to meet timing.

• Enable Simple RIU: When this parameter is enabled, there is only 1 RIU Interface appearingat the top level of the wizard. All the RIU Interfaces of the nibbles instantiated are mixedwith the single RIU at the top. In this feature, riu_nibble_sel plays an important role in theread and write of RIU data. Width of riu_nibble_sel port is equal to 9* NUM_BANKS. Forexample, if single bank is enabled, nine bits of riu_nibble select correspond to each nibbleof the bank. Bit0 corresponds to Nibble0, Bit 1 to Nibble 1 and so on. When more banksare enabled, Bit 9 corresponds to Nibble0 of Bank1 and so on. The nibble_select bit mustbe held high and the signals must be driven on RIU signals.

You can also broad cast the write data onto all Nibbles by enabling all the bits inriu_nibble_sel bus.

• I/O Standard:

• Differential IO standard: Differential IO standards supported by the selected Bank areshown here.

• Single IO Standard: Single Ended IO standards supported by the selected Bank are shownhere.

Note: I/O standard would be limited to only what XPIO banks allow.

• Number of Banks: Enables to select the number of banks to configure. The allowed values are1, 2, and 3. Default value is 1. Port width of RIU and other Control ports depends on thisparameter. The maximum number of pins in the Pin Configuration Tab are also restricted bythis parameter.

• Power Saving:

• IOB Power Saving: Enable this option to get the power saving ports of IOBs at the top levelfor user control or internally controlled by XPHY.

• IOB Power Control: Power control ports can be user driven or XPHY controlled, this optionallows user to select one of them. When user controlled option is selected, ibufdisable anddcitermdisable ports for each IO will be available at IP level.

Note: For ES1 devices IOB Power Control is always user controlled.





Pin Configuration Tab

Pin Configuration tab provides the interface level number of I/O data channels and each selectedpin allows you to set the pin direction [TX, RX and BiDir], signal type (Differential/Single ended),signal name, and also selects a pin as Data, Strobe/Clock, Input Clock or Clock Forward as shownin the following figure:

Figure 8: Pin Configuration Tab

• Bus Direction: Sets the bus direction on the selected pin. Available options are:

• TX: Pin direction is set to TX; option is not available when RX only option is selected forBus Direction under the General tab.

• RX: Pin direction is set to RX; option is not available when TX only option is selected forBus Direction under the General tab

• BIDIR: Pin direction is set to Bidirectional. This option is not available in the followingcases.





• TX only or RX only or TX and RX are selected for Bus Direction under the General tab.

• IO Type: Sets the IO type to differential or single ended.

• Signal Type: Allows the pin to be selected as data/input clock/Clk Fwd.

• Data Sets the pin as a data pin.

• Clk Fwd Valid only for the TX bus direction. The number of clock fwd pins in a interfaceshould be less than or equal to the number of data pins.

• Input Clock Sets the pin as a clock pin. The input clock should be on this pin. Only GC/GC_XCC pins can be set as input clock pins. This option is available if Clock Capable Pin isselected for XPLL Clock Source under the Basic tab.

• Enable Strobe/RdClk: This option is available only for RX and BiDir pins to choose the Strobepin associated with the Data pins.

• Strobe/RdClk IO Type: Sets the IO type to the Strobe signal to differential or single ended.

• Strobe/RdClk Name: User defined name given to Strobe signal.

• Enable WrClk: This option is available only for BiDir pins to choose the WrClk pin associatedwith the data pins. It is available when BIDIR_MODE is selected as independent WrClk andRdClk.

• Strobe/RdClk IO Type: Sets the IO type to the WrClk signal to differential or single ended.

• Strobe/RdClk Name: User defined name given to WrClk signal.

• Signal Name: User defined name given to the data/clock forward signal.

• Number of Data Channels: User selection to define the number of channels needed in theselected signal.

IO Timing Estimation Tab

IO Timing Estimation tab provides IO related timing estimation with respect to the user inputsgiven in previous tabs. IO Timing Estimation tab is shown in the following figure:





Figure 9: IO Timing Estimation Tab

The Advanced IO Wizard adds a new tab to estimate the error associated with the XPHY, I/O,and relevant clocking resources in source synchronous designs.

• BIT Period

This parameter is derived based on the interface speed mentioned in the Basic tab.

• TX/RX IOB – Error from input and output buffers.

For receiver designs, I/O settings affect the error. For example, single-ended IOSTANDARDsrequire the VREF to be properly set whereas differential inputs are not susceptible to thesame types of tuning. The timing budget accounts for internal VREF tuning. Nominal VIDswings are assumed for differential inputs.

For transmitters, single ended I/O’s can have higher duty-cycle distortion than differentialstandards. Takes into account VCC induced jitter.

• TX/RX PHY – Error from XPHY





For receivers within source synchronous designs, the XPHY uses the strobe (DQS from XCCpins) as the capture clock. As a result, clock noise is only based on the XPHY clockingstructures. The reference clock (XPHY’s PLL_CLK) only affects the tuning associated withBISC.

For asynchronous, receive designs that use SERIAL_MODE with PLL_CLK as the clock source,an alignment circuitry must be used. The error associated with dynamic phase alignmentcircuitry is not covered.

PHY accounts for all receiver errors within XPHY that are not tuned out by BISC. BISC adjustsfor center aligned and edge aligned data for a single bank by adjusting input delays(ALIGN_DELAY) and strobe delays.

For transmitters, XPHY always uses PLL_CLK as the clock source for the transmitted data. Asa result, noise associated with the XPLL must be accounted for. TX_OUTPUT_PHASE_90affects the noise associated with the XPLL.

For the transmitter, BISC is limited to the tuning of DELAY_VALUE to tune the output delaysto the supplied PLL_CLK and REFCLK_FREQUENCY settings.

• Package

During the start up sequence when BISC is performed, XPHY sends the routing used by thestrobe to deskew the nibbleslices. The strobe routing is deskewed for all on-die variationsafter BISC is done.

Please note that the package skews are not part of the BISC calibration scheme. Packageskews can be matched by PCB skews. For any unmatched package skews, the timing budgetmust add those skews separately to the timing budget.

Package delays are reported in the Package Pins tab of an implemented design or by using theFile > Export > “Export I/O Ports…” menu.

• Channel

High speed interfaces require good PCB design practices and signal integrity. As a result, PCBdesign choices and I/O settings can impact the performance. IBIS simulations are typicallyused to simulate the signal integrity associated with PCB and I/O settings. Any IOSTANDARD,SLEW, PREEMPHASIS, termination decisions should be simulated to determine the channelloss. Channel loss should also be included into the final timing budget to determine thereceiver and transmitter margins.

• Total Window Opening Remaining in TX/RX

This is calculated by removing all the calculated delays from the available Bit Period.

Summary Tab

Summary tab shows the next steps you should follow to process with pin planning as shown inthe following figure:





Figure 10: Summary Tab

User ParametersThe following table shows the relationship between the fields in the Vivado® IDE and the userparameters (which can be viewed in the Tcl Console).

Table 3: User Parameters

Vivado IDE Parameter/Value User Parameter/Value Default ValueBus Direction• TX_ONLY: 0• RX_ONLY: 1• BiDir (Beta): 2• TX+RX: 3• BiDir+Tx+Rx (Beta): 4

BUS_DIR 0





Table 3: User Parameters (cont'd)

Vivado IDE Parameter/Value User Parameter/Value Default ValueBiDir Mode

• Independent WrClk and RdClk:0

• Single Continuous Clock: 1

• Single Strobe: 2

BIDIR_MODE 1

Interface Speed (Mb/s)Range: 200-1,800 Mb/s

Note: The range is subjected to change based on belowselections:

1. Source Sync or Async.

2. Speed grade of the device selected.

DATA_SPEED 1,000

PLL Clk Input Frequency (MHz)Range: 100-1,099 MHz

Note: The rage is subjected to change based on the speedgrade selected

INPUT_CLK_FREQ 500.00

Clock to Data Relation (RX Strobe)Range:• ASYNC/NONE: 2• Center DDR: 3• Edge DDR: 4

CLK_TO_DATA_ALIGN 4

PLL Clock SourceRange:• Clock Capable Pin: IBUF_TO_PLL• Fabric (Driven by BUFG): BUFG_TO_PLL

PLL_CLK_SOURCE IBUF_TO_PLL

TX, RX Serialization FactorRange: 2,4,8

TX/RX_SERIALIZATION_FACTOR 8

Serialization FactorRange: 2,4,8

SERIALIZATION_FACTOR 8

Select if PLL is included in core or Example DesignRange:• Include PLL in Core: 0• Include PLL in Example Design: 1

PLL_IN_CORE 0

Forwarded Clock Phase (TX Signal Type = Clk Fwd)Range:• FALSE: 0• TRUE: 1

CLK_FWD_PHASE 0

Single Ended IO StandardRange:Varies with device

SINGLE_IO_STD NONE

Differential IO StandardRange: Varies with device

DIFFERENTIAL_IO_STD NONE






Vivado IDE Parameter/Value User Parameter/Value Default ValueRIU InterfaceRange:• FALSE: 0• TRUE: 1

ENABLE_RIU_INTERFACE 0

Enable Simple RIURange:• FALSE: 0• TRUE: 1

SIMPLE_RIU 0

Enable BitSlipRange:• FALSE: 0• TRUE: 1

ENABLE_BITSLIP 0

Enable Data BitslipRange:• False: 0• True: 1

ENABLE_DATA_BITSLIP 0

3-state• Serialized: 0• Combinatorial: 1

DATA_TRISTATE 1

Number of Channels BUS<0-16>_NUM_PINS 1

Signal Name BUS<0-16>_SIG_NAME Data_pins_0

Pin Direction• None: None• RX: RX• TX: TX• BiDir: BiDir

BUS<0-16>_DIR None

Signal IO Type• Differential: DIFF• Single-ended: SINGLE

BUS<0-16>_IO_TYPE SINGLE

Signal Type BUS<0-16>_SIG_TYPE Data

Enable Strobe BUS<0-16>_STROBE_EN False

Strobe Name BUS<0-16>_STROBE_NAME Strobe_0

Enable WrClk BUS<0-16>_WRCLK_EN False

WrClk Name BUS<0-16>_WRCLK_NAME WrClk_0

Strobe IO Type• Differential: DIFF• Single-ended: SINGLE

BUS<0-16>_STROBE_IO_TYPE SINGLE

WrClk IO Type• Differential: DIFF• Single-ended: SINGLE

BUS<0-16>_WRCLK_IO_TYPE SINGLE

Application Data WidthRange: 4 and 8

APPLICATION_DATA_WIDTH 8






Vivado IDE Parameter/Value User Parameter/Value Default ValueApplicationRange:• SOURCE_SYNCHRONOUS• ASYNCHRONOUS

APPLICATION_TYPE SOURCE_SYNCHRONOUS

FIFO_WRCLK_OUTRange:• False: 0• True: 1

PLL_FIFO_WRITE_CLK_EN False

Reduce Control SignalRange:• False: 0• True: 1

REDUCE_CONTROL_SIG_EN False

IOB Power savingRange:• False: 0• True: 1

ENABLE_IOB_POWER_SAVING Fallse

IOB Power controlRange:• User Controlled: 0• Wizard Controlled: 1

IOB_POWER_CONTROL User Controlled

Enable Delay Control SignalsRange:• False: 0• True: 1

DELAY_CTRL_SIG_EN False

ENABLE CDR DEBUG SIGNALSRange:• False: 0• True: 1

ENABLE_CDR_DEBUG False

Enable BLI LogicRange:• False: 0• True: 1

ENABLE_BLI True

PACKAGE PACKAGE 0.0

CHANNEL CHANNEL 0.0

Notes:1. Parameter values are listed in the table where the Vivado IDE parameter value differs from the user parameter value.

Such values are shown in this table as indented below the associated parameter.

Output GenerationFor details, see the Vivado Design Suite User Guide: Designing with IP (UG896).

The wizard delivers Verilog RTL for the core logic, example design, and example test bench.






If the IP example design project is opened, another core instance with the core name<ip_ex_inst> is instantiated in the <ComponentName>_exdes.v. For example designsimulation, the <ComponentName>_tb.v test bench file is generated.

Constraining the CoreRequired Constraints

This section is not applicable for this IP core.

Device, Package, and Speed Grade Selections

Input clock frequency selection depends on the maximum frequencies supported by IBUF/BUFG.Select the device, package and speed grades after referring to the Versal Architecture and ProductData Sheet: Overview (DS950) for details on supported maximum frequencies.

Clock Management


Banking


Transceiver Placement


I/O Standard and Placement


SimulationFor comprehensive information about Vivado® simulation components, as well as informationabout using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation(UG900).







Synthesis and ImplementationFor details about synthesis and implementation, see the Vivado Design Suite User Guide: Designingwith IP (UG896).

I/O Planning for Versal Advanced IO WizardThe Versal™ architecture Advanced IO Wizard IP defines various IO configurations using a pre-engineered application layer and a physical layer (XPHY). External high speed interfaces mustfollow the following rules:

• Specific pinout requirements driven by clocking

• Rule based engine for I/O configuration within the I/O banks

• Physical pin assignment requirements

For performance purposes, the final configuration of the IP is dependent on the I/O assignments.Therefore, you cannot complete final implementation of the IP until the IP I/O is assigned. Youmust handle the I/O assignment and implementation of this IP differently from most other IPs.However, this is similar to how memory IP does pin placement. This section describes theprocess for I/O planning and implementation of the Versal Advanced IO Wizard IP.

Versal Architecture I/O Planning Design FlowChangesThe Vivado® Design Suite has the following differences between the I/O assignment andimplementation process for the Versal architecture Advanced IO Wizard:

• Consolidated I/O Planning with the rest of the design in the main Vivado IDE I/O Planningview layout—this enables pin planning with the design RTL or after synthesizing the design.Additionally, you can pin plan all the high speed I/Os in a bank together including hard andsoft memory controllers.

• PHY implementation of the IP is now performed after synthesis as a part of the opt_designcommand, this enables netlist based I/O planning.

• Physical block (Pblock) that contains the IP is now automatically generated as a part of theopt_design command and is transient and invisible to users.






Consolidated I/O PlanningYou can perform I/O assignment in the main Vivado® IDE I/O Planning view layout along withthe rest of the design ports. This is not part of the IP configuration. The new I/O methodologyenables you to perfom the following:

• Make changes to I/O ports without regenerating of IP.

• Target IP to different devices with different pinouts without regenerating of IP.

• Perform I/O planning with multiple IPs concurrently in one environment.

• Define and store port assignments in the top-level XDC constraints file for the design ratherthan in a read-only file within the IP.

• Directly edit or replace the XDC constraint file or files to modify I/O port assignments.

Note: In the previous I/O Wizards for UltraScale and UltraScale+ releases, all I/O assignments were madeas part of customizing the IP. The tools stored the resulting constraints with the IP in a read-only XDC file.This required re-customizing the IP to modify the port assignments. In addition, these constraints were notnecessarily visible during I/O assignment and validation for the rest of the design.

PHY ImplementationThe Versal architecture IP defines using a pre-engineered test bench and PHY for interfacing userdesigns. This IP is structured so that only the physical layer (PHY) interconnect in the Xilinx®

device should be updated when pinouts change. Because the PHY implementation depends onthe I/O assignments, it must occur after the I/Os are placed and validated. To enable I/OPlanning after synthesis, the implementation of the PHY now happens as part of implementationduring the opt_design command.

Note: To generate a default LOC for all the IOs, use the xphy::generate_constraints command on asynthesized design and run the implementation flow.

Configuring the IPThe Customize IP dialog box contains basic and advanced configuration options that includedebugging. The I/O assignment process is consolidated with the rest of the design and the IPconfiguration process is consistent with any other Xilinx® IP.

Versal Architecture IP I/O Planning in the Vivado IDEWhen using the elaborated design for I/O Planning, you must set the proper elaboration optionsopening the design as follows:

1. In the Vivado® IDE, select Flow > Elaboration Settings.

2. In the Project Settings dialog box, select the Netlist model and Load constraints options.





Note: Loading the netlist model allows the elaborated design to read the synthesized IP with the selectedI/O properties, such as IOSTANDARD and OUTPUT_IMPEDANCE. If you use the black box model, youcannot do I/O Planning in the elaborated design.

There are two ways to generate the xdc commands which include default IO placements and alsorespective IO Standards:

1. Example design

2. Create a top wrapper over the IP and execute xphy::generate_constraints in tclconsole to generate the constraints.

Either one of the above steps are required before opening the elaborated settings.

Figure 11: Setting Elaboration Options

Using Advanced I/O PlannerThe I/O Planning view includes the I/O Ports and Package Pins tabs. Xilinx recommends I/Oplanning high-speed interfaces in the following order to achieve the maximum utilization ofavailable XPHY logic resources: Integrated DDRMC through NOC, Soft memory controllers,Advanced I/O wizard, I/O logic. This tool only allows for nibble and bank level granularity. If moregranularity is required, use the classic pin planning tools. If the Versal architecture Advanced IOWizard IP exists in the design, the banners of both tabs contain a message and a button to launchthe Advanced I/O Planner. The Advanced I/O Planner understands any interface in the XPHYI/O block. If there is a hard or soft memory controller, this will also appear in the Advanced I/OPlanner. The placement of these interfaces is arranged as optimal as possible based on acentralized hardware rule based engine. There is a priority to this list such as hard memorycontroller, soft memory controller, followed by any SelectIO™ interface.





Figure 12: Invoking the Advanced I/O Planner

You can use the Advanced I/O planner to either automatically or manually assign IP interfacesignal groups to specific nibble groups within the I/O banks.

Figure 13: Advanced I/O Planner Instances View





Figure 14: Advanced I/O Planner Nibble Groups View (Expandable)

Note: If you use example designs generated directly from the IP, the XDC file in the example designprovides default I/O assignments that appear in the Advanced I/O Planner.

The Advanced I/O Planner includes the following features:

• Collapsible Device Resource Tree: Device resources, such as Banks, Nibble groups, appear in acollapsible and extensible tree that varies depending on the selected device. You can collapsethe tree to target a specific area of the device, as shown in the following figure.





Figure 15: Advanced I/O Planner Nibble Groups View (Collapsible)

Note: The tree shows the resources in the order they appear on the device, because Advanced IO WizardI/O Interfaces must be assigned to adjacent I/O banks.

• Cross-selection with other views: When you select the I/O Banks and Nibble groups, thegroups are also highlighted in the Package and Device windows to aid in identifying theresources, as shown in the following figure.





Figure 16: Cross-Selecting Banks and Nibble Groups

• DRC Information: At the top of the Advanced I/O Planner, a DRC status message providesinformation about DRC violations with a link to more information, errors, and warnings asshown in the following figure.





Figure 17: Showing DRC Violations

• Signal Group Information: Click the i button located on the tool bar to view the ports underthe selected signal group in the Signal Groups dialog box as shown in the following figure.





Figure 18: Showing Signal Groups

Manually Assigning Signal GroupsPerform the following steps to manually assign signal groups to nibbles:

1. In the Signal Groups column, click menu selection button located to the extreme right.

2. Select a Signal Group to assign.

After each assignment, Vivado tool runs active DRCs, DRC violations appear in red, click moreinfo link for details. The Vivado IDE shows signal groups for each IP instance in the design. So,you can plan I/O assignments for multiple IP instances at the same time.





Figure 19: Manually Assigning Signal Groups to Nibbles

Automatically Assigning Signal GroupsYou can automatically assign signal groups for each IP instance individually or all at once. You cantarget an I/O bank or a group of I/O banks for each memory controller. Perform the followingsteps to assign signal groups automatically:

1. On the IO Instances tab, select the IP instance which is to be auto assigned.

2. Click Auto-Assign Controllers on the tool bar.

3. Select the auto assign check-box on the header.

4. Click Auto-Assign Controllers.





Figure 20: Auto-Placing IP Instances

You can choose an I/O bank where the IP instance need to be placed using the menu selectionbutton located to the extreme right of an I/O bank column as shown in the following figure.





Figure 21: Selecting I/O Banks for Auto-Placement

Un-placing Signal Groups and IP InstancesYou can un-place signal groups for the IP instances individually or all at once. Perform thefollowing to unplace signal groups:

1. Select the IP instance checkbox, and click Unplace.

2. To unplace all the IP instances, select the checkbox on the header and click Unplace.

For more details on classic pin planning, see Vivado Design Suite User Guide: I/O and Clock Planning(UG899).



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Chapter 6

Example DesignThis chapter contains information about the example design provided in the Vivado® DesignSuite.

This core provides an example design with one core instance and one example instance. Ifgenerating a TX IP instance as an example design, an RX IP is created as part of the exampledesign for a I/O loopback. Similarly if this is an RX IP instance, a TX IP is created and looped backby the example design. When bitslip is enabled, the pre-defined training pattern is compared toalign the data at RX. When data is aligned, PRBS patterns are transmitted from TX and PRBScheckers at the Rx (in the example instance) check for data integrity. When bitslip is not enabled,data from RX nibbleslices are unaligned data, and the example design checks for all possible validdata of RX for a known TX data pattern. If a pattern matches, data_check_complete outputis asserted from the example design.

Figure 22: Example Design Block Diagram

EXAMPLE DESIGN

Example IP Instance

Pattern Generator/Checker

IP Instance

exdes_clk

exdes_rst_in

clk_in

rst_in

data to I/O

data_check_complete

data from I/O

X21843-110918

Chapter 6: Example Design




Chapter 7

Test BenchThis chapter contains information about the test bench provided in the Vivado® Design Suite.The test bench is a simple Verilog code to exercise the example design and the core. This testbench performs the following tasks:

• Generates input clock signals.

• Applies reset to the example design.

• Example design RX and TX interfaces are looped back; The waveform is shown for the TX/RXloopback for 1 pin.

• If RX and TX pattern matches, the test bench sends a message in TCL console of Vivado forsuccessful test completion, as shown in the following figure. Otherwise, it waits for 500 usand sends a test failure message.

Figure 23: Test Bench

Chapter 7: Test Bench




Chapter 8

Advanced IO Wizard TutorialThe Vivado® tool flow for Versal™ devices introduces the Advanced IO Wizard, an IP-based flowfor creating and planning high speed SelectIO interfaces. In this tutorial, the Versal architectureSelectIO XPHY logic is implemented using the Advanced IO Wizard in the Vivado IP integrator,and is planned using the Vivado Advanced I/O Planner.

Design DescriptionThe tutorial design consists of a 12-bit single ended receive interface running at 600 Mb/s with a300 MHz reference clock, and a strobe signal to capture DDR source-synchronous edge-aligneddata from the I/O using the SSTL12 IOSTANDARD. The high-speed I/O data is then de-serializedinto 8 bits (1:8) and passed through the built-in FIFO provided in the I/O hardware.

The Versal architecture design solution constructed in this tutorial, project_Versal.xpr, isprovided as a design file. The project_Versal.xpr design file contains a Versal architectureXPHY logic interface created using the Vivado IP integrator, the Advanced IO Wizard, and theAdvanced I/O Planner in the Vivado® Design Suite 2020.2.

You can download the reference design files from the Xilinx website. Download the file, andextract the ZIP file contents of the design. Open the design in the Vivado tool version specifiedabove.

Note: This tutorial focuses on architectural features, design, design migration, and implementation. Thistutorial does not support simulation.

Versal Architecture XPHY Logic DesignThe simple design targeting the xcvc1902-vsvd1760-1LP-e-S device consists of a 12-bit receiveinterface with a strobe in IOBANK 705 (CLOCK_REGION X5Y0). The de-serialized data from the12-bit receive interface results in a 96-bit bus that is transmitted out of the device. The ClockingWizard IP is used to generate the 300 MHz reference clock for the Advanced IO Wizard IP froma 125 MHz input clock using an MMCM. The Advanced IO Wizard IP generates the 75 MHzfabric clock using an XPLL.

Chapter 8: Advanced IO Wizard Tutorial


https://www.xilinx.com/cgi-bin/docs/ctdoc?cid=90dee2b8-43f4-46f3-9556-89e9e02033c1;d=pg320-advanced-io-wizard.zip



Each Versal™ device XPHY cell corresponds to six single-ended PACKAGE_PINS/IOBs (or threedifferential PACKAGE_PINS/IOBs). The 12-bit receive interface requires 12 PACKAGE_PINs, plusan additional PACKAGE_PIN for the single-ended strobe. That means the 12-bit interfacerequires three XPHY cells. There will be five unused PACKAGE_PINs within the three XPHY cells.The remaining unused PACKAGE_PINs in XPHY logic interfaces can still be used for low-performance I/O logic or as a route-through path to fabric. Refer to XP IOL section of VersalACAP SelectIO Resources Architecture Manual (AM010) to get more information of using the pinsas route through.

Create a ProjectTo begin the tutorial, start the Vivado® Design Suite, create the tutorial project, and create a basicblock design.

1. Open the Vivado Design Suite. Ensure the banner at the top of the window identifies theVivado 2020.2 release.

2. Click Create Project from the Quick Start Menu and step through the following:

a. Specify the Project name project_Versal in your working area.

b. Specify RTL Project, and clear the Do not specify sources at this time check box.

c. Do not specify any HDL sources.

d. Create a constraint file called top.xdc, and select the Copy constraints files into projectcheck box.

e. In the Default Part menu, locate and select xcvc1902-vsvd1760-1LP-e-S.

f. Continue to Finish to create the new project.

3. In the Vivado Flow Navigator, click IP Integrator → Create Block Design. A popup dialog boxdisplays with the default block design name design_1.

4. Click OK. An empty block design diagram canvas open.

The Tcl commands used to create the project, constraints file, and initial block design are asfollows:

create_project project_Versal \ ./project_Versal \ -part xcvc1902-vsvd1760-1LP-e-S

file mkdir ./project_Versal/project_Versal.srcs/constrs_1/new

close [open \ "./project_Versal/project_Versal.srcs/constrs_1/new/top.xdc" w]

add_files \ -fileset constrs_1 ./project_Versal/project_Versal.srcs/constrs_1/new/






top.xdc

set_property target_constrs_file \ ./project_Versal/project_Versal.srcs/constrs_1/new/top.xdc \ [current_fileset -constrset]

create_bd_design "design_1"

Create and Configure the Advanced IO WizardNext, create and configure the Advanced IO Wizard IP for the 12-bit DDR source-sync receiveinterface.

1. In the block design canvas, click Add IP.

2. In the popup, search for Advanced IO Wizard and double-click Advanced IO Wizard to add itto the canvas.

3. On the canvas, double-click Advanced IO Wizard IP to step through IP configuration:

a. In the Basic tab under Clocking, set:

• Interface Speed: 600.00

• PLL Input Clock Frequency: 300.00

b. In the Advanced tab under IO Standard Selection, set:

• Single IO Std: SSTL12

c. In the Pin Configuration tab, specify the receive interface as follows:

• Pin Direction: RX

• IO Type: Single-ended





• Signal Type: Data

• Enable Strobe: click to select

• Strobe/RdClk Name: strbClk

• Signal Name: dataIn

• Number of Data Channels: 12

d. Skip the IO Timing Estimation tab for this tutorial.

The Tcl commands used to create and configure the receive interface are as follows:

create_bd_cell -type ip -vlnv xilinx.com:ip:advanced_io_wizard:1.0 \ advanced_io_wizard_0

set_property -dict [list CONFIG.DATA_SPEED {600.00} \ CONFIG.INPUT_CLK_FREQ {300.000} \ CONFIG.BIT_PERIOD {1667}] \ [get_bd_cells advanced_io_wizard_0]

set_property -dict [list CONFIG.DIFF_IO_STD {NONE} \ CONFIG.SINGLE_IO_STD {SSTL12}] \ [get_bd_cells advanced_io_wizard_0]

set_property -dict [list CONFIG.BUS0_NUM_PINS {12} \ CONFIG.BUS0_STROBE_NAME {strbClk} \ CONFIG.BUS0_SIG_NAME {dataIn}] \ [get_bd_cells advanced_io_wizard_0]

Create and Configure the Clocking Wizard IPNext, create and configure the Clocking Wizard IP for the 300 MHz reference clock.

1. In the block design canvas, click Add IP.

2. In the popup, search for Clocking Wizard and double-click Clocking Wizard to add it to thecanvas.





3. On the canvas, double-click the Clocking Wizard to step through IP configuration:

a. In the Clocking Features tab, set:

• Input Clock Information: For Primary Input Clock, enter Port Name clockIn, and setInput Frequency to 125.00 MHz.





b. In the Output Clocks tab, set:

• For Output Clock clk_out1, enter Port Name refClk, and set Output FrequencyRequested to 300.00 MHz.

• Click on Calculate Actual Valuesto update the Output Frequency Actual

c. Use the defaults available in MMCM Settings and Optional Port tabs.





The Tcl commands used to create and configure the Clocking Wizard are as follows:

create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wizard:1.0 clk_wizard_0

set_property -dict [list CONFIG.PRIM_IN_FREQ.VALUE_SRC USER] \ [get_bd_cells clk_wizard_0]

set_property -dict [list CONFIG.PRIM_IN_FREQ {125.000} \ CONFIG.PRIMARY_PORT {clockIn} \ CONFIG.CLKOUT_USED {true,false,false,false,false,false,false} \ CONFIG.CLKOUT_PORT \ {refClk,clk_out2,clk_out3,clk_out4,clk_out5,clk_out6,clk_out7} \ CONFIG.CLKOUT_REQUESTED_OUT_FREQUENCY \ {300.000,100.000,100.000,100.000,100.000,100.000,100.000} \ CONFIG.CLKOUT_REQUESTED_PHASE \ {0.000,0.000,0.000,0.000,0.000,0.000,0.000} \ CONFIG.CLKOUT_REQUESTED_DUTY_CYCLE \ {50.000,50.000,50.000,50.000,50.000,50.000,50.000} \ CONFIG.CLKOUT_DRIVES {BUFG,BUFG,BUFG,BUFG,BUFG,BUFG,BUFG} \ CONFIG.CLKOUT_DYN_PS {None,None,None,None,None,None,None} \ CONFIG.CLKOUT_MATCHED_ROUTING \ {false,false,false,false,false,false,false} \ CONFIG.CLKFBOUT_MULT {24.000000} \ CONFIG.CLKOUT1_DIVIDE {10.000000}] \ [get_bd_cells clk_wizard_0]

Create Constant IP, and Connect the IPsNext, create constant IPs, and connect them using Tcl commands. A block diagram shows theresults.

Note: Because the tutorial is focused on the Receive interface and Clocking Wizard, individual instructionsto step through the Constant IPs and connectivity are not provided.

The Tcl commands used to create the Constant IP and connect the IPs are as follows:

#make the parallel data a device outputmake_bd_pins_external \ [get_bd_pins advanced_io_wizard_0/data_to_fabric_dataIn]set_property name parallel_dataOut [get_bd_ports data_to_fabric_dataIn_0]

#create single bit logic 1 constant and connectcreate_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1connect_bd_net [get_bd_pins advanced_io_wizard_0/en_vtc] \ [get_bd_pins xlconstant_1/dout]

#create multi-bit constant and connectcreate_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_2set_property -dict [list CONFIG.CONST_WIDTH {9}] \ [get_bd_cells xlconstant_2]connect_bd_net [get_bd_pins xlconstant_2/dout] \





[get_bd_pins advanced_io_wizard_0/fifo_rd_en]

#connect clocksmake_bd_pins_external [get_bd_pins clk_wizard_0/clockIn]connect_bd_net [get_bd_pins clk_wizard_0/refClk] \ [get_bd_pins advanced_io_wizard_0/ctrl_clk]connect_bd_net [get_bd_pins clk_wizard_0/refClk] \ [get_bd_pins advanced_io_wizard_0/bank0_pll_clkin]connect_bd_net [get_bd_pins advanced_io_wizard_0/bank0_pll_clkout0] \ [get_bd_pins advanced_io_wizard_0/fifo_rd_clk]

#create and connect portsmake_bd_pins_external [get_bd_pins advanced_io_wizard_0/rst]set_property name rst [get_bd_ports rst_0]

make_bd_pins_external [get_bd_pins advanced_io_wizard_0/bank0_pll_rst_pll]set_property name rst_pll [get_bd_ports bank0_pll_rst_pll_0]

make_bd_pins_external [get_bd_pins advanced_io_wizard_0/intf_rdy]make_bd_pins_external [get_bd_pins advanced_io_wizard_0/dataIn]make_bd_pins_external [get_bd_pins advanced_io_wizard_0/strbClk]

The resulting block diagram is as follows:

Figure 24: Final Block Diagram





Close the Block Diagram, and Generate theRTL Wrapper

Next, use these Tcl commands to save, validate and close the block design, and generate the RTLWrapper.

Note: Because the tutorial is focused on the receive interface and Clocking Wizard, individual instructionsare not provided.

#save, validate, and close the bdsave_bd_designvalidate_bd_designclose_bd_design [get_bd_designs design_1]

#generate the top level wrappermake_wrapper -files [get_files \"./project_Versal/project_Versal.srcs/sources_1/bd/design_1/design_1.bd"] \-top

add_files -norecurse \"./project_Versal/project_Versal.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v"

Elaborate the Design, and Assign I/O PackagePins

Next, elaborate the design, and assign the I/O Package Pins using the Advanced I/O Planner.

1. In the Vivado® Integrated Design Environment (IDE), in the Flow Manager under RTLAnalysis, click Open Elaborated Design. It will take some time to open the design because ofthe Out-of-Context (OOC) Synthesis Runs.





2. In the upper right-hand corner of the Vivado IDE, be sure to have the I/O Planning Layoutselected.

3. Open the I/O Ports window, and the Package view.

4. From within the I/O Ports window, click the Open Advanced I/O Planner link to open thistool.





5. In the Advanced I/O Planner, in the I/O Instances tab, assign the Advanced IO Wizard IP toIO Bank IOBANK 705.





6. The individual nibble assignments can be adjusted using the Nibble Groups tab, as shown inthe following figure.





7. Click OK to close the Advanced I/O Planner when the nibbles are adjusted.

8. Click the Save icon to save the I/O assignments to the constraints file.

The tutorial relies on I/O auto placer in the implementation tools to place the remaining I/Osthat are not part of the Advanced IO Wizard IP. In a true design, the classic I/O Planning isavailable for the I/Os that are not part of the Advanced IO Wizard IP.

9. Close the elaborated design.

Review XDC Constraints, and RunImplementation

Finally, review the updated design constraints in the top.xdc from the Advanced I/O Planner, andimplement the design.

1. In the Sources View, open the top.xdc file located under Constraints.

2. View the updates to the top.xdc constraints file from the Advanced I/O Planner.





3. Close the top.xdc file.

4. Now, click Run Implementation.

5. After implementation is finished, you can Open Implemented Design.

6. Examine the Schematic and Device View to trace through the implementation results.

SummaryIn this tutorial, you learned how to create a Versal™ XPHY logic receive interface by using theClocking Wizard and the Advanced IO Wizard in the Vivado® IP integrator. You also learned howto perform I/O Planning on Versal™ devices for high-speed I/O using the Advanced I/O Planner.You successfully implemented the design targeting the Versal hardware.





Appendix A

DebuggingThis appendix includes details about resources available on the Xilinx Support website anddebugging tools.

Note: ILA insertion on the internal signals of Advanced IO wizard PHY could result in some flow issues.

MigrationThis appendix includes details about how a UltraScale™ and UltraScale+™ IO designs can beupdated to Versal™ IO designs.

• Versal ACAP Design Guide (UG1273) has a table that explains the IO map between thedifferent generations.

• High Speed SelectIO (HSSIO) Wizard that supports UltraScale and UltraScale+ IO designscannot directly be upgraded toVersal designs. If you have an existing HSSIO Wizard, it is notpossible to import the .XCI into Versal.

• You must build the Versal design from scratch, and you must include the CIPS IP along withthe other IPs, that are required for the design.

• You can use the Advanced IO Wizard for Source Synchronous or Asynchronous interfaces.

• The Advanced IO Wizard Basic Tab is very similar to the HSSIO Wizard Basic tab. You can mapthe required options accordingly.

• In the Versal families, the Pin Placement is not done during the Wizard creation. Hence, youmust select the number of data channels, the strobe associated and if the channels are single-ended or differential on the Pin Configuration Tab.

• The Pin Planning is then done, either in the Elaborated or Synthesized Design using theAdvanced IO Planner in Pin Planning.

• The IO Timing Estimation Tab helps you get the timing estimates of the design. For SourceSynch interfaces, the BISC does the data to clock alignment. The Wizard allows you to plug inthe information about the board to understand if you have sufficient budget for the interfacejust utilizing the BISC function.

• Summary Tab lists the groups of the Interfaces requested in the list of tabs in Advanced IOWizard.

Appendix A: Debugging


https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug1273-versal-acap-design.pdf



Finding Help on Xilinx.comTo help in the design and debug process when using the core, the Xilinx Support web pagecontains key resources such as product documentation, release notes, answer records,information about known issues, and links for obtaining further product support. The XilinxCommunity Forums are also available where members can learn, participate, share, and askquestions about Xilinx solutions.

DocumentationThis product guide is the main document associated with the core. This guide, along withdocumentation related to all products that aid in the design process, can be found on the XilinxSupport web page or by using the Xilinx® Documentation Navigator. Download the XilinxDocumentation Navigator from the Downloads page. For more information about this tool andthe features available, open the online help after installation.

Answer RecordsAnswer Records include information about commonly encountered problems, helpful informationon how to resolve these problems, and any known issues with a Xilinx product. Answer Recordsare created and maintained daily ensuring that users have access to the most accurateinformation available.

Answer Records for this core can be located by using the Search Support box on the main Xilinxsupport web page. To maximize your search results, use keywords such as:

• Product name

• Tool message(s)

• Summary of the issue encountered

A filter search is available after results are returned to further target the results.

Technical SupportXilinx provides technical support on the Xilinx Community Forums for this LogiCORE™ IP productwhen used as described in the product documentation. Xilinx cannot guarantee timing,functionality, or support if you do any of the following:

• Implement the solution in devices that are not defined in the documentation.

• Customize the solution beyond that allowed in the product documentation.

• Change any section of the design labeled DO NOT MODIFY.



https://www.xilinx.com/support.html

https://forums.xilinx.com/




https://www.xilinx.com/support/download.html






To ask questions, navigate to the Xilinx Community Forums.

Debug ToolsThere are many tools available to address Advanced IO Wizard design issues. It is important toknow which tools are useful for debugging various situations.

Vivado Design Suite Debug FeatureThe Vivado® Design Suite debug feature inserts logic analyzer and virtual I/O cores directly intoyour design. The debug feature also allows you to set trigger conditions to capture applicationand integrated block port signals in hardware. Captured signals can then be analyzed. Thisfeature in the Vivado IDE is used for logic debugging and validation of a design running in Xilinx®

devices.

The Vivado logic analyzer is used to interact with the logic debug LogiCORE IP cores, including:

• ILA 2.0 (and later versions)

• VIO 2.0 (and later versions)

See the Vivado Design Suite User Guide: Programming and Debugging (UG908).

Known Issues

• Advanced IO Wizard simulation

○ Simulations take longer to run due to full BISC execution, this will be replaced withbehavioral model in future.

○ XPHY8 has invalid data on the receiver (pattern hex22).

• Advanced IO Wizard

○ Selecting single ended IOStandards: LVCMOS will lead to an unrouteable design.

• Advanced I/O planner

○ Multiple instantiations of the same IP instance is not supported.

• Placer/Router

○ You may receive an error message that there are no free CCIO sites in few scenarios.

○ XPHY and Non-XPHY IO routing errors are combined in the same site.

• General pin planning

○ Drag and drop of IOs can lead to movement of IOs in different IO locations.




https://www.xilinx.com/cgi-bin/docs/rdoc?v=latest;d=ug908-vivado-programming-debugging.pdf



Appendix B

Additional Resources and LegalNotices

Xilinx ResourcesFor support resources such as Answers, Documentation, Downloads, and Forums, see XilinxSupport.

Documentation Navigator and Design HubsXilinx® Documentation Navigator (DocNav) provides access to Xilinx documents, videos, andsupport resources, which you can filter and search to find information. To open DocNav:

• From the Vivado® IDE, select Help → Documentation and Tutorials.

• On Windows, select Start → All Programs → Xilinx Design Tools → DocNav.

• At the Linux command prompt, enter docnav.

Xilinx Design Hubs provide links to documentation organized by design tasks and other topics,which you can use to learn key concepts and address frequently asked questions. To access theDesign Hubs:

• In DocNav, click the Design Hubs View tab.

• On the Xilinx website, see the Design Hubs page.

Note: For more information on DocNav, see the Documentation Navigator page on the Xilinx website.

ReferencesThese documents provide supplemental material useful with this guide:

Appendix B: Additional Resources and Legal Notices




https://www.xilinx.com/cgi-bin/docs/ndoc?t=design+hubs

https://www.xilinx.com/cgi-bin/docs/rdoc?t=docnav



1. Versal ACAP SelectIO Resources Architecture Manual (AM010)

2. Versal Architecture and Product Data Sheet: Overview (DS950)

3. Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)

4. Vivado Design Suite User Guide: Designing with IP (UG896)

5. Vivado Design Suite User Guide: Getting Started (UG910)

6. Vivado Design Suite User Guide: Logic Simulation (UG900)

7. Vivado Design Suite User Guide: Programming and Debugging (UG908)

8. Vivado Design Suite User Guide: Implementation (UG904)

9. Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906)

10. Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

11. Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956)

12. Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957)

13. Versal ACAP Design Guide (UG1273)

Revision HistoryThe following table shows the revision history for this document.

Section Revision Summary12/15/2020 Version 1.0

General updates • Added BiDir Support• Added Simple RIU Interface Support

07/14/2020 Version 1.0

Initial release. N/A

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© Copyright 2020 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, Versal, Virtex,Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the UnitedStates and other countries. AMBA, AMBA Designer, Arm, ARM1176JZ-S, CoreSight, Cortex,PrimeCell, Mali, and MPCore are trademarks of Arm Limited in the EU and other countries. Allother trademarks are the property of their respective owners.



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