Advanced Implantation Detector Array (AIDA):Update & Issues

Tom DavinsonSchool of PhysicsThe University of Edinburgh

presented byTom Davinson

on behalf of the AIDA collaboration(Edinburgh – Liverpool – STFC DL & RAL)

DESPEC: Implantation DSSD Concept

• SuperFRS, Low Energy Branch (LEB)• Exotic nuclei – energies ~ 50 – 200MeV/u• Implanted into multi-plane, highly segmented DSSD array• Implant – decay correlations• Multi-GeV DSSD implantation events• Observe subsequent p, 2p, , , , p, n … decays• Measure half lives, branching ratios, decay energies …• Tag interesting events for gamma and neutron detector arrays

Implantation DSSD Configurations

Two configurations proposed:

a) 8cm x 24cm “cocktail” mode many isotopes measured simultaneously

b) 8cm x 8cm high efficiency mode concentrate on particular isotope(s)

AIDA: DSSD Array Design

• 8cm x 8cm DSSDscommon wafer design for 8cm x 24cm and 8cm x 8cm configurations

• 8cm x 24cm3 adjacent wafers – horizontal strips series bonded

• 128 p+n junction strips, 128 n+n ohmic strips per wafer• strip pitch 625m• wafer thickness 1mm• E, Veto and up to 6 intermediate planes

4096 channels (8cm x 24cm)• overall package sizes (silicon, PCB, connectors, enclosure … )

~ 10cm x 26cm x 4cm or ~ 10cm x 10cm x 4cm

courtesy B.R

ubio

ASIC Design Requirements

Selectable gain 20 1000 20000 MeV FSRLow noise 12 600 50000 keV FWHM

energy measurement of implantation and decay events

Selectable threshold < 0.25 – 10% FSRobserve and measure low energy detection efficiency

Integral non-linearity < 0.1% and differential non-linearity < 2% for > 95% FSRspectrum analysis, calibration, threshold determination

Autonomous overload detection & recovery ~ sobserve and measure fast implantation – decay correlations

Nominal signal processing time < 10sobserve and measure fast decay – decay correlations

Receive (transmit) timestamp datacorrelate events with data from other detector systems

Timing trigger for coincidences with other detector systemsDAQ rate management, neutron ToF

Schematic of Prototype ASIC Functionality

Note – prototype ASIC will also evaluate use of digital signal processing

Potential advantages• decay – decay correlations to ~ 200ns• pulse shape analysis• ballistic deficit correction

Design Study Conclusions

• 4’’ or 6” Si wafer technology?- integrated polysilicon bias resistors (15M)- separate coupling capacitors (require 22nF/200V+)

• Radiation damage mitigation measures essential- detector cooling required

• Noise specification (12keV FWHM) … “not unreasonable”

• Discriminator - low threshold (<50keV) – slow, compromised for ID > 100nA- separate timing discriminator – higher threshold

• x1000 overload recovery ~ s achievable- depends on input pulse shape- optimisation requires more information

AIDA Design Concept

Detail of DSSSD detector layers and detector enclosure

Beam

courtesy Dave Seddon & Rob Page, University of Liverpool

AIDA: Current Status

• Edinburgh – Liverpool – CCLRC DL – CCLRC RAL collaboration

- 4 year grant period- DSSD design, prototype and production- ASIC design, prototype and production- Integrated Front End FEE PCB development and production- Systems integration- Software development

Deliverable: fully operational DSSD array to DESPEC

• Proposal approved & fully funded - project commenced August 2006

• Detailed specification published November 2007 • Technical Specification release to project engineers January 2007

• Detailed ASIC design & engineering underway

AIDA: Resources & Tasks

Cost

• Total announced value proposal £1.96M

Support Manpower

• CCLRC DL c. 4.2 SY FEE PCB DesignDAQ h/w & s/w

• CCLRC RAL c. 3.5 SY ASIC Design & simulationASIC Production

• Edinburgh/Liverpool c. 4.5 SY DSSD Design & productionFEE PCB productionMechanical housing/support

• Platform grant support CCLRC DL/Edinburgh/Liverpool

AIDA: Current Status

• DSSD request for tender

• Prototype ASIC design submission 2008/Q1

• FEE design underway

liquid cooling required (cf. AGATA digitiser module)

• Evaluating

10nF/100V capacitor arraysAnalog Devices AD9252 14-bit/50MSPS ADC

• DSSD response high energy heavy-ions

simulations Luigi Bardelli et al.Texas A&M (40MeV/u) November 2008GSI (100MeV/u) March 2009

Outstanding Issues: approaching the Rubicon

• Package size10cm x 26cm x 4cm (10cm x 10cm x 4cm)

• Mechanical design concepts

10cm x 26cm AIDA/ToF/Ge10cm x 26cm AIDA/4 Neutron Detector10cm x 10cm AIDA/TAS

… others?

• Review ASIC Project Specification

DESPEC project requirements satisfied?

AIDA/ToF/Ge

AIDA/4 Neutron (NERO)

AIDA/TAS

AIDA Project Information

Project web site

http://www.ph.ed.ac.uk/~td/AIDA/welcome.html

Design Documents

http://www.ph.ed.ac.uk/~td/AIDA/Design/design.html

Project Technical SpecificationASIC Project Specification v1.3FEE Specification v0.5

The University of Edinburgh (lead RO)Phil Woods et al.

The University of LiverpoolRob Page et al.

STFC DL & RALJohn Simpson et al.

Project Manager: Tom Davinson

Acknowledgements

This presentation includes material from other people

Thanks to:

Ian Lazarus & Patrick Coleman-Smith (STFC DL)Steve Thomas (STFC RAL)Dave Seddon & Rob Page (University of Liverpool)Berta Rubio (IFIC, CSIC University of Valencia)

Implantation – Decay Correlation

• DSSD strips identify where (x,y) and when (t0) ions implanted

• Correlate with upstream detectors to identify implanted ion type

• Correlate with subsequent decay(s) at same position (x,y) at times t1(,t2, …)

• Observation of a series of correlations enables determination of energy distribution and half-life of radioactive decay

• Require average time between implants at position (x,y) >> decay half-lifedepends on DSSD segmentation and implantation rate/profile

• Implantation profilex ~ y ~ 2cm, z ~ 1mm

• Implantation rate (8cm x 24cm) ~ 10kHz, ~ kHz per isotope (say)

• Longest half life to be observed ~ seconds

Implies quasi-pixel dimensions ~ 0.5mm x 0.5mm

AIDA: General Arrangement

Representative ASIC Noise Analysis

• Minimise ballistic deficitshaping time >10x tr

operate with ~ snoise dominated by leakage current for ID > 10 nA

Note – amongst other assumptions, we assume detector cooling

AIDA: Workplan

Daughtercard

connector

16 channelASIC

9222ADFADC

9222ADFADC

16 bitADC

Singleto

diffn.

16

1

2I C controls

N 2 2222222222222 22222222

Readout controlsClocksReset

10LVDS 20 pins

10LVDS 20 pins

4

- - AIDA FEE Support connections and parts for one chip

Power Supplies

Daughtercard

connector

16 channelASIC

9222ADFADC

9222ADFADC

16 bitADC

Singleto

diffn.

16

1

2I C controls

N 2 2222222222222 22222222

Readout controlsClocksReset

10LVDS 20 pins

10LVDS 20 pins

4

Daughtercard

connector

16 channelASIC

9222ADFADC

9222ADFADC

16 bit ADC

Singleto

diffn.

16

1

2I C controls

N 2 2222222222222 22222222

Readout controlsClocksReset

10LVDS 20 pins

10LVDS 20 pins

4

Daughtercard

connector

16 channelASIC

9222ADFADC

9222ADFADC

16 bit ADC

Singleto

diffn.

16

1

2I C controls

N 2 2222222222222 22222222

Readout controlsClocksReset

10LVDS 20 pins

10LVDS 20 pins

4

Daughtercard

connector

16 channelASIC

9222ADFADC

9222ADFADC

16 bit ADC

Singleto

diffn.

16

1

2I C controls

N 2 2222222222222 22222222

Readout controlsClocksReset

10LVDS 20 pins

10LVDS 20 pins

4

Xilinx 4 25XC VLX - 688FF 448 I/O

344 4used forASICS 6Timestamp and controls =

6Slow control = 22 22222= 3 2 ,

16 , 4address controls 16Logic Inspection :

: 32leaves spare

Timestamp clock and controls

Slow control interface

Readout interface

4 12XCV FX 320 /I O

Control of the FEE with operating PPC and readout to DAQ with 1 2222: 3 0

SDRAM 8 32Mx : 58 pinsSystemACE : 40 pinsFLASH2 16Mx : 43 pins4ASICs : 64 pins4ASICs : 64 pins

: 2Console pins : 6Timestamp pins

: 4Oscillator pins : 311Total pins

TEMACPHY

32MBSDRAM

SystemACE

FLASH for boot load of

LINUX

Connection forexternal

development CF

45RJ

Timestampexternalinterface

Consoleinterface

Oscillators

Timesta

mpandcontro

ls

Slowcontro

lInt erfa

ce

ReadoutInterfa

ce

- -AIDA FEE ASIC to DAQ block diagram

FPGA & FADCs

FPGA & FADCs

Water cooled metal

Water cooled metal

FPGA & FADCs

FPGA & FADCs

Water cooled metal

Water cooled metal

Water cooled metal

Water cooled metal

Water cooled metal

Water cooled metal

8cms

4cm

s

8Area required for x eightchannel FADCs with one single

to differential buffer perchannel

Allows space for routing the input signals for the second

row of buffers away from the high speed output signals of

the first row.

9cm

s

FPGA for ASIC event readout and slow control

FPGA containing PPC to transfer events to Acquisition computers.

4Mezzanine withASICS

Diagram (above) of the FEE boards as they would fit in the vertical plane. The grey rectangles are heat conductive foam pads which conform to the component outlines and conduct the heat to the water cooled metalwork. The green is pcb, the orange is a Samtec 80 pin connector with a 2.3mm height and the dark brown is the ASIC. The connections to the detector will be on the mezzanine boards to the left and to the acquisition network computers and BUTIS on the right. These are not shown.

Diagram ( alongside) shows the layout of a sub-board.