advanced features and techniques of embedded systems

Advanced Features and Techniques of Embedded Systems Design Lab Workbook embd33000-14-wkb-lab-rev1

Advanced Features and Techniques of Embedded Systems Design Lab Workbook v14.1

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Table of Contents

Lab 1: Building a Complete Embedded System ............................................ 3

Lab 2: Debugging Using the ChipScope Pro Analyzer ............................... 37

Lab 3: Extending Memory Space with Block RAM ...................................... 59

Lab 4: Direct Memory Access using CDMA Controller ............................... 83

Lab Workbook Lab1: Building a Complete Embedded System

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Lab 1: Building a Complete Embedded System Cortex-A9 Processor and Zynq EPP ZC702 Board

Introduction

This lab follows the preferred embedded design flow for creating an embedded Zynq™ extensible processing platform (EPP) system and utilizing peripherals in both the processing system (PS) and programmable logic (PL).

The overall system that you will be constructing in this lab is as follows:

Figure 1-1: Block Diagram for the Zynq EPP Generic Design

Not every peripheral in this design will be used in this lab.

The rotary_switch module: The important aspect of this module is that it resides in the programmable logic section of the Zynq device. Other peripherals, such as the DDR3 and FLASH interfaces, have their own interface modules inside the PS. The UART is part of the I/O peripheral (IOP) block inside the PS. The remaining peripherals are general-purpose digital input/output (GPIO) modules.

This lab will focus on the implementation of the rotary switch. This switch takes two phases from the switch itself. The relationship between these two phases indicates the direction and speed that the switch is being turned. Managing these phases can be a difficult task for a microprocessor because it is highly time sensitive. This would require that the processor guarantee that it checks all three outputs from the switch at a fast, periodic rate. While it is possible for the processor to handle this task, it is far easier (from the software standpoint) to simply construct a module that converts the incoming phases into a direction and a status indicating that something has changed. The faster the rotary_event_out pulses, the faster the switch is being turned.

This module is implemented in the PL and is implemented outside the embedded system. While it is possible to create IP and include it in the embedded system, it is kept external so that you can see how this type of problem can be solved.

Lab1: Building a Complete Embedded System Lab Workbook

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This mechanism is ideal for driving interrupts in the processor.

Figure 1-2: Rotary Switch Module Interface

The rotary switch can also be pressed. This signal is synchronized with the clock and passed out through the rotary_press_out port.

This type of device is convenient for scrolling though lists of information. When the desired item is highlighted, the switch can be pressed to select that item.

Looking more specifically at the Processing System module, you can se a number of peripherals that need to be manually added to the base processor. Interfaces to the DDR3 and FLASH modules are automatically included in the design.

For uniformity of presentation, the FMC-CE board is used. This small board provides a standard set of peripherals across multiple platforms that support the FMC connector. If this board is absent, ask your instructor for the proper UCF for this lab as a number of (but not all) peripherals can be duplicated on the board that you are using.

Objectives

After completing this lab, you will be able to:

Create an embedded project

Configure the processing system

Add both custom and Xilinx standard IP to the design

Build software platforms based on the hardware design

Procedure

This lab uses one of the recommended flows. You will first create a new project in the PlanAhead™ tool. Next, you will import the Rotary_LCD_top code into the project. After this step, you will create an XPS project that describes the processing system. Next, these two modules will be connected together and implemented. Finally, you will download the bitstream to the board and load the provided software to test.

This lab is separated into steps that consist of general overview statements that provide information on the detailed instructions that follow. Follow these detailed instructions to progress through the lab.

This lab comprises four primary steps: First you will create a new PlanAhead tool project and add an embedded processing system to it. Next, you will edit this embedded processor and add a number of peripherals. The third step requires you to return to PlanAhead tool and add additional IP that will connect to the embedded system. Finally, you will create code for the processor and configure the system to monitor the design's behavior on the hardware.

Note: If you are unable to complete the lab at this time, you can download the original lab files for this lab from www.xilinx.com/training/downloads.htm. These are the original lab files and do not contain any work that you may have previously completed.



General Flow

Creating the PlanAhead Tool Project Step 1

The recommended flow when the programmable logic (PL) is used is to begin with a PlanAhead tool project. Once the project is created, the logic destined for the PL can be created or imported. The processing system (PS) can then be added as though it were a hierarchically subordinate module—even though the PS often controls the action on the entire chip.

This step will walk you through the process of creating a PlanAhead tool project, importing existing source code, and creating an XPS project from within the PlanAhead software environment.

1-1. Launch the PlanAhead software and create a new project.

1-1-1. Select Start > All Programs > Xilinx ISE Design Suite 14.1 > PlanAhead > PlanAhead (32) for 32-bit systems or PlanAhead for 64-bit systems to launch the PlanAhead software.

1-1-2. Click Create New Project and click Next.

Figure 1-3: Creating a New Project in the PlanAhead Software

This will launch the New Project Wizard.



1-1-3. In the Project name field, enter zynq_generic_design, and for the Project location field, browse to the C:\training\advEmbSysDsgn\labs\buildCompleteSystem directory. Be sure to deselect the Create Project Subdirectory option. Click Next.

Figure 1-4: Setting the Name and Location of the New PlanAhead Tool Project

1-1-4. As you will be either entering HDL files or creating them from scratch, select RTL Project and click Next.

Figure 1-5: Selecting an RTL-Based Project

The HDL sources that will reside in the PlanAhead tool project have been provided for you and you will now add them.



1-1-5. Click Add Files.

Figure 1-6: Adding Existing Source Files

1-1-6. Browse to the C:\training\advEmbSysDsgn\support directory and select the following files: zynq_generic_design_pkg.vhd, zynq_generic_design_top.vhd, debouncer.vhd, meta_harden.vhd, and rotary_switch.vhd. Click OK.

1-1-7. As you will be creating various templates, select VHDL for the target language and click Next.

The IP that you will be using with the PS (an LCD controller) will be imported when the PS is built.

1-1-8. Click Next.



You will now add the constraint file, which has been completely constructed for you.

1-1-9. Click Add Files.

You should already be in the support directory.

1-1-10. Select Zynq_generic_design_FMC.ucf. Click OK.

1-1-11. Click Next.

You can now select the target device.

1-1-12. Select the target part by filtering by board and family (Zynq-7000 EPP). Select Zynq-7 ZC702 Evaluation Board and click Next then Finish.

Figure 1-7: Selecting the Evaluation Board

The PlanAhead software GUI is launched.

Questions 1

Expand the Rotary_LCD_TOP entry. Why is there a question mark ( ) next to system_i?

1-2. Now it is time to build the PS.

1-2-1. Under Flow Navigator > Project Manager, click Add Sources ( ).



1-2-2. Select Add or Create Embedded Sources from the list of sources type and click Next.

Figure 1-8: Creating the Embedded Project Source

1-2-3. Select Create Sub-Design.

Figure 1-9: Creating the New Embedded Source



1-2-4. Enter zynq_generic_design in the Module Name field. Click OK.

Figure 1-10: Naming the Embedded Source

1-2-5. Click Finish.

Xilinx Platform Studio is launched. You will use the XPS tool to construct the embedded system.

Building the Embedded System in XPS Step 2

2-1. Now that the PlanAhead tool and XPS projects have been created, you will define the components comprising the processing system (PS) and connect the various hard and soft peripherals. The soft peripherals will reside in the programmable logic (PL).

At this point, the XPS tool has opened and the XPS project has been created. A dialog box identifies this as a (currently) blank Zynq EPP project and invites you to add a processing system. Note that this dialog box may be hidden behind other open windows—you may have to search for it.

2-1-1. When you find it, click Yes.

2-1-2. Select the Zynq tab from the System Assembly View tab to view the overall PS.

Figure 1-11: Select the Zynq tab to View and Configure the PS



Next you will open the Zynq EPP system configuration tool. This tool will enable you to select most of the important PS capabilities.

There are dozens of registers that need to be configured. Some of these registers include the DDR configuration information. Because this is an established board, it is much easier to import an existing configuration and modify it to your needs.

2-1-3. Click Import Zynq Configurations ( ) which is next to the Help icon.

Figure 1-12: Importing the Board Configuration

You will be invited to choose from a set of existing configuration templates.

2-1-4. Click OK to select the only configuration template.

Figure 1-13: Selecting the Configuration Template

2-1-5. Click Yes to acknowledge that the default Zynq EPP configuration will overwrite certain files.

You will modify the existing configuration in the following steps.

Question 2

What is included in the default configuration for the 7z020?



2-2. You are now provided with a basic system—all you need to do is modify the various peripherals to meet your needs.

2-2-1. Click the Clock Generation block in the diagram in order to configure the clocks being passed from the PS to the PL.

A clock for the PL is required as there are a number of peripherals that will be implemented in the PL.

Figure 1-14: Locating the Clock Generator Module

Notice that there is a clock for each peripheral in the IOP as well as four clocks available for the PL.

2-2-2. Expand the PL Fabric Clocks entry and confirm that FCLK_CLK0 is set to 50 MHz. Click Validate Clocks to see if the settings are legal.

Figure 1-15: Changing the Clock to the PL to 50 MHz



Results of the clock validation are shown in the dialog box below the list of components.

2-2-3. Click OK to save any changes and exit the Wizard.

Not all the peripherals included in the current IOP block configuration are required. You will now remove unneeded peripherals from the IOP.

2-2-4. Click anywhere in the I/O Peripheral block.

2-2-5. Deselect all peripherals except UART 1 and Quad SPI Flash.

Figure 1-16: Deselecting all but UART 1

The peripherals in the IOP can reside only in certain groups of MIO pins. Because the ZC702 board has already been built, you must choose peripherals and pins that correspond to how the board is physically laid out.

The ZC702 board places the transmit and receive pins for the UART at pins 48 and 49.

2-2-6. Click the pull-down menu next to UART1 and select pins 48..49 from the drop-down list.

2-2-7. Click Close.

2-3. Next, the GPIOs must be connected. Recall that there are GPIOs as part of the IOP that connect directly through the MIO, GPIOs as part of the IOP that connect through the EMIO to package pins, and GPIOs that can be implemented in programmable logic and connected to the PS via a GP AXI master connection.

This lab will use PL-based GPIOs. The primary reason for this is that signals are to be routed to the FMC slots so that the FMC-CE card can be used, which allows you access to the LCD, LEDs, the rotary switch, and other devices. Because the ZC702 board is wired to support many devices on the board and the connections between the MIO are NOT routed to the FMC



connectors, you can use the PL GPIOs to gain access to the necessary pins on the package.

Alternatively, it is possible to use the GPIOs in the IOP and route these signals through the EMIO to the necessary package pins. There are two 32-bit GPIOs available in the IOP; however, because this design implements many GPIOs, all have been implemented in PL for consistency.

2-3-1. Select the Bus Interfaces tab.

Figure 1-17: Selecting the Bus Interfaces Tab

2-3-2. Select the IP Catalog and expand the General Purpose IO entry.

2-3-3. Drag-and-drop the AXI General Purpose IO peripheral into the Bus Interfaces workspace. Click Yes to acknowledge this action.

This first GPIO will be used to control the eight LEDs available on the FMC-CE board or the demo board (the user constraint file will determine which one).



2-3-4. Expand Channel 1 and set the GPIO Data Channel Width to 8 and rename this GPIO to GPIO_LED_8bits by typing the new name in the Component Instance Name field.

Figure 1-18: Configuring the 8-LED GPIO Controller

2-3-5. Click OK.

The tools will attempt to determine how this peripheral should be connected.

2-3-6. Accept the default choice (processing_system7_0) and click OK.

Figure 1-19: XPS Can Automatically Connect the New Peripheral

Note that an AXI Interconnect, addresses, and I/O ports were was automatically created and connected to and for this peripheral.



2-3-7. Repeat the above steps (2-3-3 through 2-3-6) to create a GPIO with three inputs named GPIO_rotary_switch_3bits.

2-3-8. Because all of the signals are inputs, remember to mark the Input Only field with a 1.

This will help to reduce the complexity and amount of logic generated when the GPIO module is created.

Figure 1-20: Configuring the AXI GPIO Rotary Switch Controller

2-3-9. Click OK to create the peripheral.

2-3-10. Click OK to connect the peripheral to an AXI port.

2-4. The final peripheral that needs to be included in this design is not part of the standard Xilinx peripheral library. This is "user defined" and built in the Embedded Systems Design course. You will import this peripheral and add it to the design.

2-4-1. Open Windows Explorer and browse to the C:\training\advEmbSysDsgn\support directory.

2-4-2. Copy the lcd_ip_v1_00a directory to the C:\training\advEmbSysDsgn\labs\buildCompleteSystem\zynq_generic_design.srcs\sources_1\ edk\zynq_generic_design\pcores directory.

This will place the peripheral in the proper location for the next step.

2-4-3. Return to the XPS tool and click the Rescan IP Repository icon to rescan the IP repository and make the LCD peripheral visible.

This icon is found in the IP Catalog tab above the description field.

2-4-4. Expand the Project Local PCores > USER structure.



2-4-5. Click-and-drag the LCD_IP peripheral into the Bus Interfaces workspace. Click Yes to acknowledge the addition of this IP to the design.

2-4-6. Change C_LCD_WIDTH to 11 (8 data bits and 3 control bits) and click OK.

2-4-7. Click OK to instantiate and connect the IP.

Figure 1-21: Setting the LCD Parameters

Question: 3

How can you tell if the components are connected?

2-5. At this point, many of the components for the PL are present and are connected to the processor. The tool makes certain assumptions about the peripherals and will make connections to the external ports. You will now verify the connections and make any additional connections required.

A number of peripherals have yet to be added to the system. These will be added in the last step as it is adding several more GPIO devices to the design—not an especially good use of your time.

2-5-1. Select the Ports tab in the System Assembly View and expand the GPIO_LED_8bits component.



You may wish to widen the Name and Connected Port fields. This is done by click-dragging the boundary markers in the header.

2-5-2. Expand both the (IO_IF) gpio_0 and (BUS_IF) S_AXI entries.

Figure 1-22: Viewing the Connections to the GPIO_LED_8 Peripheral

Note that the tools automatically made a number of connections.

The S_AXI_ACLK was automatically connected to the same clock that the AXI is driven by (from the PS).

The GPIO_IO port (a bi-drectional port) was connected to the external port region and given the name GPIO_LED_8bits_GPIO_IO_pin. You will correct for this shortly.

2-5-3. Because this GPIO is output only, right-click GPIO_IO and select No Connection to remove the connection from the bidirectional GPIO_IO port. Right-click GPIO_IO_O (the output only connection) and select Make External.

Figure 1-23: Making the Output Only Port of the GPIO_LED_8 Component External

2-5-4. Repeat the above process for GPIO_rotary_switch_3bits, except that this peripheral is input only. Make the GPIO_IO_I port external.

Figure 1-24: Rotary Switch Connection to External Ports



2-5-5. Expand the lcd_ip_0 component, right-click the lcd port and select Make External.

Figure 1-25: Making the lcd Port External

2-6. The Rotary Switch on the FMC-CE board produces two phases as it is turned. While this is possible for the microprocessor to handle, a more elegant solution is to convert these phases into rotation and "event" signals, which are easier for the software to manage. A block of code to manage the rotary switch is located at the top level of the design and it needs access to a clock. The 50-MHz clock generated by the processing system needs to be made external for the PL. While it is possible to bring additional clocks into the EPP, it is always best to minimize the number of clocks and connections on a board.

Rule of thumb: if you can use an existing clock without causing signal integrity issues, do so.

2-6-1. Expand the processing_system7_0 IP and locate FCLK_CLK0.

2-6-2. Right-click the FCLK_CLK0 port and select Make External.

2-7. There is a single interrupt from the PL that indicates that an event has occurred on the rotary switch line.

2-7-1. Locate the IRQ_F2P signal in the expanded processing_system7_0, right-click IRQ_F2P (PL to processor), and select Make External.

Figure 1-26: Connecting an External Interrupt Source

Note that this interrupt is two bits wide—one for each processor.



2-8. When signals were added to the external ports list, names were automatically chosen. These names are descriptive, but often verbose. This step will illustrate how external port names can be changed.

2-8-1. Expand the External Ports entry at the top of the Ports tab. Locate the external port GPIO_LED_8bits_GPIO_IO_O_pin, click once in the Name column, enter LEDs_8bits, and press Enter.

Figure 1-27: Selecting the GPIO_LED_8_GPIO_IO_pin Name for Editing

2-8-2. Repeat this process to rename GPIO_rotary_switch_GPIO_IO_I_pin to rotary_switch_3bits.

2-8-3. Repeat this process to rename lcd_ip_0_lcd_pin to lcd_11bits. Below is the final port view for the embedded portion of the design.

Figure 1-28: Final External Port Naming

2-9. Now that all the peripherals have been added and everything is connected, the peripherals must be assigned to locations in memory. Recall that as peripherals are added to the design, they are automatically given addresses based on where they are attached. You will now verify that all the addresses are assigned properly.

2-9-1. Select the Addresses tab and expand processing_system7_0's Address Map.

Peripherals that have not yet been assigned addresses will appear in the Unmapped Addresses field.

2-9-2. If any peripherals appear in the Unmapped Addresses field, select the memory "size" (that is,

decode region) and click the Generate Address icon ( ) in the upper right of the GUI.



2-10. [Optional] Earlier you were informed that there were several peripherals that had not been added to the design due to time constraints. To get to the full design, you will overwrite the current MHS file with a completed MHS file.

2-10-1. Select File > Exit to close XPS. Click Yes to confirm exit.

2-10-2. Using Windows Explorer, browse to the C:\training\advEmbSysDsgn\support directory. Copy the Zynq_generic_design.mhs file to the C:\training\advEmbSysDsgn\labs\buildCompleteSystem\zynq_generic_design.srcs\sources_1\ edk\zynq_generic_design directory.

2-10-3. Return to the PlanAhead software and double-click system_i.

2-10-4. Select the System Assembly View tab and select Bus Interfaces tab.

You should now see the remaining peripherals added as shown in the figure below.

Figure 1-29: Final Bus Interfaces View

2-11. Run a design rule check to catch any connection and address map errors.

2-11-1. Select Project > Design Rule Check to run the DRC.

Issues are displayed in the Console window.

2-12. The embedded design is now complete. Exit XPS.

2-12-1. Select File > Exit to close XPS and return to the PlanAhead software. Click Yes to confirm exit.

Alternatively, you could run synthesis from within XPS and then return to the PlanAhead software, but do not do this as it will consume valuable lab time.

Question 4

If you were building your own board, how might you implement the GPIOs?



Building the Embedded System Wrapper Step 3

Now that the processing system and all the peripherals have been defined, they need to be connected to the "outside world". This step will show you how to create instantiation templates for the embedded module, connect it to the top-level signal conditioners, and run the implementation tools.

The coding of the top-level VHDL module has been performed for you with the exception of connecting several key signals to the embedded system component. While this step is illustrated in VHDL, many of the techniques shown here are analogous to Verilog coders.

VHDL requires that a component be "defined" before it is used (Verilog does not). This step will show you how to create a top-level HDL file and extract the necessary portions for your use.

3-1. Create a component for the newly developed embedded system. If you selected VHDL during the project creation step, this selection will appear in this GUI.

3-1-1. In the Flow Navigator, select Project Manager > Project Settings under Project Manager.

3-1-2. Select VHDL from the Target Language drop-down list in the General tab.

Figure 1-30: Setting the Preferred Language Option

This ensures that the template language option is set to VHDL and that the templates will be generated in this language.

3-1-3. Click OK.

3-1-4. In the Sources > Hierarchy tab, expand zynq_generic_design_top, select system_i , then right-click system_i - zynq_generic_design (zynq_generic_design.xmp) and select Create Top HDL



Normally you would select View Instantiation Template; however this is not working in the 14.1 tool release.

Figure 1-31: Selecting View Instantiation Template

A new top level hierarchy source appears with the name zynq_generic_design_stub.

3-1-5. Double-click zynq_generic_design_stub to open it.

3-1-6. Locate the component instantiation (at or near lines 45 through 76).

This component definition has been cut-and-pasted for you into the zynq_generic_design_pkg.vhd package file.

3-1-7. Select the Libraries tab in the Sources tab and double-click zynq_generic_design_pkg.vhd to examine this package file.

A package file is a convenient place to keep VHDL component instantiations so that they do not clutter your code. Verilog uses include files to accomplish a similar task.

3-1-8. Scroll down to line 42 and compare this component definition with the one from the zynq_generic_design_stub.vhd file.

Other than some formatting and signal reorganization, these two component definitions are functionally identical.

3-2. Now that the system component has been defined, you would normally use the User Instantiation Template to instantiate the embedded system within



your HDL code. However, in the interest of time, this task has been mostly performed for you. Your job now is to make the last remaining connections.

3-2-1. Using either the Hierarchies tab or Libraries tab, double-click zynq_generic_design_top.vhd to open the top of the design.

3-2-2. Locate the instantiation of the embedded system at or near line 131.

3-2-3. Connect the Type signal name clk50MHz_from_ps at or near line 134 (in the zynq_generic_design instantiation) and again on lines 107 (the rotary switch manager module) and 122 (button debouncers) to connect the 50-MHz clock generated by the PS to the rot_sw_manager and debouncer modules using the signal clk_50MHz.

3-2-4. Select File > Save File to save the file.

3-3. There is now no reason to have the stub as it was only used to extract the implementation templates. When this feature is working, it will only be necessary to select "Generate Instantiation Template."

3-3-1. Right-click zynq_generic_design_stub.vhd and select Delete to remove this from the project.

3-3-2. Click OK.

3-4. The final step is to review the constraints for the this board. A completed UCF is provided for you and has been added to the project.

Recall that XPS generates an initial UCF for the board when synthesis is run named ps7_constraints.ucf. Because this file has not yet been produced, it is provided for you in the support directory. Normally this would be found by expanding system_i under the Embedded Design Sources folder in the Sources > Libraries tab. This UCF contains pin placements for the PS.

3-4-1. In the Sources tab, expand Constraints and double-click zynq_generic_design_FMC.ucf to open it.

3-4-2. Select File > Open File and browse to the support directory. Select Files of Type > All Files. Select ps7_constraints.ucf. Click OK.

3-4-3. Compare the two UCF files and answer the question below.

Question 5

What do you notice about the zynq_generic_system.ucf file?



3-5. [Optional] Normally, the hardware design would be implemented and a bitstream would be generated at this time. Because this process can take 15-20 minutes to complete, you will skip this step. A working bitstream file has been provided for you. The step is included only for completeness.

Please review this section only and move ahead to the step "Exit the PlanAhead software".

Use the implementation tools in the PlanAhead software to:

Synthesize

Translate

Map

Place and route

Generate the bitstream

This action will implement the hardware design that can be directly downloaded to the Zynq EPP via a download cable. You can then start using the software development tools in SDK to implement the software application on this hardware.

3-5-1. In the Flow Navigator, click Generate Bitstream under Program and Debug.

The tools are intelligent enough to understand that synthesis and implementation have not been run and will run them for you prior to attempting to build a bitstream.

Figure 1-32: Generating the Bitstream

You are asked to launch synthesis and implementation. Normally, you would click Yes.

However, do not perform this step but note what should done.



Generation takes approximately 15 minutes or more. When generation is completed, the message Process "Generate Programming File" completed successfully appears in the Console window.

SDK will automatically build the software application project and produce an Executable and Load Format (ELF) file.

3-6. From the PlanAhead tool, export the embedded system and launch the Software Development Kit (SDK).

3-6-1. Select File > Export > Export Hardware.

Figure 1-33: Exporting the Hardware from PlanAhead

The Export Hardware dialog box asks you to select what is to be exported and if SDK should be launched. Because you did not run the Generate Bitstream command, the Export Bitstream option is grayed out.

3-6-2. Select Export Hardware and Launch SDK.

You will bring the bitstream into SDK later.

Figure 1-34: Exporting the Processor Hardware and Launching SDK



The actual exporting of the embedded processor hardware is transparent to the user. The SDK tool will launch. A hardware platform project will be constructed automatically for you within SDK.

SDK creates a workspace environment consisting of project files, tool settings, and your software application. Once set, you cannot change the location of this workspace. If it is necessary to move a software application to another location or computer, use the Import and Export features built into SDK. A good location for the software workspace is the root directory of your PlanAhead/XPS tool project. While not a requirement, it is a good idea to keep the SDK-related files together.

3-6-3. Normally you would click OK to perform this task; however, this step has been done for you and you will open the SDK tool in its standalone mode.

The completed bitstream and associated hardware files can be found in the C:\training\advEmbSysDsgn\support directory.

3-7. Exit the PlanAhead software.

3-7-1. Select File > Exit to close the PlanAhead tool. Click OK.

Building and Running the Software Step 4

At this point in the design, you have created all the necessary hardware. All that remains is to create the software support, configure the board, and load the software.

4-1. Open SDK. During the normal export procedure, the SDK tool would automatically open for you. Create a hardware description platform from the hardware files found in the support directory. This step is normally performed for you by exporting the hardware from the PlanAhead tool; however, because you did not implement the design in the previous step, the hardware files are provided for you, which means you need to build the hardware description platform.

4-1-1. Select Start > All Programs > Xilinx ISE Design Suite 14.1 > EDK > Xilinx Software Development Kit to launch SDK.

4-1-2. In the Workspace Launcher dialog box, browse to the C:\training\advEmbSysDsgn\labs\workSpace directory. Click OK.

4-1-3. Close the Welcome dialog box and maximize the SDK tool as there is a lot of information to view.



4-1-4. Select File > New > Xilinx Hardware Platform Specification to begin constructing the base platform from which all the software will be developed.

Figure 1-35: Beginning the Creation of a Hardware Platform Specification

4-1-5. Enter zynq_generic_design_hw in the Project Name field. In the Target Hardware Specification field, browse to and select the zynq_generic_design.xml file in the C:\training\advEmbSysDsgn\support\zynq_generic_design_hw directory. Click Open. Click Finish.

Figure 1-36: Entering Information to Create a New Hardware Project

4-2. Create a board support package based on the hardware description exported from the PlanAhead tool.

4-2-1. Select File > New > Xilinx Board Support Package.



This will create a set of software functions and constants that will accelerate your software development.

Figure 1-37: Creating a Board Support Package

4-2-2. In the New Board Support Package Project dialog box, enter zynq_generic_design_bsp in the Project name field.

Figure 1-38: Creating a New Xilinx Board Support Package Project


The options for the Board Support Package Settings will appear.

4-2-4. Click OK to accept the default settings.



4-3. This concludes the prerequisite work before creating the application. Now you will create a new project and add the existing source code.

4-3-1. Click File > New > Xilinx C Project

Figure 1-39: Creating a C Application Project

4-3-2. Select Empty Application from the Select Project Template field and name the project hw_exerciser. Click Next.

Figure 1-40: Creating the Peripheral Tests Project



4-3-3. Select Target an existing Board Support Package, select zynq_generic_design_bsp, and click Finish.

Figure 1-41: Associating an Existing BSP to the New Application

4-3-4. Expand hw_exerciser > src. Right-click hw_exerciser > src and select Import.

Figure 1-42: Selecting the Location to Import the Source File From



4-3-5. Expand the General entry and select File System. Click Next

Figure 1-43: Importing Files into the Project

4-3-6. Click Browse and browse to the C:\training\advEmbSysDsgn\support\hw_exerciser directory and click OK.

4-3-7. From the right-hand panel, select the following files:

o hw_exerciser_main.c

o gpio_header.h

o xgpio_tapp_example.c

o lscript.ld


4-3-9. Click Yes to All if asked to overwrite the linker script.

This will load the C source file into the project and will automatically compile it.

4-4. All the software support is in place and you have now imported a design. Configure the hardware to run the software.

4-4-1. Select Xilinx Tools > Program FPGA to configure the PL.

This is done first because the design implements many of the peripherals in hardware.

4-4-2. Ensure that the bitstream points to the C:\training\advEmbSysDsgn\support\zynq_generic_design_hw\zynq_generic_design_top.bit file.



If not, browse to this file.

4-4-3. Click Program.

4-5. Because the software will be displaying data via the serial port, you will need to configure the Terminal tab.

4-5-1. Select the Terminal tab at the bottom of the GUI.

4-5-2. Click the Connect icon ( ) to open the Terminal Settings dialog box.

4-5-3. Configure the settings as shown in the following figure.

Figure 1-44: Terminal Settings

Note: The COM port setting is specific to the computer being used and may need to be different than shown. Your instructor will provide you with the proper port number.

4-5-4. Click OK.

4-6. It is finally time to run the software.

4-6-1. In the Project Explorer tab, right-click hw_exerciser and select Run As > Launch on Hardware.

4-6-2. Acknowledge any dialog boxes that may appear.



4-6-3. Return to the Terminal window to see the messages emanating from the board.

Notice the blinking LEDs on the FMC-CE card. The final stage of the test is to gently press the buttons and note the message that appears in the Terminal window. When 10 presses have been recorded, the application stops.

4-6-4. Click the Run icon ( ) to to re-run the application.

Conclusion

This lab walked you through the basics of building a complete embedded system including both hardware and software. First, you configured the PS and added PL peripherals using XPS. You then added additional logic in the PL and connected it to the PS in the PlanAhead software. Finally, you built and downloaded the bitstream and software to the device and watched the software produce output on the serial port, LED, and inputs from the buttons.



Answers

1. Expand the Rotary_LCD_TOP entry. Why is there a question mark ( ) next to system_i?

The question mark indicates that the tools do not have a file to map to this component. This should not be a huge surprise as none of the files that were imported during the creation of this project were embedded projects. You will create this embedded component in the next step.

2. What is included in the default configuration for the 7z020?

The default configuration includes:

DDR3 configuration

Clock generation for the peripherals

A collection of activated peripherals located in the IOP

This can be quite a time saver—you are basically starting from a working configured system and will now make changes to the system to customize it to your needs.

3. How can you tell if the components are connected?

Look at the AXI column in the Bus Interfaces tab. At this point in the lab, it should look like this:

Figure 1-45: Bus Interfaces View of Attached AXI Connections

Note that the axi_interconnect_1 is tied to the green shaded area, but none of the other components are. This is one way of seeing that the other components are not connected.

Figure 1-46: Bus Interface View Prior to Connecting the Components



Another way is to look at the bus name associated with the component. If it is blank, then there is no connection.

Figure 1-47: Bus Name Associated with the Component

However, there are more connections than between the peripheral and the processor. A number of these signals must be interfaced to the outside world—how will the signals from the rotary switch be received? What about the LCD and LED components?

4. If you were building your own board, how might you implement the GPIOs?

There are four 32-bit GPIOs built into the IOP block. These can be directly connected to the LCD, LED, and rotary switch using a single 32-bit GPIO, or multiple GPIOs. Two of the four GPIOs connect via the MIO and must share the 53 dedicated IOP pins with other peripherals in the IOP. The remaining two GPIOs can be routed through the EMIO to any other available pin in the package.

5. What do you notice about the zynq_generic_system.ucf file?

The constraints for the PS that were generated by the XPS tool are absent. Because these pins have a fixed usage, they do not need to be defined in the UCF. The only pin definitions in this UCF correspond to the peripherals in the PL.

Lab Workbook Lab2: Debugging Using the ChipScope Pro Analyzer


Lab 2: Debugging Using the ChipScope Pro Analyzer

Cortex-A9 Processor and Zynq EPP ZC702 Board

Introduction

It is every designer's dream to have his or her project work the first time "run" is pressed. The sad truth is that this is rarely the case.

Anyone who has worked on a mixed hardware/software design knows that it is a deep seated tradition for software designers to blame the hardware designers (and vice versa) when the system does not work as expected.

The SDK tool suite contains a powerful software debugger: the Gnu Debugger (GDB) utility. While this is more than adequate to debug any purely software-related issues, it is insufficient to determine if the issue is in hardware. Even certain types of software, particularly those that access peripherals, have to make the assumption that the hardware is working as expected.

The ChipScope™ Pro tool provides a means to determine what the issue is. This powerful tool resides in the programmable logic (PL) portion of the design and can be configured with several types of modes that can monitor various signals. While the full power of this tool is covered in the Debugging Techniques Using the ChipScope Pro Tools course, in this lab you will be introduced to an EDK specific core: the AXI Monitor.

This AXI Monitor core "snaps" onto any of the AXI connections in the PL and will graphically display waveforms based on when it is told to trigger. Triggering can—and is most useful when—a given pattern is matched.

The most simple form of triggering is when the pattern is a single value (such as a single signal such as an enable) or a collection of signals (such as the data or address fields). Triggers can also be set to activate when a range of values is specified for a collection of signals, such as "trigger when an address between 0x0003_0000 and 0x0003_ffff is observed".

Triggering can become quite sophisticated, such as "the third time an address in a a given range is seen, then trigger on an enable signal". These complexities are out of the scope of this lab and can be found in the Debugging Techniques Using the ChipScope Pro Tools course.

A typical use case is to connect the AXI Monitor module to the AXI port of interest. If there are other modules of interests, an integrated logic analyzer (ILA) is employed (as in this lab) where the output of a GPIO peripheral will be monitored.

An integrated controller (ICON) is required to manage the AXI Monitor and ILA cores and run the communications with the user PC.

Figure 2-1: Block Diagram of Typical CSP Usage in EDK

The peripheral that will be monitored in this lab is an 8-bit GPIO device that drives a bank of LEDs. The design used for this lab contains a number of peripherals of which not all will be exercised or monitored in this lab.

Lab2: Debugging Using the ChipScope Pro Analyzer Lab Workbook


You will be provided with the completed design and you will add the necessary three ChipScope Pro tool cores: the ICON, an ILA to monitor the output of the GPIO, and an AXI Monitor to observe the transactions on the AXI.

You will use the ChipScope Pro Analyzer tool to observe the resulting waveforms.

Objectives

At completing this lab, you will be able to:

Insert and connect the ICON, ILA, and AXI Monitor ChipScope Pro tool cores

Configure the triggering mechanism in the ChipScope Pro Analyzer tool

Procedure


This lab comprises three primary steps: You will open the existing project, insert the ChipScope Pro tool cores, and, finally, monitor the running design.


General Flow



Opening the Existing Project Step 1

1-1. Open the provided design and access the embedded system.

1-1-1. Select Start > All Programs > Xilinx ISE Design Suite 14.1 > PlanAhead > PlanAhead (32) for 32-bit systems or PlanAhead for 64-bit systems to launch the PlanAhead software.

1-1-2. Click Open Project.

Figure 2-2: Opening an Existing PlanAhead Tool Project

1-1-3. Browse to the C:\training\advEmbSysDsgn\labs\dbgCSP directory. Select dbg_dsgn.ppr and click OK.

Figure 2-3: Locating the PlanAhead Tool Project

The project opens in a moment or two.

1-1-4. Expand all of the sources and constraints and examine the hierarchy.

1-1-5. Right-click system_i - zynq_generic_design and select Open File.



Alternatively, you can double-click system_i - zynq_generic_design.

Figure 2-4: Opening the Embedded Design

Inserting the ChipScope Pro Tool Cores Step 2

All the work in this step will be done from within the XPS tool.

2-1. The intention is to monitor both the output of the GPIO peripheral that drives the LEDs and to monitor the transactions on the AXI connection. Because both cores require an ICON core to connect them to the ChipScope Pro Analyzer tool running on the PC, begin by adding the ICON core.

Note that this step will add the ICON to the design, but it will not be connected to the other ChipScope Pro tool components until after the other components are added to the design.

2-1-1. Select the IP Catalog tab and expand the Debug entry.

Figure 2-5: Locating the Debug Cores in the IP Catalog

2-1-2. Double-click Chipscope Integrated Controller. Click Yes to add the core to the design.

The XPS Core Config - chipscope_icon_0 dialog box opens.



2-1-3. Change the number of control ports to 2.

Figure 2-6: Configuring the ICON Core for Two Control Ports

2-1-4. Click OK to accept the changes.

2-2. Next, you will add the Integrated Logic Analyzer core to monitor the 8 bits of the GPIO_LED_8bits peripheral. The 14.1 release of the tools has a small error in it which will require you to manually modify the MHS file.

2-2-1. In the IP Catalog, double-click Chipscope Integrated Logic Analyzer (ILA) entry. Click Yes to add it to the design.

2-2-2. Change the name of the instance to GPIO_LED_8bit_monitor.

This will serve to distinguish it from other ChipScope Pro tool cores that may be added in the future.



Note that the Width of ILA Data Input Signal option is grayed out and set to 32 bits wide. This will later cause a problem when you attempt to connect it to the 8-bit bus on the output of the GPIO_LED_8bits peripheral. You will correct this after completing the GUI. Normally, you would set this to 8 here.

Figure 2-7: Non-Adjustable Data Width Option

2-2-3. Expand the Trigger Unit region and, for Trigger Unit 0, select basic with edges for the Match Type.

This will enable you to trigger on a rising or falling edge.

Figure 2-8: Setting the ILA Match Type for Trigger 0

2-2-4. Click OK to close the configuration dialog box.



2-2-5. Select the Project tab and double-click zynq_generic_design.mhs to open it.

Figure 2-9: Opening the MHS File from the XPS Tool

2-2-6. Locate the instance for this ILA.

Because it was entered most recently, it will likely be at or near the bottom of the MHS file.

2-2-7. Add the following lines of text after the other parameters defined here.

The code to add is shown on lines 194 and 195.

Recall that the width of the ILA Data Input Signal option was set to 32 bits and grayed out when the core was created (that is, it was not editable). You will fix that here in the MHS file.

Figure 2-10: Manually Adding Capabilities to the ILA Core

2-2-8. Select File > Save to save the MHS file. Click Reload to reload the MHS.

Now the ILA must be connected to the ICON component so that it can communicate with the ChipScope Pro Analyzer tool.

2-2-9. In the System Assembly View tab, select the Ports tab and expand the GPIO_LED_8bit_monitor peripheral.

2-2-10. Click in the Connected Port column, CHIPSCOPE_ILA_CONTROL row and select chipscope_icon_0 from the "source device" drop-down list (on the left) and control0 from the "source signal" drop-down list (on the right). Click anywhere outside the drop-down list area to close.



Note that you may need to scroll down to find the ICON peripheral.

Figure 2-11: Connecting GPIO_LED_8bit_monitor to the ICON

2-2-11. Click in the Connected Port column, CLK row and select processing_system7_0 from the "source device" drop-down list and FCLK_CLK0 from the "source signal" drop-down list. Click anywhere outside the drop-down list area to close.

This will connect the 50-MHz clock from the processing system (PS) to the peripheral. The 50-MHz clock is used for all of the peripherals in this system.

2-2-12. Click in the Connected Port column, DATA row and select the GPIO_LED_8bits peripheral from the source device column and GPIO_IO_O from the source signal column. Click anywhere outside the drop-down list area to close.

2-2-13. Repeat the previous step for the TRIG0 row.

Your device should now appear as in the following figure.

Figure 2-12: Final Connections for GPIO_LED_8bit_monitor

2-3. Finally, you will add the AXI Monitor core to the design. This core requires two types of connections - first, it needs to be connected to the AXI that needs to be monitored (done on the Bus Interfaces tab), then it needs to be connected to the ICON component.

2-3-1. Select the IP Catalog tab and expand Debug.

2-3-2. Add the peripheral by double-clicking the Chipscope AXI Monitor entry. Click Yes to confirm addition of this component to the design.

2-3-3. For basic monitoring, the default values are acceptable. Click OK to complete configuration of this component.

2-3-4. In the Systems Assembly View tab, select the Bus Interfaces tab.

2-3-5. Expand chipscope_axi_monitor_0.



2-3-6. Connect the AXI Monitor core to the AXI component by clicking the bus name (initially shown as "No Connection") and selecting processing_system7_0.M_AXI_GP0 from the drop-down list.

In truth, there is really only one AXI "bus" in this design and any of the choices would be valid.

Figure 2-13: Connecting the AXI Monitor Peripheral to the AXI

2-3-7. Select the Ports tab to continue making connections.

2-3-8. Expand the chipscope_axi_monitor_0 peripheral port list.

2-3-9. Click in the Connected Ports column next to CHIPSCOPE_ICON_CONTROL and select chipscope_icon_0 from the source device column (you may need to scroll down), and control1 from the source signal column. Click anywhere outside the pull-down menu to close.

Figure 2-14: Final Port Connections for the chipscope_axi_monitor_0 Peripheral

2-4. [Optional] Run a design rule check.

2-4-1. Select Project > Design Rule Check.

2-4-2. Check the messages in the Console window.

2-5. Exit XPS and return to the PlanAhead tool to complete the modification task.

2-5-1. In XPS, select File > Exit.

2-5-2. Click Yes.



2-6. Now that the cores have been inserted into the design and you have returned to the PlanAhead tool, you would normally run implementation and bitstream generation. Because time is limited, this step will be skipped. The completed files (bit and xml) have been generated for you. From this point forward, you will treat this design from a software flow.

2-6-1. In the PlanAhead tool, select File > Exit.

2-6-2. Click OK to exit.

Monitoring the Running Design Step 3

At this point all the hardware has been completed and the hardware development tools closed.

3-1. Create a hardware description platform from the hardware files found in the support directory. This step is often performed by exporting the hardware from the PlanAhead tool; however, because you did not implement the design in the previous step, the hardware files must be provided for you, which places the onus on you to build the hardware description platform.

3-1-1. Select Start > All Programs > Xilinx ISE Design Suite 14.1 > EDK > Xilinx Software Development Kit to launch SDK.

3-1-2. In the Workspace Launcher dialog box, browse to the C:\training\advEmbSysDsgn\labs\workSpace directory. Click OK.

3-1-3. Close the Welcome dialog box and maximize the SDK tool as there is a lot of information to view.

3-1-4. Select File > New > Xilinx Hardware Platform Specification to begin constructing the base platform from which all the software will be developed.

Figure 2-15: Beginning the Creation of a Hardware Platform Specification



3-1-5. Enter Zynq_generic_design_hw in the Project Name field. In the Target Hardware Specification field, browse to and select the zynq_generic_design.xml file in the C:\training\advEmbSysDsgn\support\hw directory. Click Open. Click Finish.

Figure 2-16: Entering Information to Create a New Hardware Project

3-1-6. Select File > New > Xilinx Board Support Package to create a basic board support package (BSP) for this hardware.

Figure 2-17: Creating a Board Support Package



3-1-7. Enter Zynq_generic_design_bsp into the Project name field. Leave the other options at their defaults. Click Finish.

Figure 2-18: Creating a New Xilinx Board Support Package Project

The details of how the BSP will be built appears in the next window.

3-1-8. Because you only need a basic system, click OK to accept the default settings and create the BSP.

3-1-9. Wait until you see 'Finished building libraries' in the Console window

3-2. This concludes all the background software preparation. You will now import an existing design that will increment the LEDs in a simple binary count fashion.

3-2-1. Select File > New > Xilinx C Project to create a new C project.

3-2-2. In the Select Project Template box, select Empty Application.

3-2-3. In the Project Name field, enter Zynq_simple_binary_count and click Next.

3-2-4. Select Target an Existing Board Support Package. Select Zynq_generic_design_bsp.


3-2-6. Expand Zynq_simple_binary_count and right-click src.



3-2-7. Select Import. Expand General and double-click File System. Click OK.

3-2-8. Browse to the C:\training\advEmbSysDsgn\support\csp_exerciser directory. Click OK.

3-2-9. Click Select All.

3-2-10. Click Finish. Click Yes to All to overwrite.

The files will be added to the project and automatically compiled.

3-3. The software tasks have now been completed. You will now set up all the support programs and modes to prepare for monitoring the hardware.

3-3-1. Select Xilinx Tools > Program FPGA.

Figure 2-19: Prepare to Program the PL

This step is performed because many of the peripherals reside in the programmable logic (PL), and the PL must be configured before any software can be run.

3-3-2. Click Browse. Browse to the C:\training\advEmbSysDsgn\support\hw directory and select Rotary_LCD_TOP.bit. Click Open.

3-3-3. Click Program to program the device.

Next, a serial port monitor needs to be configured to receive the text output from the hardware.



3-3-4. Select the Terminal tab and click the icon.

Figure 2-20: Terminal Tab and Connect Icon

3-3-5. Because the terminal has not been configured, the connection icon first brings up the Terminal Settings dialog box.

3-3-6. Select Serial as the Connection Type and set the baud rate to 115,200 and the data bits to 8.

Your instructor will indicate which COM port to select.

Figure 2-21: Terminal Settings

3-3-7. Click OK.

Finally, the application must be launched.



3-3-8. In the Project Explorer tab, right-click the Zynq_simple_binary_count software application and select Run As > Run Configurations.

Figure 2-22: Selecting Run Configurations

3-3-9. Double-click Xilinx C/C++ ELF to create the default Run configuration for this application.

Figure 2-23: Creating the Run Application for a Xilinx C/C++ ELF File

3-3-10. Click Run to accept the default settings and launch the application. Click OK to accept any dialog boxes that may appear.

3-3-11. Once the application begins, switch back to the Terminal tab to monitor the serial output of the device.



3-4. The software will continue to run the application in an infinite loop. You will now launch the ChipScope Pro Analyzer tool and monitor both the LEDs (the ones arranged in a linear fashion) and the AXI port.

3-4-1. Open the PlanAhead tool. Select Open Recent Project and select dbg_dsng.prr.

3-4-2. In the Flow Navigator, under Program and Debug, click ChipScope Analyzer.

This will launch the monitoring and display tool for the ChipScope Pro tool cores that have been added to the design.

3-4-3. When the ChipScope Pro Analyzer tool opens, click the icon to establish a connection between the software and the board.

The Analyzer tool will look at the JTAG connection and identify all the devices present.

Figure 2-24: Devices Present in the ZC702 JTAG Chain

3-4-4. Click OK.

When the various cores were generated, a profile was created so that the signal names would be properly labeled.

3-4-5. Select File > Import to import these signal descriptions.

3-4-6. Click Select New File. Browse to the C:\training\advEmbSysDsgn\support directory.



3-4-7. Select chipscope_axi_monitor_0.cdc and click Open.

Figure 2-25: Importing an Existing CDC File

3-4-8. Click OK to import the file. Click OK to accept any dialog boxes that may appear.

3-4-9. In the Project window, double-click the Trigger Setup entry. Also in the Project window, double-click the Waveform entry.

This will open the Trigger Setup window, where individual signals or combinations of signals can be selected to cause a trigger event, and the Waveform window, which displays the captured data after a trigger occurs.

Figure 2-26: Opening the Trigger Setup and Waveform Views



3-5. All that remains now is to configure the trigger and acquire data. Because you know the location of the GPIO_LED_8bits device, you will need to trigger on the write address. But when is the write address valid? For this you will need to access the write address control signals and condition the trigger on the write address valid signal. Follow the steps below to properly configure the triggering mechanism.

3-5-1. Maximize the Trigger Window and locate the MON_AXI_AWADDR (write address) signals.

Figure 2-27: Maximizing the Trigger Setup Window

The display defaults to binary, which is difficult to deal with when you have wide address paths.

3-5-2. Click in the Radix column in the MON_AXI_AWADDR row and select Hex to change the display radix to hexadecimal.

Figure 2-28: Selecting the Hexadecimal Radix for Trigger Setup

You can easily find the base address of the GPIO_LED_8bit peripheral by looking the xparameters.h file (for software engineers) and/or the MHS file or the Address tab in XPS (for hardware engineers) . This value is given as 0x4130_0000.

3-5-3. Enter the upper 16 bits of this address into MON_AXI_AWADDR and leave the lower 16 bits as Xs to trigger on any access to this 64K range. Just click in the Value field and enter the pattern to be matched. Press Enter to commit the value.

Figure 2-29: Setting the Match Pattern for the Write Address

The MON_AXI_AWADDR needs to be conditioned by the write address valid signal.

3-5-4. Expand M3:MON_AXI_AWADDRCONTROL to find this signal and set M_AXI_GP0/MON_AXI_AWVALID to 1.

Figure 2-30: Setting the Write Address Valid Trigger



Both the M2 match unit (which monitors the address) and the M3 match unit (which monitors the address valid) must both be satisfied if you are to collect legitimate data.

3-5-5. Click the Trigger Condition Equation box.

Figure 2-31: Opening the Trigger Condition Equation Dialog Box

3-5-6. Click the M0 box to deselect it. For both M2 and M3, select the Enable column check boxes.

The resulting equation is shown in the figure below.

Figure 2-32: Setting the Trigger Condition Equation to M2 && M3

3-5-7. Click OK.

The Analyzer tool also enables you to see events before the trigger and/or after the trigger occurs. This is done by setting the Position field. If the number is small, then few samples will be preserved prior to the trigger. If the number is large, then few samples will be captured after the occurrence of the trigger.

3-5-8. Enter 511 in the Position to field.



This means that in the buffer size of 1024 (as it was configured in hardware), 512 will be captured before the trigger occurs and 511 after the trigger occurs.

Figure 2-33: Setting the Trigger Position in the Capture Buffer

Finally, the core can be armed.

3-5-9. Click the Arm Core icon ( ).

When the trigger is matched, the sample buffer will be automatically uploaded to the Analyzer program and displayed in the Waveform window. Because the software should be running, the buffer will fill almost immediately.

3-5-10. Minimize the Trigger window. Click the Waveform member in the Project Window to see the resulting waveform.

3-5-11. Locate the MON_AXI_AWADDR, MON_AXI_WVALID, MON_AXI_WREADY, and MON_AXI_WDATA signals. Click and drag the signal names so that they are adjacent to one another (see the figure below).

3-5-12. Zoom in so that the width of the MON_AXI_WREADY signal is seen.

Figure 2-34: Sample Waveform

Note the numbers at the top of the Waveform display. These are the sample numbers relative to the triggering sample. A negative number indicates that that sample was taken prior to the trigger. Recall that this core is being driven by the 50-MHz clock from the PS; therefore, each sample time is 20 ns. From this, you can determine the time relationship to any transition.

3-5-13. Try rearming the core and capturing another signal.



Conclusion

The ChipScope Pro tool provides a powerful view into the bridge between hardware and software. Using the techniques shown in this lab, you can quickly isolate problems and determine if your focus should be on the software or the hardware.

Lab Workbook Lab3: Extending Memory Space with Block RAM


Lab 3: Extending Memory Space with Block RAM


Introduction

This lab guides you through the process of extending memory space in a Zynq™ EPP-based platform using the block RAM available in the programmable logic section of the chip.

Objectives


Add block RAM and connect to the processing system’s AXI master port in XPS

Execute the software application via block RAM

Procedure


This lab comprises five primary steps: You will first create a PlanAhead™ tool project; extend with block RAM in XPS; generate the bitstream in the PlanAhead software; create an SDK project; and, finally, verify the operation in hardware.


General Flow for this Lab

Lab3: Extending Memory Space with Block RAM Lab Workbook




1-1-1. Select Start > All Programs > Xilinx Design Tools > ISE Design Suite 14.1 > PlanAhead > PlanAhead (32) for 32-bit systems or PlanAhead for 64-bit systems to launch the PlanAhead software.




1-1-3. In the Project name field, enter extend_bram, and for the Project location field, browse to the C:\training\advEmbSysDsgn\labs\extendBRAM\ZC702\Zynq directory. Be sure to deselect the Create Project Subdirectory option. Click Next.




1-1-4. Make sure that the RTL Project option is selected and click Next.


1-1-5. In the Add Sources dialog box, select VHDL from the Target Language drop-down list.

Figure 3-4: Selecting VHDL as the Target Language



1-1-6. Click Next until you reach the Default Part dialog box.



The PlanAhead software GUI is launched.

1-2. Create a new embedded type source file. Configure the IOP to use only the UART 1 peripheral.

1-2-1. In the Flow Navigator, click Add Sources ( ).

The Add Sources wizard will be launched.

1-2-2. Select Add or Create Embedded Sources from the list of source types and click Next.

1-2-3. Click Create Sub-Design.



1-2-4. In the Module name field, enter system. Click OK.



Xilinx Platform Studio will be launched with a blank project.

1-2-6. Click Yes to add a Processing System7 instance to the system.

Figure 3-7: Adding a Processing System Instance

The Zynq tab will be displayed in the System Assembly View (SAV).

The Zynq Processing System Configuration tab provides a graphical means for selecting an initial PS configuration, including peripherals and routing choices as well as selecting physical I/O standards, configuring the PS DDR controller, and setting clocking parameters.



1-2-7. Click the Import Zynq Configurations icon ( ) to import a default set of configuration settings for the ZC702 evaluation board and enable its supported I/O peripherals.


1-2-8. Click ZC702 Development Board Template in the System Template tab and observe the summary of the selected configuration.

Figure 3-9: Selecting a Configuration Template

1-2-9. Click OK to select the default configuration template.

1-2-10. Click Yes to update the MHS file with the information being imported from this existing configuration.



This will configure the peripherals that are supported by the chosen board (ZC702) and create the required system files and settings.

Figure 3-10: Updating the MHS File

The IOPs that are configured (enabled) are displayed in different colors.

Because you do not need all the peripherals, you will deselect the unused peripherals.

1-2-11. Click the I/O Peripherals block to open the Zynq PS MIO Configuration table.

1-2-12. Deselect all the peripherals except UART 1 and click Close.

Figure 3-11: Zynq EPP PS MIO Configurations

1-3. Add GPIO and configure it to be of 8 bits wide.

1-3-1. Select the IP Catalog tab in the left window and expand General Purpose IO to view the available cores under the corresponding entries.



1-3-2. Double-click the AXI General Purpose IO core (version 1.01.b) in the IP Catalog and click Yes to add this IP to the design.

Figure 3-12: Adding the AXI GPIO IP

1-3-3. Expand the Channel 1 field, change the GPIO Data Channel Width from 32 to 8, and click OK twice to add one instance of GPIO of width 8, which will be used to drive the board LEDs and connect to the processing system.

Figure 3-13: Configuring the 8-bit LED GPIO Controller

The instance will be added to the programmable logic.




1-3-5. Change the name of the added GPIO instance to LED_8Bits.

Figure 3-14: LED_*Bits Connected to interconnect_1

1-3-6. Expand the instance and notice that it is connected to axi_interconnect_1.

1-3-7. Select the Ports tab.

1-3-8. Expand the LED_8Bits instance. Observe that the S_AXI_ACLK port under (BUS_IF) S_AXI is connected to processing_system7_0::FCLK_CLK0.

1-3-9. Expand the (IO_IF) gpio_0 of the LED_8Bits instance. Right-click the GPIO_IO port and select No Connection.

1-3-10. Right-click the GPIO_IO_O port and select Make External.

1-3-11. Expand the axi_interconnect_1 instance and observe that the INTERCONNECT_ACLK port is connected to processing_system7_0::FCLK_CLK0.

1-3-12. Similarly, observe that the INTERCONNECT_ARESETN port is connected to processing_system7_0::FCLK_RESET0_N.

1-3-13. Expand the (BUS_IF) M_AXI_GP0 port of the processing_system7_0 instance and observe that the M_AXI_GP0_ACLK port is connected to processing_system7_0::FCLK_CLK0.



Extending with Block RAM Step 2

2-1. Add an AXI BRAM Controller instance of 64KB size using the AXI PS Master 1 interface.

2-1-1. Select the IP Catalog tab in the left window and expand Memory and Memory Controller to view the available cores under the corresponding entries.

2-1-2. Double-click the AXI BRAM Controller core (version 1.03.a) in the IP Catalog and click Yes to add this IP to the design.

Figure 3-15: IP Catalog: AXI BRAM Controller

The XPS Core Config dialog box opens.

2-1-3. Expand the AXI field.



Note that by default, AXI4 is selected as the AXI4 protocol. The other possible protocol that can be selected is AXI4Lite.

Figure 3-16: AXI Block RAM Controller Configuration

2-1-4. Click OK to use the default settings.

2-1-5. Click OK to add and connect the instance to the processing system.


Figure 3-17: AXI_BRAM and AXI_BRAM_CONTROLLER Added

Notice that along with axi_bram_ctrl_0, axi_bram is also added and connected to the controller. axi_interconnect_2 is added and connected to the second M_AXI (M_AXI_GP1) interconnect of the processing system.



2-1-7. Select the Addresses tab and notice that the block RAM size is 64KB and is assigned 0x81210000 as the starting address.

This is because M_AXI_GP1 is required to map to 0x80000000 (refer to the Zynq EPP User Guide).

2-1-8. Select the Ports tab and notice that the clock and reset ports of axi_interconnect_2 and clock port of axi_bram_ctrl_0 (BUS_IF) S_AXI_ACLK are connected to processing_system7_0_FCLK_CLK0 and processing_system7_0_FCLK_RESET0_N ports.

Because you want to run the block RAM at a higher speed and LED_8Bits at a slower speed, you need to connect the clock and reset ports of axi_interconnect_2 and clock port of axi_bram_ctrl_0 to FCLK_CLK1 and FCLK_RESET1_N ports.

2-1-9. Connect the INTERCONNECT_ACLK port of the axi_interconnect_2 instance to processing_system7_0::FCLK_CLK1.

Figure 3-18: Connecting the AXI Interconnect Clock

Make sure to right click and enable Net column to view in the Ports tab.

2-1-10. Similarly, connect the S_AXI_ACLK port of the axi_bram_ctrl_0 instance to processing_system7_0::FCLK_CLK1.

2-1-11. Connect the INTERCONNECT_ARESETN port of the axi_interconnect_2 instance to processing_system7_0::FCLK_RESET1_N.

2-1-12. Expand the (BUS_IF) M_AXI_GP1 port of the processing_system7_0 instance and connect the M_AXI_GP1_ACLK port to processing_system7_0::FCLK_CLK1.

Figure 3-19: Selecting processing_system7_0 and FCLK_CLK1 for M_AXI_GP1_ACLK



At this stage the connections should look like the figure below.

Figure 3-20: AXI Block RAM Controller Added

2-1-13. Select the Zynq tab and notice that the new interconnect, M_AXI_GP1 is highlighted.

Figure 3-21: M_AXI_GP1 Interconnect



2-2. Configure the FCLK_CLK1 port of the processing system to run at 100 MHz.

2-2-1. In the Zynq tab of the SAV, click the Clock Generation block of the processing system.

2-2-2. Expand PL Fabric Clocks.

2-2-3. Change the clock frequency of the FCLK_CLK1 port to 100 MHz by typing in the Requested Frequency (MHz) column corresponding to the port.

Figure 3-22: Changing the Clock Frequency

2-2-4. Click Validate Clocks to ensure that the clocks are valid.

2-2-5. Click OK.

2-2-6. Select the Graphical Design View tab and zoom in to the bottom area to view the added block RAM controller. Verify the clock and reset connections made in the above steps.



That is, verify that FCLK_CLK1 (100 MHz) is connected to the block RAM controller and FCLK_CLK0 (50 MHz) is connected to LED_8Bits.

Figure 3-23: Added Block RAM Controller and Block RAM




Generating the Bitstream in the PlanAhead Software Step 3

3-1. Add the UCF file.

3-1-1. In the Flow Navigator of the PlanAhead software, click Add Sources.

3-1-2. Select Add or Create Constraints from the list of sources type and click Next.

3-1-3. In the Add Constraint Files dialog box, click Add Files.

3-1-4. Browse to C:\training\advEmbSysDsgn\support directory and select ExtendBRAM.ucf. Click OK.

Figure 3-24: Adding the UCF




3-2. Generate the bitstream.

3-2-1. In the Flow Navigator of the PlanAhead software, click Project Settings and make sure that VHDL is used as the language.

Figure 3-25: Setting the Preferred Language Option

3-2-2. Click OK.

3-2-3. In the Flow Navigator, click Synthesis Settings and select XST Defaults as the strategy.

3-2-4. Similarly, click Implementation Settings and make sure that ISE Defaults is used as the strategy.



3-2-5. In the Sources tab, expand Design Sources and select system. Right-click system and select Create Top HDL.

Figure 3-26: Creating the Top-Level HDL

A system_stub.vhd file will be created and added to the project, which automatically instantiates system.xmp in its hierarchy.

3-2-6. In the Flow Navigator, click Run Implementation under Implementation to run the synthesis and implementation processes.

3-2-7. Click OK to run the needed processes.

This will take few minutes.

3-2-8. Once the implementation completes, click Cancel in the Implementation Completed dialog box.

3-2-9. Make sure that the Timing Score is 0 (select the Design Runs tab at the bottom and view the Timing Score under the Implementation section of Project Summary pane).

If the Timing Score is not 0, then you will need to re-implement the design after making necessary changes to the design (e.g., lower the clock speed, constraining failing paths etc).

Before you re-implement, you will have to reset the runs (by selecting synth_1 in the Design Runs tab, right-clicking, and selecting Reset Runs) and remove system.ngc from the Sources tab (by selecting system_i instance, right-clicking, and selecting Reset…, followed by selecting All in the dialog box, and clicking OK).

3-2-10. In the Flow Navigator, click Generate Bitstream under Program and Debug to start the bitstream generation.

A system_stub.bit file will be generated in the C:\training\advEmbSysDsgn\labs\extendBRAM\ZC702\Zynq\extend_bram.runs\impl_1 directory.



Creating an SDK Software Project Step 4

4-1. Launch SDK and create a First Stage Boot Loader (FSBL).

4-1-1. In the PlanAhead software, select File > Export > Export Hardware to export the hardware.

4-1-2. In the Export to: field, select Choose Location and browse to the C:\training\advEmbSysDsgn\workSpace directory. Select all the options and click OK.

Figure 3-27: Exporting the Processor Hardware and Launching SDK

4-1-3. Click OK.

A system_hw_platform project will be created in the C:\training\advEmbSysDsgn\workSpace directory and SDK will be launched.

4-1-4. In SDK, select File > New > Xilinx C Project.

4-1-5. Select the Zynq FSBL project template and click Finish.

This will create a First Stage Bootloader application that will be downloaded first before the user application is downloaded.

4-2. Create software projects that display 'Hello World', executing from DDR and block RAM memories.

4-2-1. Select File > New > Xilinx C Project.

4-2-2. Select the Hello World in the Select Project Template window and click Next.

This will create a hello_world_0 application targeting DDR3 memory. You will download the application to see that it works from the DDR3 memory.





4-2-5. Select Hello World project template, change the application name to hello_world_bram, and click Next.

4-2-6. Change the board support package project name to hello_world_bsp_bram. Click Finish.

This will create a hello_world_bram application targeting DDR3 memory. You will change the linker script to target it to be downloaded into the added block RAM, generate the application, and finally download the application to see that it works from the block RAM memory.

4-2-7. In the Project Explorer tab, right-click hello_world_bram and select Generate Linker Script.

4-2-8. Select axi_bram_ctrl_0_S_AXI_BASEADDR as the memory area used from the Code section drop-down list.

Figure 3-28: Generating the Linker Script

4-2-9. Click Generate to generate the linker script.

4-2-10. Click Yes to overwrite the linker script.

The program will be compiled again.

4-3. Create a software project that tests the LEDs.


4-3-2. Click Finish with the default settings (with a Standalone operating system).



The Software Platform Settings dialog box opens, showing the OS and libraries selections.


You want to create a standalone_bsp_0 software platform project without requiring any additional libraries support.

The library generator will run in the background and will create the xparameters.h file in the C:\training\advEmbSysDsgn\workSpace\standalone_bsp_0\ps7_cortexa9_0\include directory.


4-3-5. Select the Empty Application project template and enter led_test as the project name. Click Next.

4-3-6. Select the Target an existing Board Support Package option with standalone_bsp_0 selected and click Finish.

The led_test project will be created in the Project Explorer tab of SDK.

4-3-7. In the Project Explorer tab, right-click led_test and select Import.

4-3-8. Select General > File System and click Next.

4-3-9. Browse to the C:\training\advEmbSysDsgn\support directory and select the led_test.c file to import.


This will generate the led_test.elf file.

4-3-11. Double-click the led_test.c source file to open it. Examine the program.

This program gets a handle to the GPIO device by using XGpio_Initialize function (on line 17) and then uses it to communicate to the IP on line 25 by using the XGpio_DiscreteWrite function call. The for loop iterates between 0 and 255, outputting the binary pattern on line 25. The inner for loop is a software delay loop so that user can visualize the pattern on the board when it is running. The two for loops are nested in a non-terminating while loop.



Verifying Operation in Hardware Step 5

5-1. Connect the ZC702 board to your machine. Program the device with the system.bit file using the Program FPGA tool in SDK.

5-1-1. Connect the ZC702 board to your machine.

5-1-2. Power ON the ZC702 board.

5-1-3. In SDK, select Xilinx Tools > Program FPGA.

The Program FPGA dialog box box opens.

5-1-4. Make sure that the bitstream path is pointing to C:\training\advEmbSysDsgn\workSpace\system_hw_platform\system.bit.

5-1-5. In the BMM File field, delete the entry.

Figure 3-29: Programming the Device

5-1-6. Click Program to download the hardware bitstream.

Note: Notice that the Done LED (DS3) on the ZC702 board goes High after the device is programmed. If not, re-program the device with system.bit.

5-2. Open a terminal in SDK to view the output of the software application. Create a Run configuration for the led_test application and run the application.

5-2-1. In SDK, set up a Terminal window and connection to the appropriate COMx port with a baud rate of 115200.

5-2-2. In the Project Explorer tab, select led_test, right-click, and select Run As > Run Configurations.



5-2-3. Double-click Xilinx C/C++ ELF to create a run configuration for led_test.

5-2-4. Make sure that in the Main tab’s C/C++ Application field, Debug\led_test.elf is displayed.

If not, click Browse and select the C:\training\advEmbSysDsgn\workSpace\led_test\Debug\led_test.elf file.

5-2-5. Make sure that the Project field displays led_test.

If not, click Browse and select the application file.

5-2-6. Make sure that the name of the configuration is led_test Debug.

5-2-7. Select the Device Initialization tab. Select Reset Entire System from the Reset Types drop-down list.

5-2-8. Click Apply and then click Run to download and run the led_test application.

5-2-9. Click OK to reset the entire system.

5-2-10. Select the Terminal1 window and view the led_test application output running the LEDs on the board.

5-3. Download the first stage bootloader, download the hello_world and hello_world_bram applications and verify functionality using the xmd console.

Because the device is programmed, you need to download and execute the first stage bootloader first.

5-3-1. Open the XMD Console window and type the following commands:

stop // to terminate the running led_test application on board and halt the processor

connect arm hw

cd C:/training/advEmbSysDsgn/workSpace/zynq_fsbl_0/Debug

dow zynq_fsbl_0.elf

con

stop

cd C:/training/advEmbSysDsgn/workSpace/hello_world_0/Debug

dow hello_world_0.elf // downloads in DDR3 memory

con // you should see Hello World in the Terminal window



stop

cd C:/training/advEmbSysDsgn/workSpace/hello_world_bram/Debug

dow hello_world_bram.elf // downloads in block RAM memory

con // you should see Hello World in the Terminal window

stop // execute this after you are satisfied with the functionality

disconnect 64

5-3-2. In SDK, select File > Exit.

5-3-3. In the PlanAhead software, select File > Exit.

Conclusion

This lab led you through adding block RAM to a processing system. You verified the functionality by creating an application, targeting to the added block RAM, and executing the application from the added block RAM.

Lab Workbook Lab4: Direct Memory Access using CDMA Controller


Lab 4: Direct Memory Access using CDMA Controller


Introduction

This lab guides you through the process of enabling a high-performance slave port of the processing system, adding an AXI central DMA controller, and performing DMA operations between various memories.

Objectives


Enable a high-performance (HP) port of the processing system

Add and connect the CDMA controller in the programmable logic

Perform DMA operation between various memories

Procedure


This lab comprises six primary steps: You will first create a PlanAhead™ tool project; add a block RAM controller; enable a high-performance port and add a CDMA controller; generate the hardware bitstream; create an SDK project; and, finally, verify operation in hardware.


General Flow for this Lab

Lab4: Direct Memory Access using CDMA Controller Lab Workbook




1-1-1. Select Start > All Programs > Xilinx Design Tools > Xilinx ISE Design Suite 14.1 > PlanAhead > PlanAhead (32) for 32-bit systems or PlanAhead for 64-bit systems in order to launch the PlanAhead software.




1-1-3. In the Project name field, enter plCDMA, and for the Project location field, browse to the C:\training\advEmbSysDsgn\labs\plCDMA\ZC702\Zynq directory. Be sure to deselect the Create Project Subdirectory option. Click Next.




1-1-4. Make sure that the RTL Project option is selected and click Next.


1-1-5. In the Add Sources dialog box, select VHDL from the Target Language drop-down list.

Figure 4-4: Selecting VHDL as the Target Language



1-1-6. Click Next until you reach the Default Part dialog box.



The PlanAhead GUI will be launched.

1-2. Create a new embedded type source file. Configure IOP to use only UART 1 peripheral.

1-2-1. In the Flow Navigator, click Add Sources ( ).

The Add Sources wizard will be launched.

1-2-2. Select Add or Create Embedded Sources from the list of source types and click Next.

1-2-3. Click Create Sub-Design.



1-2-4. In the Module name field, enter system. Click OK.



Xilinx Platform Studio will be launched with a blank project.

1-2-6. Click Yes to add a Processing System7 instance to the system.

Figure 4-7: Adding a Processing System Instance

The Zynq tab will be displayed in the System Assembly View (SAV).

The Zynq Processing System Configuration tab provides a graphical means for selecting an initial PS configuration, including peripherals and routing choices as well as selecting physical I/O standards, configuring the PS DDR controller, and setting clocking parameters.



1-2-7. Click the Import Zynq Configurations icon ( ) to import a default set of configuration settings for the ZC702 evaluation board and enable its supported I/O peripherals.


1-2-8. Click ZC702 Development Board Template in the System Template tab and observe the summary of the selected configuration.

Figure 4-9: Selecting a Configuration Template

1-2-9. Click OK to select the default configuration template.

1-2-10. Click Yes to update the MHS file.

This will configure the peripherals that are supported by the chosen board (ZC702) and create the required system files and settings.

The IOPs that are configured (enabled) are displayed in different colors.

Because you do not need all the peripherals, you will deselect the unused peripherals.

1-2-11. Click the I/O Peripherals block to open the Zynq PS MIO Configuration table.



1-2-12. Deselect all the peripherals except UART 1 and click Close.

Figure 4-10: Zynq EPP PS MIO Configurations

Adding an AXI BRAM Controller Step 2

2-1. Add AXI BRAM Controller instance of 64KB size using the AXI PS Master 0 interface so that it can be accessed from the processor.


Figure 4-11: IP Catalog: AXI BRAM Controller



2-1-3. Expand the AXI field.



Note that by default, AXI4 is selected as the AXI4 protocol and the data width selected is 32 bits. The other possible protocol that can be selected is AXI4Lite.

Figure 4-12: XPS Core Configuration: AXI BRAM Controller

2-1-4. Click OK to use the default settings.




Enabling an HP Port and Adding a CDMA Controller Step 3

3-1. Enable a high-performance port of the processing system and add a CDMA Controller instance.

3-1-1. Using Windows Explorer, copy the pcores directory from the C:\training\advEmbSysDsgn\support directory and paste it under the C:\training\ZC702\labs\plCDMA\ZC702\Zynq\plCDMA.src\sources_1\edk\system directory.

3-1-2. Click Yes to overwrite the pcores directory.

Note: This step is needed only on a Windows machine (not on a Linux machine) as there is a bug in the Tcl script file of the AXI CDMA pcore that will cause the PlatGen process to fail. Copying this directory will make the PlatGen process successful.

3-1-3. Select Project > Rescan User Repositories.

Note that the DMA and Timer catalog entry appears under the Project Local PCores folder in the IP Catalog.

3-1-4. Select the Zynq tab in System Assembly View.

3-1-5. Click the High Performance AXI 32b/64b Slave Ports block.

Figure 4-13: Selecting the High Performance Port Block in the Zynq Tab

3-1-6. Expand the High Performance Slave AXI Interfaces field (if necessary) and select the Enable S_AXI_HP0 interface option because you will connect the central DMA controller to this port.



Note that C_S_AXI_HP0_DATA_WIDTH is set to 64.

Figure 4-14: Enabling the HP Interface

3-1-7. Click OK.

You will see left-most arrow going from the High Performance AXI 32b/64b Slave Ports block to the Programmable Logic to Memory Interconnect block is highlighted.

Figure 4-15: High-Performance Port Connection



3-1-8. Select the IP Catalog tab in the left window and expand the DMA and Timer folder under Project Local Pcores to view the available cores.

Figure 4-16: IP Catalog: AXI Central DMA

3-1-9. Double-click the AXI Central DMA core (version 3.03.a) in the IP Catalog and click Yes to add this IP to the design.





Figure 4-17: AXI Block RAM Controller and CDMA Controller Added

Notice that axi_cdma controller is added and connected to axi_interconnect_3, which in turn masters on to the HP0 port. It is also connected to axi_interconnect_2 with the axi4lite protocol.

3-2. Add another AXI Block RAM Controller instance so that it can be accessed from the central DMA controller.






3-2-3. Expand the AXI field and select the Slave Single Port BRAM option to access only one port of the already added block RAM using this controller.

3-2-4. Make sure that the Slave AXI Supports Narrow Bursts option is selected because the CDMA is master on this controller.

Figure 4-18: Enabling the AXI Slave Single Port Block RAM

3-2-5. Click OK to use the settings.



3-2-6. Select the User will make necessary connections and settings option and click OK to add and connect the instance to the processing system.

Figure 4-19: Instantiate and Connect IP Dialog Box

Note that the block RAM controller has been added without an associated memory block and that S_AXI is not connected.

Figure 4-20: AXI Block RAM Controller: No Connection

You will make the CDMA as a master to this controller and connect Port A to the Port B of the block RAM instance.

3-3. Connect the axi_bram_ctrl_0_bram_block_1 instance’s PortA to axi_bram_ctrl_0 and PortB to axi_bram_ctrl_1.

3-3-1. Click the Bus Name column of the S_AXI interface of the axi_bram_ctrl_1 instance.

The axi_bram_ctrl_1.S_AXI Connection Dialog dialog box opens.



3-3-2. Select the axi_interconnect_3 entry in the left pane and select axi_cdma_0.M_AXI in the right pane.

Figure 4-21: Connecting the AXI Block RAM Controller to AXI CDMA

3-3-3. Click OK.

3-3-4. Double-click the axi_bram_ctrl_0 instance and expand the AXI field.

3-3-5. Select the Slave Single Port BRAM option. Click OK.



You will connect this controller’s PortA to the PortA of the block RAM.

Figure 4-22: AXI BRAM Controller 0: Selecting Slave Single Port BRAM

3-3-6. Click in the Bus Name column of PORTB of the axi_bram_ctrl_0_bram_block_1 instance and connect it to axi_bram_ctrl_1_BRAM_PORTA.

Figure 4-23: Connecting the AXI BRAM Port B to the AXI BRAM Controller Port A



At this time, the Bus Interfaces tab should look like the following figure.

Figure 4-24: Bus Interfaces Tab after the AXI Block RAM and CDMA Controller Connections

3-4. Configure to use a faster clock domain (100 MHz).

3-4-1. In the Zynq tab of the SAV, click the Clock Generation block of the processing system.

3-4-2. Expand PL Fabric Clocks.

3-4-3. Change the clock frequency of the FCLK_CLK0 port to 100 MHz by typing in the Requested Frequency column corresponding to the port.

Figure 4-25: Configuring the PL Fabric Clock

3-4-4. Click Validate Clocks to ensure that the clocks are valid.

3-4-5. Click OK.

3-4-6. Select the Ports tab.



3-4-7. Expand (BUS_IF) S_AXI of the axi_bram_ctrl_1 and connect S_AXI_CLK to processing_system7_0::FCLK_CLK0.

Figure 4-26: AXI BRAM Controller 1 to FCLK_CLK0

3-5. Connect the CDMA interrupt request to the interrupt controller port of the PS.

3-5-1. Click the cdma_introut port under the Connected Port column of axi_cdma_0.

The Interrupt Connection Dialog dialog bx opens.

3-5-2. Select the axi_cdma_0 entry in the left pane [Unconnected Interrupt(s)] and click the right arrow to assign it to the interrupt controller of the PS.

Figure 4-27: Connecting the Interrupt Port

3-5-3. Click OK.

3-6. Assign an address of 0x40020000 to axi_bram_ctrl_1 with an address space of 64Kb.

3-6-1. Select the Addresses tab.

Note that the axi_bram_ctrl_1 instance has its size and address range as unassigned.



3-6-2. Under Umapped Addresses, select 64Kb as the size and change the start address to 0x40020000.

Figure 4-28: Assign an Address to AXI BRAM Controller 1

This address is hard coded into the cdma_test.c program. If you happen to use some other address, then make sure to change the address on line 16 of the cdma_test.c program.


Generating the Bitstream in the PlanAhead Software Step 4

4-1. Run implementation and generate the bitstream in the PlanAhead software.

4-1-1. In the Flow Navigator of the PlanAhead software, click Project Settings and make sure that VHDL is used as the language.

4-1-2. In the Flow Navigator, click Synthesis Settings and make sure that XST Defaults is used as the strategy.

4-1-3. Similarly, click Implementation Settings and make sure that ISE Defaults is used as the strategy.

4-1-4. Click OK.

4-1-5. In the Sources tab, expand Design Sources select system.

4-1-6. Right-click on system under Sources pane, and select Create Top HDL.

Figure 4-29: Creating the Top-Level HDL



A system_stub.vhd file will created and added to the project, which automatically instantiates system.xmp in its hierarchy.

4-1-7. In the Flow Navigator, click Run Implementation under Implementation to run the synthesis and implementation processes.

4-1-8. Click OK to run the needed processes.

4-1-9. Once the implementation completes, click Cancel in the Implementation Completed dialog box.

4-1-10. Make sure that the Timing Score is 0.

Figure 4-30: Checking the Timing Score

If the Timing Score is not 0, then you will need to re-implement the design after making necessary changes to the design (e.g., lower the clock speed, constraining failing paths etc).

Before you re-implement, you will have to reset the runs (by selecting synth_1 in the Design Runs tab, right-clicking, and selecting Reset Runs) and remove system.ngc from the Sources tab (by selecting system_i instance, right-clicking, and selecting Reset…, followed by selecting All in the dialog box, and clicking OK).

4-1-11. In the Flow Navigator, click Generate Bitstream under Program and Debug to start the bitstream generation.

A system_stub.bit file will be generated in the C:\training\ZC702\labs\plCDMA\ZC702\Zynq\plCDMA.runs\impl_1 directory.



Creating an SDK Software Project Step 5

5-1. Launch SDK and create a First Stage Bootloader (FSBL).

5-1-1. In the PlanAhead software, select File > Export > Export Hardware to export the hardware.

5-1-2. Select the Open SDK option and make sure that all the other options are selected.

5-1-3. Click OK to export the hardware and open SDK.

A system_hw_platform project will be created in the C:\training\advEmbSysDsgn\labs\plCDMA\ZC702\Zynq\plCDMA.sdk\SDK\SDK_Export directory.

5-1-4. In SDK, select File > New > Xilinx C Project.

5-1-5. Select the Zynq FSBL project template and click Finish.

Figure 4-31: Creating the FSBL Project

This will create a First Stage Bootloader application that will be downloaded first before the user application is downloaded.



5-2. Create a software project that tests the DMA transfer.


5-2-2. Click Finish with the default settings (with a Standalone operating system).

The Software Platform Settings dialog box opens, showing the OS and libraries selections.

5-2-3. Click OK to accept the default settings

You want to create a standalone_bsp_0 software platform project without any additional libraries support.

The library generator will run in the background and will create the xparameters.h file in the C:\training\advEmbSysDsgn\labs\plCDMA\ZC702\Zynq\plCDMA.sdk\SDK\SDK_Export\ standalone_bsp_0\ps7_cortexa9_0\include directory.


5-2-5. Select the Empty Application project template and enter cdma_test as the project name. Click Next.

Figure 4-32: Creating the CDMA Test Application



5-2-6. Select the Target an existing Board Support Package option with standalone_bsp_0 selected and click Finish.

Figure 4-33: Targeting an Existing BSP

5-2-7. In the Project Explorer tab, expand cdma_test, right-click src folder, and select Import.

Figure 4-34: Importing the CDMA Test Application

5-2-8. Select General > File System and click Next.



5-2-9. Browse to the C:\training\advEmbSysDsgn\support directory and select the cdma_test.c file to import.

Figure 4-35: Selecting the cdma_test.c File


The cdma_test application contains the source files needed to build the object executable.elf file. The project will automatically build without errors. A successful build is indicated in the Console tab when the sizes of all of the program segments are displayed before the build complete message.

5-2-11. Double-click the cdma_test.c source file to open it. Examine the program.

Besides opening source files, the software developer can use this view to open other resource files and set tool options for software applications and software platforms.

The program performs transfer between various memories using processor and DMA modes (poll and interrupt mode) enabling measurement of performance improvement. The main routine, which starts at line 148, first initializes various devices, disables data caches, and then presents a menu. Via the menu, the user can select the size of the transfer (in number of words) and various memory combinations. The program then transfers the desired block of memory using a processor, then using DMA controller in poll mode, and, finally, using it in the interrupt-driven mode. It also calculates performance improvement over the processor by moving the block. The program iterates the data movement until the Exit selection (by typing 5).



Verifying Operation in Hardware Step 6

6-1. Connect the ZC702 board to your machine. Program the device with the system.bit file using the Program FPGA tool in SDK.

6-1-1. Connect the ZC702 board to your machine.

6-1-2. Power ON the ZC702 board.

6-1-3. In SDK, select Xilinx Tools > Program FPGA.

The Program FPGA dialog box box opens.

6-1-4. Make sure that the bitstream path is pointing to C:\training\advEmbSysDsgn\labs\plCDMA\ZC702\Zynq\plCDMA.sdk\SDK\SDK_Export\ system_hw_platform\system.bit.

6-1-5. In the BMM field, delete the entry of the BMM File field, and click Program to download the hardware bitstream.

Figure 4-36: Programming the Device

6-1-6. Click Program to download the hardware bitstream.

6-2. Open a terminal in SDK to view the output of the software application. Create a Run configuration for the cdma_test application and run the application

6-2-1. In SDK, set up a Terminal window and connection to the appropriate COMx port and baud rate of 115200.

6-2-2. In the Project Explorer tab, select cdma_test, right-click, and select Run As > Run Configurations.



6-2-3. Double-click Xilinx C/C++ ELF to create a run configuration for cdma_test.

6-2-4. Make sure that in the Main tab’s C/C++ Application field, Debug\cdma_test.elf is displayed

If not, click Browse and select the ELF file.

6-2-5. Make sure that Project field displays cdma_test.

If not, click Browse and select the application file.

6-2-6. Make sure that the Name of the configuration is cdma_test Debug.

Figure 4-37: Run Configuration Dialog Box:Main Tab

6-2-7. Click Run to download and run the cdma_test application.

6-2-8. Click OK to reset the entire system.

The application will be downloaded in DDR3 memory. The processing system will be initialized and the application will be run.



6-2-9. Select the Terminal tab and follow the menu. Try transferring DMA between various memories.

Figure 4-38: Console Output (1)

Figure 4-39: Console Output (2)



6-2-10. When done, in SDK, select File > Exit.

6-2-11. In the PlanAhead software, select File > Exit.

Conclusion

This lab led you through adding a CDMA controller to a processing system so that you can perform DMA transfers between various memories. You verified the functionality by creating an application and executing from the application from DDR3 memory.

advanced features and techniques of embedded systems

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