advanced computer structure laboratorymedinamo/acsl/acsl_recitations.pdf · using hardware...

Advanced Computer

Structure Laboratory

Moti Medina

[email protected]

Recitation Nr.1

copyrights © Moti Medina

Presentation’s copyrights © Moti Medina

Today:

General Information (Syllabus).

Important points.

Schedule.

Chapter 1: Orientation

Hand Out #1: “The Decoder”


Course Websites

http://www.eng.tau.ac.il/~marko Course’s Staff.

Course’s Topics.

Logistics and Rules.

Requirements (reports).

Course Material (Lab notes, Handouts etc.).

www.eng.tau.ac.il/~medinamo Recitations (Presentations etc.).

Announcements.

Grades.

http://www.eng.tau.ac.il/~marko

http://www.eng.tau.ac.il/~medinamo


Course’s Staff

Prof. Guy Even.

T.A: Moti Medina.

Lab Engineer: Marko Markov.

For Office hours and additional information see the Course’s Websites.


Course’s Goal

Designing and implementing digital circuits on a FPGA.

Main Topics Using Hardware designing Software tools: Digital

Circuits design, Logical Simulation, placement and

wiring, Electrical Simulation.

Using FPGA.

Designing a RISC processor (Control and Data path)

and implementing it as part of the RESA computer.

FPGA – Field Programmable Gate Array.

RISC – Reduced Instruction Set Computer


Requirements

Grading Due to Requirement

40%

Submitting via

mail before

the relevant

Lab

Pre-Lab

Reports

60%

Submitting via

mail on the

next Lab

Post-Lab

Reports


Schedule Week

Nr. Recitation Subject

Handout

#

1 Orientation 1

1 The RESA's Bus 2

2 Bus Slave (with I/O control logic( 3

3 Monitor slave 4

4 Monitor slave Cont. 4

5 Read/Write machine 5

6 Load/Store machine 6

7 Test Load/Store machine 6


Schedule

8 DLX – Design and Test 7

9 DLX – Implementation + timing 7

10 DLX – Implementation + testing 7

11 DLX - Program 7

Recommended reading material: the matching chapter in

the Lab notes.

On the green labeled weeks, a recitation will be held.

Pay attention to the remarks on your returned Handout

2’s reports.


דגשים

משמעויות בדיקה " )היכרות"הן מטלות 2ו 1מטלות

(.בעיקר

התרגולים מורכבים מ:

הסבר קצר של נקודות עיקריות של הפרק המתאים

.בחוברת הקורס

נקודות מנחות לפתרון המטלה.

מה בסוף?


דגשים

יש להגיש בזמןחות מסכמים "חות מכינים ודו"דו

נא ליצור קשר איתי ( מילואים)בעיות אישיות )במעבדה

.על איחורים שאינם מאושרים יורדו נקודות, (מראש


דגשים

ח מסכם יש להגיש "דו(מודפס לPDF ) עם הפרוט :הבא

(.ז"ללא ת, ללא שמות)צוות ' מס

ח המסכם"נושא הדו.

כללי –חות "הגשת דו:

2-3)לכל תשובה יש להוסיף הוכחת נכונות קצרה (.שורה)ומוטיבציה ( שורות

נא להוסיף הערות ל: Test Vectors, Wave Forms, Computer Printouts


דגשים

נוכחות.

שעת קבלה.

שלשות/בזוגותעבודה.

יש לגבות את –ית יינתן חשבון בשרת /לכל סטודנט

אין לסמוך , בסיום העבודה במעבדהעבודותיכם בשרת

.על העותקים השמורים במחשבים האישיים

שבועיים לאחר סוף יש לסיים את כל מטלות הקורס עד

.הסימסטר



The RESA Computer

Will be elaborated later.



Work flow

Design entry (Think before, Top Down approach, Remarks are

Important, Use the Software to draw your design)

Simulation (Find mistakes in connections, wrong polarities,

Names etc.)

Implementation )‘.bit’ file (configuration file) )

Running your design on the RESA

Technical Assistance will be given in the Lab


Please read before the next recitation

Chapter 2: The RESA’S Bus


Hand Out #1: The Decoder

Presentation.

Advanced Computer


Moti Medina

[email protected]

Recitation Nr.2



Today:

Chapter 2: The RESA’s Busses

Handout #2 presentation



A bus protocol

A Synchronous protocol – There is a global clock signal, which is present in all the devices that are connected to the bus.

In each transaction, one word of data is transmitted.

There are two types of transactions: Read & Write.

The party, which initiates the transaction is called the master and the party which is asked to respond is called the slave.

The purpose of a protocol is to coordinate the usage of the common resource, namely, the bus.



Serial bus

The PC bus controller is implemented on the PC.

Information/Control signals are transferred serially between the PC to the XSA board.

Parallel bus Connects two masters

(PC, Student’s designed master) and two slaves (main memory, monitor slave with logic analyzer)

Pay Attention: The Bus protocols are

synchronous, Each with his own

Clock signal.


The Parallel bus protocol- A transaction

The Master signals the Bus Controller

that the Bus is used by him.

The Beginning of the transaction. The Master Signals the

Slave (actually to all the slaves, why?) – that in the next

c.c, information will be transmitted along the bus by him.

A Read Transaction

Protocol Signals


The Parallel bus protocol- A read transaction

The Master’s information is ready

to be sampled by the Slave.

The required information is ready

and being sampled by the Master.

The Slave signals that the

required information will be

transmitted on the next c.c.


that the bus is not used by him.


The Parallel bus protocol- A write transaction

The Master’s information is ready

to be sampled by the Slave.

The Slave is sampling the information

that was sent by the Master.

The Slave signals that the

information will be read and

processed on the next c.c.


that the bus is not used by him.


Hand Out #2

The BUS_INF module should be designed according to the specifications.

Some of the Modules are already given.

You may observe the implementation of those modules.

You should sample all Control Signals.

Follow the Handout instructions/Questions with great care.


Block Diagram – General

This block

is given to you

This block

is given to you


Block Diagram - BUS_INF

Additional Logic,

FF’s

R1

R2

Communication between the CPU and the bus interface is implemented by 3 registers.

Given Control Signals

wr_req,rd_req

busy

ACK_N

Required Control Signals

in_init

DONE

AS_N

WR_N

CE0,CE1,CE2

DE1,DE2

Missing Blocks

Contention solving modules (using buffers).

Additional Logic, FF’s. R0 in_init in_init

busy busy


Wave forms – CPU ‘read’ instruction


Wave forms – CPU ‘write’ instruction


Wave forms – CPU ‘read after write’ instruction



Chapter 3: A Simple Slave Device

Advanced Computer


Moti Medina

[email protected]

Recitation Nr.3



Today:

Chapter 3: A Simple Slave Device



Chapter 3: A Simple Slave Device–3.1 The RESA

A Spartan II XC2S50 FPGA (50000 gates) [There is a newer one in the Lab!]

A CPLD XC9572XL (serves as an interface between the PC parallel port and the FPGA)

A 8MB Memory (read-write memory, serves as the main memory of the Application)

Flash Memory.

Programmable oscillator.

LED indicator.

VGA & PS2 ports.


3.2 The RESA Monitor Program

The RESA program is

a suite of programs,

which is used to

diagnose and setup

the RESA.

Configure RESA

FPGA

1. Use XLINIX to

make a ‘.bit’ file.

2. Use RESA to

program the

FPGA using the

‘.bit’ file.

‘.bit’



Access RESA Address

space:

Reading results

(outputs) from memory

(i.e. after an application

completes its

execution).

Writing (loading

programs, i.e. DLX’s

assembly programs) to

the memory.



Run and Debug.

Upload programs.

Set single-step mode

or continuous mode.

‘.cod’



Use monitor program

menus:

Initiates read/write

transactions to single

RAM and Slave

addresses.

“built-in monitoring”

(We will see it later).



Edit your programs.

Compile your programs.

Use a DLX simulator to

test your program.

Generate Graphs.

Hardware interface

“Black Box”

Was partially

implemented on

Handout #2.

‘.txt’ ‘.cod’



Please read the Monitor Program user’s guide before the next lab

meeting.


3.3 The I/O control logic

A bus interface

module (just like in HandOut

#2, serves one master and one

Slave).

We will use it from

now on. I/O Control Logic

clk

Step_en

Reset

ACK_N

DO[31:0]

Card_sel

AI[9:0]

WR_IN_N

SACK_N

SDO[31:0]

AS_N

MAO[31:0]

MDO[31:0]

WR_OUT_N

IN_INIT

From outputs

of Bus Master

From outputs

of Bus Slave

To Inputs

of Bus Master

To shared inputs

of Bus master and slave

To inputs

of Bus Slave


3.3.2 Input Signals of the bus master device

clk

STEP_EN - This signal is a

one clock cycle pulse that

causes the master (e.g. a

CPU) to perform one step.

RESET

I/O Control Logic

clk

Step_en

Reset

ACK_N

DO[31:0]

Card_sel

AI[9:0]

WR_IN_N

SACK_N

SDO[31:0]

AS_N

MAO[31:0]

MDO[31:0]

WR_OUT_N

IN_INIT

From outputs

of Bus Master

From outputs

of Bus Slave

To Inputs

of Bus Master

To shared inputs


To inputs

of Bus Slave

ACK_N - The acknowledge

signal is sent by the slave in a

bus transaction. This signal is

active low.

DO[31:0] - This is the data-out

bus for the master and slave

devices.


3.3.2 Output Signals of the bus master device

AS_N - This is the address-strobe signal. This signal is active low.

MAO[31:0] - This is the address-out bus (no sharing with the slave device).

MDO[31:0] - This is the data-out bus (no sharing with the slave device).

I/O Control Logic

clk

Step_en

Reset

ACK_N

DO[31:0]

Card_sel

AI[9:0]

WR_IN_N

SACK_N

SDO[31:0]

AS_N

MAO[31:0]

MDO[31:0]

WR_OUT_N

IN_INIT

From outputs

of Bus Master

From outputs

of Bus Slave

To Inputs

of Bus Master

To shared inputs


To inputs

of Bus Slave

WR_OUT_N - This is the R/W signal

generated by the bus master

(high→read transaction, low→write

transaction).

IN_INIT - low→master is active and

the bus is inaccessible. high→master

is idle and the bus can be accessed by

the Monitor program (i.e. RESA).


3.3.3 Input Signals of the bus slave device

clk

DO[31:O] - This is the data-out bus (shared with the bus master device).

AI[9:0] - This is the address-in bus of the slave device. There can be 1024 different addresses for devices in the FPGA.

I/O Control Logic

clk

Step_en

Reset

ACK_N

DO[31:0]

Card_sel

AI[9:0]

WR_IN_N

SACK_N

SDO[31:0]

AS_N

MAO[31:0]

MDO[31:0]

WR_OUT_N

IN_INIT

From outputs

of Bus Master

From outputs

of Bus Slave

To Inputs

of Bus Master

To shared inputs


To inputs

of Bus Slave

CARD_SEL - Indicates that the

slave of the current transaction is on

the FPGA. (computed by the I/O C.L

from the 22 upper bits of the

Address in the RESA bus).

WR_IN_N - This is the R/W signal

(high→read transaction, low→write

transaction).


3.3.3 Output Signals of the bus slave device

SDO[31:0] - Data-out bus.

SACK_N - Ack signal

generated by the slave device

that marks SDO validity. This

signal is active low.

I/O Control Logic

clk

Step_en

Reset

ACK_N

DO[31:0]

Card_sel

AI[9:0]

WR_IN_N

SACK_N

SDO[31:0]

AS_N

MAO[31:0]

MDO[31:0]

WR_OUT_N

IN_INIT

From outputs

of Bus Master

From outputs

of Bus Slave

To Inputs

of Bus Master

To shared inputs


To inputs

of Bus Slave


Hand Out #3 Design according to the specifications:

Group’s ID Component.

Monitor Slave (the slave device).

Run simulations in order to check your Design (The Monitor Slave).

Connect all the designed components in such a way that the following values could be read: reg_out[31:0]

step_num[4:0]

state[3:0]

reg_write[4:0]

ID[7:0]

Implement your Design and produce a bit file.

Create Configuration Labels.

Run your implementation on the RESA\ computer by using the RESA\ monitor program.


Hand Out #3

Print Design

Simulations

Label report

Data snapshots of three sequential steps Make sure that:

step_num[4:0] advances.

reg_write[4:0] advances.

ID[7:0] is read.

Pay attention to Handout#2’s remarks.

The simulations that you submit should be consistent with the protocol that we have learnt.


Slave Address Partitioning

Every Page has 32 words of 32 bit.

WA[4:0] – chooses a word out of 32 words in

a page.

PA[1:0] - chooses a page (1 out of 4).

BA[2:0] – chooses a block (1 out of 8).

AI[9:0] WA[4:0] PA[1:0] BA[2:0]

0 4 5 6 7 9 : : :


Block Diagram

I/O control logic

input & outputs

Given

To

you AI[?:?]

“Private wires”

(master, slave)


Block Diagram - The Master


Building Blocks

AI[9:0]

state[3:0]

Reg_write[3:0]

Schematic

Schematic

Vhdl Code

This component is a

degenerated Master –

it doesn’t initiate

Transactions. This

component reacts to its

input signals only.

0x20

0x40 0x60

0x0

The Actual

addresses

of those

inputs. Chooses the

Data to be

outputted.

The Monitor Slave is a Slave. It

enables a read transaction from

four dedicated inputs.

The Monitor Slave implements

the Bus Protocol that we have

learnt.

Simple

concatenation.

????


Building Blocks An optional implementation :slave control

0 or more (According to

the slave)

Fill in the Logic (address dependent) Up deriv’ & inv’


Building Blocks

Wave forms



Chapter 4: Built – In Self Monitoring

Advanced Computer


Moti Medina

[email protected]

Recitation Nr.4



Today:

Chapter 4: Built-In Self Monitoring



Chapter 4: Built-In Monitoring

Our Goal is to run our application (e.g. DLX),

step by step and to monitor the values of the registers and the control signals.

In order to enable such monitoring, our Design will include additional hardware that will be responsible of reading various values from the application without changing the behavior of the application.

On the last recitation we have encountered hardware that implements the required functionality (i.e. Monitor Slave) – we will expand that hardware so it will provide us with more complicated services.


General Structure

The FPGA contains:

The Application (e.g.

the DLX processor).

The Monitor Slave.

I/O control logic.

The PC monitor

program.


Monitoring Tasks

Reminder: General DLX Control FSM. The Control of the DLX starts each

instruction execution in the fetch state.

Passes through Decode, Ex, Me, Write Back.

Returns to the fetch state.

An instruction execution is an interval of Clock Cycles between two consecutive entries to the fetch state.


Monitoring Tasks , Cont.

To be more precise,

the DLX’s control FSM

in our lab will have an

additional state – Init. /step_en


Monitoring Tasks, Cont.

We have Two Modes:

Single – Step

Each execution of an Instruction waits until an

appropriate signal arrives from the PC monitor

program.

Continuous

The execution of the next instruction is

unconditional.


Monitoring Tasks, Cont.

If the DLX is running in single-step mode, we will

be sampling only when the DLX is in Init state,

this doesn’t suffice. For example :

Monitoring the bus activity of the DLX.

Monitoring internal signals of the application over

several consecutive cycles.

Conclusion: reporting current values is not

enough for debugging a design.


The Logic Analyzer


The Logic Analyzer, Cont.

Part of the Monitor Slave that stores past

signals.

Contains a RAM in which the monitored

signals are stored – these values can be

reported later to the PC monitor program.

This implementation enables us to monitor

signals during an instruction execution.


The Logic Analyzer, Cont.

Required Functionality:

Storing the monitored signals cycle by cycle

during the execution of an instruction.

Answering bus read transactions in which

the PC monitor program asks about sampled

values (after the instruction’s execution is

completed).


32x32 RAM

Mux

2x5

Counter

5 bitStatus

Register

DIN[31:0]

clk

WE

a

b

clk

rst

DIN

STATUS

DOUT[31:0]WE

clk

ce

ce

AI[4:0]

Monitored signals

The Logic Analyzer - Structure

The 5-bit counter generates the address

into which sampled values are stored. After

an execution of an application’s instruction,

the counter is reset by L.A’s logic. The

counter’s output value equals the number of

cycles that elapsed since the beginning of

the last instruction.

Logic Analyzer

32 X 32-bit RAM that stores the sampled values from the application. In each clock cycle, up to 32 signals (i.e. bits) can be stored.


32x32 RAM

Mux

2x5

Counter

5 bitStatus

Register

DIN[31:0]

clk

WE

a

b

clk

rst

DIN

STATUS

DOUT[31:0]WE

clk

ce

ce

AI[4:0]

Monitored signals

The Logic Analyzer – Structure, Cont.

The Logic Analyzer’s RAM

is filled “row by row” with

the sampled values until

the execution of the current

instruction ends.

Logic Analyzer


The Logic Analyzer – Structure, Cont.

Status Register

Latches the value of the Logic Analyzer’s counter so that the

Monitor Slave can report the number of rows that contain

relevant data in the Logic Analyzer’s RAM.

32x32 RAM

Mux

2x5

Counter

5 bitStatus

Register

DIN[31:0]

clk

WE

a

b

clk

rst

DIN

STATUS

DOUT[31:0]WE

clk

ce

ce

AI[4:0]

Monitored signals

Logic Analyzer


Slave Address Partitioning - Reminder

Every Page has 32 words of 32 bit.

WA[4:0] – chooses a word out of 32 words in

a page.

PA[1:0] - chooses a page (1 out of 4).

BA[2:0] – chooses a block (1 out of 8).

AI[9:0] WA[4:0] PA[1:0] BA[2:0]

0 4 5 6 7 9 : : :


Hand Out #4

Design and implement over the RESA computer:

Monitor Slave (Including the Logic Analyzer)

Project’s Blocks:

I/O Logic.

The Master from Handout#3.

Monitor

The Slave from Handout#3.

ID Register from Handout#3.

Logical Analyzer.


Block Diagram

There may be additional

Input/Output Terminals

Monitor Slave


Building Blocks

Wave forms

The Information could be

read from the Monitor

Slave Only Here !

Pay attention – one c.c,

before & after.


Building Blocks

Elaborated Wave Forms


Hand Out #4

Recommended schedule:

Next week:

Designing over the Xlinix platform.

Beginning Simulations.

The week after:

Finishing simulations.

Implementing over the RESA computer.

Monitoring the application using the PC Monitor.


Hand Out #4

Attached:

Examples: L.A Control Signals (Wave Forms(


Hand Out #4 Additional Submission guidelines:

1. Submit a simulation showing: 1. Sampling process of the Logic Analyzer.

2. Reading Process from the Monitor:

1. Logic Analyzer (The values saved in 1.1)

1. L.A’s RAM.

2. L.A’s Status/ID.

2. External Inputs.

3. Control signals.



2. Using Resa, submit snapshots and graphical waveforms showing two step_en cycles:

1. Sampled signal: 1. state[3:0].

2. reg_write[4:0].

3. step_num[4:0].

4. in_init.

2. External Inputs. 1. Master’s RAM.

2. step_num[4:0].

3. LA’s status/ID.

4. New Control Signals.



3. Make sure that the sampled signals, indeed convince that your design is correct – please attach a proper documentation.



Chapter 5: A Read Machine and a Write

Machine.

Advanced Computer


Moti Medina

[email protected]

Recitation Nr.5



Today:

Chapter 5: A Read Machine and A Write

Machine



Chapter 5: A Read Machine and A Write Machine

This chapter deals with designing a bus

master that is capable of initiating bus

transactions. We consider two types of

machines: a read machine and a write

machine.

The Components that will be designed are

the basis of the final DLX RISC.


Chapter 3: Reminder

The RESA Architecture

CPU.

Memory.

Bus (up to 2 Masters & 2 Slaves).

FPGA

XSA


5.1 A Read Machine

The Read Machine is an application that

reads the contents of a memory address

AO. The address AO is initialized to 0x00.

After reading, the machine stores the

value in a register.

The Read Machine is connected as a bus

master to the I/O Control Logic.


5.1 A Read Machine – The state diagram

The machine exits the wait state when the STEP_EN signal is active.

The machine initiates a read transaction in the fetch state.

The machine waits for an ack signal during the wait4ack state.

The machine writes the fetched value in its register when entering the load state. The address AO is incremented, i.e., AO = AO+1.

The reset signal causes the machine to transition to the wait state, and AO is initialized to 0x00 - regardless of the current state of the Read machine.

/STEP_EN

STEP_EN

/ACK

ACK


5.2 A Write Machine

The Write Machine is an application that

writes your favorite constant value to a

memory address AO. The address AO is

initialized to 0x00.

The Write Machine is connected as a bus

master to the I/O Control Logic.


5.2 A Write Machine – The state diagram

The machine exits the wait state when the STEP EN signal is active.

The machine initiates a write transaction in the store state.

The machine waits for an ack signal during the wait4ack state.

In the "terminate" state, the address AO is incremented, i.e., AO = AO+1.

The reset signal causes the machine to transition to the wait state, and AO is initialized to 0x00 - regardless of the current state of the Write machine.

/STEP_EN

STEP_EN

/ACK

ACK


Hand Out #5

Attached:

Examples: Implementing State machines in

VHDL.

http://www.eng.tau.ac.il/~marko/examples/SM_R.vhd


Hand Out #5 Submission Guidelines:

First Write Machine, then Read Machine!

Post lab should be submitted in two different projects: Read Machine

Write Machine

There should be two simulations (two for each project) that show: All the control signals of the state machine.

RDO[31:0], WDO[31:0]

The Machine’s state.

A full cycle of the Machine (i.e. 1st simulation).

A Reset disrupted cycle (i.e. 2nd simulation).

RESA: In order to prove that your design (read & write machine) is

successful, show a data snapshot before and after the reading & writing activities.

To complete the proof, present an appropriate L.A wave forms.


Block Diagram

VHDL

VHDL

Additiona

l logic

16-bit counter

VHDL

Additional

inputs/outputs

Additiona

l logic

VHDL counter

(RAM Address)

16-bit counter VHDL counter

(RAM Address)


Example: SM_R.vhd(Principles)

Defining constants that represent the states in the state machine.

constant F0_STAY : std_logic_vector(3 downto 0) := "0000 ";




constant F1_UP : std_logic_vector(3 downto 0) := "0100 ";



constant F0_DOWN : std_logic_vector(3 downto 0) := "0111 ";

constant F1_DOWN : std_logic_vector(3 downto 0) ;= "1000 ";

constant F2_DOWN : std_logic_vector(3 downto 0) := "1001 ";

Defining constants that represent the inputs and outputs of the state

machine.

constant STAY : std_logic_vector(1 downto 0) := "00 ";

constant UP : std_logic_vector(1 downto 0) := "01 ";

constant DOWN : std_logic_vector(1 downto 0) := "10 ";


Example - Cont: SM_R.vhd Representing the transfer function of the state machine:

Current state.

Input

Next State.

case state is

when F0_STAY =>

if (f_in= “00”) then

state <= F0_STAY;

else

state <= F1_UP;

end if;

when F0_DOWN =>

if )f_in= “00”( then

state <= F0_STAY;

else

state <= F1_UP;

end if;


Example - Cont: SM_R.vhd

Add this line, even if you covered all the

possible cases.

when others => null;

end case;


Example - Cont: SM_R.vhd The machine outpus are a function of the machine’s state.

f_num <="00" when ((state = F0_STAY) or (state = F0_DOWN)) else

"01 " when ((state = F1_STAY) or (state = F1_DOWN) or (state = F1_UP)) else

"10 " when ((state = F2_STAY) or (state = F2_DOWN) or (state = F2_UP)) else

"11";

move <= STAY when ((state = F0_STAY) or (state = F1_STAY)

or (state = F2_STAY) or (state = F3_STAY)) else

UP when ((state = F1_UP) or (state = F2_UP) or (state = F3_UP)) else

DOWN;


Building Blocks Wave forms (Write Machine)

Single c.c Should be

implemented

One or more c.c.

No need to

sample signals

here!



Chapter 6: A Load/Store Machine.

Advanced Computer


Moti Medina

[email protected]

Recitation Nr.6



Today

Chapter 6: A Load/Store Machine



Chapter 6: A Load/Store Machine

This chapter focuses on designing

memory accesses in the DLX design.

We will consider a 2 instruction RISC,

called the Load/Store Machine.

The Load/Store Machine executes DLX

programs that consist only of simplified

load and store instructions.


RS1

RS1

6.1 Specification

The instruction set of the Load/Store Machine

consists only of load and store instructions.

Modified Load/Store Instructions:

Note that we allow the source register to be only R0.

Recall that the value stored in Register R0 is always zero.

R0


6.1 Specification

I – Format:

Load/store instructions are encoded in the I-Format.

Encoding:

IR[31:26] Instruction

100011 Load

101011 Store


6.2 Memory Accesses

the Load/Store Machine accesses

the main memory during fetch, load

and store states.

we would like to simplify the control

of the DLX and allocate only one

state for each of the actions rather

than four (e.g. Read and Write

Machine).


6.2 Memory Accesses

The way this is done is by cascading state machines.

Communication between the Load/Store Machine

and the I/O Control Logic is done via a state

machine called the Memory Access Control (MAC).

The Memory Access Control resembles the Read

and Write Machines.


6.2 Memory Accesses

Formula Functionality Signal

- Memory read - active during fetch and load states mr

- Memory write – active during the store state mw

mr + mw Either mr or mw is active req

(/ack) • req Read/Write transaction is being performed busy


Wave Forms

wait4req wait4ack next wait4req


6.3 Implementation


6.4 The GPR environment Inputs

Outputs (one is for future design)

There are two implementations

for RO (#1,#2)


6.4 The GPR environment The GPR can support one of two operations in each cycle:

Write the value of input C in register R[Cadr] if gpr_we = 1.

Read the contents of the registers with indexes Aadr and Badr. The outputs A

and B are defined by:


6.4 The GPR environment For register debugging, we

append third register D (same

functionality as A,B).

RESAb1 Monitor can read the contents of register D by

addressing it with Dadr and

reading the output R[Dadr]

using the Monitor slave.


Block Diagram

Please output the state

Load / Store Machine

Input A,B


6.5 A Simulation environment

It is not a trivial task to generate manually

the signals fed to the Load/Store Machine

by the RESA bus.

The I/O SIMUL Module encapsulates the

I/O Control Logic, the RESA bus and the

main memory.


6.6 Testing

Test by simulation the transitions of the control

of your design.

Testing Combinational Circuitry.

Testing finite state machines (e.g. Test Vectors)

“covering” all the transitions of the FSM by paths (beginning

in the initial state).

For each path, one needs to compute input values that will

cause the control to traverse the path.

check if indeed the reset signal initializes the control, and if

the step enable signal causes a a transition to the fetch state.


6.6 Testing


6.6 Testing

Testing of RTL instructions (replacing I/O

Logic with the I/O SIMUL- Simulation).

Testing executions of whole instructions

(Simulation)

Testing executions of whole instructions

(replacing I/O SIMUL with the I/O Logic,

and implementing the design)



Chapter 7: A simplified DLX

Advanced Computer


Moti Medina

[email protected]

Recitation Nr.7



Today:

Chapter 7: A Simplified DLX



Chapter 7: A Simplified DLX

In this recitation we describe a simplified

DLX-Architecture which you will be

implementing on the RESA-CPU.


7.1 General Architecture

There are only two instruction formats: I-Type and

R-Type.

The memory is word addressable which means

that only words (32 bits) can be read from and

written to the main memory. This means that

successive word addresses in memory have

successive addresses (instead of increments by 4

as in the DLX which is byte-addressable).



The architectural registers of

the simplified DLX are all 32

bits wide:

32 General Purpose Registers

(GPR): R0 to R31 (Note that R0

always holds the value 0).

Program Counter (PC).

Instruction Register (IR).

Special Registers: MAR, MDR, A,

B and C.



The main modules in the data

path of the simplified DLX are

as follows:

The GPR-File is a dual-port RAM

which supports either two reads

or one write.

The ALU supports 2's

complement integer addition,

subtraction, comparison and

bitwise logical operations.

The Shifter supports logical left

and right shifts by one position.



There are two instruction formats:

I-Type-Format

IR[31:26]holds Operation’s encoding.

Four fields



R-Type-Format IR[31:26]=06

IR[5:0]holds Operation’s encoding.

Five fields


7.1 General Architecture Instruction Set

Load/Store – instructions (I-Type)

Immediate instructions (I-Type)

Shift /Compute –Instructions (R-Type)

imm ≡ value of the immediate field in an I-Type-Instruction.

sext(imm) ≡ 2's complement sign extension of imm to 32

bits.



Test – Instructions (I-Type)

Jump – instructions (I-Type)

imm ≡ value of the immediate field in an I-Type-Instruction.

sext(imm) ≡ 2's complement sign extension of imm to 32

bits.



Miscellaneous –instructions (I-Type)

Encoding of the Instruction Set Tables 7.1 and 7.2 in the course’s lab notes

specify the binary encoding of the instructions.


7.2 Implementation Data Path

ALU environment

Shifter environment

a zero is pushed in from the right (left)

in case of a left (right) shift.

control inputs:

Shift-indicates whether a shift

should take place (otherwise the

output equals the input).

right-indicates whether the shift is a

right shift

The GPR environment

As in the Load/Store Machine


7.2 Implementation Control

Access to the memory is done via the Memory Access Control module

as described for the Load/Store Machine.


7.2 Implementation The reset signal causes a transition in the control of the DLX to init

state.


7.2 Implementation step_en – from the I/O control Logic.


7.2 Implementation busy - from the Memory Access Control.


7.2 Implementation D2..D13 - corresponds to the decoding of the instructions.


7.2 Implementation else - corresponds to an illegal instruction, namely, when all

D2..D13 are not satisfied.


7.2 Implementation bt-(branch taken) corresponds to the event that the condition of a

conditional branch is satisfied.


7.2 Implementation - Summery

c

/Init

SavePC


Hand Out #7

This Handout includes four sections.

Recommended schedule and guidelines are in the Handout.

The weight of this handout is 400 points.

Questions 2 and 4 requires the approval of the lab’s engineer (the form located in the website), please attach it to the submitted project.

Please attach to your project the timing report produced by Xlinix which verifies that your design meets the timing requirements.

The Programming assignment will be published in the following weeks.


Building blocks

ALU environment Inputs: A[31:0], B[31:0], ALUF[2:0], TEST, ADD.

Outputs: ALU_OUT[31:0], NEG.

Reminder #1:

Let A[n-1:0], B[n-1:0] {0,1}n ,

Denote [·] the two’s comp’ representation,

So: [A[n-1:0]] - [B[n-1:0]] = [A[n-1:0]] + [¬B[n-1:0]] + 1

Reminder #2:

; ' ( , )n

B XOR B ADD'B


Building blocks

ALU environment – cont. Use the ADDSUB16 component in the following way:


Building blocks we suggest that you use three 16-bit adder/subtractors from the Xilinx

library (ADSU16) to build a 32-bit Conditional Sum Adder.

Reminder #3: “Digital Logic Design: a rigorous approach” By Guy Even

and Moti Medina.

Chapter 15 – Addition (15.4 Conditional Sum Adder)

Chapter 16 – Signed Addition

Reminder #4: “Computer Architecture - Complexity and Correctness” By

S.M.Müller and W.J.Paul .


Building blocks

The GPR

environment The GPR environment is

identical to that of the

Load/Store Machine.

Please implement AEQZ.

A CADR selection

mechanism should be

implemented.


Building blocks

The IR environment Inputs: IR_CE, CLK.

Outputs: IR_OUT[31:0], sext(imm).

Sext(imm[15:0]) = imm[15]16 imm[15:0]

The PC environment 32 bit Register with a RESET port.


Building blocks

The MMU Input: AO[31:0].

Output: 08•AO[23:0]

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