advanced co a

7/24/2019 Advanced Co A

http://slidepdf.com/reader/full/advanced-co-a 1/3

Yogesh Chauhan ( 12-1-5-004)

Write a case study on:

i) TI ASC:

The Advanced Scientifc Computer, or ASC, was a supercomputer architecture

designed by Texas Instruments (TI) between 1!! and 1"#$ %ey to the ASC&s

design was a sing'e highspeed shared memory, which was accessed by a number

o processors and channe' contro''ers, in a ashion simi'ar to Seymour Cray&s

groundbrea*ing C+C !!$ -hereas the !! eatured ten sma''er computers

eeding a sing'e math unit (A./), in the ASC this was simp'ifed into a sing'e 0core

processor eeding the A./$ The core A./2C3/ was one o the frst to inc'ude

dedicated vector processing instructions, with the abi'ity to send the same

instruction to a'' our cores$

4emory was accessed so'e'y under the contro' o the memory contro' unit, or 4C/$

The 4C/ was a twoway, 56!bit2channe' para''e' networ* that cou'd support up to

eight independent processors, with a ninth channe' or accessing 7main memory7

(or 7extended memory7 as they reerred to it)$ The 4C/ a'so acted as a cache

contro''er, o8ering high speed access on the eight processor ports to a

semiconductorbased memory, and hand'ing a'' communications to the 5bit

address space in main memory$ The 4C/ was designed to operate asynchronous'y,

a''owing it to wor* at a variety o speeds and sca'e across a number o perormance

points$ 9or instance, main memory cou'd be constructed out o s'ower but 'ess

expensive core memory, a'though this was not used in practice$ At the astest, it

cou'd sustain transer rates o 0 mi''ion #5bit words per second per port, or a

tota' transer capacity o !4words2sec$ This was we'' beyond the capabi'ities oeven the astest memories o the era$

The main A./2C3/ was extreme'y advanced or its era$ The design inc'uded our

basic cores that cou'd be combined to hand'e vector instructions$ :ach core

inc'uded a comp'ete instruction pipe'ine system that cou'd *eep up to twe've sca'ar

instructions in;ight at the same time, a''owing up to #! instructions in tota' across

the entire C3/$ 9rom one to our vector resu'ts cou'd be produced every !ns, the

basic cyc'e time (about 1! 4<=), depending on the number o execution units

provided$ Imp'ementations o this sort o para''e'2pipe'ined instruction system did

not appear on modern commodity processors unti' the 'ate 1s, and vector

instructions (now *nown as SI4+) unti' a ew years 'ater$

The processor inc'uded 0 #5bit registers, a huge number or the time, a'though

they were not genera' purpose as they are in modern designs$ Sixteen were used or

addresses, another sixteen or math, eight or index o8sets and another eight or

vector instructions$ >egisters were accessed externa''y using a >ISC'i*e 'oad2store



system, with instructions to 'oad anything rom bits to !bit (two registers) at a

time$

4ost vector machines tended to be memory'imited, that is, they cou'd process data

aster than they cou'd get it rom memory$ This remains a ma?or prob'em on modern

SI4+ designs as we'', which is why considerab'e e8ort has been put into increasingmemory throughput in modern computer designs (a'though 'arge'y unsuccessu''y)$

In the ASC this was improved somewhat with a 'oo*ahead unit that predicted

upcoming memory accesses and 'oaded them into the A./ registers invisibi'ity,

using a memory interace in the C3/ *nown as the memory bu8er unit (4@/)$

The 73eriphera' 3rocessor7 was a separate system dedicated entire'y to uic*'y

running the operating system and programs running within it, as we'' as eeding

data to the main C3/$ The 33 was bui't out o eight 7virtua' processors7, B3&s, which

were designed to hand'e instructions and basic integer math on'y$ :ach B3 inc'uded

its own program counter and registers, and the system cou'd thus run eight

programs at the same time, 'imited by memory accesses$ %eeping eight programs

running a''owed the system to shue execution o programs on the main C3/

depending on what data was avai'ab'e on the memory bus at that time, attempting

to avoid 7dead time7 when the C3/ was waiting on memory$ This techniue has a'so

made its appearance in modern C3/&s, where it is *nown as simu'taneous

mu'tithreading or, according to Inte', <yperThreading$

The 33 a'so inc'uded a set o sixtyour #5bit registers *nown as the

communications register (C>)$ The C> put the 73eriphera'7 in the 33, and was the

main storage system or state inormation between the various parts o the ASCD theC3/, B3s, and channe' contro''ers$

The ASC instruction set inc'ude a 7bitreverse7 instruction that was intended to

speed up the ca'cu'ation o ast 9ourier transorms$ @y the time the ASC was in

production better 99T a'gorithms were deve'oped that did not reuire this operation$

TI o8ered a bounty to the frst person to come up with a va'id use or the bit reverse

instruction$ The bounty was never co''ected$

ii) STA-100: The STA>1 was a vector supercomputer designed, manuactured, and mar*eted

by Contro' +ata Corporation (C+C)$ It was one o the frst machines to use a vector

processor to improve perormance on appropriate scientifc app'ications$

The name STA> was a construct o the words STrings and A>rays$ The 1 came

rom 1 mi''ion ;oating point operations per second (49.E3S), the speed at which



the machine was designed to operate$ The computer was announced very ear'y

during the 1"s and was supposed to be severa' times aster than the C+C "!,

which was then the wor'd&s astest supercomputer with a pea* perormance o #!

49.E3S$ En August 1", 1"1, C+C announced that Fenera' 4otors had p'aced the

frst commercia' order or a STA>1$

The main memory had a capacity o !6,6#! superwords (S-E>+s), which are 615

bit words$G1H The main memory was #5way inter'eaved to pipe'ine memory

accesses$ It was constructed rom core memory with an access time o 1$50 s$ The

main memory was accessed via a 615bit bus, contro''ed by the storage access

contro''er (SAC), which hand'ed reuests rom the stream unit$ The stream unit

accesses the main memory through the SAC via three 150bit data buses, two or

reads, and one or writes$ Additiona''y, there is a 150bit data bus or instruction

etch, I2E, and contro' vector access$ The stream unit serves as the contro' unit,

etching and decoding instructions, initiating memory accesses on the beha' o the

pipe'ined unctiona' units, and contro''ing instruction execution, among other tas*s$

It a'so contains two read bu8ers and one write bu8er or streaming data to the

execution units$G1H

The STA>1 has two pipe'ines where arithmetic is perormed$ The frst pipe'ine

contains a ;oating point adder and mu'tip'ier, whereas the second pipe'ine is

mu'tiunctiona', capab'e o executing a'' sca'ar instructions$ It a'so contains a

;oating point adder, mu'tip'ier, and divider$ @oth pipe'ines are !bit or ;oating

point operations and are contro''ed by microcode$ The STA>1 can sp'it its ;oating

point pipe'ines into our #5bit pipe'ines, doub'ing the pea* perormance o the

system to 1 49.E3S at the expense o ha' the precision$G1H

The STA>1 uses I2E processors to ooad I2E rom the C3/$ :ach I2E processor isa 1!bit minicomputer with its own main memory o !6,6#! words o 1! bits each,

which is imp'emented with core memory$ The I2E processors a'' share a 150bit data

bus to the SAC$

advanced co a

Documents