advance instrumentation i

Advance Instrumentation - I

IC Department 1 Prof. J. B. Vyas

Chapter-1 Operational amplifier

An operational amplifier is a basically very high gain DC amplifier that uses feedback for the control of gain, input impedance, output impedance and frequency characteristics. The operational amplifier is an extremely efficient and versatile device and is primarily used to perform various mathematical functions, such as computation and summation. The characteristics of an ideal operational amplifier are constant gain over frequency, infinite non inverting input impedance, zero output impedance, infinite common mode rejection, no DC offset and zero amplifier noise. Commercially available operational amplifiers are excellent but not ideal, so that one can expect deviation from characteristics predicted from ideal assumption.

1. The performance of real operational amplifier The actual characteristics of real Operational Amplifier are considerably more complicated. The real operational amplifier may be modeled as shown in figure1. There are two input terminals, and a single output terminal. If the output of Operational Amplifier eo is nominally positive with respect to ground, the lower input terminal is also positive and is therefore called the non inverting input. The upper input terminal input waveform is inverted with respect to ein and is therefore called inverting input. The resistance seen looking in to the amplifier between positive and negative terminal is Rd (differential input impedance). The resistance seen looking back in to the amplifier from the output terminal is Ro (open loop output impedance). A DC Input offset voltage eos, two input bias current Ip and In, a frequency dependent open loop gain of the Operational Amplifier A, a common mode input impedance Rcm, an input noise current Ina and an input noise voltage ena is also included in the model.

2. Input offset voltage and input offset current. All Operational Amplifier requires small and relatively constant (Ip and In) at each input to make transistor in active region. The average value of these current is called the input bias current IB=(IP+IN )/2. The difference of these current is called the input offset current IOFF=( IP+IN). The circuit of figure 2 shows a feedback back configuration including the main source of offset error. Rs is included to reduce the output offset voltage to zero. The low level DC input signal is converted to a square wave AC with analogue switches S1 and S2, amplified as AC by a low noise amplifier O1 at a fixed gain G= (R1+R2)/R1 and demodulated to DC by the output switches S3 and S4. The DC offset voltage of the amplifier eos1= (R1+R2)/R1 is then eliminated by the blocking capacitor CO(non polarized 4.7uF to 10uF). The offset voltage eos2 of the buffer O2 may be either negligible or turned out using as offset adjusting potentiometer. The maximum switching frequency FO is mainly depends on the settling time of the operational amplifier O1.



-

(ep-en)A

ens

Ina Ip

A

In

Ro

Ina

eo

+

Rcm

Rd

en

ep

Rc

eos

In

-

Ip

A

100K

R2

Equivalent ckt. for feedbackconfiguration

eo

+990 E

R1

e-

Rs

e+

1K

eos



sposp RIee =

21 Ree

IRe on

nn +=

( ) onp eAeeand =

( )[ ]2121

1//

1RRIRIe

RRARA

e nsposo +

++

=

( )[ ]

22

// 211

21

OFFBn

OFFBp

nsposo

IIandIIIinsertingI

RRIRIeR

RRe

=+=

++

=

++

++

+=

2121

22121

221

RRRRRsIOFFRs

RRRRIBeos

RRR

eo

21

21 RIeRR

e OFFoso

+=

Referring to the circuit, Let

1

2

3

Where A is the open loop gain of the amplifier, eos is the input offset voltage, Ip is the current flowing into positive terminal and In is the current flowing into negative terminal of opamp. Substituting the values of ep and en equation (3) we get

4

Now if A is large, then equation (4) becomes

5

We obtain

6

If Rs = R1R2/R1+R2, Then equation (6) gives out an offset error of

7

Equation (7) can be used to limit the output offset drift due to variation in bias current and input offset voltage with tempearture variation. It is interesting to note that the offset produced at the output is not dependent upon the inverting and non inverting configuration of the circuit. This means that for each configuration, the offset error referred to the input side will be different, even though overall gain may be same.

Example A type 741 operational amplifier has the following paarmeters Input offset volatge=7.5mV (max) Input offset volatge temperature sensitivity=6V/C Input offset current=300nA Input offset current temperature sensitivity=0.5nA/C Compute the DC error with the offset adjustment for the ampliifer shown in figure over the temperature 0 to 50 degreeC



21

21 RIeRR

e OFFoso

+=

Non Inverting Amplifier

RcR1

eo

+

en

R2

ep

RcmA

-

Rd

( )AeeeRe

Ree

lRe

Ree

Ie

R

npo

cm

n

d

pnn

d

po

s

sin

=

+

=

=

Solution

eo=101*50C *6V/C-100K*0.5nA*50C eo=30.3mV-2.5nV eo=27.8mV The output offset varies from 0 to 27.8mV over the temperature of 0 to 50 degree.

3. The Input impedance and there effects

The infinite input impedance and zero output impedance of the ideal amplifier are approached in the real circuit as a normally high input impedance and output impedance of few hundred ohms in magnitude. Although the real opamp ahs high input impedance, loading effect cannot be neglected. Common mode input impedance is usually high typically greater than 10Mohms. In comparison of source3 impedance, it is essentially infinite and has little effect on circuit operation. The differential input impedance however may be as low as 10K Ohms or as high as 100MOhms depending upon amplifier type. The open loop input impedance figure changes considerably when the amplifier is use with feedback connection.

4. The Input impedance of a non inverting amplifier

Consider the equivalent circuit of figure, we wish to obtain an expression for the closed loop input impedance.

8

9

10



1

222

1

21RR

esRcmR

RR

RRAIsRd

RcmesRd

esesAd

+

++++

+=

cmin RARR /)1(1 ++=

en en

R2

Rc

eoRd

Inverting Amplifier

-

ARcm

+

R1

( )

+

=

=

+

=

=

=

s

o

in

no

cmd

nonns

nss

s

sin

Aee

RR

AeeRR

e

Ree

Ree

Ree

I

Ie

R

1

//

1

21

1

From 8, 9, 10 we have

Setting R2/Rd=R2/Rcm=0 in the above equation we have for Rin

Where =R1/R1+R2 = feedback factor

5. The Input impedance of an inverting amplifier

Substituting these equations,



R1

eo

Equivalent cirucit for output impedence

+

-

A

R2

Rout

Rs(ep-en)A

Ro

12

2

)(

Re

Ree

and

Ree

ReeAe

I

nno

no

o

npoo

=

+

=

( )

+

+=

+++=

)//(//1

)//(1

21

1

2

1

2

1

cmdin

cmd

RRA

RRR

RRAR

RR

ARR

Aeoes

5. The Output impedance of an inverting and non inverting amplifier

Assume Ip and In are zero then we have



21//)1/( RRARoRout ++=

21

1

21

11

RRR

where

RRRA

eo

Io

o

+=

++

+=

( )

+

+= )//(//1

21 cmdin RRA

RRR

e+

ed/2

+

A

ecm

eoAcm

-

-

ed/2

+

Effect of common mode gain

+

-

e-

Ro is open loop impedance of opamp From these equations, we have

That is Rout is reduced. The output impedance of the circuit is function of open loop output impedance of opamp Ro, of amplification A and of resistor R1 and R2.

Example 2: A type 741 amplifier with an open loop output impedance of Ro=70 and an open loop DC gain A=2*105 is used in the circuit with R1=3K and R2=27K Hence feedback factor =0.1 The resulting impedance at zero frequency is Rout= 70/(1+2*105)//30000 = 0.0035

Example 3 : A type 741 amplifier with Rd=2M, Rcm=400M and an open loop DC gain A=2*105 is used as non inverting amplifier with R1=1K and R2=100K Thus from equation, input impedance is

Rin =363M

7. Common mode Rejection The ideal operational amplifier provides an output proportional to differential voltage applied to its input terminals and produces no output for common mode voltage (Voltage common to both of its terminal). However, in practical case, because of slightly different gains between the inverting and non inverting inputs common mode voltages are not entirely cancelled in the output.



egaincommoninopenloopga

AACMRR

CMRRe

eAe

cm

cmDo

mod==

+=

Acm

A

ed/2

ecm/CMRR

e+

-

-

ecm

-

ed/2

+

e-

+

+

Equaivalent offset voltage induced by common mode gain

eo

2

1log20)0()(

+==

cmfffCMRRfCMRR

For the circuit shown above, the output voltage is given by

eo=A(ep-en)+Acm(ep+en)/2 or eo=eDA+ecmAcm 22 Where eD is the differential voltage, ecm the common mode voltage, Acm the common mode gain and A the differential gain (or open loop gain) of the operational amplifier. from equation 22, we have

CMRR is common mode rejection ration of amplifier. The error term (A*(ecm/CMRR)) in the equation 23 can be modeled as an additional offset voltage equal to the common mode voltage divided by the CMRR.

CMRR is normally expressed in terms of dB and it is given by CMRR(dB)=20log(A/Acm). For many operational amplifier, the CMRR as a function of frequency can be approximated by

24

where fcm is the corner frequency of the CMRR and CMRR (f=0) the common mode rejection ration at f=0. In the case of operational amplifier connected in the non inverting configuration, the input common mode voltage ecm varies directly with the input signal es.



+

R2

Acm

A

-

Non-inverting amplifier with common mode error

ecm/CMRR

R1

e+

eo

es

e-

+

+=

CMRRCMRR

RR

ee so11

1

2

2

20010001log2070)1(

+== dBKHzfCMRR

This is because the feedback provides a voltage at the inverting terminal, which follows that at the non-inverting input (en-ep)

Hence, ep=es+es/CMRR and en=eo(R1/R1+R2) If the open loop gain of the operational amplifier is large, then

25

Inverting amplifier have no error due to common mode gain because the non-inverting input is grounded (ep=0) and ecm=0.

Example 4: A type 741 operational amplifier has the following specifications Common mode rejection ration (f=0)= 70dB Corner frequency of CMRR fcm = 200Hz. Determine the CMRR of the amplifier with R1=1K, and R2=100K at the operating frequency f=1KHz.

Solution: From equation (24)

Therefore CMRR=56dB from equation 25 we have eo=es(101)+((1+63)/63) eo=101.16es Hence error due to common mode gain will be 1.6mV pp for an input voltage of 100mv PP.

8. Supply voltage Rejection ration (SVRR) the output voltage of ideal operational amplifier depends only on the input voltage and is independent of power supply voltage. In real operational amplifier, the output voltage is a function of power supply voltage. The SVRR may be defined by



ply

o

e

e

ASVRR

sup

1

=

2)()(

ripplerippleo

eeASVRRe

+

=

peakVpeake ply =

= 3.02

9.05.1sup

pmVpeVe

o

o

==

5.43.010010150 6

c

DC

ffj

AA+

=

1

C

-

eo

Ro

+

Equivalent cirucit for frequency response

A

(ep-en)A

es

SVRR= Change in input offset voltage/change in power supply voltage Different manufacturer uses the different terms related to SVRR, such as the power supply rejection ration(PSRR) and power supply sensitivity(PSS). These terms are expressed either in a microvolt per volt or in dB. Let the ripple on the plus supply is going positive while the ripple on the negative side is moving negative. If the ripple on the plus and minus are unequal, ripple appears on the operational amplifier output therefore,

26

example5: A type 741 operational amplifier has a PSRR of 150V/V(max.). It is utilized as a non-inverting amplifier with a closed loop gain of Acl=100. There is a 1.5V ripple on the positive supply and a 0.9Vp-p ripple on the negative supply. Determine the ripple that appears on the amplifier output? Solution: from equation 26 we have

9. Frequency response

Open loop gain of an operational amplifier is an important factor in circuit design. It determines the accuracy of the closed loop gain frequency response, input and output impedance. An open loop gain of a single pole operational amplifier may be represented by

27



fcf

andff

AA

c

DC

1

2

tan

1

=

+

=

Where ADC is the open loop gain of the amplifier at zero frequency, fc the corner frequency (or 3 dB cut off frequency) and f the operating frequency. The equation may be expressed in rationalized form:

28

where is the phase angle. example 6: A type 741 amplifier has the following parameters: open loop gain ADC=2*105, corner frequency fc=5Hz. Compute the magnitude of gain A and phase angle at f=10KHz. Solution: from equation 28 we have A = 20 log (ADC)-10log[1+(f/fc)2] = 40dB = -89.97 The gain bandwidth product is 2*105*5Hz or 1MHz In the case of a non-inverting amplifier circuit, by utilizing equation 27, the resulting amplitude eo/es is Acl=A/(1+A) 29 Where feedback factor =R1/R1+R2, substituting of equation 27 into equation 29results in expression of closed loop gain that can be written as



eo

e+

2.7K

741

es

3K

R1

R2

27K

-

+

Rs

Non Inverting Amplifiere-

IiA

AAclo

+

++=

11)1(

1

111

1)11(1

+++

+=

DC

C

DCcl A

ffjA

A

DC

clo

C

clcl

AA

ffj

AA )11(

1

0+

++

=

Chapter-2 example 7: A type 741 amplifier has the following parameters: open loop gain ADC=2*105, corner frequency fc=5Hz. Determine the closed loop gain of the non inverting amplifier shown in figure at f=10KHz.

Solution: from equation 31 we have Aclo = 2*105/(1+0.1*2*105)= 9.9995 from equation 31 we have for closed loop gain Acl0=9.8053 = -11.3 The bandwidth of amplifier fB=100KHz In the case of a inverting amplifier circuit, by utilizing equation 27, the resulting amplitude eo/es is

32

Where feedback factor 1=R1/R2, substituting of equation 27 into equation 32results in expression of closed loop gain that can be written as

or as

33



)111

1)(11(0

+++

=

DC

DCcl A

AA

)111

1(

)1111(

tan 1

++=

++

=

DCCB

DCC

Affbandwidth

Aff

741C

+

R2

R1

e-

eo

R

27K

es

2.5K

2.7K-

e+

Inverting Amplifier

where Acl0 is the closed loop gain of the inverting amplifier at zero frequency.

34

The phase angle

example 8: A type 741 amplifier has the following parameters: open loop gain ADC=2*105, corner frequency fc=5Hz. Determine the closed loop gain of the non inverting amplifier shown in figure at f=20KHz.

Solution: The feedback factor 1=2.7/27=.1, from equation 34 we have Aclo = 2*105/(1+0.1*2*105)= 9.9995 from equation 33 we have for closed loop gain Acl=9.766 = -12.4 The bandwidth of amplifier fB=91KHz



12)1111(

1

+

+= nDCCBAff

e-

741C

+

2.5K

eo

R2

e-

e+

e+

R1

R1

e-

3K

+

-

+

eo

R

12K

R1

12K

2.5K

es

2.5K

741C

3K

-

741C

3K

12K

-

e+

Fig.13 Extending GBP by cascading

example 9: A type 741 amplifier has the following parameters: open loop gain ADC=2*105, corner frequency fc=5Hz. Determine the bandwidth of the amplifier shown in figure 13

Solution: The feedback factor 1=0.25, from equation 34 we have The overall gain of the circuit is 64. The bandwidth is

Number of stages=3 The bandwidth is fB=102KHz

10. slew rate The slew rate is defined as the maximum rate of change of output voltage per unit time. S=slew rate=(deo/dt)max. The slew rate is generally expressed in volts/microseconds.



-

D

C

e-

e+

e-

es

e+

eo

Q2

+

IC2 Q82N1070

Fig.14 EQUAIVALENT REAL OPERATIONAL AMPLIFIER

Q72N1070

Q1

Q3

Figure 14 illustrates the slewing problem. The input signal is large enough to fully saturate Q1 while turning Q2 completely off. Q1 then directs all available bias current into current mirror and Q3 and D. with Q2 off Q3, can only sink its current. C and I through the second stage IC2. And because I=C(de/dt), the output voltages maximum rate of change is de0/dt. The 741 operational amplifiers, for instance, used a 30pF compensation capacitor that charges from a 20uA bias current source and yields a 0.66uV/s slew rate. For a sinusoidal signal, instantaneous voltage can be written as es=eosinwt. The slew rate is defined as (deo/dt)max so we differentiate instantaneous voltage to obtain

des/dt=eo(2f)cos(2f)

it is maximum when cos(2f) is =1 so (des/dt)max=eo(2f)=S 35

example 10: A type 741 internally compensated operational amplifier has a slew arte of 0.5uV/s. Determine the maximum amplitude available at the output of the amplifier for a sine wave with a frequency of 33KHz. Solution: The undistorted maximum output voltage eo=S/2f=2.4V peak or 4.8V peak-peak Driving the amplifier beyond its slew rate results in triangular output that decreases with increase in frequency. 11. Noise In operational amplifiers, noise is an unwanted signal. Most noise is broadband and is due to the random thermal motion of electron charges. AS a results noise voltage and noise current are super imposed on the inputs of the opamp. If the signal levels from the sensors are very low, then the noise sources become significant. A circuit model for nose discussion is shown here. in figure15.



+ena

e-

Figure 15, Ampliifer with input current and volatgenoise errors

-

eo

e+R1

Rs

A

R2

BL

Hcenano ff

ffee +

= ln1

BL

Hcisnano ff

ffRIe +

= + ln2

BS fKTRe 44 =

BL

Hcisnano ff

ffRIe +

=

ln3

101028.1

The total input referred noise for the amplifier is calculated as follows.

Noise voltage component is

36

Noise current Ina+component is

37

Noise current Ina-component is

38

The Resistor Rs noise component is

39

where K is Boltzman constant is 1.38*1023j/degree absolute and T is absolute temperature in Kelvin.

The Resistor R2 noise component is



Bno fKTRRRR

e 221

15 4

+=

Bno fKTRRRR

e 121

26 4

+=

26

25

24

23

22

21 )()()()()()( nonononononono eeeeeee +++++=

=

ofsourcenoisepoweroisepowertotaNF lnlog10

++++= 2

1

26

25

24

23

22

)()()()()()(1log10

no

nonononono

e

eeeeeNF

nVRMSe

nVe

no

no

26.469

90100100ln20020

1

1

=

+

=

nVRMSe

KpAe

no

no

4.1370

9010

100ln200040*5.0

2

2

=

+

=

40


41

Total Noise 42

The amplifier noise figure is

43

if the noise signal is applied to the non inverting input and Rs is the source resistance. Then

44

From this equation this can be seen that when Rs is small, noise voltage will dominant, a and when large source resistance Rs is involved noise current will become important.

Example 11. A type 741 amplifier has the following parameters: Input noise voltage ena=20nV/Hz. Voltage noise corner frequency fcc=200Hz. Input noise current Ina=0.5pA/Hz. Current noise corner frequency fci=2000Hz.The operational amplifier is used in the non inverting mode with a closed loop gain of 100. Determine the value of the minimum noise figure (NF) in the frequency band from 10Hz to 100Hz. The ambient temperature is 300K. Solution: Choose R1=1K and R2=99K. Noise figure has its minimum value when Rs=ena/Ina=40k. Hence, the optimum source resistance Rs=40K. Bandwidth is fB=90Hz. Noise voltage component is

Noise current Ina+component is



nVrmseno 16.2444 =

nVrmseno 8412.35 =

nVrmseno 22.386 =

uVrmseno 47.1=

nVrmse

pAe

no

no

918.33

9010100ln2000990*5.0

3

3

=

+

=

+= 2

2

)(106.59614)(1.21008271log10

nv

nvNF

Noise current Ina-component is




Total Noise

The amplifier noise figure is

NF=15.59dB



Data sheets

General purpose Operational Amplifier 741C Sr. No parameter amplitude Unit

1. Input offset voltage 7.5 mV 2. Input offset voltage drift 6 V/C 3. Input bias current 800 Na 4. Input offset current 300 nA 5. Input offset current drift 0.5 nA/C 6. Input resistance (differential) 2 M 7. Input resistance (Common mode) 400 M 8. CMRR 70(minimum) dB 9. SVRR 150 V/V 10. Large signal Voltage Gain 2*105 11. Slew Rate 0.5V V/sec 12. Open loop output resistance 70 13. Unity gain bandwidth 1 MHz 14. Input noise voltage 20 nV/Hz 15. Input noise current 0.5 pA/Hz 16. From the graph, the 3dB corner frequencies 17. Open loop gain 5 Hz 18. SVRR 200 Hz 19. CMRR 200 Hz

Very low noise Operational Amplifier OP27 Sr. No parameter amplitude Unit

20. Input offset voltage 0.3 mV 21. Input offset voltage drift 1.8 V/C 22. Input bias current +/-150 Na 23. Input offset current 135 nA 24. Input offset current drift 0.1 nA/C 25. Input resistance (differential) 4 M 26. Input resistance (Common mode) 2000 M 27. CMRR 94(minimum) dB 28. SVRR 86(min.) dB 29. Large signal Voltage Gain 8*105 30. Slew Rate 2.8 V/sec 31. Open loop output resistance 70 32. Unity gain bandwidth 8 MHz 33. Input noise voltage 3 nV/Hz 34. Input noise current 0.4 pA/Hz 35. From the graph, the 3dB corner frequencies 36. Open loop gain 10 Hz 37. SVRR 10 Hz 38. CMRR 2000 Hz



+

++++

+++

+

++

= )//(211

)//(1

11

211

21

121

1

1

1RRI

eee

eRRIeesA

Ae na

rnans

rlOFFoso

es

e+

R2

e-

Inverting Amplifier

-15V

+15V

990E

1K

R1

+

Rs

741

100K

eo

-

+

+

++

= )//(1

11

211

1

1RRIeesA

Ae OFFoso

Inverting Amplifier

Figure illustrates the Inverting amplifier configuration

The application of Kirchoffs current law to the amplifier yields the relationship

Where 1 the feedback factor = (R1/R2), erl, er2 and ens are the noise voltage generated by the resistance R1, R2 and Rs respectively.

Example 1: A type 741C operational amplifier has the following specifications Input offset voltage drift = 1.8nV/C Input offset current drift = 50pA/C Supply Voltage rejection ration= 86dB Large signal voltage gain= 4*105 Compute the DC errors with offset adjustment of the amplifier shown in figure above over the temperature range from 0 to 50C. Calculate n bit accuracy.

Solution: Reducing equation for DC error gives,



1)2log(72.5

10000log1)2log(

log

=Error

olatgeFullscaleV

n

( )[ ])1/(//// 21 ARRRRR cmdin ++=

21121 /)//()1/( RRRandRRARoRout +=++=

mVe

eeAcloSVRRe

32

4.146.15*100*10*50

2**

sup

6

sup

=

=

=

+

A) Offset drift and gain error substituting the values in this equation we get eo=100.97(-99.01mV+90nV-2.5mV) or eo=-9997.283mV B) Error due to supply voltage variation

SVRR=10-86dB/20=50V/V

Total error er=10000mV-(9997.28mV-3mV)=5.72mV C) n-bit accuracy may be calculated as follows:

n=10 bits Input impedance of the amplifier

Rin= 1K ohms Output impedance of the amplifier

Rout =0.015ohms



++++++

+

+= )//(2)1()//(1

1 211221RRIeeeeRRIe

CMRRopCMRRop

eA

Ae narrnansOFFosSo

990 E

R1

e-

1K

Non Inverting Amplifier

e+

eo

-

+

99K

Rs

OP27

es

R2

Chapter-3 Non-inverting Amplifier

Figure 2 illustrates the non- inverting amplifier.

The application of Kirchoffs current law to the amplifier yields the relationship

Where the feedback factor = (R1/R1+R2).

Example 2: A type OP27 operational amplifier has the following specifications Large signal voltage gain= 8 X 105 Common mode rejection ration= 94dB Supply Voltage rejection ration= 86dB Input noise Voltage ena =3nv/Hz Voltage noise corner frequency fce = 27Hz Input noise current ina =0.4pA/Hz Current noise corner frequency fci = 140Hz

Compute the AC errors of the amplifier shown in figure (2) in the frequency band 1Hz to 333Hz. Calculate the n bit accuracy for the full scale output voltage of 10V AC (peak to peak).

Solution:



2

101log20)0()(

+==Hz

ffSVRRfSVRR B

20/6610 dB

2

21log20)0()(

+==KHzffCMRRfCMRR B

20/9.9610 dB

2

1

)1(

+

+

=

DCc

clo

op

opclos

samp

AffA

CMRRCMRRAe

ee

210105621.1194.999810000

fmV

mVeamp+

=

BL

Hcenaclono ff

ffeAe +

= ln1

BL

Hcinaclono ff

ffIRRAe +

= ln)2//1(22

SVRR(100Hz) = 86dB-20dB = 66dB or

= 0.5mV/V

esup= RR * Aclo * (Power supply ripple)

=0.5mV*100*10mV = 0.5mV Peak to Peak

Common mode rejection ration

CMRR(100Hz) = 97dB-0.1dB = 96.9dB or

=70795

Error due to bandwidth

Where Aclo= ADC/(1+ADC))=99.998

at f=333Hz, eamp=1.15mV

Noise calculation Bandwidth fB=fH-fL = 333Hz-1 Hz =332Hz Noise voltage component is

eno1= 6.6VRMS

Noise current component is



BSclono fRAe 103 1028.1 =

Bclono fRAe 2104 1028.1 =

Bclono fRAe 1105 1028.1)1( =

25

24

23

22

21 )()()()()( nononononono eeeeee ++++=

1)2log(15.1

10000log1)2log(

log

=Error

olatgeFullscaleV

n

cloDCcdB AAff /3 =

cmin RARR /)1(1 ++=

21//)1/( RRARoRout ++=

eno2= 2.7VRMS


eno3=7.3VRMS


eno4=0.74VRMS


eno3=7.3VRMS

Total Noise

eno= 12.57Vrms or 75.42V peak to peak

In the above error analysis, the AC error terms are dominated by the error due to bandwidth. Hence, the n-bit accuracy may be calculated as follows:

n=12 bits Maximum operating frequency of the amplifier fmax=Slewrate/2eo fmax=2.8V/sec/25V fmax= 89KHz

3-dB bandwidth of the amplifier

=80KHz Input impedance of the amplifier

Rin= 2G ohms Output impedance of the amplifier

Rout =8.7 milliohms



OP27

An inverting integartor

R

-

e+

R

+

es

e-

C

eo

++=

tOFF

BosOFF

tos

ts

o

RIRIedt

CIdt

RCedt

RCe

e

000 2

= OFFoso IR

e

Cdtde 1

( )OFFo ICdtde 1

=

Integrator If a capacitor is placed as the feedback resistor in the inverting amplifier, the results is an Integrator. The integrator shown in figure, provides the out put which is proportional to the time integral of the input signal.

This circuit is very important in the instrumentation as a charge balancing amplifier for variable capacitance and piezo electric transducers. The transfer function of integrator is given by

In the above equation eos is the offset voltage of operational amplifier. IB the bias current, IOFF the offset current and RC the time constant of the integrator. If the input voltage es is reduced to zero then the change in output voltage

Adjusting the eos to zero, then

An offset current of IOFF=300nA causes the output voltage to rise at a rate of 1V/sec. If C=0.3uF. The performance of the integrator may be improved by selecting the FET input amplifier (such as GA3140) and a high quality capacitor (Teflon or polycarbonate)

Example1 : An integrator can be used to separate DC offset from AC signal without a coupling capacitor. One such circuit is shown in figure.



es

39 K

10 K

e+-

C

R

e-

Separation of DC Offset from AC signal

eo

e-

+

+

-

e+

eo

10 K

OP27

1uF

CA3140

= dtRCwte

ep

o

sin

wRCwte

ep

o

cos=

The integrator feeds a signal er back to the input to reduce the DC level of the output to zero. In this case feedback signal is added with the input signal on the resistor 10K to remove DC offset. Low frequency cutoff is set by the integrator equal to 1/ 2RC and OP27 serve as buffer.

Integrator in frequency domain

If the input voltage is sinusoidal input voltage es=em sin wt then output voltage becomes



+

+

=

+

+

+

+

+

=

fcfjfo

fjfofjA

Loopgain

fcfjfo

fjfofjA

fcfjfo

fj

Ae

e

DC

DC

DC

s

o

11

11111

=

fof

fcf 11 tantan90

R

e-

+

C

OP27eo

Differentiating circuit

es

-

e+

R

+

++

++

=

RCsRCse

RCsInRs

e

RCsA

Ae soso 11

11

The amplitude of output voltage is therefore inversely proportional to the angular frequency. If the open loop gain of the amplifier is A is not infinite then

The phase shift

Where ADC is the open loop DC gain, fc is the open loop -3dB cutoff frequency, fo is the integrator cutoff frequency and f is the operating frequency. If the fo =1000Hz, ADC=2*103, fc=5Hz then at f=100kHz, the loop gain = 10 and phase shift =-90 degree. The integrator is stable for all frequency but the phase margin is -180-(-90)=-90 degree.

Differentiating circuits Using the capacitor as input element to the operational amplifier yields a differentiating circuit. Circuit shown here gives output proportional to derivative of input.

The application of KCL to the summing points yields the relationship



+

+

=

+

+

+

+

+

=

fcfjfo

fjA

Loopgain

fcfjfo

fjfofjA

fcfjfo

fj

fofjA

e

e

DC

DC

DC

s

o

11

11111

=

fof

fcf 11 tantan

2RI

RIdt

deRCe

dtde

RCe OFFBososso ++=

eo

C

R

OP27

es

R

e+-

e-

Practical Differentiating circuit

R1

+

if the open loop gain of the amplifier is infinite, then

If the input voltage is sinusoidal input voltage es=em sin wt then output voltage becomes eo=wRCepcoswt. If A is not infinite then the transfer function becomes.

Phase shift

At high frequencies phase shift becomes -180 degree. the phase margin =-180-(-180)= 0 degree. Hence, the differentiating circuit is unstable. One practical method of removing instability is shown in figure. The resistor R1 is added to the input to limit high frequency gain of differentiating circuit. It makes the circuit less susceptible to high frequency noise and ensures dynamic stability. The corner frequency where gain limiting resistor comes in to the picture is given by f1=1/2R1C. For this reason, f1 should greater than 10 times of the highest input frequency.



++

+

+

=

++

+

+

+

+

=

111

11

111

111

ffj

offjfo

fjffjA

Loopgain

ffjfo

fjfofj

ffjA

jffo

RRc

fofj

Ae

e

DC

DC

DC

s

o

+

=

1tantan

1tan 111 f

ffof

fcf

ff

Transfer function of the circuit is given by



Rs

R2

+R2=1K

+

Load

R2

-

R1

R1=1K

current booster

-

Constant currentsourec for groundedload booster

eo1

eo2 A

es

A

Voltage controlled current source for grounded loads In instrumentation, the measurement of resistance is generally carried out with a current source rather than a voltage source I order to eliminate the error due to the lead resistance of the resistance probe. A constant current source with no common mode voltage is shown in figure.



2112

21)1(12

2

RR

eoeo

RR

eeseo

ReLIo

RseLeo

=

=

+=

+= 122

122 R

RsRR

ReL

ResIo

)4(' 11 mARRIee sr +=

2/)'( ReeI po =

+

= mA

Re

RR

Is

so 4

2

1

From the above equations, eliminating eo1 and eo2, we get

The output current becomes independent of the voltage when the condition R2=R1-Rs is fulfilled. Hence, Io=es/Rs

The output resistance of the current source can be adjusted to infinity by slightly varying R2. When larger output current is needed, a current booster (example LH002C) may be used. As shown in figure.

Voltage to current transmitter Current transmitter are ideal for a variety of applications (like Temp. transmitter) requiring high noise immunity current mode signal transmission. The most straight forward circuit is shown in figure. In the voltage to current converter, the operational O1 forces its input voltage es across the resistor Rs. Neglecting the transistor base current error, the load current becomes

Is=es/Rs

The input voltage to current converter is

The operational amplifier O2 controls the output current by causing the resistor R2 voltage to equal the difference between the supply voltage and the input voltage. The current through the load will be

or



[ ]

++++

+=

6

533652112

6

5 21)//)(()(1RR

eRIeRRIIeeRR

e DOFFosOFFOFFososo

56

6

34

4

21

1,,

,

1

)1)(1()1)(1(5.0

log20

modlg

RRR

RRR

RRR

CMRRCMRR

where

CMRR

oras

egaincommonainaDifferentiCMRR

pn

OP

OP

np

npIA

IA

+=

+=

+=

+=

++

++=

=

Chapter-4 Instrumentation amplifier

Instrumentation amplifiers are commonly used for separating low level differential signals from high common mode noise. They have the following important characteristics. Very high input impedance High CMRR wide range of gain set by a single external resistor wide bandwidth less settling time These amplifiers are widely used in conditioning strain gauge bridges, Thermocouples, current shunts and biological probes. The most popular configuration for instrumentation amplifier using operational amplifier is shown in figure 1. The transfer function of the instrumentation amplifier is

1

Where (R6+2R5)/R6 is the differential gain and eD the differential signal. In the above equation the DC error terms are dominated by the input offset voltages. In the configuration shown in figure 1, common mode rejection depends on matching of R1, R2, R3 and R4. the common mode rejection ration of the instrumentation amplifier is given by

and CMRRop the common mode rejection ration of the operational amplifier.

Example 1: A type 741C operational amplifier has the following specifications Input offset voltage drift = 1.8nV/C Input offset current drift = 50pA/C Supply Voltage rejection ration= 86dB Common mode rejection ration= 97dB Large signal voltage gain= 4*105 Compute the DC errors with offset adjustment of the instrumentation amplifier shown in figure above over the temperature range from 0 to 50C. The differential input signal eD/2=5mV and the common mode signal ecm=10VDC. Calculate n bit accuracy for the full



mVVVeegainSVRR 75.02

)985.14(015.151000/502

)(=

=

+

mVengSubstituti

ee

cms

n

npcmcms

8.3001998.0,10000141

)1)(1(

=

==

++=

999E

-

139.890K

+

+

O3

eo

139.890K

1001E

-

R4 R2

R3

1000E

-

R5

R6

+

O1

R5

e2=ecm+eD/2

280E R1

Instrumentation Amplifier Using Three Op-amps

e1=ecm-eD/2

999E

O2

scale output voltage of 10VDC. The resistors values are R1=1001, R2=R3=999, R4=1000, R5=139860 and R6=280. .

DC error (with offset zero and power supply voltage tolerance of 1%). (1) offset voltage drift over temperature

edrift=eos3-IOFF3R=2.41V (2) supply voltage variation error

SVRR=10-86/20=50V/V

3) Error due to common mode



1)2log(55.4

10000log1)2log(

log

=Error

olatgeFullscaleV

n

-

O3

10K

R3

280E

R2

R1

+

R4

O2

Figure 2

+

+

-

1000E

O4

Instrumentation Amplifier for DCapplication

139.890K

e2=ecm+eD/2

-15V

-

-

R5

+

e1=ecm-eD/2

R5

1001E

eo

139.890K

999 E

+15V

999ER6

O1

4) Gain error

10V-5mV*1.99999*498.88*1.9984278=30.34mV The gain errors may be reduced to zero by connecting 277K parallel to R6. that is, =0.001996 then eo=10V. Hence gain error=0. n-bit accuracy may be calculated as follows:

n=11 bits

Hence we can interface this amplifier with an 11bit ADC. Common mode rejection ration of the amplifier

CMRRIA=20log(496.00669*1320.5959)=116dB. It is important to note that the CMRR of the instrumentation amplifier increases with gain. Figure 2 shows the circuit configuration with the value of all the components.



( )2

1

121

22

+

+

+

=

DCc

clo

cloDD

amplitude

AffA

Aee

e

2

101log20)0()(

+==Hz

ffSVRRfSVRR B

20/6610 dB

peaktomvpeakeweget

pnmVengSubstituti

ee

cms

cms

n

npcmcms

=

==

=

==

++=

71.1

500025.0,50005.08.3

8.001996.0,00002.1

)1)(1(

Example 2. A type OP27 amplifier has the following parameters: Input noise voltage ena=3nV/Hz. Voltage noise corner frequency fcc=27Hz. Input noise current Ina=0.4pA/Hz. Current noise corner frequency fci=140Hz.The Supply Voltage rejection ration= 86dB Common mode rejection ration= 94dB Large signal voltage gain= 8*105 Compute the AC errors in the frequency band from 1hz o 100hz for the instrumentation amplifier shown in figure. Calculate n bit accuracy for the full scale output voltage of 10Vpeak peak AC. The resistors values are R=1000, R5=139860 and R6=280.

Solution:

Error due to bandwidth

Where =0.0019968 (at f=0), fc=10Hz, =1.00002, Aclo= 500.49 and eD=10mV peak to peak. We get e amplitude=0 at f=0 and eamplitude =0.2mV at f=100Hz.

Error due to power supply ripple.

SVRR(100Hz) = 86dB-20dB = 66dB or

= 0.5mV/V esup= RR * Aclo * (Power supply ripple)

=0.5mV*100*10mV = 0.5V Peak to Peak Error due to common mode signal Chossing the value so resistors The resistors values are R1=1000, R2=R3=999.9, R4=1000.



1)2log(712.1

10000log1)2log(

log

=Error

olatgeFullscaleV

n

1K280E

e1=ecm-eD/2

R5

O2

Instrumentation Amplifier for ACapplication

-

1K

R3

O3

-

1K R1

-

Figure 3

1000E

R2

R5

139.890K

-

+

eo

+

R4

R6

O1

+

O4

+

270K/390K

e2=ecm+eD/2

139.890K

C

3. Noise calculation

Bandwidth fB=fH-fL = 99Hz eno=0.492mV peak-to-peak

The n-bit accuracy may be calculated as follows:

n=11.5 bits or 12 bits



es

1mA

R

Voltage to Frequency converter

+

Figure 1

Monostable

-

O1

SW+

e-

-

comperator

e+

C

=

=

ONt

ONRR tC

IIdtC

IIeo

0

==1

010

tss

o tRCe

eodtRCe

e

RON

sRON

ON

ONR

IRtef

IIt

Tt

tt

II

==+

=1

Voltage to frequency converters

In the voltage to frequency converters analog input voltages can be converted to a proportional frequency. the block schematic of the voltage to frequency converter based on charge balancing circuit technique is shown in the figure1. The operation of the circuit is as follows.

During the charging period, the integrator charges for a fixed period tON which is set by the mono-shot. The output of the integrator is given by

During discharge period, the integrator output voltage cross zero triggers a one shot. Hence,

equating the above equations, we get



ON

ON

T

t

Voltage to Frequency conversion waveform

Figure 2

t 1

t

ON

T

t

( ).

11 jwwheresRCsT

tRIeo ONR =

+

=

( ) sONR ftRIeo =

example: if R=40K, IR=1mA and tON=25sec then for es=10V the frequency output f=10KHz.

Frequency to Voltage converters For F to V, the same circuit and components of V to F converter may be used as shown in the figure 3. The one shot is activated by the TTL input logic(fs) and it switches 1mA current sink into the integrator input for a measured time period tON. The integrator acts as a first order low pass filter for the current waveforms. The filtered output is directly proportional to the frequency.

Choosing the 3dB cutoff frequency of the filter 1/2RC then



+

e-

Figure 3

+15V

SW

C

fs

O1eo

-

2.2K

e+

R

Monostable

12K

1nF

1mA

-

+

comperator

Frequency to Voltage converter



Chapter-5 ACTIVE FILTERS

Active filters are used in data acquisition systems for two reasons: 1) To limit the bandwidth of the processed signal to less than half the sampling frequency in order to eliminate frequency aliasing and 2) To reduce electrically generated noise in the system.

Active filters are frequency selective amplifiers used either to pass or reject selected bands of frequencies. The most common and basic types of filters are low pass (LP), high pass (HP), band pass (BP) and band rejection (BR).

These filters are very popular due to their advantages over passive filters, which are as follows:

1. No inductors 2. High input and low output impedance providing easy of coupling. 3. Control of gain 4. Easy to tune 5. Small size and weight 6. Less shielding problems.

Active filters have the following disadvantages compared with the passive filters.

1. Require a power supply. 2. Inject more noise 3. Lower Q-factor 4. Signal level limitations 5. Sensitivity to temperature 6. Efficiency decreases as frequency increases(limited frequency

range)

The most commonly used response is Butterworth. The Butterworth low pass filters have an amplitude frequency response. This is flat in the pass band and drops sharply just before the cutoff frequency. Their step response shows a considerable overshoot. This increases for higher order filters.



BUTTERWORTH LOW PASS FILTERS

The transfer function of a low pass filter has the general form

A(S) = A0_____________ (1(1)).. 1+C1S+C2S2+. +CnSn

Where C1, C2,..Cn are constants (positive and real). The order of the filter is equal to the highest power of S (= jW/Wc). It is advantageous for the realization of filters if the denominator polynomial is written in factored from.

A(S) = A0______________ (2) (1+a1S+b1S2)(1+a2S+b2S2)

Where ai and bi are constants (positive and real). The coefficient ai and bi in equation (2) are determined as follows:

For even order n:

ai = 2 cos [ P(2i -1) / 2n] for i = 1 to n 2 bi = 1

For odd order n:

a1 = 1 b1 = 0 And

ai = 2 cos [ P(i -1) / n ], for i = 2 to n+1 2 bi = 1

The coefficients of the Butterworth polynomials up to the order 10 are shown in the Table 1 and Table 2.



Table 1 factor of Butterworth polynomials_________________________ Butterworth polynomial

n 1 s + 1 2 s2 + 1.41421356s + 1 3 (s + 1) (s2 + s + 1) 4 (s2 + 0.76536686s + 1)) (s2 + 1.84775907s + 1) 5 (s + 1) (s2 + 0.61803399s + 1) (s2 + 1.61803399s + 1) 6 (s2 + 0.51763809s + 1) (s2 + 1.41421356 s + 1) (s2 +1.93185165s + 1) 7 (s + 1) (s2 +0.44504187s + 1) (s2 +1.24697960s + 1) (s2 +1.80193774s + 1) 8 (s2 +0.39018064s + 1) (s2 +1.11114047s + 1) (s2 +1.66293922s + 1) (s2 +1.96157056 s + 1) 9 (s + 1) (s2 +0.34729636 s + 1) (s2 + s + 1) (s2 + 1.53208889s + 1) (s2 + 1.78201305s + 1) 10 (s2 +0.31286893s + 1) (s2 +0.90798100 s + 1) (s2 +1.41421356 s + 1) (s2 +1.78201305s + 1) (s2 +1.97537668s + 1)

Table 2 coefficients of the Butterworth polynomial q(s) = sn + an-1 sn-1 ++ a1s + 1

n a1 a2 a3 a4 a5 a6 a7 a8 a9 2 1.41421356 3 2.00000000 2.00000000 4 2.61312593 3.41421356 2.61312593 5 3.23606798 5.23606798 5.23606798 3.23606798 6 3.86370331 7.46410162 9.14162017 7.46410162 3.86370331 7 4.49395921 10.09783468 14.59179389 14.59179389 10.09783468 4.49395921 8 5.12583090 13.13707118 21.84615097 25.68835593 21.84615097 13.13707118 5.12583090 9 5.75877048 16.58171874 31.16343748 41.98638573 41.98638573 31.16343748 16.58171874 5.75877048 6.39245322 20.43172909 42.80206107 64.88239627 74.23342926 64.88239627 42.80206107 20.43172909 6.39245322

ACTIVE SECOND ORDER LOW PASS FILTER

According to equation (2). The transfer function of second order low pass filter has the general from,

A(S) = ALPF___ (3) 1+a1S+b1S2

= ALPF___ 1+ 2S+S2



R5R4

e1eS

0

Figure 1: Sallen-Key Configuration

e0/G

+

-

U13

26

C4

e0R1 R3

C2

0

Active low pass filters can be designed using operational amplifiers with positive feedback. The gain of the amplifier must be fixed by the internal negative feedback in the configuration shown in figure 1. The positive feedback is caused by capacitor C2.

Apply Kirchhoffs current law (KCL) to the network and obtain

(es e1) = (e1 e0)C2s + (e1- e0 / G) (4) R1 R3

(e1 e0 /G) = e0C4s (5) R3 G

Where s = jw and the closed loop gain G = (R5 + R4) / R4. From equation (4) and (5), the transfer function becomes

e0 = G______________________ (6) es 1 + s ( R3C4 + R1C2 - R1C2G + R1C4 ) + s2 R1R3C2C4

Substituting s = sWc

in equation (6), we get

e0 = G______________________ (7) es 1 + sWc ( R3C4 + R1C2 - R1C2G + R1C4 ) + s2Wc2 R1R3C2C4

Comparing the coefficients of equation (7) with those of equation (3) gives

ALPF = G = (R5 + R4) / R4 (8)



a1 = Wc ( R3C4 + R1C2 - R1C2G + R1C4 ) (9) b1 = Wc2 R1R3C2C4 (10)

Solving equation (8), (9), and (10), we arrive at the design equations _____________________

R3 = a1 + a12 4b1 (1 G + C4 / C2) (11) 2WcC4

R1 = ________2b1_____________________ (12) C2Wc[a1 + a12 4b1 (1 G + C4 / C2) ]

ALPF = G = (R5 + R4) / R4 (13)

EXAMPLE 1:

Design a Butterworth low pass filter using Sallen-key configuration. The filter must meet the following specifications: the stop band attenuation Amin = 54 dB. The pass band attenuation Amax = 3 dB. The pass band frequency where attenuation is Amax. fc = 10 KHz. The stop band frequency fs = 20 KHz. overall gain of the filter = unity.

Solution : 1. Determine the order of the filter

n = log {10(Amin / 10) -1 / 10(Amax / 10) -1 } 2 log { fs / fc}

Order of the filter n = 9 In order to satisfy the low pass filter stop band specification a 9th order filter is required.



2. Get the Butterworth polynomials from table 1.

A(S) = 1_______________________ (1+S) (1+a1S+S2) (1+a2S+S2) (1+a3S+S2) (1+a4S+S2) Where a1 = 0.34729636 a2 = 1 a3 = 1.53208839 a4 = 1.87938524 and S = jW/Wc

3. Plot the poles and zeros of the filters

S1 = -1 S2 = -0.17365 + j0.9548 S3 = -0.5 + j0.866 S4 = -0.766 + j0.6428 S5 = -0.9397 + j0.342



Figure: 2 Pole-Zero Diagrams

4. Compute the 3-dB cutoff frequency of the overall filter

fc = fs______________ = 10KHz {10(Amin / 10) -1 / 10(Amax / 10) -1 } 1/2n

5. Get the 3-dB cutoff frequencies of the individual filter stages ___________________________

= {- (ai2 - 2 ) + (ai2 - 2 ) + 4 } / 2 1st stage = fc =10.00 Hz 2nd stage = 1 fc = 15205 Hz 3rd stage = 2fc = 12720 Hz 4th stage = 3fc = 9172 Hz 5th stage = 4fc = 7026 Hz

6. Get the pole pair quality factor Qi, of the individual filter stages. __

Qi = bi for i = 1, 2, 3. ai

1st stage = Q0 = 1 2nd stage = Q1 = 2.879 3rd stage = Q2 = 1.000 4th stage = Q3 = 0.6527



5th stage = Q4 = 0.5321

7. Plot the magnitude and phase response of the filter (figure 3)

Figure 3 Amplitude and phase response of the 9th order Butterworth low . pass filter. 8. Get the 1st and 2nd order filter configurations

ALPF = 1 __________

R3 = ai + ai2 4 C4/C2 2 fcC4



R1 = 1_____________ where i = 1,2,3,4. fcC2 {ai + ai2 4 C4/C2}

9. Choose high quality capacitors (Example : Polycarbonate or Teflon)

1st stage C6 = 1.5 nF 2nd stage C2 = 47 nF & C4 = 1nF 3rd stage C2 = 4.7 nF & C4 = 1nF 4th stage C2 = 2.2 nF & C4 = 1nF 5th stage C2 = 1.5 nF & C4 = 1nF

10. Get the values of resistors

1st stage R5 = 10.61 K 2nd stage R3 = 8.5265 K & R1 = 1.2642 K 3rd stage R3 = 22.058 K & R1 = 4.8866 K 4th stage R3 = 35.961 K & R1 = 6.4035 K 5th stage R3 = 44.717 K & R1 = 23.728 K

For good stability choose metal film resistors.

11. Choose the opamp and check the slew rate

Opamp OP 27 has a slew rate of 2.8 v/ sec. and a unity gain bandwidth of 8MHz. for 10V peak AC the operating frequency is 45KHz. hence, Opamp OP 27 has been selected for this filter.

12. Draw the circuit diagram of the 9th order Butterworth low pass filter with the values of all the components.



C2

R3

C4eS

0

Second order

R1e0

+

-

U13

26

eS

First order

e0

C6

+

-

U13

26

0

R5



Active high pass filters (HPF)

High pass filter characteristics can be derived from corresponding low pass filter transfer function through replacement of S by 1/S. a 2nd order high pass filter transfer function is described by

A(S) = ___AHPF S2 / b1_____ (14) 1 + a1 S + 1 S2 b1 b1 Now, the equation (14) can be implemented by using Sallen-Key configuration.

Active second order HPF If the resistors (R1, R3) and capacitors (C2, C4) are interchanged in the low pass filter circuit (figure 1), then the circuit becomes HPF (figure 4)



R5

+

-

U13

26

C3

0

R6

e0C1

eS

Figure 4: Sallen-Key Configuration

0

R4

R2

The transfer function of the circuit is given by

e0 = GR2R4C1C3s2______________________ (15) es 1 + s (R2C1 + R4C3 + C3R2 - GR4C3) + R2R4C1C3s2

Where G = ( R5 + R6 ) / R5 and s = jW, substituting s = SWc in equation (15) we get

e0 = GR2R4C1C3s2Wc2______________________ (16) es 1 +sWc (R2C1 + R4C3 + C3R2 - GR4C3) +R2R4C1C3s2 Wc2

comparing the coefficients of equation (16) with those of equation (14) gives

AHPF S2 = GR2R4C1C3s2Wc2 (17) b1 a1 = Wc (R2C1 + R4C3 + C3R2 - GR4C3) (18) b1

1 = R2R4C1C3 Wc2 (19) b1

Solving equation (17), (18) and (19), we get ________________________

R2 = a1 + a1 1 [4b1( C1+C3)(1-G)] / C1a12 (20)



2b1 (C1 + C3) Wc

R4 = 2(C1 +C3)__________________________ (21) WcC1C3 {a1 + a1 1 [4b1( C1+C3) (1-G)] / C1a12 }

EXAMPLE 2:

Design a 4th order Butterworth high pass filter using the Sallen-key configuration. The filter must meet the following specifications: gain of the filter AHPF = 1 and 3dB cut off frequency fc = 668 Hz.

1. Get the Butterworth polynomials from the Table 1.

A(S) = ALPF____________ (1+a1S+S2) (1+a2S+S2) Where a1 = 0.76536686, a2 = 1.84775907

2. Substituting S = 1/S, obtain the Butterworth polynomials for HPF.

A(S) = AHPF S4_________ (1+a1S+S2) (1+a2S+S2)

3. Get the 2nd order HPF circuit.

R4eS

R2

C3

e0

C1

+

-

U13

26

0

4. Choose capacitors C1 = C3 = 0.1 F

5. For unity gain AHPF = 1 and G = 1 R4 = 2 and R2 = a1____ a1CWc 2CWc



6. Get the values of resistors 1st Stage R4 = 6226, R2 = 912 2nd Stage R4 = 2597, R2 = 2201

7. Choose opamp : OP-27

8. Draw the circuit diagram of the 4th order Butterworth HPF with the values of all the components.



2243

2

43

1

3

1 sCRRCsRRR

RR

e

e

s

o

++

=

5V

-15V

-4.4V

TTL INPUT

5K

5V

-5V

5K

2N2222A

-

2N2222A

2N2907

1N4148

10K

1N4148

+

10K

A

1K

1N4148

3K

Chapter-6 Current switch

Assignment 7

Using the configuration shown in the figure1, design a unity gain second order Butterworth low-pass filter with -3dB cut off frequency of 280 Hz.



A

R3

A

+

-

+R4

R6

R1

C

-

-

eo

Tow - Thomas Circuit

+

R2

R5

es

C

A



C3

0.1uF

es

C3

0.1uF

R4

2579 E

R4

-

Aeo

R2712 E

+

2201 E

-

C1

0.1uF +

A

C1

0.1uF

6226 E

R2

Band pass Filter



21)(

SQS

ASA F

SBPF

++=

Plot the magnitude and phase response of the filter

Figure 5 Amplitude and Phase response of the 4th order Butterworth high pass filter

Active Band Pass Filter

Band pass characteristics can be derived from low pass filter transfer function through replacement of S by Q(S2+1)/S. Therefore, the transfer function of the second order BPF is

22

Where Q= fC/fB fC the center frequency of the filter and fB = (fH-fL) the bandwidth of the filter. The frequency response of the magnitude and phase are shown in figure 6 for Q=10 and ABPF=1



sRR

CCRRs

RRCCRRR

sRRCRR

e

e

s

o

31)54(31

31543211

31532

2

+

++

++

+=

CWcSRR

CRRSCWcRRRRR

WcSRRCRR

e

e

s

o

31312

313211

31532

222

++

++

+=

321

31

21

RRRRR

Cfc

+=

122

RRABPF =

CRfQ c 2=

CfQRc

=2

BPFcCAfQR

21=

)2(2 23 BPFc AQCfQR

=

Second Order Band Pass Filter The multiple feedback band pass filter circuit is sown in figure 7

23

Substituting s=SWc and C4=C5=C in equation (23) we have

24

Comparing of coefficients of equation, (24) with those of equation (22), we get the following equations.

25

26

27

From equation (27) the bandwidth of the filter fB=1/R2C which is independent of R1 and R2. Solving equations (25), (26) and (27) gives the following relations.



C4

R2R1

-

C5

eoA

Fried Circuit

+

R3

es

-

R3

68K

A

34K

R1C5

0.1uF

+

R2

170 E eo

es

C4

0.1uF

Example 3: Design a Second order Butterworth BPF using the FRIED circuit. The filter must meet the following specifications. Center Frequency of the filter fC=312Hz, Q=10 and the gain of the filter ABPF=1

Solution: Choose capacitors C4=C5=C= 0.1F. The computed values of resistors are

R2= 68K R1=34K OR 68K//68K R3=170



2

2

1

)1()(SQ

SSASA BRF++

+=

222

3

4

222

1

2

1

1

sCRRCsRR

sCRRR

e

e

in

o

++

+

=

2222

3

4

2222

1

2

1

)1(

c

c

in

o

WSCRRCSWcRR

WSCRRR

e

e

++

+

=

RCfc 2

1=

1

2

RRABRF =

42 / RRQ =

Active Band Rejection Filter

Band stop characteristics can be derived from low pass filter transfer function through replacement of S by S/Q(S2+1). Therefore, the transfer function of the second order BRF is

28

Where Q= fC/fB fC the center frequency of the filter and fB = (fH-fL) the bandwidth of the filter. The frequency response of the magnitude and phase are shown in figure 8 for Q=10 and ABPF=1

Second Order Band Reject Filter Figure 9 shows the circuit connection for BRF. Its transfer function is found to be

29

Substituting s=SWc in equation (29)

30

Comparing of coefficients of equation, (30) with those of equation (28), we get the following equations.

31 32

33

Example 4: Design a Second order Butterworth BRF using configuration shown in figure. The filter must meet the following specifications. Center Frequency of the filter fC=50Hz, Bandwidth of the filter fB=6Hz and the gain of the filter ABRF=1



U4

R4

R4

U2

R2

+

HP

R1

U3

-

R2

R

BP

-

-

LP

+

es

C

+

eo

R

+

R3

BR

-

Universal Active low pass filter

C

U1

Solution: Choose capacitors C= 0.2F. For ABRF=1, R1=R2=10K Q factor= fC/fB=25/3. From equation 33 we have R4= 3.3K R3=27K and R= 27K//27K



R1

34K

R2

D1LM336

+

sine wave

-

+

O2 741R3

C5

0.1uF

-

Square Wave

R1

C4

0.1uF

12K OpenCollector

+15V

10K

68K

O1

LM311

170 E

sine waveBPFCOMPARATOR

Precision AC Source Generation of low frequency sine wave for applications like strain gauge instrumentation system is much easier to use an analog comparing circuit and a band pass filter. The block diagram of such a circuit is shown in figure 1.

Fig. Block diagram of sine wave generator

The basis of a sine wave oscillator is the series connection of an analog comparing circuit and a band pass filter as in figure 2. The comparing circuit O1 and the reference diode D1 supply a constant square wave output voltage, which is subsequently filtered. The band pass filter O2 removes harmonics and gives out a very clean sine wave.



R1

C

+

O3

-

-

SW2

R

C1

+

O2

Figure 1: Auto Zero Amplifier

SW3

+

O1Ro

eo

SW1

-

es

Chapter-7 Auto Zero Amplifier Auto zero amplifier are most widely used in DC low level signal measurement. The block schematic of these amplifiers is shown in the figure 1.

In this method the switches SW1, SW2 and SW3 are toggled at a nominal rate, which forces the circuitry to alternate between auto zero and sampling cycle. With the switches flipped down, the inputs of the instrumentation amplifier are shorted together and a feedback loop closed around input stage to null its offset. SW3, R, C and O2 forms the integrator, which stores offset value to be algebraically added to the input signal voltage during sampling cycle. When the switches are flipped up, the circuit is forced in to the sampling cycle. During this period the zeroed amplifier resumes amplifying differential input signal, which SW3 then transmits to the output stage. SW3, R1 and C1 form the sample and Hold circuit to store the amplified signal during the auto zero cycle. In the sample mode, the output of the instrumentation amplifier = Gain(input voltage + offset voltage) + Integrator output voltage But in the AUTO ZERO MODE, the integrator output voltage=-Gain(Offset voltage) Therefore, the output of the instrumentation amplifier = Gain*input voltage



S4

+

S2

Ro

OP27

-

S1

S3es

C1

C

Figure 1: Chopper Amplifier

eo OP27

-

R2

R3

R1

O2

Oscillator

+

O1

1.5K

1nF

Chopper amplifier

To avoid the drift problems usually associated with the DC amplifier, chopper amplifier are often used for microvolt measurement. In a chopper amplifier the DC input voltage is converted into an AC amplified by an AC amplifier and then convert back into a DC voltage proportional to the original DC input signal. The principal of operation of a chopper amplifier is illustrated in figure1 . The four analogue switches (S2-S3) and (S1-S4) are controlled by the signal A and A* at a frequency fO generated by the oscillator. these switches are used as chopper for pulsed modulation and demodulation.



current

U1eo

e-

Rf

-

+

Rf

InaRs Ip

Rd

erf

eo

ens

eos

Figure 2: practical I to V converter

In-15V

Ina

-

ena

+

0 to 1.992mA

741C

Current to Voltage converter The current to voltage converter generally used to convert the current output signal produced by most DAC into a voltage output.

The source current Io must flow through feedback resistor Rf since no current can flow into the operational amplifier input since the inverting input of the operational amplifier is at virtually ground potential. The ideal output voltage is given by eo=IoRf Error budget analysis of current to voltage converter. A practical I-V converter using opamp 741 is ash own in figure2. The transfer function of the circuit is given by



[ ]rfnsnafnafOFFosfo eeIReRIeRIAA

eo ++++++

= 21

mVVuVeegainSVRR 015.02

)9.14(1.151/1502

)(=

=

+

2

1

+

=

DCc

clo

clofofo

AffA

ARIRIe

BL

Hcenaclono ff

ffeAe +

= ln1

BL

Hcinaclono ff

ffIRRAe +

= ln)2//1(22

Where A is the open loop gain, ena the input noise voltage of operational amplifier, Ina the input noise current of operational amplifier, ens the input noise voltage of resistor Rs and erf the input noise voltage of Resistor Rf. DC error (with offset zero and power supply voltage tolerance of 1%).

(3) offset voltage drift over temperature (T=50C)=0.3mV (4) offset current drift =-0.032mV (5) supply voltage error

Total DC errors: 0.283mV

AC errors 1. Error due to power supply 150V/V*1*10mV=1.5mVp-p (100Hz)

2. Gain error

Where Aclo= ADC/ (1+ADC)) ADC is the open loop gain of the amplifier. If ADC is 2*105 and fC=5Hz, then the gain error becomes 0 at f=0 and 1.25mV at f=3KHz.

3. Noise calculation

Bandwidth fB=fH-fL = 90Hz Noise voltage component is

ena=20nV/Hz, fce=200Hz and fB=90Hz eno1= 0.47VRMS

Noise current component is

Ina=0.5pA/Hz, fci=2KHz eno2= 0.088VRMS




BSclono fRAe 103 1028.1 =

fclono fRAe 2104 1028.1 =

24

23

22

21 )()()()( nonononono eeeee +++=

1)2log(29.0

2550log1)2log(

log

=Error

olatgeFullscaleV

n

cloDCcdB AAff /3 =

eno3=0.044VRMS

The Resistor Rf noise component is

eno4=0.044VRMS

Total Noise

eno= 0.48Vrms or 2.88V peak to peak

Maximum operating frequency of the amplifier fmax=Slewrate/2eo fmax= (0.5V/sec)/22.55V fmax= 34KHz

3-dB bandwidth of the amplifier

=1MHz Hence, the n-bit accuracy may be calculated as follows:

n=10 bits



Chapter-8 Sample and hold circuit A sample and hold circuit is a voltage memory device that stores a given voltage on a high quality capacitor accurately over periods ranging from microvolts to several minutes. These devices are widely used in analog signal processing and data conversion systems.

Figure 1 shows, a sample and hold circuit consisting of an analog switch S1, two (unity gains) buffers U1 and U2 and hold capacitor CH When the switch closes (in he hold mode) the capacitor charges to the input voltage. The voltage across the capacitor ec is given by

1AC

ON H

tR C

c se e e

=

(1)

where RON is the on resistance of the switch S1 and tAC the acquisition times. Re arranging the equation (1) gives

ln sAC ON Hs c

et R C

e e

=

To charge the capacitor to 99% of the input voltage ,the required time or the acquisition time tAC =6.9 RONCH , when the switch opens in the hold mode the capacitor retains the charged voltage eC and thus holds the desired voltage for a specified period . the output voltage eo is given by

1( )H

C H

tR R C

o ce e e

=P

(2)

where R1 is the input resistance of the operational amplifier and Rc the capacitor leakage resistance (mega ohm microfarad).



From equation (2) we have 1( ) ln cH c H

o

et R R C

e

=

P

the self-discharge time constant ( the length of time required for an open-circuited capacitor to discharge to 36.8% of its charged voltage) becomes

tH=(R1||RC)CH (3)

Example 1: determine the acquisition time to 0.1% full scale or a 10V step input with CH =10nF and TON=300 . Solution: tAC=6.9RONCH=20.7 sec.

Example 2: assuming the following specifications determine the self-discharge time constant of the capacitor CH. Input resistance of the operational amplifier U2 (CA3140),R1=1.5 Hold capacitance CH=0.01 F(poly carbonate) Leakage resistance of the capacitor =1010 - F. Solution : Using equation (3) we get tH=6000secs. With 741 operational amplifiers ,tH becomes 4seconds. Therefore , the U2 must be a FET input operation amplifier.

Important S/H characteristics

Acquisition time : the time required for the circuit output yo become equals to the input . the output then follows the input until the circuit is again put in the hold mode.

Drop rate : the rate of of change in output voltage with time while in the hold mode. Droop rate typically varies from 1mV to 5mV per second.

Pedestal error : charge injection is the phenomenon of moving small amount of charge from the main signal path switch to or from the hold capacitor during switching . the error resulting charge transfer may be referred to as pedestal error or hold step.

Aperture time : the time delay between switching off the control voltage and the actual cut off of the series switch . during this time the output signal may change slightly. In high-speed applications variation in aperture time can become important .such variations is called aperture uncertainty or aperture jitter.

It has been pointed out that operational amplifier U2 must have FET input. Employing feedback as shown in the figure 2 can eliminate its offset voltage.

In the sample mode ,diodes D1 and D2 are off. The output of the operational amplifier U1 becomes

0 0( )s ose e e A e= + in the above equation ,A is the open loop gain of the operational amplifier U1 .if A is infinite then e0=es.



In the hold mode , the output voltage remains constant .resistor R and diodes D1,D2 prevents operational amplifier U1 becoming saturating in this mode of operation .

figure 2: S/H circuit with feedback

Maximum allowable input frequency A S/H amplifier stores (in the hold mode) an instantaneous voltage (sample value ) at a desired instant time. The constant on this time is aperture uncertainty ( figure 3). The aperture error is

sap ap

dee t

dt=

(4) where des/dt is the input signal slew rate and tap the aperture time. any sinusoidal signal follows the from: es=ep sinwt

des/dt

eap

des/dt

eap

tap



The maximum rate of change of input sinusoidal signal is

max2s pde f edt

= (5)

but

12np

ape

e += (6)

where n is the number of bits of desired resolution . from equation 4,5 and 6 we have

1

1max

22 napf t +=

for tap =1nsec and n=12 the maximum frequency that can be handled by a S/H circuit (to within LSB) is 19.4KHz.



Software programmable gain amplifier Gain =1,or 2,5,10,20,50,100,200.

Figure 4: software programmable gain amplifier One of the most common uses of an analog multiplexer is to alter the gain of an amplifier. The figure 4 shows a SPGA with gains of 1, 2,5,10,20,50,100, and 200. the gain error due to on resistance of the switch is completely eliminated by placing the multiplexer in the feedback path of the operational amplifier. The analog multiplexer Mux 08 provides a make before brake operation necessary to prevent the amplifier from open loop during gain switching.



Error= mIDRON+2RONnID

-

U1 +

0 to 7

0 to 7

0 to 7

n=8

8-ch mux

2

8-ch mux

1

8-ch mux

8

8-ch mux

e0

m=8



Analog multiplexers Analog multiplexers are used for time-sharing of analog to digital converters between a number of different analog information channels. An analog multiplexer consists of a group of analog switches arranged with inputs connected to the individual analog channels and output connected in common. the switches in the multiplexer can be addressed by a digital input code.

Single ended analog multiplexers

Figure 1 shows an n-channel single ended multiplexer with a buffer amplifier .figure 2 shows the equivalent circuit of an n-channel multiplexer, which is characterized by series resistance RON ,shunt capacitance CD and a leakage current ID . the amplifier input bias current (IB) is also shown in the figure

.

Where a switch S1 is closed in the multiplexer with n inputs , input to the amplifier charges up to

e1 RON (nID+IB)with a time constant =nCDRON

in a large low level multiplexing configuration , he error can be serious . for example , if the leakage current ID is 100nA ,and RON = 100 ., and n=64 , the error voltage is approximately 0.655mV. the time constant also becomes quite large for a large number of inputs . suppose the capacitance of each switch is 14pF and the time constant is 0.6sec. a 4sec delay will be required to each within 0.1 % of the final value.

Analog signals

Digital codes

E0 n-channel analog mux

-

+



multiplexing employing block switching

when several channels need to be measured simply tying to gether the outputs of the different multiplecers may not be advisable . this can cause heavy capacitance loading on the selected channel . by using multi tire architecture as shown in figure 3 ,the capacitance can be lowered significantly .

the input error is redused to

mIDRON+2RON (nID + IB )

if m=n=8 then the error for the example above is redused to 0.27 mV.

The total capacitance on the output of the selected input channel is reduced to

C=CD (m+2n ). And the associated delay is reduced by a factor of three.

Integrating or Dual-slope analog to-digital converters

Integrating ADCs operate by the indirect method of converting a voltage to time period , which is then measured by a counter ./ thos type of ADCs is widely used in most digital voltmeters(DVM) and digital panel meters (DPM) . the converter is illusterated in the simplified figure 1 a and its timing diagram for one conversion cycle is also shown in figure 1b. figure 1c shows the operation of ADC for the bipolar signals.



-

U1 +

+ U2 -

R

Control logic

counter

Figure 1 block diagram of an integrating ADC

n- bit Data EOC

start

clock

S1 S2 S3

es

eR

es , eR are always opposite polarity.

S1

S2

S3

C



the conversion cycle consists of two separate integration intervals. At ,rest the switches S1 and S2 are open and S3 is closed . the integrator U1 output is zero. At start of conversion , the switch S3 is open and the unknown input voltage .

es=-[eDC +eAC(sin wt+ )] is connected to the integrator input through the switch S1 . where eAC(sin wt+ ) is a DC input with an AC interference signal superimposed upon it and is the phase angle of the interference signal at the start of the integration. The input voltage is integrated for a fixed period of time t1 . at the end of time period t1 ,the output of the integrator is given by

[ ]1

01

0

1sin( )

t

DC ACe e e wtRC

= + + (1) RC is the time constant of the integrator . the equation (1) may be simplified as

( )101 1cos( ) cosDC ACe t ee wtRC wRC

= + (2)

at the time period t1 , the counter overflow , causing S1 to be opened and the reference voltage er to be connected to the integrator input through the switch S2, the integrator output decreases until it crosses zero, and the zero crossover detector U2 changes state , indicating the end of conversion (EOC). The integrator U1 output becomes

2

02 01

0

1 tre e e dt

RC=

(3)

the voltage er is the reference voltage. At the end of the time period t2,e02=0. hence the equation (3) becomes

( ) ( ) 21Dc AC re e e tCOS wt COSRC wRC RC

+ = (4)

OR

( ) ( )12 1Dc AC rr r

e t e et COS wt COS

e we RC = + = (5)

where 1 sin( 1)tan1 cos( 1)

wt

wt = +

we can write the equation (5) as



2 1DC

tr

er errore= + (6)

if error is zero ,t1=n1/fc and t2=n2/fc .then equation (6) gives 2 1

DC

r

en n

e= (7)

where fc = the clock frequency to the converter. If er and n1 are constant then the net count n2 present in the counter at the end of time period t2 is directly proportional to the input voltage eDC. Normal mode line frequency rejection The series or normal mode rejection (NMR) of the converter is given as the ratio of the maximum error produced by the sine wave to the peak magnitude of the sine wave .from equation (6) NMR is

10K

100K

Level Translator

S4 S5

-

+

-

+

To the ADC

S4

S5

es

Figure 1c:for bipolar operation of ADC

t1 fixed

t2 variable

voltage

time

es

Figure 1b timing diagram



1

cos( ) cos( )AC

error wt

e wt

+=

the NMR is generally expressed in dBs as

120logcos( ) cos( )

wt

wt

= +

where = 111

sin( )tan

1 cos( )wt

wt

a plot of the NMR of the integrating ADC is shown in figure2.



Chapter-9 Advantages of Integrating ADC ! Simplicity ! Relatively low cost ! High accuracy and linearity ! Excellent noise rejection ! No sample and hold required ! Non critical component ! No missing codes ! Neither the clock frequency nor the integration time influence the result ! Offers excellent differential and integral linearity

Disadvantages of ADC ! Low speed (3 to 100 reading / second) ! Requires a stable ripple free reference voltage ! If the main frequency is not constant , these ADC s require a phase locked

loop(PLL) to track the main frequency.

Integrating ADC interface

Figure 3 shows an integrating ADC interface. An integrating ADC offers a high line frequency rejection, good resolution and linearity. This is available as an inexpensive 13-bit ADC (ICL7109) chip. In this ADC, an input voltage integration phase, a reference integration phase and an auto-zero phase are carried out in 8192 clock periods, serving to eliminate offset voltages and determine the magnitude and polarity of sampled voltage. The ADC integrates the input signal for only 2048 clock periods. To achieve high normal-mode line frequency rejection, the integration period is made equal to the



period of the mains supply by incorporating phase locked loop (PLL) and a divide-by-2048 counter. Hence, the clock frequency fc for the ADC is 2048 fs , where fs is the frequency of the mains supply.

The stability of the reference voltage is a major factor in the overall absolute accuracy of the ADC. An external reference voltage is employed. This has a temperature coefficient of 2 ppm/C. A change in temperature of 35C in the environment introduces a 0.25 bit error having REFIN and INLO at analog common minimizes the rollover errors of ADC. The components are selected for 4.096 V full scales.

advance instrumentation i

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