ads8555evm-pdk evaluation module (rev. a)

User’s GuideADS8555EVM-PDK Evaluation Module

ABSTRACT

This user's guide describes the operation and use of the ADS8555 evaluation module (EVM). The ADS8555 isa 6-channel, simultaneous sampling, 16-bit successive approximation (SAR) analog-to-digital converter (ADC).Each input channel on the device can support true bipolar input ranges up to ±12 V. The device includes aprogrammable, internally buffered voltage reverence. The ADC includes a serial programming interface (SPI)interface and a parallel interface (word and byte mode) for data communication. Device configuration is achievedthrough simple static digital input pins (hardware mode) or through communications to the SPI interface (controlregister configuration in software mode). This user's guide covers the circuit description, schematic diagram, andbill of materials for the ADS8555 circuit board. This EVM hardware and software can also be used to supportthe ADS8556, ADS8557, and ADS8558 devices from this family. Other devices can be tested by desoldering theADC and reprogramming the EVM (see Section 6.3). Detailed instructions for using other family members areprovided later in this document.

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Table of Contents1 ADS8555EVM-PDK Overview.................................................................................................................................................3

1.1 ADS8555EVM-PDK Features............................................................................................................................................ 31.2 ADS8555EVM Features.....................................................................................................................................................3

2 EVM Analog Interface.............................................................................................................................................................42.1 ADC Supply, Input, Voltage Reference, and Digital Connections...................................................................................... 42.2 ADC Amplifier Drive........................................................................................................................................................... 5

3 Digital Interface.......................................................................................................................................................................63.1 Parallel Interface................................................................................................................................................................ 63.2 Serial Interface (SPI)..........................................................................................................................................................63.3 I2C Bus and EEPROM....................................................................................................................................................... 63.4 Connections to the PHI Connector.....................................................................................................................................7

4 Power Supplies....................................................................................................................................................................... 84.1 External Power Connections and Test Points.................................................................................................................... 84.2 Low-Dropout Regulator (TPS7A3001 for HVSS)............................................................................................................... 84.3 Low-Dropout Regulator (TPS7A4700 for AVDD, HVDD)................................................................................................... 9

5 Installing the ADS8555EVM Software................................................................................................................................. 106 ADS8555EVM Operation...................................................................................................................................................... 12

6.1 Connecting the Hardware and Running the GUI..............................................................................................................126.2 Jumper Settings for the ADS8555EVM............................................................................................................................136.3 Modifying Hardware and Using Software to Evaluate Other Devices in the Family.........................................................146.4 EVM GUI Global Settings for ADC Control and Registers............................................................................................... 156.5 Time Domain Display....................................................................................................................................................... 166.6 Frequency Domain Display.............................................................................................................................................. 176.7 Histogram Display............................................................................................................................................................ 18

7 Bill of Materials, Layout, and Schematics.......................................................................................................................... 197.1 Bill of Materials.................................................................................................................................................................197.2 Board Layout....................................................................................................................................................................227.3 Schematics.......................................................................................................................................................................23

8 Revision History................................................................................................................................................................... 26

TrademarksKeysight™ is a trademark of Keysight Technologies.LabVIEW™ is a trademark of National Instruments.Microsoft® and Windows® are registered trademarks of Microsoft Corporation.All trademarks are the property of their respective owners.

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1 ADS8555EVM-PDK OverviewThis document describes how to connect the EVM to your computer and test equipment to evaluate deviceperformance and understand device features. The document also describes how to install and use theassociated evaluation module software.

1.1 ADS8555EVM-PDK FeaturesFigure 1-1 shows the proper component connection for the ADS8555EVM. The ADS8555 evaluation module kitincludes the following features:

• Hardware and software required for diagnostic testing as well as accurate performance evaluation of theADS8555 ADC.

• Digital and analog interface power with universal serial bus (USB) power. External power is required for thehigh-voltage ±15-V supply.

• Easy-to-use evaluation software for the 64-bit Microsoft® Windows®7, Windows® 8, and Windows® 10operating systems.

• Precision host interface (PHI) controller translates the USB (2.0) or higher to parallel or serial digitalcommunications.

Signal

Source

Included in kit

ADS8555EVM

PHI Board

xxxxx

xx

xxxxxxxx

xxxx

ADS8555

GUI

Signal

Source

+15V, -15V, GND

Figure 1-1. System Connection for Evaluation

1.2 ADS8555EVM Features• Six input channels connected to external single-ended signals that are source applied to subminiature version

A (SMA) connectors or headers.• Serial and parallel interface connects to the PHI controller via a 60-pin connector (J2).• High-voltage power supplies (HVDD and HVSS) are not included. Connect common lab supplies via screw

terminal J1.• Analog low-voltage supplies (AVDD = 5 V) are generated using an external 15-V supply and a low-dropout

regulator (LDO). HVDD (12-V supply) is also generated using the 15-V supply and an LDO. HVSS (–12-Vsupply) is generated using the –15-V supply and an LDO.

• Digital low-voltage supply (DVDD = 3.3 V) is generated using USB power from the PHI controller.• Integrated or external voltage reference options are available.

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2 EVM Analog InterfaceThe ADS8555EVM is an evaluation module built using a two-board modular EVM system. One board is a digitalcontroller (PHI), and the other board contains the ADC and associated analog circuitry. Both boards and theassociated cables form the ADS8555EVM-PDK.

2.1 ADC Supply, Input, Voltage Reference, and Digital ConnectionsFigure 2-1 shows the decoupling on AVDD, BVDD, HVDD, and HVSS and the voltage reference. The decouplingcapacitors match the recommendations in the ADS8555 data sheet. The layout (see Figure 7-1) uses theshortest possible connections to the decoupling capacitors and connects the ground end to the GND planeusing vias. The ADS8555 can use an external or internal voltage reference. This reference can be selected bychanging the position of JP06 to INT for internal or EXT for external. Figure 2-1 also shows the analog inputsignal and digital signal connections.

49.9R81

49.9R82

49.9R83

DB0/SEL_A DB1/SEL_B DB2/SEL_C DB3/DCIN_CDB4/DCIN_BDB5/DCIN_ADB6/SCLK

DB7/HBEN/DCEN DB8/SDO_A DB9/SDO_B DB10/SDO_CDB11DB12DB13/SDIDB14/REFBUFEN

DB15

49.9R84

49.9R85

49.9R86

49.9R87

49.9R88

49.9R89

49.9R90

49.9R91

49.9R92

49.9R93

49.9R94

49.9R95

49.9R96

DB0/SEL_A 17

DB1/SEL_B 16

DB2/SEL_C 15

DB3/DCIN_C14

DB4/DCIN_B13

DB5/DCIN_A12

DB6/SCLK11

DB7/HBEN/DCEN 10

DB8/SDO_A 7

DB9/SDO_B 6

DB10/SDO_C5

DB114

DB123

DB13/SDI2

DB14/REFBUFEN 1

DB1564

CONVST_A23

CONVST_B22

CONVST_C21

CH_A0 33

CH_A1 36

CS/FS 19

RD20

STBY24

BUSY/INT18

HW/SW 62

PAR/SER 61

RANGE/XCLK27

REFEN/WR63

REFIO 51

RESET 28

WORD/BYTE 29

CH_B0 39

CH_B1 42

CH_C0 45

CH_C1 48

REFC_A54

REFC_B56

REFC_C58

ADS8555SPMR

U2A

49.9R80 49.9

R79 49.9R78

49.9R77 49.9

R76 49.9R75 49.9

R74 49.9R73 49.9

R72 49.9R71 BUSY/INT

HW/SW REFEN/WRSTBY

CS/FS

~RD WORD/BYTE PAR/SER

RESET

RANGE/XCLKCH_A0

CH_B0

CH_C0

CH_A1

CH_B1

CH_C1

AVDD26

AVDD34

AVDD35

AVDD40

AVDD41

AVDD46

AVDD47

AVDD50

AVDD60

BVDD9

HVDD31

AGND25

AGND32

AGND37

AGND38

AGND43

AGND44

AGND49

AGND52

AGND53

AGND55

AGND57

AGND59

BGND8

HVSS30

ADS8555SPMR

U2B

GND

AVDD

10uFC71

GND

GND

GND

10uFC72

10uFC73

49.9R97

49.9R98

49.9R99

CONVST_A

CONVST_B

CONVST_C

1µF C1

1µF C2

1µF C3

1µF C4

GND

1µF C5

1µF C6

GND

1µF C7

GND

HVSSHVDD

1µF C27

GND

GND

1µF C28

BVDD

GND

49.9R35 SCLK_RETURN

49.9R46 ~RD_RETURN

VIN 2

TEMP3

GND 4

TRIM/NR 5

VOUT6

REF5025AIDGKR

U6A

GND

0.22R48

EXT

10uFC38 GND

AVDD

1µF C37

TP8

VREF

0 R47

INT

1

2

3

JP06

100nF C39

GND

470nF 25V

C40

GND

Figure 2-1. ADC Signal and Supply Connection

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2.2 ADC Amplifier DriveFigure 2-2 shows the op amp configuration for each ADC drive input. The default configuration is a noninvertingbuffer configuration. The gain of this circuit can be adjusted by changing R03 and R02 as needed. C02 canbe used to limit the amplifier bandwidth or compensate the amplifier. R01 and C01 can also be used to createa low-pass filter. Jumper JP00 can be used to completely bypass the amplifier. This diagram only shows onechannel, but this circuit is repeated six times. For other channels, see Figure 7-2.

GND

HVDD

HVSS

GND

1.00k

R01

TP10

A0in

0

R03

1.00k

R02 DNP

GND

100pF

C02

DNP

1

2

3

JP00

TP9

A0

GND

GND

100nF

C03

100nF

C04

GND

CH_A0

1

2

3

4

5

OPA209AIDBVRU00

24.9

R04

1000pFC01

AM

P

BY

PS

1

2

3

4

5

J00

220pF

C05

Figure 2-2. Amplifier Drive Circuit

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3 Digital InterfaceAs noted in Section 1.1, the EVM interfaces with the PHI and communicates with the computer over theUSB. There are two devices on the EVM with which the PHI communicates: the ADS8555 ADC (over SPI orparallel) and the EEPROM (over I2C). The electrically erasable programmable read-only memory (EEPROM)comes preprogrammed with the information required to configure and initialize the ADS8555 platform. When thehardware is initialized, the EEPROM is no longer used.

3.1 Parallel InterfaceThe parallel interface signals are generated on the PHI controller and are connected through J2. Each of thesesignals has a 47-Ω resistor between the device and the controller to slow down the signal edges in order tominimize signal overshoot. The digital signals can be monitored on the J3, J4, and J5 test headers.

3.2 Serial Interface (SPI)The ADS8555 ADC uses SPI serial communication in mode 1 (CPOL = 0 and CPHA= 1). Because the serialclock (SCLK) frequency can be as fast as 36 MHz, the ADS8555EVM offers 47-Ω resistors between thecontroller and device to aid with signal integrity. Typically, in high-speed SPI communication, fast signal edgescan cause overshoot; these 47-Ω resistors slow down the signal edges in order to minimize signal overshoot.

3.3 I2C Bus and EEPROMThe circuit shown in Figure 3-1 is used with the EVM controller (PHI) for EVM identification. This circuit is notrequired by the ADS8555 for operation. The switch (S1) is write protected and does not need to be changed forEVM operation.

EVM_ID_SDA

EVM_ID_SCL

EVM_ID_PWR

GND

2

1

3

S110.0k

R101

100nF

C74

GND

EVM_ID_PWR

GND

0

R102 EVM_ID_WP

A01

A12

A23

VSS 4

SDA 5

SCL 6

WP7

VCC 8

U3

BR24G32FVT-3AGE2

Figure 3-1. I2C Bus and EEPROM

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3.4 Connections to the PHI ConnectorConnector J2 is used to connect the PHI digital controller printed circuit board (PCB) to the ADS8555EVM. Thisconnector has all the digital signals as well as the BVDD supply. The power for the BVDD supply is from theUSB connection. This connector also provides I2C signals that are used on the EEPROM identification circuit.The digital signals can be monitored on the J3, J4, and J5 test headers. Figure 3-2 provides a schematicshowing the various connections to the PHI connector.

10uF

C75

GND

BVDD

3.6V

D7

Zener

GND GND

1 1

3 3

5 5

7 7

9 9

1111

1313

1515

1717

1919

2121

2323

2525

2727

2929

3131

3333

3535

3737

3939

4141

4343

4545

4747

4949

5151

5353

5555

5757

5959

2 2

4 4

6 6

8 8

1010

1212

1414

1616

1818

2020

2222

2424

2626

2828

3030

3232

3434

3636

3838

4040

4242

4444

4646

4848

5050

5252

5454

5656

5858

6060

GND MP1

GND MP2

GND MP3

GND MP4

J2

QTH-030-01-L-D-A

EVM_ID_SDA

EVM_ID_SCL

EVM_ID_WP

DB3/DCIN_C

DB4/DCIN_B

DB0/SEL_A

DB1/SEL_B

DB6/SCLK

DB7/HBEN/DCEN

DB8/SDO_A

DB9/SDO_B

DB10/SDO_C

DB11

DB12

DB13/SDI

DB14/REFBUFEN

DB15

1 2

3 4

5 6

J5

TSW-103-07-G-D

PAR/SER

HW/SW

REFEN/WR

WORD/BYTE

STBY

~RD

CS/FS

BUSY/INT

RESET

RANGE/XCLK

DB2/SEL_C

DB5/DCIN_A

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15

17

19

21

23

25

27

29

31

16

18

20

22

24

26

28

30

32

J3

TSW-116-07-G-D

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15

17

19

16

18

20

J4

TSW-110-07-G-D

CONVST_A

CONVST_B

CONVST_C

GND

GND

GND

WORD/BYTE

CONVST_B

CS/FS

DB3/DCIN_C

DB4/DCIN_B

DB0/SEL_A

DB1/SEL_B

DB6/SCLK

DB7/HBEN/DCEN

DB8/SDO_A

DB9/SDO_B

DB10/SDO_C

DB11

DB12

DB13/SDI

DB14/REFBUFEN

DB15

DB2/SEL_C

DB5/DCIN_A

SCLK_RETURN

~RD

BUSY/INT

RESET

STBY

RANGE/XCLK

PAR/SER

~RD_RETURN

CONVST_C

CONVST_A

HW/SW

REFEN/WR

EVM_ID_PWR

BVDD

BVDD

100k

R55

100k

R56

100k

R57

100k

R50

100k

R49

TP1 5.5V

DNP

Figure 3-2. Connections to PHI Connector

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4 Power SuppliesThe ADS8555 device uses four power supplies: AVDD (5 V), BVDD (3.3 V), HVDD (12 V), and HVSS (–12 V).The two high-voltage power supplies require an external ±15-V supply and are connected on a screw terminalstrip (J1). The ±15-V supplies are regulated from ±15 V to ±12 V for HVDD and HVSS. The digital voltage supply(BVDD), is generated with the USB power. The analog supply (AVDD) is generated using the external 15-Vsupply and an LDO to generate 5 V.

4.1 External Power Connections and Test PointsThe screw terminal block J1 is used to connect the external high voltage supplies. These supplies are notprovided in the evaluation module kit and the expectation is that a low-noise lab supply is used to provide thispower (for example, Keysight™ E3632A). The high-voltage supplies have transient voltage suppressor diodes tohelp protect the ADC from transients. These supplies are typically connected to ±15 V. For details on operation,see the ADS8555 data sheet. Figure 4-1 also shows how each supply has a light-emitting diode (LED) monitorfor quick verification that power is applied.

Green

1

2

D4APT2012LZGCK

HVSS HVDD

GND GND

HVSSHVDD

AVDD

Green

1

2

D5APT2012LZGCK

GND

6.65k R20

AVDD

Green 1

2

D3APT2012LZGCK

BVDD

Green

1

2

D6APT2012LZGCK

GND

6.65k R30

BVDD

10.0k R18

10.0k R19

GND

D1

SMAJ15A

GND

D2

SMAJ15A

GND

10µF

C20

10µF

C26

-15V+15V

1

2

3

J1

Figure 4-1. External Power Connections and Test Points

4.2 Low-Dropout Regulator (TPS7A3001 for HVSS)As shown in Figure 4-2, the –15-V external power is connected to the TPS7A3001 LDO to generate –12 V. ThisLDO output can be programmed to different voltages by changing the feedback network R6 and R7. This LDOwas selected for low noise and flexibility.

OUT 1

FB2

NC3

GND 4

EN5

NR/SS 6

DNC 7

IN8

PAD 9

TPS7A3001DRBR

U4

-15V

GND

10.0k

R7

50V

10nF

C17

50V

10nF

C19

GND

25V

10uF

C16

GND

TP3

-15V

25V

10uF

C18

GND

0

R5

0

R4

HVSS

93.1k

R6

Figure 4-2. Low-Dropout Regulator (TPS7A3001 for HVSS)

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4.3 Low-Dropout Regulator (TPS7A4700 for AVDD, HVDD)The 15-V external power is connected to two LDOs (TPS7A4700RGWR). One LDO generates AVDD (5 V), andone generates HVDD (12 V). As shown in Figure 4-3, the TPS7A4700RGWR LDO output can be programmedto different voltages by installing or uninstalling the resistors connected on pins 4-12. This LDO was selected forlow noise and flexibility.

0 R16

0 R8

25V 22uF

C8

100k

R3

1µF 25V

C10

25V 10uF

C9

0 R17

DNP 0 R15

DNP 0 R10

0 R9

DNP

+15VTP2

+15V

0

R2

0

R1OUT

1

NC2

SENSE 3

6P4V2 4

6P4V1 5

3P2V6

GND 7

1P6V8

0P8V9

0P4V10

0P2V11

0P1V12

EN13

NR14

IN15

IN16

NC17

NC18

NC19

OUT 20

PAD 21

TPS7A4700RGWR

U1

GND

GND

GND

GND

0 R27

0 R26

DNP

HVDD

0 R40

DNP 0 R36

25V 22uF

C29

100k

R29

1µF 25V

C36

25V 10uF

C30

0 R45

DNP 0 R39

0 R38

DNP 0 R37

DNP

0

R28

0

R25 OUT

1

NC2

SENSE 3

6P4V2 4

6P4V1 5

3P2V6

GND 7

1P6V8

0P8V9

0P4V10

0P2V11

0P1V12

EN13

NR14

IN15

IN16

NC17

NC18

NC19

OUT 20

PAD 21

TPS7A4700RGWR

U5

GND

GND

GND

GND

AVDD+15V

Figure 4-3. Low-Dropout Regulator (TPS7A4700 for AVDD, HVDD)

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5 Installing the ADS8555EVM SoftwareDownload the latest version of the EVM GUI installer from the Tools and Software folder of the ADS8555EVMand run the GUI installer to install the EVM GUI software on your computer. Accept the license agreements andfollow the on-screen instructions shown in Figure 5-1 to complete the installation.

Figure 5-1. ADS8555 Software Installation Prompts

As a part of the ADS8555EVM GUI installation, a prompt with a Device Driver Installation (as shown in Figure5-2) appears on the screen. Click Next to proceed.

Figure 5-2. Device Driver Installation Wizard Prompts

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The ADS8555EVM requires the LabVIEW™ run-time engine and may prompt for the installation of this software,as shown in Figure 5-3, if not already installed.

Figure 5-3. LabVIEW™ Run-Time Engine Installation

Verify that C:\Program Files (x86)\Texas Instruments\ADS8555EVM is as shown in Figure 5-4 after theseinstallations.

Figure 5-4. ADS8555EVM GUI Folder Post-Installation

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6 ADS8555EVM OperationThis section provides step-by-step instructions for connecting the ADS8555EVM to the computer and evaluatingthe performance of the ADS8555.

6.1 Connecting the Hardware and Running the GUI1. Set the jumpers according to Section 6.2.2. Physically connect P2 of the PHI to J10 of the ADS8555EVM. Install the screws to assure a robust

connection.3. Connect the USB on the PHI to the computer first.

a. LED D5 on the PHI lights up, indicating that the PHI is powered up.b. LEDs D1 and D2 on the PHI start blinking to indicate that the PHI is booted up and communicating with

the PC; Figure 6-1 shows the resulting LED indicators.4. As shown in Figure 6-2, start the software GUI. Notice that the LEDs blink slowly when the FPGA firmware is

loaded on the PHI. This process takes a few seconds, afterwards the AVDD and DVDD power supplies turnon.

5. Connect the external ±15-V power supplies and GND to J1. This connection generates the AVDD, HVDD,and HVSS supplies (HVDD = 12 V, HVSS = –12 V, and AVDD = 5 V).

6. Connect the signal generator. The default input range is ±10 V (or 10 Vpk). A common input signal applied isa sinusoidal 1-kHz, 9.9-Vpk signal with a 0-V offset. This signal is adjusted just below the full-scale range toavoid clipping.

JP06

External/Internal

Vref configuration

JP00 t�JP05

Bypass amplifier

jumper

ADS8555EVM

PHI

Controler

Input signals

connected to first

two channels.

+15V, -15V, GND

External Supply

Test point

headers

Figure 6-1. ADS8555EVM Hardware Setup and LED Indicators

Select EVM GUI from

start menu, or

associated shortcut.

Figure 6-2. Launch the EVM GUI Software

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6.2 Jumper Settings for the ADS8555EVMThe amplifiers and reference can be configured with jumpers. The amplifier jumpers (JP00–JP05) determine ifthe amplifier is used or if an external signal is directly connected to the ADC input. JP06 is used to select eitherthe internal or external reference option. Make sure that the GUI configuration for the device reference matchesthe setting of JP06. The GUI software starts up in the internal reference mode, so make sure the JP06 is in theINT position. Table 6-1 lists the various jumper settings for the ADS8555EVM.

Table 6-1. Jumper SettingsJUMPER SETTING DEFAULT FUNCTIONJP00–JP05 AMP/BYPS AMP These eight jumpers determine if the amplifier is used to buffer the inputs signals

or if the amplifier is bypassed. Choosing AMP connects the amplifier between eachSMA connector (JP00–JP05) and the ADC input. The default amplifier configurationis noninverting (gain = 1 V/V). The amplifier gain configuration can be adjusted bysoldering and desoldering different resistors. Choosing the bypass configuration (BYPS)connects the SMA connectors directly to the ADC input.

JP06 INT/EXT INT This jumper selects either the internal or external mode on the voltage reference. Usingthe internal mode disconnects the external reference. Using the external mode connectsthe external REF5025 2.5-V reference to the ADC reference input. Make sure that theGUI settings for the voltage reference match the setting on this jumper.

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6.3 Modifying Hardware and Using Software to Evaluate Other Devices in the FamilyThe ADS8555 is part of a family of related devices. This EVM hardware and software support the entire familybecause all the devices are pin-for-pin compatible. The Table 6-2 lists other compatible devices in the family. Thefollowing procedure shows how to modify the hardware and software to evaluate the other devices in this family.

1. Desolder the ADS8555 and replace this device with the device you want to evaluate.2. Enable the EEPROM for writing. This process is done by changing switch S2 to the WR_EN (top) position

using tweezers. Figure 6-3 details this process.3. Connect the EVM and start the GUI as described in Figure 6-2.4. Under the Tools menu in Figure 6-4, select Load EEPROM to load the EEPROM according to the device that

is currently installed. When this procedure is successfully completed, the status bar at the top of the softwareupdates according to the device installed on the hardware.

Table 6-2. Compatible DevicesDEVICE RESOLUTION PARALLEL

DATA RATESERIAL DATARATE OTHER FEATURE

ADS8555 16 630 450 Does not have partial power-down mode

ADS8556 16 630 450 —

ADS8557 14 670 470 —

ADS8558 12 730 500 —

Use tweezers to change

position of switch S1

^WR_EN_�as shown to

allow the EPROM write

operation.

Figure 6-3. Enable EEPROM for Writing

1. On the ^tools_�menu

select ^load EEPROM_

2. Under ^Supported Devices_�

select the desired devices and

press ^Load EEPROM_X

3. After pressing ^load

EEPROM_�it will take a few

minutes to load the EEPROM.

4. The top of the status bar on the

software will indicate what the EVM

connected has been updated to.

Figure 6-4. Configure EEPROM and Software for the New Device




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6.4 EVM GUI Global Settings for ADC Control and RegistersFigure 6-5 shows the Register Map page. This page can only be accessed by selecting Software device mode.Editing the CONFIG_REG configures the different ranges and voltage references available on the ADS8555.See the ADS8555 data sheet for register field details. The left hand side of this GUI contains importantconfigurations such as interface selection, device mode, range selection, and sampling rate. These controlsare always available on the left hand side of the GUI regardless of which page is selected. Also, if Hardwaremode is used, the hardware input select pins on the device are set according the controls on the left hand side.For example, when in hardware mode if the Parallel Interface is selected, than the PAR/SER pin on the device isdriven low by the PHI to select parallel interface mode.

Select ^Software_�

mode to access the

^Register Map Config_

Select different

^Pages_�here.

Edit control

register contents

here.

Select serial or

parallel digital

interface.

Select sampling

rate.

Figure 6-5. EVM GUI Global Settings for ADC Control and Registers





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6.5 Time Domain DisplayThe time domain display tool allows visualization of the ADC response to a given input signal. This tool isuseful for both studying the behavior and debugging any gross problems with the ADC or drive circuits. Theuser can trigger a capture of the data of the selected number of samples from the ADS8555EVM, as per thecurrent interface mode settings indicated in Figure 6-6 by using the Capture button. The sample indices are onthe x-axis and there are two y-axes showing the corresponding output codes as well as the equivalent analogvoltages based on the specified reference voltage. Switching pages to any of the analysis tools described in thesubsequent sections causes calculations to be performed on the same set of data.

Figure 6-6. Time Domain Display




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6.6 Frequency Domain DisplayThe spectral analysis tool, shown in Figure 6-7, is intended to evaluate the dynamic performance (SNR, THD,SFDR, SINAD, and ENOB) of the ADS8555 ADC through single-tone sinusoidal signal fast Fourier transform(FFT) analysis using the 7-term Blackman-Harris window setting. The FFT tool includes windowing optionsthat are required to mitigate the effects of noncoherent sampling (this discussion is beyond the scope of thisdocument). The 7-term Blackman-Harris window is the default option and has sufficient dynamic range toresolve the frequency components of up to a 24-bit ADC. The None option corresponds to not using a window(or using a rectangular window) and is not recommended.

Figure 6-7. Frequency Domain Display





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6.7 Histogram DisplayNoise degrades ADC resolution and the histogram tool can be used to estimate effective resolution, whichis an indicator of the number of bits of ADC resolution losses resulting from noise generated by the varioussources connected to the ADC when measuring a DC signal. The cumulative effect of noise coupling to theADC output from sources such as the input drive circuits, the reference drive circuit, the ADC power supply,and the ADC itself is reflected in the standard deviation of the ADC output code histogram that is obtained byperforming multiple conversions of a DC input applied to a given channel. As shown in Figure 6-8, the histogramcorresponding to a DC input is displayed on clicking the Capture button.

Figure 6-8. Histogram Display




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7 Bill of Materials, Layout, and SchematicsThis section provides a bill of materials (BOM), a PCB layout for the ADS8555EVM, and schematics for theADS8555EVM.

7.1 Bill of MaterialsTable 7-1 lists the bill of materials (BOM) for the ADS8555EVM.

Table 7-1. Bill of Materials (BOM)DESIGNATOR QTY VALUE DESCRIPTION PART NUMBER MANUFACTURER!PCB 1 Printed circuit board ADS8555 Any

C1–C7, C10, C27, C28,C36, C37 12 1uF CAP, CERM, 1 uF, 25 V, +/-

10%, X7R, 0603 C0603C105K3RACTU Kemet

C01, C11, C21, C31, C41,C51 6 1000pF CAP, CERM, 1000 pF, 50 V,

+/- 5%, C0G/NP0, 0603 GRM1885C1H102JA01D MuRata

C03, C04, C13, C14, C23,C24, C33, C34, C43, C44,C53, C54

12 0.1uFCAP, CERM, 0.1 µF, 50 V,+/-10%, X7R, AEC-Q200 Grade1, 0603

C0603C104K5RACAUTO Kemet

C05, C15, C25, C35, C45,C55 6 220pF CAP, CERM, 220 pF, 50 V, +/-

5%, C0G/NP0, 0603 06035A221JAT2A AVX

C8, C29 2 22uF CAP, CERM, 22 uF, 25 V, +/-10%, X7R, 1210 GRM32ER71E226KE15L MuRata

C9, C16, C18, C30, C38,C71, C72, C73, C75 9 10uF CAP, CERM, 10 uF, 25 V, +/-

10%, X5R, 0805 CL21A106KAFN3NE Samsung Electro-Mechanics

C17, C19 2 0.01uF CAP, CERM, 0.01 µF, 50 V,+/-10%, X7R, 0603 885012206089 Wurth Elektronik

C20, C26 2 10uFCAP, CERM, 10 µF, 50 V,+/-10%, X7R, AEC-Q200 Grade1, 1206

CGA5L1X7R1H106K160AC TDK

C39, C74 2 0.1uF CAP, CERM, 0.1 uF, 50 V, +/-10%, X7R, 0603 C0603C104K5RACTU Kemet

C40 1 0.47uF CAP, CERM, 0.47 uF, 25 V, +/-10%, X7R, 0603 GRM188R71E474KA12D MuRata

D1, D2 2 15V Diode, TVS, Uni, 15 V, 24.4Vc, 400 W, 16.4 A, SMA SMAJ15A Littelfuse

D3–D6 4 Green LED, Green, SMD APT2012LZGCK Kingbright

D7 1 3.6V Diode, Zener, 3.6 V, 500 mW,SOD-123 MMSZ4685T1G ON Semiconductor

H1–H4 4Hex Standoff Threaded #4-40Aluminum 0.250" (6.35mm)1/4"

1891 Keystone

H5–H8 4 MACHINE SCREW PANPHILLIPS, 5/16", 4-40 PMSSS 440 0031 PH B&F Fastener Supply

H13, H14 2 Machine Screw Pan PHILLIPSM3 RM3X4MM 2701 APM HEXSEAL

H15, H16 2 ROUND STANDOFF M3STEEL 5MM 9774050360R Wurth Elektronik

J00–J05 6 SMA Straight Jack, Gold, 50Ohm, TH 901-144-8RFX Amphenol RF

J1 1 Terminal Block, 3.5mm Pitch,3x1, TH ED555/3DS On-Shore

Technology

J2 1 Header(Shrouded), 19.7mil,30x2, Gold, SMT QTH-030-01-L-D-A Samtec

J3 1 Header, 100mil, 16x2, Gold,TH TSW-116-07-G-D Samtec

J4 1 Header, 100mil, 10x2, Gold,TH TSW-110-07-G-D Samtec

J5 1 Header, 100mil, 3x2, Gold, TH TSW-103-07-G-D Samtec

www.ti.com Bill of Materials, Layout, and Schematics




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Table 7-1. Bill of Materials (BOM) (continued)DESIGNATOR QTY VALUE DESCRIPTION PART NUMBER MANUFACTURER

JP00–JP06 7 Header, 100mil, 3x1, Tin, TH PEC03SAAN Sullins ConnectorSolutions

R1, R2, R03, R4, R5, R13,R23, R25, R28, R33, R43,R53, R102

13 0 RES, 0, 5%, 0.1 W, AEC-Q200Grade 0, 0603 CRCW06030000Z0EA Vishay-Dale

R01, R11, R21, R31, R41,R51 6 1.00k RES, 1.00 k, 0.1%, 0.1 W,

0603 RT0603BRB071KL Yageo America

R3, R29 2 100k RES, 100 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 CRCW0603100KFKEA Vishay-Dale

R04, R14, R24, R34, R44,R54 6 24.9 RES, 24.9, 1%, 0.1 W, 0603 RC0603FR-0724R9L Yageo

R6 1 93.1k RES, 93.1 k, 1%, 0.1 W, 0603 RC0603FR-0793K1L Yageo

R7, R18, R19, R101 4 10.0k RES, 10.0 k, 1%, 0.1 W, 0603 RC0603FR-0710KL Yageo

R8, R10, R16, R27, R36,R39 6 0 RES, 0, 5%, 0.063 W, 0402 RC0402JR-070RL Yageo America

R20, R30 2 6.65k RES, 6.65 k, 1%, 0.063 W,AEC-Q200 Grade 0, 0402 CRCW04026K65FKED Vishay-Dale

R35, R46, R71– R99 31 49.9 RES, 49.9, 1%, 0.063 W, AEC-Q200 Grade 0, 0402 CRCW040249R9FKED Vishay-Dale

R47 1 0 RES, 0, 1%, 0.1 W, AEC-Q200Grade 0, 0603 RMCF0603ZT0R00 Stackpole Electronics

Inc

R48 1 0.22 RES, 0.22, 1%, 0.1 W, AEC-Q200 Grade 0, 0603 ERJ-3RQFR22V Panasonic

R49, R50, R55, R56, R57 5 100k RES, 100 k, 1%, 0.0625 W,0402 RC0402FR-07100KL Yageo America

S1 1 Switch, Slide, SPDT 100mA,SMT CAS-120TA Copal Electronics

SH-JP00–SH-JP06 7 1x2 Shunt, 100mil, Flash Gold,Black SPC02SYAN Sullins Connector

Solutions

TP2–TP23 22 Test Point, Miniature, Black,TH 5001 Keystone

U00–U05 6

2.2 nV/rtHz, 18 MHz,Precision, RRO, OperationalAmplifier, 4.5 to 36 V, -40to 125 degC, 5-pin SOT23(DBV5), Green (RoHS & noSb/Br)

OPA209AIDBVR Texas Instruments

U1, U5 2

36V, 1A, 4.17μVRMS,RF Low-Dropout (LDO)Voltage Regulator, RGW0020A(VQFN-20)

TPS7A4700RGWR Texas Instruments

U2 116 Bit Analog to DigitalConverter 6 Input 1 SAR 64-LQFP (10x10)

ADS8555SPMR Texas Instruments

U3 1 I2C BUS EEPROM (2-Wire),TSSOP-B8 BR24G32FVT-3AGE2 Rohm

U4 1

Vin -3V to -36V,-200mA, Ultra-Low-Noise,High-PSRR, Low-Dropout(LDO) Linear Regulator,DRB0008A (VSON-8)

TPS7A3001DRBR Texas Instruments

U6 1

3 µVpp/V Noise, 3ppm/°C Drift PrecisionSeries Voltage Reference,DGK0008A (VSSOP-8)

REF5025AIDGKR Texas Instruments

C02, C12, C22, C32, C42,C52 0 100pF CAP, CERM, 100 pF, 50 V, +/-

5%, C0G/NP0, 0603 885012006057 Wurth Elektronik

Bill of Materials, Layout, and Schematics www.ti.com



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Table 7-1. Bill of Materials (BOM) (continued)DESIGNATOR QTY VALUE DESCRIPTION PART NUMBER MANUFACTURER

FID1, FID2, FID3 0 Fiducial mark. There is nothingto buy or mount. N/A N/A

R02, R12, R22, R32, R42,R52 0 1.00k RES, 1.00 k, 0.1%, 0.1 W,

0603 RT0603BRB071KL Yageo America

R9, R15, R17, R26, R37,R38, R40, R45 0 0 RES, 0, 5%, 0.063 W, 0402 RC0402JR-070RL Yageo America

TP1 0 Test Point, Miniature, Black,TH 5001 Keystone





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7.2 Board LayoutFigure 7-1 shows the PCB layout for the ADS8555EVM.

Figure 7-1. Board Layout




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7.3 SchematicsFigure 7-2 shows a schematic for the amplifier drive section of the ADS8555EVM. The amplifier is by default a buffer and can be bypassed by using ajumper.

GND

HVDD

HVS S

GND

1.00k

R01

TP10

A0in

0

R03

1.00k

R02 DNP

GND

100p F

C02

DNP

1

2

3

JP0 0

TP9

A0

GND

GND

100n F

C03

100n F

C04

GND

GND

HVDD

HVS S

GND

1.00k

R11

TP12

A1in

0

R13

1.00k

R12 DNP

GND

100p F

C12

DNP

1

2

3

JP0 1TP11

A1

GND

GND

100n F

C13

100n F

C14

GND

GND

HVDD

HVS S

GND

1.00k R21

TP18

B0in

0

R23

1.00k

R22 DNP

GND

100p F

C22

DNP

1

2

3

JP0 2

TP17

B0

GND

GND

100n F

C23

100n F

C24

GND

GND

HVDD

HVS S

GND

1.00k R31

TP20

B1in

0

R33

1.00k

R32 DNP

GND

100p F

C32

DNP

1

2

3

JP0 3

TP19

B1

GND

GND

100n F

C33

100n F

C34

GND

GND

HVDD

HVS S

GND

1.00k R41

TP14

C0in

0

R43

1.00k R42

DNP

GND

100p F

C42

DNP

1

2

3

JP0 4

TP13

C0

GND

GND

100n F

C43

100n F

C44

GND

GND

HVDD

HVS S

GND

1.00k R51

TP16

C1in

0

R53

1.00k R52

DNP

GND

100p F

C52

DNP

1

2

3

JP0 5

TP15

C1

GND

GND

100n F

C53

100n F

C54

GND

CH_A0

CH_A1

CH_B0

CH_B1

CH_C0

CH_C1

1

2

3

4

5

OPA209 AIDBVRU00

1

2

3

4

5

OPA209 AIDBVRU01

1 2

3

4 5

OPA209 AIDBVRU02

1

2

3

4

5

OPA209 AIDBVRU03

1

2

3

4

5

OPA209 AIDBVRU04

1

2

3

4

5

OPA209 AIDBVRU05

24.9

R04

24.9

R14

24.9

R24

24.9

R34

24.9

R54

24.9

R44

1000 pFC01

1000 pFC11

1000 pFC21

1000 pFC31

1000 pFC41

1000 pFC51

AM

P

BY

PS

BY

PS

BY

PS

BY

PS

BY

PS

BY

PS

AM

P

AM

P

AM

P

AM

P

AM

P

1

2

3

4

5

J02

1

2

3

4

5

J01

1

2

3

4

5

J00

1

2

3

4

5

J03

1

2

3

4

5

J04

1

2

3

4

5

J05

220p F

C05

220p F

C15

220p F

C25

220p F

C35

220p F

C45

220p F

C55

Figure 7-2. Amplifier Drive Schematic





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Figure 7-3 shows the LDOs used to generate the AVDD, HVDD, and HVSS supplies.

0 R16

0 R8

25V 22uF

C8

100k

R3

1µF 25V

C10

25V 10uF

C9

0 R17

DNP 0 R15

DNP 0 R10

0 R9

DNP

+15 VTP2

+15 V

0

R2

0

R1OUT 1

NC 2

SENSE 3

6P4V2 4

6P4V1 5

3P2V6

GND 7

1P6V8

0P8V9

0P4V10

0P2V11

0P1V12

EN13

NR 14

IN15

IN16

NC 17NC 18NC 19

OUT 20

PAD 21

TPS7A47 00RGWR

U1

GND

D1

SMAJ15 A

GND

D2

SMAJ15 A

GND

10µ F

C20

10µ F

C26

Gree n

1

2

D4APT2012LZGCK

HVSS HVDD

GND GND

HVSSHVDD

AVDD

Gree n

1

2

D5APT 2012LZ GCK

GND

6.65 k R20

AVDD

Gree n 1

2

D3APT2012LZGCK

OUT 1

FB 2

NC3 GND 4

EN5

NR/SS 6

DNC 7

IN8

PAD 9

TPS7A30 01DRBR

U4

-15V

GND

10.0 k R7

50V 10nF

C17

50V 10nF

C19

GND

25V 10uF

C16

GND

TP3

-15V

25V 10uF

C18

GND

0

R5

0 R4

GND

GND

GND GND

0 R27

0 R26

DNP

HVDD

HVSS

-15V+15 V

1

2

3

J1

0 R40

DNP 0 R36

25V 22uF

C29

100k

R29

1µF 25V

C36

25V 10uF

C30

0 R45

DNP 0 R39

0 R38

DNP 0 R37

DNP

0

R28

0

R25 OUT 1

NC 2

SENSE 3

6P4V2 4

6P4V1 5

3P2V6

GND 7

1P6V8

0P8V9

0P4V10

0P2V11

0P1V12

EN13

NR 14

IN15

IN16

NC 17NC 18NC 19

OUT 20

PAD 21

TPS7A47 00RGWR

U5

GND

GND

GND GND

AVDD

BVDD

Gree n

1

2

D6APT2012LZGCK

GND

6.65 k R30

BVDD

93.1 k R6

TP21

GND

GND

TP22

GND

GND

TP23

GND

GND

+15 V

10.0 k R18

10.0 k R19

Figure 7-3. LDO Schematic




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Figure 7-4 shows the ADC decoupling, digital connections, and reference connections.

10u FC75

GND

49. 9R81

49. 9R82

49. 9R83

BVDD

3.6 V

D7Ze ner

EVM _ID_SDA

EVM _ID_SCL

EVM_ID_PWR

GND

2

1

3

S110. 0k R101

100 nF

C74

GND

EVM_ID_PWR

GND

0 R102 EVM _ID_WP

DB0/SEL_ A DB1/SEL_ B DB2/SEL_ C DB3/DCIN_CDB4/DCIN_BDB5/DCIN_ADB6/SCL K

DB7/HBEN/DCEN DB8/SDO _A DB9/SDO _B DB10/SDO_C

DB11DB12DB13/SDIDB14/REFBUFEN

DB15

49. 9R84

49. 9R85

49. 9R86

49. 9R87

49. 9R88

49. 9R89

49. 9R90

49. 9R91

49. 9R92

49. 9R93

49. 9R94

49. 9R95

49. 9R96

DB0/SEL_A 17

DB1/SEL_B 16

DB2/SEL_C 15

DB3/DCIN_C14

DB4/DCIN_B13

DB5/DCIN_A12

DB6/SCLK11

DB7/HBEN/DCEN 10

DB8/SDO_A 7

DB9/SDO_B 6

DB10/SDO_C5

DB114

DB123

DB13/SDI2

DB14/REFBUFEN 1

DB1564

CONVST_A23

CONVST_B22

CONVST_C21

CH_A0 33

CH_A1 36

CS/FS 19

RD20

STBY24

BUSY/INT18

HW/SW 62

PAR/SER 61

RANGE/XCLK27

REFEN/WR63

REFIO 51

RESET 28

WORD/BYTE 29

CH_B0 39

CH_B1 42

CH_C0 45

CH_C1 48

REFC_A54

REFC_B56

REFC_C58

ADS85 55SPM R

U2A

GND GND

1 1

3 3

5 5

7 7

9 9

11 11

13 13

15 15

17 17

19 19

21 21

23 23

25 25

27 27

29 29

31 31

33 33

35 35

37 37

39 39

41 41

43 43

45 45

47 47

49 49

51 51

53 53

55 55

57 57

59 59

2 2

4 4

6 6

8 8

1010

1212

1414

1616

1818

2020

2222

2424

2626

2828

3030

3232

3434

3636

3838

4040

4242

4444

4646

4848

5050

5252

5454

5656

5858

6060

GND MP1

GND MP2 GND MP3

GND MP4

J2

QTH-030-01-L-D-A

EVM _ID_SDAEVM _ID_SCL

EVM _ID_WP

DB3/DCIN_CDB4/DCIN_B

DB0/SEL_ A DB1/SEL_ B

DB6/SCL KDB7/HBEN/DCEN DB8/SDO _A DB9/SDO _B DB10/SDO_C

DB11DB12DB13/SDIDB14/REFBUFEN

DB15

49. 9R80 49. 9

R79 49. 9R78

49. 9R77 49. 9

R76 49. 9R75 49. 9

R74 49. 9R73 49. 9

R72 49. 9R71 BUSY/INT

HW/SW REFEN/WRSTBY

CS/FS

~RD WORD/BYTE PAR/SER

1 2 3 4 5 6

J5

TSW-103-07-G-D

PAR/SER HW/SW REFEN/WR

WORD/BYTE

STBY

~RD CS/FS BUSY/INT

RESET

RESET

RANG E/XCLK

RANG E/XCLK

DB2/SEL_ C

DB5/DCIN_A

1 2 3 4 5 6 7 8 9 10

11 1213 14151719212325272931

161820222426283032

J3

TSW-116-07-G-D

CH_A0

CH_B0

CH_C0

CH_A1

CH_B1

CH_C1

AVDD26

AVDD34

AVDD35

AVDD40

AVDD41

AVDD46

AVDD47

AVDD50

AVDD60

BVDD9

HVDD31

AGND25

AGND32

AGND37

AGND38

AGND43

AGND44

AGND49

AGND52

AGND53

AGND55

AGND57

AGND59

BGND8

HVSS30

ADS85 55SPM R

U2B

GND

AVDD

10u FC71

GND

GND

GND

10u FC72

10u FC73

49. 9R97

49. 9R98

49. 9R99

CONVST_A

CONVST_B

CONVST_C

1 2 3 4 5 6 7 8 9 10

11 1213 14151719

161820

J4

TSW-110-07-G-D

CONVST_ACONVST_BCONVST_C

GND

GND

GND

1µ F C1

1µ F C2

1µ F C3

1µ F C4

GND

1µ F C5

1µ F C6

GND

1µ F C7

WORD/BYTE

CONVST_B

CS/FS

DB3/DCIN_CDB4/DCIN_B

DB0/SEL_ A DB1/SEL_ B

DB6/SCL KDB7/HBEN/DCEN DB8/SDO _A DB9/SDO _B DB10/SDO_CDB11DB12DB13/SDIDB14/REFBUFEN

DB15

DB2/SEL_ C

DB5/DCIN_A

SCLK_ RET URN

~RD

BUSY/INT

RESET

STBYRANG E/XCLK

PAR/SER

~RD_RETURN

CONVST_C

CONVST_A

HW/SW

REFEN/WR

GND

HVSSHVDD

1µ F C27

GND

GND

1µ F C28

BVDD

GND

49. 9R35 SCLK_ RETURN

EVM_ID_PWR

49. 9R46 ~RD_RETURN

VIN 2

TEMP3 GND 4

TRIM/NR 5 VOUT 6

REF502 5AIDG KR

U6A

GND

0.2 2R48

EXT

10u FC38 GND

AVDD

1µ F C37

TP 8 VREF

0 R47

INT

1

2

3

JP06

100 nF C39

GND

470 nF 25V

C40

GND

BVDD

BVDD

100 kR55

100 kR56

100 kR57

100 kR50

100 kR49

TP 1 5.5 V

DNP

A01

A12

A23

VSS 4 SDA 5

SCL 6

WP 7

VCC 8

U3

BR24G32 FVT-3AGE2

Figure 7-4. ADC, Reference, and Digital I/O Schematic





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8 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (November 2009) to Revision A (May 2021) Page• Changed entire document because of substantial changes in EVM hardware and software.............................1

Revision History www.ti.com



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STANDARD TERMS FOR EVALUATION MODULES1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or

documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordancewith the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility

evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are notfinished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. Forclarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditionsset forth herein but rather shall be subject to the applicable terms that accompany such Software

1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or productionsystem.

2 Limited Warranty and Related Remedies/Disclaimers:2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License

Agreement.2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM

to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused byneglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that havebeen altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specificationsor instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality controltechniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.

2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or creditUser's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warrantyperiod to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair orreplace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall bewarranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) daywarranty period.

WARNINGEvaluation Kits are intended solely for use by technically qualified,professional electronics experts who are familiar with the dangers

and application risks associated with handling electrical mechanicalcomponents, systems, and subsystems.

User shall operate the Evaluation Kit within TI’s recommendedguidelines and any applicable legal or environmental requirementsas well as reasonable and customary safeguards. Failure to set up

and/or operate the Evaluation Kit within TI’s recommendedguidelines may result in personal injury or death or propertydamage. Proper set up entails following TI’s instructions for

electrical ratings of interface circuits such as input, output andelectrical loads.

NOTE:EXPOSURE TO ELECTROSTATIC DISCHARGE (ESD) MAY CAUSE DEGREDATION OR FAILURE OF THE EVALUATIONKIT; TI RECOMMENDS STORAGE OF THE EVALUATION KIT IN A PROTECTIVE ESD BAG.

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3 Regulatory Notices:3.1 United States

3.1.1 Notice applicable to EVMs not FCC-Approved:FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or softwareassociated with the kit to determine whether to incorporate such items in a finished product and software developers to writesoftware applications for use with the end product. This kit is not a finished product and when assembled may not be resold orotherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the conditionthat this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit mustoperate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:

CAUTIONThis device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may notcause harmful interference, and (2) this device must accept any interference received, including interference that may causeundesired operation.Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority tooperate the equipment.

FCC Interference Statement for Class A EVM devicesNOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 ofthe FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment isoperated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if notinstalled and used in accordance with the instruction manual, may cause harmful interference to radio communications.Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required tocorrect the interference at his own expense.

FCC Interference Statement for Class B EVM devicesNOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 ofthe FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residentialinstallation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordancewith the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interferencewill not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, whichcan be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or moreof the following measures:

• Reorient or relocate the receiving antenna.• Increase the separation between the equipment and receiver.• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.• Consult the dealer or an experienced radio/TV technician for help.

3.2 Canada3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247

Concerning EVMs Including Radio Transmitters:This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:(1) this device may not cause interference, and (2) this device must accept any interference, including interference that maycause undesired operation of the device.

Concernant les EVMs avec appareils radio:Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitationest autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doitaccepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.

Concerning EVMs Including Detachable Antennas:Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna typeand its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary forsuccessful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna typeslisted in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibitedfor use with this device.

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Concernant les EVMs avec antennes détachablesConformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type etd'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillageradioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotroperayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Leprésent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans lemanuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antennenon inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation del'émetteur

3.3 Japan3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に

輸入される評価用キット、ボードについては、次のところをご覧ください。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page

3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certifiedby TI as conforming to Technical Regulations of Radio Law of Japan.

If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow theinstructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):1. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal

Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule forEnforcement of Radio Law of Japan,

2. Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect toEVMs, or

3. Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japanwith respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please notethat if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.

【無線電波を送信する製品の開発キットをお使いになる際の注意事項】開発キットの中には技術基準適合証明を受けていないものがあります。技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用

いただく。2. 実験局の免許を取得後ご使用いただく。3. 技術基準適合証明を取得後ご使用いただく。

なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。日本テキサス・イ

ンスツルメンツ株式会社東京都新宿区西新宿６丁目２４番１号西新宿三井ビル

3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page

3.4 European Union3.4.1 For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):

This is a class A product intended for use in environments other than domestic environments that are connected to alow-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment thisproduct may cause radio interference in which case the user may be required to take adequate measures.

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4 EVM Use Restrictions and Warnings:4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT

LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling

or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety informationrelated to, for example, temperatures and voltages.

4.3 Safety-Related Warnings and Restrictions:4.3.1 User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user

guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable andcustomary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to inputand output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, orproperty damage. If there are questions concerning performance ratings and specifications, User should contact a TIfield representative prior to connecting interface electronics including input power and intended loads. Any loads appliedoutside of the specified output range may also result in unintended and/or inaccurate operation and/or possiblepermanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting anyload to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuitcomponents may have elevated case temperatures. These components include but are not limited to linear regulators,switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using theinformation in the associated documentation. When working with the EVM, please be aware that the EVM may becomevery warm.

4.3.2 EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with thedangers and application risks associated with handling electrical mechanical components, systems, and subsystems.User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronicand/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safelylimit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility andliability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors ordesignees.

4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes allresponsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility andliability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and localrequirements.

5. Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurateas possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites asaccurate, complete, reliable, current, or error-free.

6. Disclaimers:6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT

LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALLFAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUTNOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESSFOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADESECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.

6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BECONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL ORINTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THEEVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY ORIMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.

7. USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITSLICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANYHANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLYWHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGALTHEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.

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8. Limitations on Damages and Liability:8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,

INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESETERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OFSUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL ORREINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING,OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OFUSE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TIMORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HASOCCURRED.

8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDEDHEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR INCONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAREVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARECLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.

9. Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not ina resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicableorder, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),excluding any postage or packaging costs.

10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating tothese terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive reliefin any United States or foreign court.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2019, Texas Instruments Incorporated

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IMPORTANT NOTICE AND DISCLAIMERTI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCEDESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANYIMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRDPARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriateTI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicablestandards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants youpermission to use these resources only for development of an application that uses the TI products described in the resource. Otherreproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third partyintellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available eitheron ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’sapplicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2021, Texas Instruments Incorporated

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