Ginsburg/Ogunnika 6.376 Final Presentation 1

Adjustable Linear Range Operational Transconductance Amplifier with Noise Compensation

• Overall topology– Basic WLR with bulk drive, gate degeneration, source degeneration

– Variable gain amplifier between drain and gate of the source degeneration transistor to lower source degeneration

– Gate of input transistor driven with a weighted sum of its drain (for gate degeneration) and the input voltage

– Current steering sets the VL and is compensated to keep noise low

• Theoretical linear range:– Actual linear range varies

from 73mV to 1.25 V

• N varies from 5.5 to 13.7

Brian Ginsburg, Muyiwa Ogunnika

np

tLt V

11

122

Ginsburg/Ogunnika 6.376 Final Presentation 2

Block Diagram

)1(1

1

2A

AA

V nptL

0<A<1

gmb +

+

gm

A1-A

Vin

gs

1/gmn

-A/gmp

gmp+

2ngv

iout

2nsv

Ginsburg/Ogunnika 6.376 Final Presentation 3

Variable Linear Range Performance

• Linear range varies from 73mV to 1.248V

• Each OTA has 45 transistors

• Common mode input range is from 1.25V to 3 V at highest current levels; increases to 0.85V-3V at low bias current levels

• In resonant filter, f90 can vary from 100Hz to 10kHz, and Q can be variable from 1 to 6, though not for all VL

-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0

pvin ()

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0.6

Cu

rre

nt (

uA

)

i(vout)

AwrlaTest

Ginsburg/Ogunnika 6.376 Final Presentation 4

Stability of the OTA

• No load capacitor• 1kHz bandwidth• 100mV linear range• Unity-gain feedback• <5% overshoot in step

response• OTA also stable with 10%

component mismatch• Power with 5pF cap and

10kHz bandwidth <3.47μW 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Time (ms)

1.80

1.85

1.90

1.95

2.00

2.05

2.10

Vo

ltag

e (

V)

v(vin)v(vout)

agmCFilter

Ginsburg/Ogunnika 6.376 Final Presentation 5

Circuit Details

Variable Gain Amplifier

Vcmb

VonVop

Vin Vip

Vcmb

vtailsd

I=5uA

I=5uA

L='6*l'

M=pmsd

W='12*l'L='6*l'

M=pmsd

W='12*l'

L='6*l'

M=2

W='12*l'

L='6*l'

M=2

W='12*l'

L='6*l'

M=2

W='12*l'

I=5uA

2IBSks

ILVLks ILVLks

Ap

nVGA

1Gain

Gate Drive Weighted Adder

vtailvld vtailvli

Ap

AnBp

Bn

SpSn

L='6*l'

M=3

W='12*l'L='6*l'

M=3

W='12*l'L='6*l'

M=3

W='12*l'L='6*l'

M=3

W='12*l'

L='3*l'

M=2

W='12*l'

L='3*l'

M=2

W='12*l'

I=5uA I=5uAIHVLkg ILVLkg

INGDn

pInGate VAAVV )1(

HVLLVLBS III

BS

LVL

BS

HVL

I

I

I

IA 1

Ginsburg/Ogunnika 6.376 Final Presentation 6

Noise Impact of VL Variation

• Observations– For fixed VL, as IB drops, noise improves for fixed

IBS

– As VL decreases, noise shoots up

• Solutions– For fixed VL, have IBS=kbIB

– Make kb inversely dependent on VL

– IBS=(1+6(1-A))IB/20– Power overhead varies from 30% to 130%

2

4

AAkI

IN

p

nn

gBS

BG

Effective number of noise sources from gate drive circuit:

Theoretical N vs. VL

Actual N vs. VL

Dashed: Fixed kb

Solid: Variable kb

• At Q=2, 10kHz– VL=1.25, N=5.4– 21.3μW

• 0.4dB variation from unity in passband, >50dB attenuation at high frequencies

Ginsburg/Ogunnika 6.376 Final Presentation 7

Final Layout

• Fits in less than one quarter of the chip!

• Most of the additional circuitry is kept very small

• Conclusions• Questions