adc - a 10bit 100msps adc with folding interpolation and analog encoding -thesis

December 1993

FFFFFINALINALINALINALINAL R R R R REPOREPOREPOREPOREPORTTTTT

William T. ColleranIntegrated Circuits & Systems LaboratoryElectrical Engineering DepartmentUniversity of CaliforniaLos Angeles, CA 90095-1594

Funded by TRW Electronics Systems Group, TRW LSI Products Group,and the State of California MICRO Program.

A 10-bit, 100 MS/s A/D Converterusing Folding, Interpolation,

and Analog Encoding

vii

Table of Contents

Chapter 1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 Applications for High-Speed Low-Power A/D Converters . . . . . . . . . . . . . . .3

1.1.1 Ultrasound Imaging Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.1.2 High–Definition Television . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.1.3 Radar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.1.4 Digital Sampling Oscilloscopes . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.2 Design Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.2.1 SHPi Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

1.3 General Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

1.3.1 Terminology and Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

1.3.2 Quantization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

1.3.3 Fundamental Limits to Performance . . . . . . . . . . . . . . . . . . . . . . . .63

References 77

Chapter 2

Pipelined Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

2.1 Architectural Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

2.1.1 Flash Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

2.1.2 Feedback or Multi-pass Converters . . . . . . . . . . . . . . . . . . . . . . . .81

2.1.3 Feedforward Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

2.1.4 Pipelined Feedforward Converters . . . . . . . . . . . . . . . . . . . . . . . . .85

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2.1.5 Folding Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

2.1.6 Algorithmic (Cyclic) Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

2.1.7 Architecture Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

2.2 10–Bit High–Speed Converter Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

2.2.1 Timing Scheme for Pipelined Converter . . . . . . . . . . . . . . . . . . . . 94

2.3 Pipelined Feedforward Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

2.3.2 Hardware Complexity (Parts and Power) . . . . . . . . . . . . . . . . . . . 98

2.3.3 Performance (Yield and SNR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

References 107

Chapter 3

Sample-and-Hold Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

3.1 Sampling Bridge Topology and Operation . . . . . . . . . . . . . . . . . . . . . . . . 116

3.2 Error Sources in Diode Sampling Bridges . . . . . . . . . . . . . . . . . . . . . . . . . 125

3.2.1 Aperture Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

3.2.2 Small–Signal Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

3.2.3 Preamplifier Track–Mode Distortion . . . . . . . . . . . . . . . . . . . . . . 133

3.2.4 Diode Bridge Track–Mode Distortion . . . . . . . . . . . . . . . . . . . . . . 141

3.2.5 Finite Aperture Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

3.2.6 Hold Pedestal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

3.2.7 Feedthrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

3.2.8 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

3.2.9 Droop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

3.2.10 Thermal Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

3.3 Track-and-Hold Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

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3.3.1 Preamplifier and Sampling Bridge . . . . . . . . . . . . . . . . . . . . . . . .195

3.3.2 Postamplifier Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

3.3.3 Clock Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

3.3.4 Design Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

3.4 Interstage Track–and–Hold Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

References 212

Chapter 4

Coarse Quantizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

4.1 4-Bit Flash Quantizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

4.1.1 Differential Reference Ladder . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

4.1.2 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221

4.1.3 Layout and DAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

References 224

Chapter 5

Digital–to–Analog Converter and Residue Amplifier . . . . . . . . . . . .229

5.1 Segmented Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

5.2 Effects of Mismatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231

5.3 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234

5.4 Residue Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236

References 239

Chapter 6

Folding Fine Quantizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

x

6.1 Concept of Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

6.1.1 Linear Folding Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

6.2 Sinusoidal Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

6.2.2 Sinusoidal Folding Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

6.3 Non-uniform Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

6.4 Folding and Interpolating A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . 256

6.4.1 Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

6.4.2 Cycle Pointer (Coarse Quantizer) . . . . . . . . . . . . . . . . . . . . . . . . 258

6.4.3 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

References 259

Chapter 7

Gain Stabilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

7.1 Gain Matching Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

7.2 Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

References 267

Chapter 8

Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

8.1 Circuit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

8.2 Test Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

8.3 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

References 284

xi

Chapter 9

8–Bit A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

9.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285

9.2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287

Chapter 10

Conclusions and Suggested Further Research . . . . . . . . . . . . . . . .301

10.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301

10.2 Further Research Opportunities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305

References 307

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309

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List of Figures

Figure 1.1. Examples of increasing DSP complexity in communications systems. (a)

A classical system with analog demodulator followed by baseband A/D

conversion and DSP. (b) Advanced system with IF A/D conversion using

digital demodulation and signal processing. (c) Emerging system with

RF A/D conversion followed by digital downconversion, demodulation,

and baseband signal processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Figure 1.2. Basic Reflection imaging system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 1.3. Phased array imaging system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 1.4. Current medical ultrasound imaging system utilizing one A/D converter

after the received signals have been delayed and summed. . . . . . . . . . . . . . . . . 6

Figure 1.5. Emerging medical ultrasound imaging system with an array of ADCs

with digital delays and summation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 1.6. A typical digital television system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 1.7. Proposed MUSE encoder system.Note the complexity of the digital cir-

cuitry following the A/D conversion consistent with the trend depicted in

figure 1.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 1.8. Typical phased array radar system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 1.9. Typical sampling oscilloscope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 1.10. A/D converter performance comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 1.11. Fill codes for SHPi mask layers. Layer names refer to those listed in ta-

ble 1.6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 1.12. Cross-section and plan view of minimum-size SHPi device. . . . . . . . . . . . . . . . 16

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Figure 1.13. Cross-section and plan view of SHPi device. . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 1.14. SHPi transistor model used for SPICE simulations. . . . . . . . . . . . . . . . . . . . . . .17

Figure 1.15. Track-and-hold terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 1.16. Quantizer transfer functions or quantization characteristics. (a) Uniform

quantizer. (b) Non-uniform quantizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 1.17. Unipolar (a) and bipolar (b) quantization characteristics. . . . . . . . . . . . . . . . . . .21

Figure 1.18. Ideal quantizer transfer functions. (a) Midtread characteristic. (b) Midris-

er characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 1.19. Quantizer notation, threshold and quantization levels. . . . . . . . . . . . . . . . . . . . .24

Figure 1.20. Quantization transfer functions including error sources (a) Offset error.

(b) Gain error. (c) Linearity error. (d) Missing codes.. . . . . . . . . . . . . . . . . . . . . .25

Figure 1.21. Quantizer models. (a) Nonlinear model. (b) Statistical model. . . . . . . . . . . . . . .27

Figure 1.22. Quantization noise models. (a) Ideal quantizer. (b) Quantizer with

threshold level errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 1.23. Distribution of quantization error.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 1.24. The functions, , and . By plotting the normalized versions,, and

versus the shapes of the above functions become independent of

. Also, equals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 1.25. NPR of ideal midriser quantizer with Gaussian noise input. Quantizer

resolution indicated on curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 1.26. Optimum loading factor and NPR for Gaussian noise input. . . . . . . . . . . . . . . . .39

Figure 1.27. The functions ,, and . By plotting the normalized versions,, and versus

the shapes of the above functions become independent of . . . . . . . . . . . . . . . .40

Figure 1.28. SNR of ideal midriser quantizer with sinusoidal input. Quantizer resolu-

xv

tion indicated on curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 1.29. SNR of ideal midriser quantizer plotted versus sinusoidal input ampli-

tude. Approximation is based upon equation 1.17.. . . . . . . . . . . . . . . . . . . . . . . 45

Figure 1.30. Difference between actual SNR and approximated SNR from figure

1.29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 1.31. The inverse cosine function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 1.32. The function for several values of n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 1.33. Harmonic levels for an ideal 8-bit midriser quantizer.. . . . . . . . . . . . . . . . . . . . . 55

Figure 1.34. Harmonic levels for an ideal 10-bit midriser quantizer.. . . . . . . . . . . . . . . . . . . . 56

Figure 1.35. Peak harmonic number versus analog input amplitude.. . . . . . . . . . . . . . . . . . . 57

Figure 1.36. Peak harmonic power for ideal midriser quantizer.. . . . . . . . . . . . . . . . . . . . . . . 58

Figure 1.37. The function evaluated at for peak harmonics. (lower) . (upper) . . . . . . . . . . . . 59

Figure 1.38. Harmonic levels for an 8-bit midriser quantizer with 1/4 LSB rms thresh-

old errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 1.39. Thermal limit to achievable resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 1.40. Aperture uncertainty causes amplitude errors. . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 1.41. Maximum aperture jitter consistent with 1/2 LSB errors for various values

of resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 1.42. Maximum attainable resolution limited by aperture jitter. . . . . . . . . . . . . . . . . . . 67

Figure 1.43. Quantization error waveforms. (a) Ideal quantizer. (b) Quantizer with

threshold level errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 1.44. Segment of quantization error waveform with non-zero threshold

errors, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

xvi

Figure 1.45. Achievable resolution as limited by metastability errors. . . . . . . . . . . . . . . . . . . .76

Figure 2.1. Flash or parallel A/D converter topology.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Figure 2.2. Feedback or multi-pass A/D converter topology.. . . . . . . . . . . . . . . . . . . . . . . . .82

Figure 2.3. Successive approximation A/D converter topology. . . . . . . . . . . . . . . . . . . . . . .83

Figure 2.4. Feedforward A/D converter topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Figure 2.5. Pipelined A/D converter topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Figure 2.6. Folding A/D converter topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Figure 2.7. Algorithmic A/D converter topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Figure 2.8. Bit serial A/D converter topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Figure 2.9. SNR degradation in folding A/D converters due to mismatches. Quantiz-

er resolution indicated on plot.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Figure 2.10. Yield in folding A/D converters for 8 (lower) or 16 (upper) folds per stage.

is 64 mV (left) or 128 mV (right). The normalization of the independent

variable to INL refers to maximum specified INL above which point a

converter fails the performance test, e.g. if maximum specified INL is

1/2 LSB, and is 1/2 mV; then the appropriate value on the independent

axis for determining yield is 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Figure 2.11. Typical 2 stage pipelined A/D converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Figure 2.12. Alternative implementation of 2-stage pipelined A/D converter. . . . . . . . . . . . . .94

Figure 2.13. Conventional timing scheme for pipelined A/D converter. . . . . . . . . . . . . . . . . . .95

Figure 2.14. Output signals from converter elements in pipelined A/D employing con-

ventional timing scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

Figure 2.15. Modified timing scheme for pipelined A/D converter. . . . . . . . . . . . . . . . . . . . . .97

xvii

Figure 2.16. Output signals from converter elements in pipelined A/D employing

modified timing scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 2.17. Comparison of A/D converter complexity versus fine quantizer resolu-

tion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 2.18. 5-6 pipeline partitioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 2.19. 4-7 pipeline partitioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 2.20. 10 bit A/D converter yield (upper) and mean SNR (lower) versus

segmented DAC current source mismatch for both 4-7 and 5-6

partitioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Figure 2.21. 10 bit A/D converter yield (upper) and mean SNR (lower) versus coarse

quantizer INL for both 4-7 and 5-6 partitioning. . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 2.22. 10 bit A/D converter yield (upper) and mean SNR (lower) versus fine

quantizer INL for both 4-7 and 5-6 partitioning. . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 2.23. 10 bit A/D converter SNR (upper) and gain error (lower) versus DAC gain

error for both 4-7 and 5-6 partitioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Figure 2.24. 10 bit A/D converter SNR (upper) and gain error (lower) versus fine

quantizer gain error for both 4-7 and 5-6 partitioning. . . . . . . . . . . . . . . . . . . . 106

Figure 2.25. Histogram of A/D converter SNR for 4-7 (upper) and 5-6 (lower)

partitionings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Figure 2.26. Block diagram of selected A/D converter architecture.. . . . . . . . . . . . . . . . . . . 108

Figure 3.1. Track-and-hold building-blocks (a) and operation (b). . . . . . . . . . . . . . . . . . . . 116

Figure 3.2. Prototype diode bridge track-and-hold circuit with emitter follower

preamplifier and postamplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 3.3. Diode-bridge track-and-hold with differential pair controlling bridge

current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

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Figure 3.4. Diode-bridge switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Figure 3.5. Diode-bridge models in track mode. (a) Large-signal model. (b) Small-

signal model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

Figure 3.6. Diode bridge operation in track mode. (a) t. (b) . (c) . . . . . . . . . . . . . . . . . . . . .123

Figure 3.7. T/H topologies. (a) Single-ended. (b) Differential. . . . . . . . . . . . . . . . . . . . . . . .124

Figure 3.8. Aperture jitter gives rise to amplitude error.. . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Figure 3.9. SNR as limited by clock jitter and quantization noise. Quantizer resolu-

tion labelled on curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

Figure 3.10. Small-signal models of diode-bridge in track mode. (a) Full model. (b)

Simplified model when parallel networks are combined.. . . . . . . . . . . . . . . . . .131

Figure 3.11. Emitter follower preamplifier with capacitive load used to simulate dy-

namic distortion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

Figure 3.12. Simulated THD of the emitter follower preamplifier with capacitive load

versus load capacitance, , bias current, , amplitude, , and input frequen-

cy, . In each case, the parameter is varied in a 1, 2, 5, 10 pattern which

approximates exponential spacing (i.e. each value is about twice the

previous one) while maintaining integer values. . . . . . . . . . . . . . . . . . . . . . . . .135

Figure 3.13. Large-signal model of diode bridge in track mode with finite bias imped-

ances, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142

Figure 3.14. Diode bridge with current perturbations caused by dynamic current

into. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146

Figure 3.15. Linear, time-varying model of diode bridge and hold capacitor used for

finite aperture analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

Figure 3.16. Response of bridge current (a) and small-signal bridge resistance (b)

over finite aperture time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

xix

Figure 3.17. Frequency response induced by finite aperture time assuming a linear

small-signal bridge model. Upper curves represent frequency response

with constant bridge resistance, . Lower curves include the effect of

bridge turn-off governed by .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 3.18. Large-signal model for simulating finite aperture effects. . . . . . . . . . . . . . . . . . 153

Figure 3.19. Simulated THD due to finite aperture time as a function of input ampli-

tude, , input frequency, , aperture time, , and bridge slew rate, . Param-

eters are swept in a 1, 2, 5, 10 fashion to approximate an exponential

sweep with integer values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Figure 3.20. Charge injection at bridge turn-off gives rise to hold pedestal distortion.

(a) Typical bridge circuit showing auxiliary diodes which control bridge

bias voltages in hold mode. (b) Diode small-signal capacitance-voltage

characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Figure 3.21. Comparison between distortion due to hold pedestal predicted by anal-

ysis and simulation (upper); and between distortion predicted by simple

approximations and simulation (lower). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Figure 3.22. A bootstrapped bridge center-tap reduces hold pedestal distortion. (a)

Unity-gain buffer drives bridge center-tap from output node. (b) Diode C-

V characteristic still determines residual charge injection. . . . . . . . . . . . . . . . . 166

Figure 3.23. Diode-bridge track-and-hold with differential pair controlling bridge cur-

rent. Diodes D5 and D6 conduct during hold-mode while diodes D1

through D4 are cut-off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 3.24. Small-signal models of bridge in hold mode. (a) Model including all com-

ponents. (b) Equivalent model simplified through symmetry. . . . . . . . . . . . . . . 172

Figure 3.25. Small-signal frequency response of diode bridge in hold mode. . . . . . . . . . . . 174

Figure 3.26. Cross-coupled capacitors between complementary bridges reduce

feedthrough and hold pedestal error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Figure 3.27. Feedthrough versus cross-coupling capacitance normalized to optimum

xx

value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178

Figure 3.28. Cross-coupling scheme for reduced feedthrough with series connected

diodes as coupling elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178

Figure 3.29. Feedthrough versus area of cross-coupled diode structure normalized to

the optimum area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

Figure 3.30. Cross-coupling can partially cancel hold pedestal error by cancelling

charge expelled by bridge diodes during bridge turn-off. Note that charge

injection from a bridge diode connected to the top node of one bridge is

cancelled by the cross-coupled element connected to the bottom node

of the complementary bridge. Likewise, injection from a diode connected

to the bottom of one bridge is cancelled by the cross-coupled element

connected to the top of the complementary bridge. . . . . . . . . . . . . . . . . . . . . .180

Figure 3.31. Noise sources affecting track-and-hold operation. represents the total

jitter noise power on the drive signals to the diode bridge including the

jitter on the incoming clock and that added by the clock buffer circuitry.

represents the mean-square noise voltage at the hold capacitors. This is

an approximation assuming that the dominant component is thermal

noise and exists during both track mode and hold mode. causes base

shot noise which is integrated on the hold capacitor during hold mode

giving rise to voltage noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

Figure 3.32. Single-pole RC low pass filter for analysis of kT/C noise. . . . . . . . . . . . . . . . . .184

Figure 3.33. kT/C noise at the hold capacitors. In the differential implementation the

two independent sources contribute to the total noise power perturbing

the held voltage, resulting in doubled noise power compared to a single-

ended version. Signal amplitude is also doubled, thus quadrupling signal

power and increasing SNR by 3 dB over the single-ended case. . . . . . . . . . . .185

Figure 3.34. Base shot noise integrates on the hold capacitors during the hold interval

adding a noise component to the held voltage. . . . . . . . . . . . . . . . . . . . . . . . . .186

Figure 3.35. Postamplifier input bias current causes droop on hold capacitor. . . . . . . . . . . .187

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Figure 3.36. A differential T/H implementation largely cancels droop effects. . . . . . . . . . . . 189

Figure 3.37. Thermal contour of minimum-size SHPi device (2 µm X 8 µm emitter

area) dissipating 1 mW on a 250 µm thick substrate. . . . . . . . . . . . . . . . . . . . 191

Figure 3.38. Thermal contour of large device (75 µm X 75 µm emitter area) dissipat-

ing 200 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Figure 3.39. Emitter follower buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Figure 3.40. A single-ended T/H circuit based on a diode-bridge with emitter follower

preamplifier, differential pair current switch with resistive loads, and

emitter follower postamplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

Figure 3.41. A differential track-and-hold implementation with linearity compensa-

tion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Figure 3.42. Differential preamplifier and bridge with compensation. . . . . . . . . . . . . . . . . . . 198

Figure 3.43. Layout of differential preamplifier and diode bridge with feedforward

compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

Figure 3.44. Postamplifier implementations. (a) An operational amplifier connected

as a voltage follower. (b) A differential pair configured as a voltage fol-

lower. (c) A differential pair-based follower with enhanced perfor-

mance. (d) An open-loop unity-gain postamplifier with linearity

compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

Figure 3.45. Differential postamplifier implementation.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Figure 3.46. Layout of differential postamplifier with feedback bootstrapping. . . . . . . . . . . . 203

Figure 3.47. Clock buffer schematic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

Figure 3.48. Layout of first track-and-hold clock buffer circuit. . . . . . . . . . . . . . . . . . . . . . . . 205

Figure 3.49. Complete track-and-hold circuit (with postamplifier shaded). The clock

buffer has not been drawn for simplicity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

xxii

Figure 3.50. Layout of first track-and-hold circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

Figure 3.51. Simulated T/H output spectrum. Fs=100 Msps, Fin=43.75 MHz. . . . . . . . . . . .207

Figure 3.52. Second stage track-and-hold block diagram with feedback to bridge cen-

ter-tap nodes to reduce gain-loss due to hold pedestal error. . . . . . . . . . . . . . .208

Figure 3.53. Second track-and-hold with bootstrapped center-tap.. . . . . . . . . . . . . . . . . . . .209

Figure 3.54. Layout of second T/H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209

Figure 3.55. Interstage postamplifier schematic which provides high input imped-

ance and voltage gain of 2. Output emitter followers are not shown

for simplicity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210

Figure 3.56. Second T/H postamplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212

Figure 3.57. Second T/H with replica. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213

Figure 4.1. Flash or parallel A/D converter topology.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218

Figure 4.2. Differential reference ladder with comparators. . . . . . . . . . . . . . . . . . . . . . . . . .219

Figure 4.3. Differential reference ladder showing comparator input bias

currents.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220

Figure 4.4. Three dimensional depiction of differential reference ladder with compar-

ator connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

Figure 4.5. Interpolation between preamplifiers reduces loading on differential refer-

ence ladder and reduces power by halving the number of comparator

pre-amplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222

Figure 4.6. Differential reference ladder drawn to emphasize circular symmetry, and

including reference to interpolated thresholds in grey. . . . . . . . . . . . . . . . . . . .223

Figure 4.7. Coarse quantizer preamplifier array driven by differential reference lad-

der. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

xxiii

Figure 4.8. Coarse quantizer comparator with internal DAC current switch. . . . . . . . . . . . 226

Figure 4.9. Coarse quantizer latch array with current segment inputs and differential

DAC output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Figure 5.1. Fully-segmented current-output reconstruction DAC.. . . . . . . . . . . . . . . . . . . . 231

Figure 5.2. 10-bit yield for a fully-segmented DAC with 4 bit resolution versus cur-

rent segment mismatch assuming maximum INL is 1/2 LSB. . . . . . . . . . . . . . 232

Figure 5.3. 10 bit A/D converter yield (upper) and mean SNR (lower) versus

segmented DAC current source mismatch for both 4-7 and 5-6

partitioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

Figure 5.4. Segmented DAC current source array with scrambled wiring matrix at

top. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Figure 5.5. Segmented DAC current source array with common centroid

layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

Figure 5.6. Segmented DAC current source array with trimmable layout. . . . . . . . . . . . . . 237

Figure 5.7. Residue amplifier implementations. (a) Typical approach using

transconductance cell and subtracting currents at output. (b) Improved

approach subtracting currents at transconductor emitter. . . . . . . . . . . . . . . . . 238

Figure 5.8. Residue amplifier and its replicas. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Figure 6.1. Architecture of feedforward quantizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Figure 6.2. Folding A/D converter architecture. Analog folding with F folds reduces

fine quantizer resolution to . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Figure 6.3. Reduction in dynamic range seen be comparator array for (a) sawtooth

and (b) triangle folding characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Figure 6.4. Translinear-based current-mode folding circuit. . . . . . . . . . . . . . . . . . . . . . . . . 246

Figure 6.5. Current-mode folding circuit using cascodes.. . . . . . . . . . . . . . . . . . . . . . . . . . 247

xxiv

Figure 6.6. A folding function which is not piece-wise linear. The transfer function

shown is sinusoidal for convenience but could be any non-saturating,

periodic function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

Figure 6.7. An array of phase-shifted, non-linear folding blocks with comparators de-

tecting zero-crossings can circumvent the need for an inverse-sine

quantizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248

Figure 6.8. Linear superposition implements non-uniform interpolation to generate

multiple sinusoids equally-spaced in phase from two quadrature sinuso-

ids. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249

Figure 6.9. Translinear sinusoidal folding circuit with voltage drive. . . . . . . . . . . . . . . . . . .250

Figure 6.10. Translinear sinusoidal folding circuit with current drive. . . . . . . . . . . . . . . . . . .251

Figure 6.11. Folding circuit based upon hyperbolic tangent transfer function of volt-

age driven differential pairs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252

Figure 6.12. Folding circuit based on wired-OR interconnection. . . . . . . . . . . . . . . . . . . . . .253

Figure 6.13. Fully-differential sinusoidal folding circuit with differential reference lad-

der, overflow compensation, and common-mode de-bias circuitry.. . . . . . . . . .253

Figure 6.14. Differential non-uniform interpolation ladder generates sinusoids equally

spaced in phase from quadrature inputs. Distortion is minimized due to

symmetry of circuit enabling use of simple, low-power emitter follower

buffers.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254

Figure 6.15. (a) Differential non-uniform interpolation ladder. (b) Phasor representa-

tion of quadrature and interpolated signals. (c) Corresponding voltage

waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255

Figure 6.16. Threshold error at interpolated thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . .256

Figure 6.17. Folding, interpolating, and analog encoding fine quantizer using quadra-

ture folded waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257

xxv

Figure 6.18. Improved encoding scheme significantly reduces hardware complexity.

All circuits are differential but are shown single-ended for simplicity.. . . . . . . . 258

Figure 6.19. Cycle pointer incorporating analog encoding. Actual circuit is differential

but is shown single-ended for simplicity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

Figure 6.20. Layout of fine quantizer analog circuitry including differential reference

ladder, folding amplifiers, interpolation ladder, and analog multipliers

from the encoding block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Figure 7.1. Effects of component gain errors on A/D transfer function. (a) Effect of

fine quantizer gain error. (b) Effect of DAC gain error. . . . . . . . . . . . . . . . . . . . 264

Figure 7.2. 10 bit A/D converter SNR (upper) and gain error (lower) versus DAC gain

error for both 4-7 and 5-6 partitioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Figure 7.3. 10 bit A/D converter SNR (upper) and gain error (lower) versus fine

quantizer gain error for both 4-7 and 5-6 partitioning. . . . . . . . . . . . . . . . . . . . 266

Figure 7.4. Gain-matching replica circuits and feedback loops which adjust compo-

nent gains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Figure 8.1. 10-bit A/D converter with constituent components highlighted. Die size is

approximately 4 mm X 4 mm (160 mil X 160 mil). Analog input is at top,

left of chip. Digital outputs are at bottom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Figure 8.2. Die photograph of 10-bit A/D converter with nominal DAC layout. Un-

used area surrounding DAC degeneration resistors is reserved for use

in other ADC versions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

Figure 8.3. Die photograph of 10-bit A/D converter with common centroid recon-

struction DAC layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

Figure 8.4. Die photograph of 10-bit A/D converter with trimmable reconstruction

DAC layout.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Figure 8.5. A/D converter test setup. All synthesizers are phase-locked to one mas-

ter synthesizer. Pulse generator supplies ECL clock signal to DUT upon

xxvi

trigger from low phase-noise synthesized source. Four pulse generators

are used to supply clocks to DUT, but only one is shown for simplicity.

Off-chip reconstruction DAC is helpful for real-time debugging of system.

Digitized data is captured in fast, deep memory and analyzed on work-

station off-line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274

Figure 8.6. A/D converter test setup. Synthesizers, pulse generators, spectrum an-

alyzer, and filter bank are housed in rack on left. High-speed memory

and workstation are on right. Power supplies, oscilloscopes, and test fix-

tures are on bench in rear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275

Figure 8.7. Digital output spectrum from A/D converter when sampling a 5.87 MHz

sinusoidal input at 75 Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276







Figure 8.11. Differential linearity as measured by a histogram test with fin = 6MHz

and fs = 75Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .280

Figure 8.12. Integral linearity as measured by a histogram test with fin = 5.87MHz

and fs = 75Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281

Figure 8.13. Differential linearity as measured by a histogram test with fin = 49.6 MHz

and fs = 75 Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282

Figure 8.14. Integral linearity as measured by a histogram test with fin = 5.87 MHz

and fs = 75 Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283

Figure 8.15. Beat frequency test. fS = 75 Msps, fin = 37.501 MHz. ADC output is

decimated by 2 then applied to reconstruction DAC and displayed on os-

cilloscope. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284

xxvii

Figure 9.1. 8-bit A/D converter architecture. T/H derives from input T/H in 10-bit

ADC. Quantizer is based upon 7-bit fine quantizer, also from 10-bit con-

verter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

Figure 9.2. 8-bit A/D converter with overlays to indicate location of constituent com-

ponents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

Figure 9.3. Die photograph of 8-bit A/D converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

Figure 9.4. Measured SNR and harmonic distortion versus input frequency at

25 Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289


50 Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290


100 Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291


125 Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292


150 Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293


175 Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294


200 Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295


200 Msps with T = -40 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

Figure 9.12. Measured SNR and harmonic distortion versus input frequency at 25

Msps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

Figure 9.13. Measured SNR versus input frequency at several sample rates.. . . . . . . . . . . 298

xxviii

Figure 9.14. Measured integral linearity error versus power supply variation at sever-

al temperatures with fS = 100 Msps. Upper curves plot peak INL. Lower

curves plot RMS INL.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299

xxix

List of Tables

Table 1.1. Comparison of performance requirements for HDTV and medical ul-

trasound imaging applications along with design goals for this work. . . . . . . . . . 3

Table 1.2. Requirements for medical ultrasound imaging applications. . . . . . . . . . . . . . . . . 7

Table 1.3. Requirements for HDTV applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 1.4. Performance goals for this development. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 1.5. SHPi NPN characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 1.6. SHPi mask layers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 1.7. SHPi NPN transistor SPICE model parameters. . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 1.8. Optimum quantizer loading and NPR for Gaussian noise input. . . . . . . . . . . . . 38

Table 2.1. Comparison among several A/D converter architectures. . . . . . . . . . . . . . . . . . 89

Table 3.1. Bias voltages across bridge elements in track mode and hold

mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

xxxi

ACKNOWLEDGEMENTS

I am grateful to the many people who supported and encouraged me during the work

leading to this thesis: professors, colleagues, friends, and family. My advisor at UCLA, Dr. Asad A.

Abidi, helped select a challenging and worthwhile research topic and guided me throughout this

endeavor. I am grateful to him and the other members of my committee, Henry Samueli, Gabor C.

Temes, Siegfried G. Knorr, Milos D. Ercegovac, and William E. Slater. My colleagues at UCLA

have been a constant source of support, contributing in innumerable ways to the work described

here. I feel privileged to have worked with these stimulating researchers, especially John Angell,

James Chang, Ramon Gomez, Eric Holmberg, Patrick Pai, Gary Sullivan, and Tyson Tuttle. In

addition to their other contributions, Pat Pai and James Chang assisted greatly in the preparation of

this manuscript. TuongLong Huy Phan proved invaluable, tirelessly laying out the integrated

circuits, and Maryam Rofougaran skillfully drew many of the figures appearing in this manuscript.

Several people outside of UCLA were also supportive of my efforts. Binoy Rosario, Brian Boso,

Wink Gross, Ken Weigel and Jim Marsh made fabrication of the circuits possible at Tektronix

Integrated Circuit Operation. Fred Weiss provided access to TriQuint Semiconductor’s Gallium

Arsenide MESFET process for a precursor to this project which led to our beneficial relationship

with Tektronix. K.C. Wang, Peter Asbeck, Randy Nubling, and Derrick Cheung funded a parallel

development of a Gallium Arsenide HBT A/D converter at the Rockwell International Science

Center and shared results of their work with me. Tino Gomez of TRW’s Analog and Digital

Products department assembled all of the fixtures required during the evaluation of the integrated

circuits. His expert abilities eased the difficulty of testing greatly. Throughout my graduate studies

at UCLA I received financial support from TRW, Inc. and through the University of California

MICRO program. My management at TRW, especially Bill Ashley, Fred Carper, Ken deGraaf, and

Keith Kelley, has been consistently supportive during this arduous process. Most importantly, my

family, Mom and Dad, Bud, Beth, and Brian gave me constant moral support and encouragement -

more than they realize. Without their faith and inspiration this work very likely would not have been

completed. I cannot adequately express the love and gratitude I feel for them.

xxxii

VITA1961 Born, Bangor, Maine

1983 B. S., Electrical Engineering (Magna Cum Laude)

University of Notre Dame

Notre Dame, Indiana

1983–1985 Member of Technical Staff

Electronic Systems Group

TRW, Inc.

Redondo Beach, California

1985 M. S., Electrical Engineering

University of Southern California

Los Angeles, California

1985–1987 MICRO Fellow

Department of Electrical Engineering

University of California


1987–1992 TRW Fellow

Department of Electrical Engineering

University of California


1992–1993 Department Staff

Electronic Systems Group

TRW, Inc.

Redondo Beach, California

xxxiii

PUBLICATIONS

W. T. Colleran and A. A. Abidi, “A 10-Bit 75MHz Two-Stage Pipelined Bipolar

A/D Converter,” to appear inIEEE Journal of Solid-State Circuits,vol. 28, no. 12,

Dec. 1993.

W. T. Colleran, T. H. Phan, and A. A. Abidi, “A 10b 100Ms/s Pipelined A/D

Converter,”1993 IEEE International Solid-State Circuits Conference Digest of

Technical Papers,vol. 36, San Francisco, CA., pp.68-69, Feb. 1993.

W. T. Colleran and A. A. Abidi, “A 26dB Wideband Matched GaAs MESFET

Amplifier,” IEEE Transactions on Microwave Theory and Techniques, vol. 36, no.

10, pp. 1377-1386, Oct. 1988.

W. T. Colleran and A. A. Abidi, “A 26dB Wideband Matched GaAs MESFET

Amplifier,” IEEE International Solid-State Circuits Conference Digest of Technical

Papers, vol. 31, San Francisco, CA, pp. 196–197, Feb. 1988.

W. T. Colleran and A. A. Abidi, “Wideband Monolithic GaAs Amplifier using

Cascodes,”Electronics Letters, vol. 23, no. 8, pp. 951–952, Aug. 27, 1987.

xxxv

ABSTRACT OF THE DISSERTATION

A 10-bit 100 Megasample-per-SecondAnalog-to-Digital Converter UtilizingFolding, Interpolation, and Analog

Encoding Techniques

by

William Thomas Colleran

Doctor of Philosophy in Electrical Engineering

University of California, Los Angeles, 1993

Professor Asad A. Abidi, Chair

Monolithic implementations of data converters at the 10 bit, 100 megasample-per-second

(Ms/s) level are considered a high priority for many applications today including ultrasound

imaging, high definition television, radar signal processing, and instrumentation. Several

drawbacks including excessive power consumption and die size prevent current high-speed

conversion methods from being extended to the 10-bit level. The purpose of this research project

was to develop more efficient architectures for high–speed, medium–resolution converters, and to

evolve the circuit designs necessary for these architectures.

Analog-to-digital (A/D) converters that are known to work at the highest speed typically

involve aflasharchitecture, preceded by adiode-bridgesample-and-hold (S/H) circuit. However,

single-chip implementations of flash converters with resolution greater than 8 bits are difficult to

attain because these topologies involve large device count and large power dissipation. Further,

xxxvi

multi–chip realizations yield degraded performance and increased power dissipation compared to

monolithic approaches due to the overhead incurred when driving signals between chips.

Innovative architectures which include subranging, pipelining, analog encoding, folding,

and interpolation have been investigated for a monolithic A/D converter which includes anon-chip

S/H function to enhance overall converter performance. These techniques resulted in a topology

which is highly integrable yet which approaches the performance of a fully parallel or flash A/D

converter. The integrated circuit dissipated 800 mW while digitizing 50 MHz input signals at

75 Ms/s with 56 dB signal-to-noise-plus-distortion ratio.

Chapter 1

Introduction

Analog-to-digital (A/D) conversion and digital-to-analog (D/A) conversion lie at the heart

of most modern signal processing systems where digital circuitry performs the bulk of the complex

signal manipulation. As digital signal processing (DSP) integrated circuits become increasingly

sophisticated and attain higher operating speeds more processing functions are performed in the

digital domain. Driven by the enhanced capability of DSP circuits, A/D converters (ADCs) must

operate at ever-increasing frequencies while maintaining accuracy previously obtainable at only

moderate speeds. This trend has several motivations and poses important consequences for analog

circuit design. The motivations for processing most signals digitally are manifold: digital circuits

are much less expensive to design, test, and manufacture than their analog counterparts; many

signal processing operations are more easily performed digitally; digital implementations offer

flexibility through programmability; and digital circuitry exhibits superior dynamic range, thereby

better preserving signal fidelity. As a consequence of the aforementioned advantages accrued by

DSP, fewer and fewer operations benefit from analog solutions. Figure 1.1 illustrates the evolution

towards systems relying upon more sophisticated DSP hardware with a concomitant reduction in

analog circuit content. This move portends two important ramifications for the role of analog

circuitry in future systems. First, only Radio Frequency (RF) processing and data conversion

(including anti-aliasing filters) will remain as important niches where analog implementations

exhibit advantages over digital approaches. Data converters will continue to play a significant role

2 Chapter 1 Introduction

in advanced electronic systems operating in the RF and Intermediate Frequency (IF) regimes.

Further, since A/D conversion generally requires more power and circuit complexity than D/A

conversion to achieve a given speed and resolution, ADCs frequently limit performance in signal

processing systems. This fact underscores the second consequence of enhanced DSP performance

on the role of analog circuit design. That is, since A/D conversion limits overall system

performance, development of improved A/D conversion algorithms and circuitry represents an

extremely important area of research for the foreseeable future.

This dissertation describes the results of research into the development of new techniques

for achieving high-speed, low-power A/D conversion where high-speed refers to converters capable

of operation in excess of 50 megasamples per second (Ms/s) and low-power implies dissipation

below one Watt. Important parameters of ADCs in addition to speed and power dissipation such as

resolution, linearity, dynamic distortion, and yield are addressed. Since, generally one of these

Figure 1.1. Examples of increasing DSP complexity in communicationssystems. (a) A classical system with analog demodulator followed by basebandA/D conversion and DSP. (b) Advanced system with IF A/D conversion usingdigital demodulation and signal processing. (c) Emerging system with RF A/Dconversion followed by digital downconversion, demodulation, and basebandsignal processing.

RF BasebandSignal Signal

RFSignal

IFSignal

RFSignal

AnalogDemodulator

A/DConverter DSP

RFMixer

Digital Mixer,Demodulator,& Processing

A/DConverter

A/DConverter

DigitalDemodulator& Processing

(a)

(b)

(c)

1.1 Applications for High-Speed Low-Power A/D Converters 3

aspects of ADC performance can be improved at the expense of others, design techniques utilized

when approaching high-speed A/D conversion have historically required large power dissipation.

Conversely, many applications which require low power dissipation such as portable digital

voltmeters (DVMs) led to designs which are fundamentally limited in speed. The purpose of this

research was to develop new A/D conversion techniques which are inherently fast yet which

consume low power. Table 1.1. compares the performance goals for this project along with the

requirements for two important applications of high-speed A/D converters which served as

motivations for this work: High-Definition Television (HDTV) and medical ultrasound imaging

systems. These and other applications for high-speed, low-power ADCs are next described in detail.

1.1 Applications for High-Speed Low-Power A/D

Converters

As mentioned previously, the ever-increasing speed and sophistication of monolithic DSP

hardware is enabling unprecedented improvements in system performance. Frequently, however;

a. INL and DNL are defined in section 1.3.1.

Parameter UnitsHDTV

RequirementUltrasound

RequirementDesignGoal

Resolution bits 10 10 10

Sample Rate Msps 75 40 100

Input Bandwidth MHz 30 15 50

Power mW 1000 500 750

INLa bits 1 1 1

DNL bits 1 1/2 1/2

SNR dB 52 56 59

SFDR dB 56 58 65

S/(N+D) dB 50 54 58

Table 1.1. Comparison of performance requirements for HDTV and medicalultrasound imaging applications along with design goals for this work.


such enhancements are limited by the attainable A/D converter capabilities. In such instances,

increased ADC performance is particularly advantageous (and valuable) since system viability is

directly impacted. Several applications where high-speed, low-power A/D converters play a pivotal

role in determining overall system performance are detailed below. The converter requirements for

these applications helped determine practical design goals for this research project.

1.1.1 Ultrasound Imaging Systems

Medical ultrasound imaging is by far the most important commercial application of high-

speed, low-power ADCs of the type described here. In this application, A/D converters digitize

electrical signals from an array of piezo-electric transducers which respond to acoustic echoes from

a patient’s body. The digitized data from the converter array can then be combined to form an image

of the tissue within the body. The diagnostic utility of such real-time imaging is obvious, leading to

an impressive commercial market. Currently over 10,000 medical ultrasound machines are sold

worldwide annually. Systems now under development use arrays of 128 A/D converters generating

a worldwide annual market of over 1 million chips. Suitable ADCs must meet stringent

performance criteria such as listed in table 1.1 and at present no such component exists.

A basic reflection imaging system (Fig. 1.2) [1], [2] utilizes a piezo-electric transducer

which emits acoustic energy when excited electrically or conversely electrical energy when excited

acoustically. With the switch in the transmit position a pulse generator excites the transducer

resulting in propagated wavefronts emanating from the transducer. Immediately following pulse

Figure 1.2. Basic Reflection imaging system.

DisplaySignalProcessor

Transducer

PatientPulse

Generator

R

T


transmission the switch is changed to the receive position using the same transducer. When the

wavefront encounters a discontinuity, as shown, a scattered wave is produced indicated by the

reflected vectors. This scattered wave is received by the transducer and the resultant electrical signal

is processed and displayed giving information about the size and location of the discontinuity. The

processing usually comprises bandpass filtering, gain control, and envelope detection. Although

conceptually simple, such a system can only form one-dimensional images containing information

describing the distance a discontinuity lies from the transducer. Two-dimensional images can be

formed by physically scanning the transducer across the region of interest, but a superior approach

relies on an array of transducers which can be electrically controlled to scan a two-dimensional

field.

In array imaging systems which use electronic deflection and focusing, or phased array

systems as they are often called, each transducer receives reflected signals from every point in the

field of view (Fig. 1.3). The outputs of all transducers are appropriately delayed and summed to

represent the energy reflected from a specific point within the view field. In this manner signals from

the desired point undergo constructive interference, while those signals from other points sum in an

uncorrelated manner. By electronically controlling the delay elements in the array, the beam is

steered through the region of interest forming a real-time two-dimensional image. Current medical

ultrasound systems employ analog delay-lines and summing electronics with A/D conversion

occurring after the received signals have been summed (Fig. 1.4). Such systems place only modest

restrictions on A/D performance usually requiring 8-bit resolution at video sample rates while

Figure 1.3. Phased array imaging system.

Summer

SignalProcessor

ControlledDelayControlled

DelayControlledDelayControlled

Delay

ControlUnit

TransducerArray

Display


tolerating power dissipation well above one Watt. However, the analog delay-lines and summing

electronics are cumbersome, difficult to control, and degrade signal fidelity. Therefore, ultrasound

systems currently under development incorporate one ADC per transducer channel enabling use of

digital delays and summation (Fig. 1.5) [1], [2], [3]. Image resolution in phased array systems

increases with the number of array elements and the frequency of emitted pulses. To enhance image

quality, emerging ultrasound units use larger arrays (128 to 256 elements) and higher RF pulse

frequencies (up to 15MHz) than their predecessors. This type of system gives superior image

quality, but because of the large number of ADCs required, the power dissipation and price of each

converter must be minimized. Additionally, sample rates and input bandwidths must increase to

accommodate the increased transducer frequencies and amplitude resolution must improve to 10

bits. This combination of performance specifications (summarized in table 1.2) represents a very

Figure 1.4. Current medical ultrasound imaging system utilizing one A/Dconverter after the received signals have been delayed and summed.

Figure 1.5. Emerging medical ultrasound imaging system with an array ofADCs with digital delays and summation.

DelayDelay

DelayDelay

SignalProcessor

ControlUnit

TransducerArray

Σ ADC

Display

DigitalDelayADC

ADCADC

ADC

SignalProcessor

ControlUnit

TransducerArray

ΣDigital

Summer

DigitalDelayDigital

DelayDigitalDelay

Display


stringent and as yet elusive goal, but the magnitude of the ultrasound market provides compelling

motivation to develop such A/D converter technology. Note that the modest die cost of $10 per

screened component places a restriction on the die size and yield of the converter given a certain

wafer cost.

1.1.2 High–Definition Television

Debate rages today over what form future television systems will assume. Unquestionably

the next generation of video equipment will deliver unprecedented picture quality with spatial

resolution increasing to millions of pixels and amplitude resolution improving to better than one

part-per-thousand. Because of this dramatic improvement, the inchoate system has been dubbed

High–Definition Television or HDTV. Almost certainly HDTV will rely upon a digital transmission

standard taking advantage of the powerful image compression algorithms developed to reduce the

required amount of transmitted data. Such a system (Fig. 1.6) requires A/D conversion of the

incoming rasterized signal from a video camera at rates far in excess of current video signals. After

modulation and transmission, the received signal is demodulated, digitized, and processed for

display. The exact form of the receiver system depends on available technology and will follow the

ParameterUltrasound

RequirementUnits

Resolution 10 bits

Sample Rate 40 Msps

Input Bandwidth 15 MHz

Power 500 mW

INL 1 bits

DNL 1/2 bits

SNR 56 dB

SFDR 58 dB

Power Supplies +/– 5 V

Die Cost <10 $

Selling Price <40 $

Table 1.2. Requirements for medical ultrasound imaging applications.


trend depicted in figure 1.1. Therefore, the A/D converter in the receiver will migrate towards the

antenna eventually operating at RF sample rates. At present, broadcast studio equipment places

more demanding constraints on ADCs than home television units. An operational broadcast

encoding system has been in use in Japan for several years. This system, the Multiple Sub-Nyquist

Sampling Encoding (MUSE) system, (Fig. 1.7) [4] requires one A/D converter operating above 40

Ms/s for each of the 3 signals comprising an HDTV image in RGB format. Digitization at even

higher rates is required for an HDTV composite signal. Increased dynamic range of the HDTV

Figure 1.6. A typical digital television system.

Figure 1.7. Proposed MUSE encoder system.Note the complexity of thedigital circuitry following the A/D conversion consistent with the trend depictedin figure 1.1.

RASTERIZEDSIGNALS

MODULATION

TRANSMISSIONCHANNEL

DEMODULATIOND/A DIGITALPROCESSING

DISPLAY

CAMERA

A / D

A / D

A/D

A/D

A/D

LPF

LPF

TCIEncoder

HDTV inRGB

21~22MHz 44.55

MHz

8 MHz

InterfieldPre-filter

Field OffsetSubsampling(24.3 MHz)

InterfieldPre-filter

12 MHzLPF

48.6Ms/s

MIX

EmphasisControl

Synchronize,and Add

16.2 Ms/s

Frame OffsetSubsampling

MotionArea

Detection

MotionVector

Detection

TransmissionEqualization

LPFD/A

32.4 Ms/s16.2 Ms/s

Audio/VITSignal Adder12.15

MBd1,350Kb/s

Audio (4 Channels),Independent Data

Input

32.4 MHz13 MHz

LPF

MUSEOUT

FMModulation TX

AudioEncoder

TimeCompression LPF

LPF

LPF

LPFMTX

Timecompression

γ−1

ζ

S

M

S

M

SamplingConversion

48.6 32.4

SamplingConversion

48.6 32.4


video signal also mandates digitization with 10-bit resolution. Table 1.3 summarizes the A/D

converter requirements for HDTV. Note that the sample rate and input bandwidth are higher than

those required for ultrasound systems (Table 1.2), but that higher power consumption and die cost

are tolerable.

1.1.3 Radar

Radar and electronic warfare (EW) systems represent another important application of

high-speed, low-power A/D converters. Many modern systems employ phased-array techniques

such as those used in ultrasound machines (Fig. 1.5) with the piezo-electric transducers replaced by

RF antennas. At present, digitization usually occurs after downconversion (Fig. 1.8) so this

application incorporates baseband A/D conversion [3]. The sample-rate and resolution of the ADC

depend upon the desired spatial resolution and discrimination of the radar image. Sample-rates

above 50 Msps with greater than 8 bit resolution are often desirable. Jam resistant radars require

higher resolution A/D converters to enable detection of small signals in the presence of high-

powered interference.

ParameterHDTV

RequirementUnits

Resolution 10 bits

Sample Rate 75 Msps


Power 1000 mW

INL 1 bits

DNL 1 bits

SNR 52 dB

SFDR 56 dB

Power Supplies +/– 5 V

Die Cost <25 $

Selling Price <100 $

Table 1.3. Requirements for HDTV applications.


EW systems often place more stringent requirements on ADCs than radars by employing

IF and RF A/D conversion. In such systems an incoming radar signal is digitized (preferably at RF

frequencies) then stored in a high-speed memory called a digital RF memory (DRFM). This digital

data can then be converted back to analog form and transmitted to the originator confusing its signal

processing algorithms. Alternatively, the stored radar signature can be used later for threat analysis.

Similar techniques are used in radar range finders and terrain mapping systems. In each of these

applications higher sample-rates and digitizable signal bandwidths improve performance; therefore,

radar systems always serve as an application for faster A/D converters.

1.1.4 Digital Sampling Oscilloscopes

Much instrumentation in general and digital sampling oscilloscopes (DSOs) in particular

rely upon fast, accurate A/D converters to perform their functions. A DSO comprises an ADC

(preceded by signal conditioning circuitry), a buffer memory, and a display (Fig.1.9) [5], [6]. Some

Figure 1.8. Typical phased array radar system.

Figure 1.9. Typical sampling oscilloscope.

"I" (In-Phase) Channel

"Q" (Quadrature) Channel

Detector

Detector

DigitalProcessor

ADC

ADC

RF Weighting,Delay, and Combining

Network

Antenna Array

LocalOscillator

90 degreePhase Shifter

Low Rate Digital

Play back

Write ReadGain Adjust

Analog Input Signal Conditioning ADC Buffer Memory

Clock & Control

1.2 Design Goals 11

DSOs require only 8-bit A/D conversion because the display is limited to that resolution; however

as more emphasis is placed upon digital storage and analysis of captured waveforms, limitations of

display resolution no longer determine ADC accuracy. Therefore, newer DSOs are migrating to 10

and 12 bit A/D converters and are functioning as digital waveform recorders, not merely

oscilloscopes. Some sampling oscilloscopes utilize high-speed sampling gates with very small

aperture times to effect extremely high input bandwidths, often in the tens of GHz. The sample-rates

of these circuits, however, are usually quite slow, around a few megasamples/second. This

technique, sometimes called equivalent-time sampling, introduces aliasing whose effects can be

tolerated if a narrowband, periodic signal is being viewed. In many instances, however, aperiodic

or broadband signals must be digitized mandating Nyquist rate sampling which implies a sample-

rate greater than twice the bandwidth of the incoming signal. To properly digitize such waveforms,

very high sample-rate A/D converters are desirable. Because some DSOs are portable battery-

powered units, low-power ADCs are mandatory. The combination of the above converter

requirements; 10 to 12 bit resolution, high-speed, and low-power form a formidable set of

specifications.

1.2 Design Goals

The design goals for this project were established based upon the requirements of the

applications described above and upon the capabilities of other A/D converters extant. A summary

of reported performance (Fig. 1.10) shows no 10-bit resolution converters capable of 50 Msps

operation while consuming less than 1 Watt. To address this need, development of a 10-bit,

100 Msps A/D converter consuming 750 mW was undertaken with the goal of achieving in excess

of 9.5 effective bits of resolution for analog input signals at 50 MHz. To ensure that commercially

viable techniques were utilized throughout, untrimmed operation was required from standard +5 V

and –5.2 V power supplies using a conventional oxide-isolated silicon bipolar process. These

performance goals are summarized in table 1.4 along with more explicit specifications for measures

of dynamic linearity such as signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR).

Notice that the SFDR requirement is quite stringent at 65 dB. This is consistent though with the

ideal SFDR for a 10-bit ADC which is approximately 90 dB. The bipolar process used for this

project provides lateral PNP transistors and trimmable thin-film Nichrome (NiCr) resistors;

however, to keep the design as generally applicable as possible, PNP transistors were not used nor

was trimming of resistors allowed.


Figure 1.10. A/D converter performance comparison.

ParameterPerformance

GoalUnits

Resolution 10 bits

Sample Rate 100 Msps


Power 750 mW

INL 1 bits

DNL 1/2 bits

SNR 59 dB

SFDR 65 dB

S/(N+D) 58 dB

Table 1.4. Performance goals for this development.

1 10 100 1000Sampling Frequency (Msps)

6

7

8

9

10

11

12R

eso

luti

on

(B

its)

BipolarCMOSBiCMOSThis work

650mW [18]

150mW [17]

3.5W, AD 9005

500mW [19]

900mW [20]

750mW, Design Goal

180mW [21] 300mW [22]

2.5W [23]

75mW [17] 300mW [24] 800mW [12]

1.6W Siemens SDA 820012mW [25]

400mW [26]

2.0W [13]

2.5W, AD 9028

2.7W [27]2.0W [28]

1.2 Design Goals 13

1.2.1 SHPi Process †

The semiconductor process used for this project is called SHPi provided by Tektronix, Inc.

of Beaverton, Oregon. SHPi is an oxide-isolated bipolar process with NPN transistors which exhibit

a maximum cutoff frequency, ft, of approximately 8.5 GHz. The process provides NPN, PNP, and

JFET transistors as well as Schottky diodes, trimmable thin-film resistors, implanted resistors, and

two-level gold interconnect metal. Only NPN transistors, Schottky diodes, and untrimmed resistors

were used during this development. Minimum size devices exhibit approximately 4GHz ft at the

low bias conditions used. A summary of SHPi NPN device parameters is included in table 1.5.

†. The information contained in this section was drawn largely from theSHPi Full Custom Inte-grated Circuit Design Guide published by Tektronix Integrated Circuits Operation. This documentis available as part number 070-7035-00 from Bipolar Products Group, Integrated Circuits Opera-tion, Tektronix, Inc. P.O. Box 500 Beaverton, Oregon 97077.

Parameter Value Units

MinimumDevice Size

27 X 15 µm2

MinimumEmitter Size

1.6 X 8 µm2

Ic for peak ft 1.0 mΑ

ft 8.5 GHz

β 100

rb 275 Ω

re 10 Ω

rc 100 Ω

VA 25 V

tf 12 ps

Cje 33 fF

Cjc 34 fF

Ccs 18 fF

Table 1.5. SHPi NPN characteristics.


The SHPi process was developed for high-performance analog applications and delivers

excellent component matching. For example, adjacent minimum-size transistors exhibit VBE

mismatches with 200µV standard deviation. Likewise,β mismatches show standard deviations of

1%. Thin-film resistor matching depends upon geometry and device separation, but with proper

design can be reduced to less than 0.5% standard deviation. The complexity of the SHPi process

limits integration to only modest levels (8–10 thousand components for reasonable yield). This limit

arises from the large number of mask steps required (14 as shown in table 1.6) when NiCr resistors

and two layer interconnect are used. An additional mask is necessary to manufacture JFETs on the

same substrate, but this option was not invoked. Both layers of interconnect metal are gold with

4µm pitch and 60 mΩ/sq sheet resistance. This implementation provides for dense layouts with

excellent current-carrying capability and minimal parasitic resistance. To facilitate description of

integrated circuit layouts the SHPi mask layers will be consistently drawn as depicted in figure 1.11.

Mask Number

Layer Name Mnemonic

1 Buried Layer bl

2 Isolation is

3 Channel Stop ch

4 Substrate Contact sc

5 Deep Collector dc

6 p+ Contact pp

7 Active Base ab

8 Emitter e

9 Contact ct

10 Nichrome ni

11 1st Metal 1m

12 1st Via 1v

13 2nd Metal 2m

14 Passivation pa

Table 1.6. SHPi mask layers.

1.2 Design Goals 15

A plan view (using the layer fill-patterns shown in figure 1.11) and a cross-section of a minimum-

size SHPi NPN transistor is shown in figure 1.12. Larger devices are created by adding multiple

emitter and collector stripes (Fig. 1.13).

Accurate computer simulation is critical to the successful development of high-

performance integrated circuits. Accurate simulations in turn depend upon accurate modeling of

device behavior. The transistor model used for simulations during this development was provided

by Tektronix and is a macrocell (Fig. 1.14) based on the standard SPICE BJT model. The

parameters used with this subcircuit are listed in table 1.7.

Figure 1.11. Fill codes for SHPi mask layers. Layer names refer to thoselisted in table 1.6.

#########

bl

is

ch

sc

dc

pp

ab

e

ct

ni

1m

1v

2m

pa


1.3 General Considerations

1.3.1 Terminology and Notation

Much of the nomenclature commonly used to describe data converters and their related

circuits is idiosyncratic to the field. Therefore, a brief discussion of the more important terminology

will now be undertaken.

A sample-and-hold (S/H) or track-and-hold (T/H) circuit is frequently required to capture

rapidly varying signals for subsequent processing by slower circuitry. Although a S/H refers to a

device which spends an infinitesimal time acquiring signals and a T/H refers to a device which

spends a finite time in this mode, common practice will be followed and the two terms will be used

interchangeably throughout this discussion as will the termssample andtrack. The function of a

track-and-hold circuit is to buffer its input signal accurately during track mode providing at its

output a signal which is linearly proportional to the input, and to maintain a constant output level

Figure 1.12. Cross-section and plan view of minimum-size SHPi device.

N2

S

ize:

27

x 15

mic

rons

BB ECN2

n EPI

n+ bl

p+p+ p

n emitter

Thin Oxide

p+ ch p+ ch

c b e bmetal

Oxide

n+ buried layer

n+dc Oxide

p- Substrate

15 mµ

27 mµ

1.3 General Considerations 17

during hold mode equal to the T/H output value at the instant it was strobed from track to hold by

an external clock signal (Fig. 1.15). Several parameters describe the speed and accuracy with which

this operation is performed. Thetrack modeis the state when the T/H output follows the T/H input.

Thehold mode refers to the period when the T/H output is maintained at a constant value. Thetrack-

Figure 1.13. Cross-section and plan view of SHPi device.

Figure 1.14. SHPi transistor model used for SPICE simulations.

N4

S

ize:

42

x 18

mic

rons

CC E1

E2

B B BN4C

n EPI

n+ bl

p+p+ p

n emitter

Thin Oxide

p+ ch

c b e

Oxide

n+ buried layer

b

n+dc

e

p- Substrate

Metalcb

n+dc

Metal

p+ ch

Oxide

42 mµ

18 mµ

b

e sub

dsubrbx

dcb

q1

rcx

c


to-hold transition is the instant when the circuit switches from the track mode to the hold mode and

the hold-to-track transition refers to the switch from hold mode back to track mode. The time

between successivetrack-to-hold transitions is thesample period whose reciprocal is thesample

rate.

While in track–or sample–mode, the T/H functions as a simple buffer amplifier. Operation

in this mode is described by the same specifications which characterize any analog amplifier such

as gain, offset, bandwidth, nonlinearity, distortion, slew rate, and settling time. These parameters

are not peculiar to T/H circuits and need not be elaborated upon further.

While in the hold mode two effects are of primary importance. The first isdroop which

Parameter Value Units Parameter Value Units

ise 1.91e–16 A tf 12 ps

isc 7.9e–16 A tr 12 ns

bf 100 cje 33 fF

br 24 cjc 5.7 fF

vaf 25 V vje .65 V

var 4.5 V vjc .65 V

ikf 5.962 mA mje 0.4

ikr 3.084 mA mjc 0.4

ne 1.5

nc 1.5 dcb

rbx 35 Ω cjo 28 fF

rb 237 Ω vj .65 V

rbm .1 Ω mj 0.4

rcx 95 Ω dsub

rc 9 Ω cjo 18 fF

re 9 Ω vj .65 V

irb 70 µA mj 0.4

Table 1.7. SHPi NPN transistor SPICE model parameters.


describes the decay of the output signal as energy is lost from the storage element (usually a

capacitor) within the T/H circuit. Droop is frequently caused by leakage or bias currents discharging

a capacitor and manifests itself as an approximately constant increase or decrease of output voltage

with time. The second important aspect of hold mode performance isfeedthrough which describes

the unwanted presence at the T/H output of a signal component proportional to the input signal. The

feedthrough signal is usually described as the ratio of the unwanted output signal to the input signal

amplitude.

Theacquisition time is the duration during which the T/H must remain in the track mode to

enable the circuit to accurately replicate the input signal, thereby ensuring that the subsequent hold

mode output will lie within a specified error band of the input level that existed at the track-to-hold

transition (after gain and offset effects have been removed). The remainder of time during the track

mode exclusive of acquisition time is called thetrack time during which the T/H output is a replica

of its input.

The settling time describes the interval between the track-to-hold transition and the time

when the T/H output has settled to within a certain error band of its final value. The remainder of

the time during the hold mode represents the maximum time available for A/D conversion if the

T/H is used for that purpose.Conversion time of an A/D converter is the interval between the

convert command and the instant when the digital code is available at the ADC output. Therefore,

the minimum sample period of a practical A/D converter system is the sum of acquisition time,

Figure 1.15. Track-and-hold terminology.

Track/Hold Input

TimeHold Sample Hold

AmplitudeAcquisition

timeTracktime

Settlingtime

A/D Conversiontime

Track/Hold Output


settling time, and conversion time.

The track-to-hold transition determines many aspects of T/H performance. Thedelay time

is the time elapsed from the execution of the external hold command until the internal track-to-hold

transition actually begins. In practical circuits this switching occurs over a non-zero interval called

the aperture time measured between initiation and completion of the track-to-hold transition.

Practical circuits do not exhibit precisely the same sample period for each sample. This random

variation from sample to sample is caused by phase noise on the incoming clock signal and further

exacerbated by electronic noise within the T/H itself. The standard deviation of the sample period

is termed theaperture jitter and limits amplitude resolution in A/D conversion. Finally, at the track-

to-hold transition, circuit effects frequently give rise to a perturbation at the T/H output. This effect

which manifests itself as a discontinuity in the T/H output waveform calledhold jump or hold

pedestal can depend on the input signal giving rise to distortion.

A quantizer is a device which maps a continuous range of input levels onto a finite set of

discrete digital code words. Ananalog-to-digital converter (A/D converter) comprises a quantizer

along with other signal conditioning circuitry such as amplifiers, filters, T/H circuits etc. In spite of

this difference, the terms quantizer and A/D converter are often used synonymously. A quantizer

can be uniquely described by its transfer function orquantization characteristic which indicates the

device’s discrete outputs as a function of the continuous input signal. The quantization

characteristic therefore contains two sets of information: the first includes the digital codes

associated with each output state, and the second includes thethreshold levels which are the set of

input amplitudes at which the quantizer transitions from one output code to the next (Fig. 1.16). The

digital coding can take on one of several forms including natural binary, sign plus magnitude, offset

binary, ones complement, twos complement, binary coded decimal (BCD), and Gray code each of

which has advantages in particular applications. An ADC’s actual threshold levels are denoted by

Tk where the indexk ranges from 0 toM giving a total of values. Correspondingly, ideal

thresholds levels are denotedTk* . The ideal thresholds can be located arbitrarily along the abscissa;

however, evenly spaced thresholds are most common. (Such devices are called uniform quantizers.)

In general, optimum performance results when the threshold locations match the probability density

function of the incoming signal. However, in the absence ofa priori knowledge of the input signal

statistics, uniform quantization outperforms other arrangements. Therefore, uniform quantizers are

most commonly used and will be dealt with exclusively here. Quantizers whose ideal thresholds are

M 1+


located symmetrically about the origin are calledbipolar quantizers while those whose thresholds

are restricted to positive (or negative) values are termedunipolar (Fig. 1.17). Note that these

characteristics differ only in the location of their respective origins. TheFull-Scale Range, FSR, of

a uniform quantizer represents that portion of the transfer function domain spanned byM equal-

Figure 1.16. Quantizer transfer functions or quantization characteristics. (a)Uniform quantizer. (b) Non-uniform quantizer.

Figure 1.17. Unipolar (a) and bipolar (b) quantization characteristics.

Output

Input

(a)

ThresholdLevels

QuantizationLevels

OutputCodewords

000

001

010

011

100

101

110

111 Output

Input

(b)

ThresholdLevels

QuantizationLevels

OutputCodewords

0000

0001

0010

0011

1111

1110

1101

1100

Input

(a)

Output

3

2

1

4

6

7

0

5

5 6 7321 40

FS

FSR

-1-2-3

1 2 3-1/2

-3/2

-5/2

1/2

5/2

7/2Output

Input

(b)

-7/2

3/2

+FS

-FS

FSR


length intervals between adjacent ideal thresholds. The length of these intervals is called the

quantization step or simplyQ. The relationship between the Full-Scale Range and the quantization

step can be stated succinctly:

(1.1)

A term related to Full-Scale Range isFull-Scale, FS, which is the magnitude of the Full-Scale

Ranges’s maximum excursion from the transfer function origin. Because bipolar and unipolar

quantization characteristics differ in their definition of the origin, the meaning of Full-Scale varies

when applied to differing types of characteristics. In a unipolar quantizer the Full-Scale Range

spans from 0 to FSR,so while in a bipolar quantizer the Full-Scale Range is centered

at the origin spanning from to , so . Figure 1.17 illustrates these

differences. Quantization levels, ( ), are assigned values midway between

adjacent ideal thresholds, i.e. . These outputs must be so assigned

because the corresponding digital code words have no specific analog value. Therefore, the gain of

the A/D converter is implicitly defined. Figure 1.18 illustrates the two most common quantization

Figure 1.18. Ideal quantizer transfer functions. (a) Midtread characteristic.(b) Midriser characteristic.

QFSRM

=

FS FSR=FSR− 2⁄ FSR 2⁄ FS FSR 2⁄=

Qk* k, 0 … M 1−, ,=

Qk* Tk

* Tk 1+*+( ) 2⁄=

-1-2-3

1 2 3-1/2

-3/2

-5/2

1/2

5/2

7/2Output

Input

(b)

-7/2

3/2

Output

Input

-1

-2

-3

-1/2-3/2-5/2

1/2 5/23/2

1

2

3

(a)


characteristics, themidtread characteristic and themidriser characteristic. For anN-bit bipolar

(unipolar) quantizer, a midtread characteristic has thresholds and has one quantization

level with value zero ( ). A midriser characteristic has thresholds, one of

which has value zero ( ). By convention, and for each characteristic so

only physical thresholds actually exist. Midriser quantizers have quantization

levels which map neatly onto the binary output codes expressible with anN-bit digital word. For

this reason midriser quantizers are utilized more frequently than their midtread counterparts. The

ideal thresholds and quantization levels for a uniform quantizer whether bipolar or unipolar,

midtread or midriser can be defined by the following relationships:

(1.2)

. (1.3)

are related as follows:

(1.4)

Figure 1.19 depicts an ideal (bipolar, midriser) quantization characteristic showing the relationship

M 1+ 2N=FSR 2⁄ M 1+ 2N 1+=FSR 2⁄ T0 ∞−≡ TM ∞≡

M 1− M 2N=2N

Tk*

∞− for k 0=kQ OffT− for 1 k M 1−≤ ≤

∞ for k M=

=

Qk* kQ OffQ− for 0 k M 1−≤ ≤=

Q M OffT andOffQ, , ,

Midriser: M 2N=

Midtread: M 2N 1−=

QFSRM

=

Unipolar:OffT 0=

OffQ 0=

Bipolar:OffT

M2

Q=

OffQM 1−( )

2Q=


between these values.

Real quantizer transfer functions fall short of the ideal because imperfections in fabrication

cause actual thresholds to deviate from their desired placement. Such non-idealities can be

expressed in several ways (Fig 1.20). An error which causes all thresholds to shift from their ideal

positions by an equal amount is called anoffset and is usually denoted∆. Non-ideality which results

in an erroneous quantizer step size,Q, is calledgain error or scale-factor error. Q can be defined

as a function of FSR (equation 1.1) or alternativelyQ can be assigned the value which minimizes

threshold errors as calculated by linear regression. In the latter case equation 1.1 still holds, but FSR

is a function ofQ instead of vice-versa.Linearity error refers to the deviation of the actual threshold

levels from their ideal values after offset and gain errors have been removed. Excessive linearity

error results inmissing codes, a condition wherein a valid output code, sayQj, never occurs because

its defining interval has become vanishingly small, . Linearity error is

quantified by thethreshold level errors,

(1.5)

Figure 1.19. Quantizer notation, threshold and quantization levels.

TM2

1+

T0 ∞−≡TM ∞=

TM2

1−

TM2

TM 1−

T1

Q0

Q1

QM 1−

QM 2−

Tj Tj 1+,[ ] Tj 1+ Tj≤

εk Tk ∆ Tk*−−=


wherek is defined for thresholds 0 throughM but has meaning only for the real thresholds 1 through

. This array of error terms, also calledIntegral Nonlinearity or simply INL, is frequently

described by its peak value or its root-mean-square (rms) value:

(1.6)

Figure 1.20. Quantization transfer functions including error sources (a)Offset error. (b) Gain error. (c) Linearity error. (d) Missing codes.

-1-2-3

1 2 3-1/2

-3/2

-5/2

1/2

5/2

7/2Output

Input

(a)

-7/2

3/2

OffsetError

Ideal

Actual

-1-2-3

1 2 3-1/2

-3/2

-5/2

1/2

5/2

7/2Output

Input

(b)

-7/2

3/2

Ideal

Actual

-1-2-3

1 2 3-1/2

-3/2

-5/2

1/2

5/2

7/2Output

Input

(c)

-7/2

3/2

ThresholdErrors

Ideal

Actual

-1-2-3

1 2 3-1/2

-3/2

-5/2

1/2

5/2

7/2Output

Input

(d)

-7/2

3/2

MissingCode

Ideal

Actual

M 1−

σe1

M 1− εk2

k 1=

M 1−

∑ =


Related to INL is theDifferential Nonlinearity or DNL:

. (1.7)

Since DNL is defined by a first-order difference equation, it is valid only for the range

and only has physical meaning over . The element array of DNL values is

also frequently described by its statistical properties such as peak and rms. The terms integral and

differential arise when describing the above two error measures because DNL can be defined as the

first-order difference of the INL sequence.

(1.8)

Several terms are commonly used to describe the relative power of the analog input to an A/D

converter. Theloading factor, LF, expresses the rms amplitude of the input waveform relative to the

quantizer FSR:

. (1.9)

The reciprocal of loading factor is referred to ascrest factor, CF, which is in turn related to thesignal

factor, SF. Signal factor differs from crest factor by including the rms value of only the signal input

while crest factor includes the rms of the signal plus noise input.

. (1.10)

1.3.2 Quantization †

The quantization process can be described by a nonlinear input–output transfer function as

depicted in figure 1.21 and described in section 1.3.1. The quantized output signal, , is the

dk Tk Tk 1− Q−−=

1 k M≤ ≤2 k M 1−≤ ≤ M 2−

dk T=k

Tk 1−− Q−

Tk Tk 1−− Tk* Tk 1−

*−( )−=

Tk ∆− Tk*−( ) Tk 1− ∆− Tk 1−

*−( )−=

εk εk 1−−=

LFrmsamplitudeoftotalinput

FSR 2⁄=

SFFSR 2⁄

rmsamplitudeofsignalinput=

Q x( )


sum of the original input signal,x, and a quantization error, where

. (1.11)

Here is the error resulting when the input signal,x, is quantized with finite resolution. This

quantization error, as shown in figure 1.22, is a deterministic function of the input signal,x.

However, subject to certain simplifying constraints [7], [8]; can be approximated as a

random noise component. The constraints necessary to justify this statistical model are:

• is a stationary process

• is uncorrelated withx

• The elements of are uncorrelated with each other

• The probability density function of is uniform over

†. The description of quantization in this section follows that given inby Martin and Secor in“High speed analog–to–digital converters in communication systems: Terminol-ogy, architecture, theory, and performance,” D. R. Martin and D. J. Secor, tech.rep., TRW Electronic Systems Group, Redondo Beach, CA, Nov. 1981.

Figure 1.21. Quantizer models. (a) Nonlinear model. (b) Statistical model.

NonlinearityInput Output

QuantizationNoise U x( )

Q x( )

Q x( ) x U x( )+=x

Input Output

x

(a)

(b)

U x( )

U x( ) Q x( ) x−=

U x( )

U x( )

U x( )

U x( )

U x( )

U x( ) Q 2⁄− Q 2⁄,( )


Under these constraints is often modelled as a uniformly distributed random variable

thereby simplifying the analysis of quantizer performance.

Quantizer operation is frequently characterized by signal-to-noise ratio (SNR) which

expresses (usually in decibels) the ratio of the output signal power to the output noise power. Since

the quantization noise is assumed to be uniformly distributed on (Fig. 1.23) the

Figure 1.22. Quantization noise models. (a) Ideal quantizer. (b) Quantizerwith threshold level errors.

Figure 1.23. Distribution of quantization error.

U x( )Q 2⁄

Q 2⁄−

x

-FSR/2

FSR/2

U x( )Q 2⁄

Q 2⁄−

x

-FSR/2

FSR/2

(a)

(b)

U x( )

Q 2⁄− Q 2⁄,( )

Q 2⁄Q 2⁄−

1 Q⁄pQ x( )

x


output noise power, or variance, can be easily calculated.

(1.12)

The power of the output signal (assuming a quantizer with unity gain) can be calculated as a

function of the loading factor, LF.

(1.13)

where a midriser characteristic has been assumed. The quantizer SNR is therefore given by:

(1.14)

where the subscriptQ modifying SNR refers to quantization noise as distinct from thermal noise or

other deleterious error sources which compromise overall signal to noise ratio. In decibels, this

expression simplifies to

. (1.15)

When evaluated for a sinusoidal input with amplitude equal to Full-Scale (i.e. ) the

σQ2 x2pQ x( ) xd

∞−

∞

∫=

x2 1Q

xdQ 2⁄−

Q 2⁄

∫=

1Q

13

x3Q 2⁄−

Q 2⁄=

13Q

Q3

8Q− 3

8−( )=

Q2

12=

σS2 LF2 FSR 2⁄( ) 2 LF2 2NQ 2⁄( )

2LF2Q222N 4⁄= = =

SNRQ

σS2

σQ2

LF2Q222N 4⁄Q2 12⁄

3 22N LF2××= = =

SNRQ 6.02N 4.77 20 LF( ) dBlog+ +=

LF 1 2⁄=


SNR expression evaluates to

(1.16)

which is a frequently used equation for predicting optimum A/D performance. For a 10-bit

converter maximum SNR is 61.97 dB. Another formulation based upon equation 1.14 and using the

input amplitude to determine the signal power gives the following alternative expression for

quantizer SNR under the condition of a sinusoidal input:

(1.17)

which when expressed in decibels simplifies to

. (1.18)

This formula, equivalent to equation 1.15, emphasizes that under the present assumptions, SNR

depends only upon the input amplitude relative to the quantizer step,Q. A quantizer at peak loading

(i.e. with the input amplitude, ) gives maximum signal-to-noise ratio

(1.19)

which equates to equation 1.16. Because they express the relationship between quantizer resolution

and maximum achievable SNR, equations 1.16 and 1.19 can be used to assess the performance of

any quantizer relative to the ideal. By replacing the maximum achievable SNR by the actual SNR

and solving for the equivalent resolution,N, a figure of merit called the number-of-effective-bits,

Neff, results.

(1.20)

SNRQ 6.02N 1.76dB+=

SNRQ

σS2

σQ2

A2 2⁄Q2 12⁄

6 A Q⁄( ) 2×= = =

SNRQ 20 A Q⁄( ) 7.78dB+log=

A 2N 2⁄( ) Q×=

SNRMax

σS2

σQ2

A2N

2Q=

62N 2⁄( ) Q

Q

2

× 32

22N×= = =

Neff log223

SNRActual

( )1 2⁄ 1

2log2

23

SNRActual

( )= =


or if SNR is known in decibels,

. (1.21)

The number-of-effective-bits (sometimes referred to as effective-number-of-bits, ENOB) is a

commonly used metric for summarizing the performance of non-ideal quantizers.

Equation 1.15 predicts that the SNR in dB will increase linearly with increasing loading

factor (also in dB). This relationship holds until maximum SNR is achieved at for

sinusoidal inputs. Further increases in loading factor yield decreasing SNR because the quantizer

becomes overloaded (i.e. the quantizer input exceeds Full-Scale) thereby producing a severely

distorted output.

In practice, A/D converters encounter inputs which are more complicated than simple

sinusoids. Under conditions with such complicated signal environments, the A/D converter input

can be simulated by a Gaussian noise source. The ratio of the input noise power to the quantization

noise power can then be used as a measure of quantizer fidelity. This performance metric is call

noise-power-ratio, NPR, and is calculated in a manner similar to SNR. Equations 1.12 and 1.13 are

again used to predict the quantization noise power and signal noise power respectively with the

modification that the signal power is due to a Gaussian noise input as characterized by its power

relative to the quantizer loading factor, LF. Therefore, equation 1.15 predicts NPR as well as SNR

if the proper value of LF is used. To minimize overload with a Gaussian input, a substantially

reduced LF as compared to the sinusoidal input case must be used. For example, reducing the

Gaussian input standard-deviation to one fourth of the Full-Scale amplitude (LF=1/4) reduces the

probability of overload to 0.0064%, . This selection results in the following

simplified expression for NPR:

(1.22)

The above simplified analyses are based upon the assumptions that quantization noise is

uniformly distributed and uncorrelated with the input signal. These assumptions are only

approximated in practice, and to the extent that such approximations are invalid the preceding

derivations will produce erroneous results. In particular, the preceding equations for SNR and NPR

neglect overloading effects and therefore predict unbounded performance for increasing loading

Neff

SNRActualdB1.76−

6.02=

LF 1 2⁄=

1 erf 4 2⁄( )−

NPRQ 6.02N 7.27− dB=


factor. A more accurate analysis of quantizer distortion based on work by Max [9] and modified by

Martin and Secor [10] which avoids the aforementioned simplifying assumptions follows.

The mean-square quantization error for a quantizer whose input isx with probability

density function and whose output is can be expressed as

(1.23)

where represents the expectation operator. Note that the quantization error depends on

the probability density of the input and is not assumed to be uniformly distributed. If we define the

quantizer output as a noise component plus a signal component with a possibly non-unity gain term,

i.e.,

(1.24)

then by suitable selection of the signal gain,g, we can ensure that the quantization noise, , is

uncorrelated with the output signal,gs. Zero correlation between output signal and output noise

means

(1.25)

which implies

(1.26)

Therefore,

(1.27)

Px x( ) U x( )

σQ2 U x( ) x−[ ] 2Px x( ) xd

∞−

∞

∫=

E U x( ) x−[ ] 2 =

E •

U x( ) u≡ gs nQ+=

nQ

0 E gs nQ =E= gs u gs−( )

E= gsu E gsgs −

gE su g2E s2 =

gE su

E s2 =


This value ofg ensures thatgs is a minimum mean-square estimate of the input, u. Note that the

quantization error, , isnot assumed to be uncorrelated with the input as in the previous simplified

analysis. The SNR of the quantizer is given by

(1.28)

wherePS is the output signal power,

(1.29)

PT is the total output power,

(1.30)

andPN is the output noise power resulting from input noise.PN can be calculated in exactly the

same manner asPS with the input,s, taken to be the noise component of the total input. This

substitution results in an expression forPN corresponding to equation 1.29:

(1.31)

The SNR of a quantizer can be calculated given the statistical properties of its input by determining

PS, PT, and PN which in turn requires evaluation of

. This procedure will be performed for a

sinusoidal input and for a Gaussian input.

A quantization characteristic,f(x), can be represented by

nQ

SNRPS

PT PS PN−−=

PS E gs( ) 2 =

E= g2s2 g2E s2 =

E su

E s2

2

E s2 =

E su [ ] 2

E s2 =

PT E u2 =

PNE nu [ ] 2

E n2 =

E s2 , E u2 ,E n2 ,E su ,andE nu


(1.32)

where is the indicator function defined by

(1.33)

andM, Qi, and Ti are as defined previously in section 1.3.1. For concreteness a bipolar, midtread

quantizer characteristic will be assumed resulting in quantization levels and

threshold levels,

(1.34)

(1.35)

For a Gaussian input with probability density function

(1.36)

f x( ) QiI x Ti Ti 1+,( , )i 0=

M 1−

∑=

I x a b, ,( )

I x a b, ,( )1if a x b<≤0otherwise

=

M 2N=M 2N 1−=

Qi* i

M2

12

+−( ) Q= 0 i M 1−≤ ≤

Ti*

∞−

iM2

−( ) Q

∞

=

i 0=

1 i M 1−≤ ≤

i M=

Pn x( ) 1

2πσ2e

x2

2σ2−

=


(which is plotted in normalized form in figure 1.24) the total output power from the quantizer is

Figure 1.24. The functions , , and . By plotting the

normalized versions , , and versus the

shapes of the above functions become independent of . Also,

equals .

-3 -2 -1 0 1 2 3x/sigma

0

.25

.5

.75

1f(

x)

Pn(x) * AFn(x)Gn(x)/A

1

2π

Fn x( )Gn x( ) σ⁄

Pn x( ) σ×

x σ⁄

Pn x( ) σ× Gn x( ) σ⁄=

fx()

Pn x( ) Fn x( ) Gn x( )Pn x( ) σ× Fn x( ) Gn x( ) σ⁄ x σ⁄

σ Pn x( ) σ×Gn x( ) σ⁄


(1.37)

where (also plotted in figure 1.24) is the complementary integral of the Gaussian

probability density function, related to the familiar complementary error function.

(1.38)

Here the dependence uponσ has been left implicit for clarity. In the reduction of equation 1.37 to

its most simplified form the identities and were used to replace

and respectively. Note that if ideal thresholds are used is replaced by ,

is replaced by , and simplifies to .

The correlation between the input Gaussian noise, u, and the output noise, n, is

(1.39)

where , the complementary integral of the weighted Gaussian probability density function,

PT f x( )[ ] 2Pn x( ) xd∞−

∞

∫=

Qi2 Fn Ti( ) Fn Ti 1+( )−[ ]

i 0=

M 1−

∑=

Q02Fn T0( ) Qi

2Fn Ti( ) Qj 1−2 Fn Tj( ) QM 2−

2 Fn TM( )−j 1=

M 1−

∑−i 1=

M 1−

∑+=

Q02 Qi

2 Qi 1−2−( ) Fn Ti( )

i 1=

M 1−

∑+=

Fn x( )

Fn x( ) Pn u( ) udx

∞

∫=

Fn ∞−( ) 1= Fn ∞( ) 0=Fn T0( ) Fn TM( ) Ti Ti

* Qi

Qi* Qi

*( ) 2Qi 1−

*( ) 2− 2Ti* Q

E nu xf x( ) Pn x( ) xd∞−

∞

∫=

Qii 0=

M 1−

∑ xPn x( ) xdTi

Ti 1+

∫=

Qi Qi 1−−( ) Gn Ti( )i 1=

M 1−

∑=

Gn x( )


is given by:

(1.40)

and is plotted in figure 1.24. The input noise power is which can be combined

with to give the output noise power,

. (1.41)

The resultant NPR at the quantizer output is

(1.42)

wherePs from equation 1.28 is ignored since a Gaussian noise source is being used. Note that this

calculation requires approximatelyM evaluations of , the complementary integral of

, andM evaluations of , the complementary integral of for each value of

the input parameterσ, hence LF. A plot of the NPR based upon this method (Fig. 1.25) indicates an

approximately linear dependence of NPR on LF for small values of LF in agreement with the

simplified result in equation 1.15. Also evident in this region is the 6 dB per bit dependence of NPR

upon resolution. However, the new plot more accurately predicts NPR at high LF by accounting for

the effects of overloading. These overloading effects are ignored by the previous approach leading

to erroneous results. Efficient system design mandates judicious selection of loading factor to

optimize quantizer NPR, and the above results serve as a guide in this regard. Optimum loading

factor, crest factor (the reciprocal of loading factor), and NPR are tabulated in table 1.8 This

information, also presented graphically in figure 1.26, can be used when selecting system gain

parameters to achieve desired performance in a complex signal environment where A/D

overloading is unavoidable.

Similar analysis to that performed for Gaussian noise inputs can be applied for the case of

Gn x( ) uPn u( ) udx

∞

∫σ2π

e z− zd

x2

2σ2

∞

∫−= =

σ2π

e

x2−2σ2

=

E n2 σ2=E nu

PnE nu [ ] 2

E n2

E nu [ ] 2

σ2= =

NPRQ

Pn

PT Pn−=

Fn x( )Pn x( ) Gn x( ) xPn x( )


Figure 1.25. NPR of ideal midriser quantizer with Gaussian noise input.Quantizer resolution indicated on curves.

Resolution(Bits)

OptimumLoading Factor

(dB)

Optimum CrestFactor

Optimum NPR(dB)

2 –5.98 1.99 8.70

3 –7.40 2.34 14.10

4 –8.57 2.68 19.33

5 –9.57 3.01 24.55

6 –10.45 3.33 29.82

7 –11.22 3.64 35.17

8 –11.90 3.94 40.57

Table 1.8. Optimum quantizer loading and NPR for Gaussian noise input.

-20 -18 -16 -14 -12 -10 -8 -6Loading Factor (dB)

0

10

20

30

40

50

60

70N

PR

(d

B)

N=2

3

4

5

6

7

8

9

10

11

N=12


sinusoidal inputs to ascertain quantizer SNR under such conditions. For a sinusoidal input with

9 –12.51 4.22 46.03

10 –13.06 4.50 51.55

11 –13.55 4.76 57.11

12 –14.00 5.01 62.71

13 –14.42 5.26 68.35

14 –14.80 5.49 74.01

15 –15.14 5.72 79.70

16 –15.47 5.94 85.41

Figure 1.26. Optimum loading factor and NPR for Gaussian noise input.

Resolution(Bits)

OptimumLoading Factor

(dB)

Optimum CrestFactor

Optimum NPR(dB)

Table 1.8. Optimum quantizer loading and NPR for Gaussian noise input.

2 4 6 8 10 12 14 16Resolution (Bits)

-20

-18

-16

-14

-12

-10

-8

-6

-4

-2

0

Op

tim

um

Lo

adin

g F

acto

r (d

B)

0

10

20

30

40

50

60

70

80

90

100

Maxim

um

NP

R (d

B)


amplitude A the probability density function is

(1.43)

which is plotted in figure 1.27. Identical analysis which led to the use of , the

complementary integral of the Gaussian probability density function, in equation 1.37 necessitates

Figure 1.27. The functions , , and . By plotting the

normalized versions , , and versus the shapes

of the above functions become independent of .

Ps x( )

1

π A2 x2−for x A<

0otherwise

=

Fn x( )

-1 -.5 0 .5 1x/A

0

.25

.5

.75

1

1.25

1.5

f(x)

Ps(x) * AFs(x)Gs(x)/A

x A⁄

1π

Ps x( ) A×Fs x( )Gs x( ) A⁄

fx()

Ps x( ) Fs x( ) Gs x( )Ps x( ) A× Fs x( ) Gs x( ) A⁄ x A⁄

A


utilization of , the complementary integral of the sinusoidal probability density (Fig. 1.27):

(1.44)

Likewise, calculation of the correlation between the input sinusoid and the output signal requires

evaluation of the complementary integral of the weighted sinusoidal probability density function,

, (Fig. 1.27) which has the form:

. (1.45)

These two functions, and , can be used with the following equations (analogous to

equations 1.37 through 1.39 derived for the Gaussian input case) to determine the total output

power,PT, and .

(1.46)

Fs x( )

Fs x( ) Ps u( ) udx

∞

∫1

π A2 u2−ud

x

A

∫= =

12

1π

xA

( )asin− x A<

1 x A−<0 x A>

=

Gs x( )

Gs x( ) uPs u( ) udx

∞

∫u

π A2 u2−ud

x

A

∫= =

1π A2 x2− x A≤

0 x A>

=

Fs x( ) Gs x( )

E su

PT f x( )[ ] 2Ps x( ) xd∞−

∞

∫=

Qi2 Fs Ti( ) Fs Ti 1+( )−[ ]

i 0=

M 1−

∑=

Q02 Qi

2 Qi 1−2−( ) Fs Ti( )

i 1=

M 1−

∑+=


Since is 1 for and 0 for this expression for can be further simplified to

(1.47)

whereJ is the smallest integer such that andK is the largest integer such that .

is calculated as follows:

. (1.48)

This expression can also be simplified if the input amplitude is less than to

(1.49)

whereJ andK are defined as above. Since the input signal power is known, , the

output signal power can be easily calculated

. (1.50)

Fs x( ) x A−< x A> PT

PT Q=J 1−2 Qi

2 Qi 1−2−( ) Fs Ti( )

i J=

K

∑+

A TJ<− TK A<E su

E su xf x( ) Ps x( ) xd∞−

∞

∫=

Qii 0=

M 1−

∑ xPs x( ) xdTi

Ti 1+

∫=

Qi Qi 1−−( ) Gs Ti( )i 1=

M 1−

∑=

VFS

E su Qi Qi 1−−( ) Gs Ti( )i J=

K

∑ Q Gs Ti( )i J=

K

∑= =

E s2 A2 2⁄=

PsE su [ ] 2

E s2

E su [ ] 2

A2 2⁄= =


This expression can be expanded using equation 1.49 giving

(1.51)

The signal to quantization noise ratio is then given by

(1.52)

wherePn from equation 1.28 is ignored since a noiseless source is assumed. As in the Gaussian

noise input case, determination of the SNR requiresM evaluations of andM evaluations of

for each value of the sinusoidal input amplitude,A. By performing these calculations, the

plot of SNR versus loading factor, LF, found in figure 1.28 results. Note the approximate linear

dependence of SNR on loading factor (when both are expressed in dB) and the 6 dB per bit

dependence of SNR on resolution. Both of these trends are predicted by the simple approximation

of SNR found in equation 1.15. However, figure 1.28 indicates two additional characteristics not

predicted by that equation. First, SNR degrades for loading factors which lead to clipping of the

input sinusoid (LF greater than –3 dB). Second, SNR deviates slightly from linear dependence upon

LF with each trace exhibiting a series of bumps along the SNR curve. These bumps arise because

of the non-uniform probability density of the input sinusoid which is near its peak a high percentage

of the time. As the loading factor increases, the sinusoid peak travels from one threshold to the next

resulting in small variations in SNR. The local SNR minima occur when the input sinusoid’s peak

equals a quantizer threshold while the local SNR maxima occur when the input peak is midway

between thresholds. The data displayed in figure 1.28 is more exhaustive than might appear at first

glance because forunclipped sinusoidal inputs, SNR depends solely on the input amplitude and not

on the quantizer resolution. Therefore, a quantizer with a given loading factor and resolution

Ps

Q Gs Ti( )i J=

K

∑2

A2 2⁄2Q2

A2Gs Ti( )

i J=

K

∑2

= =

2Q2

A2

1π A2 Ti

2−i J=

K

∑2

=

2Q2

π21

Ti

A( )

2

−i J=

K

∑2

=

SNRQ

Ps

PT Ps−=

Fs x( )Gs x( )


behaves identically to another quantizer with different resolution but loading factor adjusted

appropriately to maintain constant input amplitude (measured in LSBs orQ steps). Since loading

factor is inversely proportional to the quantizer Full-Scale Range,

, (1.53)

maintaining constant amplitude,A, requires a constant product. Therefore, if an increase

in resolution by one bit is accompanied by a reduction in loading factor of 6.02 dB, identical SNR

will be obtained. For example, referring to figure 1.28, the SNR indicated on the N=3 curve at LF=

–4 dB (approximately 19.7 dB) is repeated exactly on the N=4 curve at LF= –10.02 dB. This

technique can be used to ascertain the SNR for any resolution quantizer (up to N=12) with any

Figure 1.28. SNR of ideal midriser quantizer with sinusoidal input. Quantizerresolution indicated on curves.

-12 -10 -8 -6 -4 -2Loading Factor (dB)

0

20

40

60

80S

NR

(d

B)

N=2

3

4

5

6

7

8

9

10

11

N=12

LFrmsofinput

FSR 2⁄

1

2A

M2

Q

2M

AQ

( )2

2N

AQ

( )= = = =

LF 2N×


loading factor (assuming no clipping) from the figure. A 12-bit quantizer with –61 dB loading factor

can be seen from the N=3 curve at LF= –6.82 (–61 + 6.02(12–3)) to exhibit an SNR of 17 dB.

Alternatively, the exclusive dependence of SNR on amplitude can be emphasized by plotting SNR

versus amplitude,A, independent of quantizer resolution (Fig. 1.29). In this format, the SNR is seen

to depend solely on input amplitude with local minima occurring when the amplitude equals a

threshold value and maxima occurring between thresholds. The approximation for SNR included in

this graph along with the actual SNR data follows equation 1.17 and is accurate to within 1/2 dB for

amplitudes above 16 LSBs (Fig. 1.30).

Similar analysis to that performed above for the Gaussian and sinusoidal input cases can

determine quantizer SNR (or NPR) for any input signal whose statistics are known. Additionally,

the above technique can be easily modified (by substituting for and for ) to predict

Figure 1.29. SNR of ideal midriser quantizer plotted versus sinusoidal inputamplitude. Approximation is based upon equation 1.17.

0 4 8 12 16 20 24 28 32Amplitude (LSBs)

0

10

20

30

40

SN

R (

dB

)

Actual SNRApproximation

Ti* Ti Qi

* Qi


performance of non-ideal quantizers. This procedure, although more accurate than other

approaches, is mathematically tedious and numerically intensive. Therefore, the simple and

intuitive approximation of equation 1.15 remains a powerful and frequently-used predictor of

quantizer signal-to-noise ratio.

Until now quantization noise power has been calculated without regard to spectral content

while determining signal-to-noise ratio. However, in many applications the quantization noise

spectrum of an A/D converter is of particular interest. The spectrum of an instantaneous nonlinear

quantization characteristic can be determined by calculating the Fourier series expansion of a

quantizer output in response to an input sinusoid. Since the quantizer is assumed to be time-

invariant, its output corresponding to an input sinusoid with period T will also be periodic with

period T, thus permitting a Fourier series expansion. If an input signal

is applied to an ideal quantizer (the rationale for selecting the amplitude will become evident

shortly), the resultant output waveform will be

Figure 1.30. Difference between actual SNR and approximated SNR fromfigure 1.29.

0 4 8 12 16 20 24 28 32Amplitude (LSBs)

-2

-1

0

1

2S

NR

(dB

)

x t( ) A 2πt T⁄( )cos−=

A−


(1.54)

where the function represents the quantization characteristic previously described in

equation 1.32 (and repeated here for convenience).

(1.55)

and is the indicator function defined by

(1.56)

Using equations 1.54 through 1.56 the quantizer output can be expressed as

(1.57)

where the values represent the time at which the input sinusoid crosses the threshold .

(1.58)

The motivation for selecting the sinusoidal amplitude as is now apparent. Since the inverse

cosine function monotonically decreases with its argument, selecting a negative sinusoidal

amplitude ensures that the values of will increase with the index,i, from the smallest value to the

largest as the thresholds, , index from the most negative value to the most positive. This simple

definition is problematic however, because the inverse cosine is undefined for arguments whose

magnitude is greater than 1, a condition which arises in equation 1.58 for any thresholds, , whose

magnitude is greater thanA. Since this situation implies that some thresholds are never crossed and

their corresponding quantization levels never appear at the output, , a simple solution lies in

restricting the range of summation in equation 1.57 to those values of which actually occur for

a given input level,A. The range over which the time points are defined is likewise suitably

limited by using the variablesJ andK whereJ is the smallest integer such that andK is

Q t( ) f x t( )( ) f A 2πt T⁄( )cos−( )= =

f •( )

f x( ) QiI x Ti Ti 1+,( , )i 0=

M 1−

∑=

I x a b, ,( )

I x a b, ,( )1if a x b<≤0otherwise

=

Q t( ) QiI t t i ti 1+, ,( )i 0=

M 1−

∑=

ti Ti

tiT2π cos 1− Ti

A−( )=

A−

tiTi

Ti

Q t( )Qi

tiA TJ<−


the largest integer such that . The quantizer output becomes

(1.59)

where the time instances are

(1.60)

The endpoints of the time interval are arbitrarily chosen to be and . Also,

the symmetry of the input cosine can be used to define the quantizer output over the interval

.

(1.61)

The periodic quantizer output can be expressed as a Fourier series

(1.62)

where the coefficients and of the expansion are:

(1.63)

(1.64)

TK A<

Q t( ) QiI t t i ti 1+, ,( ) for 0<t<T 2⁄i J 1−=

K

∑=

ti

tiT2π cos 1− Ti

A−( )= J i K≤ ≤

tJ 1− 0= tK 1+ T 2⁄=

T 2 t T≤ ≤⁄

Q t( ) Q T t−( )= for T 2 t T≤ ≤⁄

Q t( )a0

2an

n2πtT

( ) bnn2πt

T( )sin+cos

n 1=

∞

∑+=

an bn

an2T

Q t( )n2πt

T( )cos

0

T

∫=

bn2T

Q t( )n2πt

T( )sin

0

T

∫=


Substituting the expression for (equation 1.59) into the definition for yields

(1.65)

which can be further simplified by noting that each value of is multiplied by the term . By

modifying the definition of to exclude the unnecessary term , simplifies to

(1.66)

with defined as

(1.67)

Because is an even function, it is orthogonal to ; therefore, all of the

coefficients are zero. The expansion for is therefore

(1.68)

Q t( ) an

an4T

QiI t t i ti 1+, ,( )n2πt

T( ) tdcos

i J 1−=

K

∑0

T 2⁄

∫=

4T

Qin2πt

T( ) tdcos

ti

ti 1+

∫i J 1−=

K

∑=

2πn

Qi

n2πti 1+T

( )sinn2πti

T( )sin−

i J 1−=

K

∑=

2πn

Qi 1− Qi−( )n2πti

T( )sin

i J=

K

∑=

2Qπn

− n2πti

T( )sin

i J=

K

∑=

ti 2π T⁄ti T 2π⁄ an

an2Qπn

− nti( )sini J=

K

∑=

ti

ti cos 1− Ti

A−( )= for J i K≤ ≤

Q t( ) n2πt T⁄( )sin bn

Q t( )

Q t( )a0

2an

n2πtT

( )cosn 1=

∞

∑+=


The power in each harmonic, †, is simply related to its Fourier coefficient:

(1.69)

When compared to the power in the fundamental component of the output signal the harmonic

distortion results.

(1.70)

which when expressed in dBc becomes

(1.71)

The coefficient of the fundamental component, , can be simplified as follows

(1.72)

†. Here the notation is used for the power in then-th harmonic to avoid confusion with the

noise power, .

P n( )

P n( )

Pn

P n( )12

an2=

HDn

P n( )

P 1( )

12

an2

12

a12

an2

a12

= = =

HDn 10an

2

a12

log 20an

a1 log= =

a1

a12Qπ− cos 1− Ti

A−( )( )sin

i J=

K

∑=

2Qπ− 1

Ti

A( )

2

−i J=

K

∑=


Using equation 1.69 with equation 1.72 to calculate the fundamental signal power gives

(1.73)

Notice that this expression for signal power isidentical to equation 1.51 which predicts quantizer

output signal power based upon the statistics of the input signal Equation 1.73 indicates that is

the weighted sum of positive ordinates along the unit circle as the abscissa is stepped uniformly

within the range (–1,1).

It is instructive to examine the form of the Fourier coefficients, , to ascertain the nature

of the distortion products emanating from the quantizer. The expressions for and can be

combined to give the consolidated equation

(1.74)

The argument of this summation, , closely resembles then-th Chebyshev

Polynomial, , defined as:

(1.75)

which can also be expressed by the recurrence relation

(1.76)

Ps P1 a12 2⁄= =

12

2Qπ−( )

2

1Ti

A( )

2

−i J=

K

∑2

=

2Q2

π2 1

Ti

A( )

2

−i J=

K

∑2

=

Ps

an

an ti

an2Qπn

− ncos 1− Ti

A−( )( )sin

i J=

K

∑=

ncos 1− Ti A⁄−( )( )sin

Tn x( )

Tn x( ) ncos 1− x( )( )cos=

Tn 1+ 2xTn x( ) Tn 1− x( )−=


leading to the following polynomial forms for the first 4 functions:

(1.77)

can be expressed in terms of by noting that

(1.78)

so that

(1.79)

The first few functions of , abbreviated for simplicity, are

(1.80)

The behavior of can most easily be envisioned when kept in the form .

The argument of the sine function, (plotted in figure 1.31 for reference), is a

monotonically increasing function of its argument spanning from 0 to as the threshold index,i,

sweeps fromJ to K. The sine of this argument (when the parametern is equal to 1) exhibits one

maximum when is zero and is equal to zero itself at both endpoints ( ). In

T0 1=

T1 x=

T2 2x2 1−=

T3 4x3 3x−=

T4 8x4 8x2− 1+=

ncos 1− x( )( )sin Tn x( )

Tn x( )d

xdTn′ x( )= ncos 1− x( )( ) n

1 x2−sin=

Sn x( ) ncos 1− x( )( )sin≡ Tn′ x( )1 x2−

n=

ncos 1− x( )( )sin Sn x( )

S0 0=

S1 1 x2−=

S2 2x 1 x2−=

S3 4x2 1−( ) 1 x2−=

S4 8x3 4x−( ) 1 x2−=

Sn x( ) ncos 1− x( )( )sin

cos 1− Ti A⁄−( )π

Ti A⁄− Ti A⁄− 1±=


fact, this function is the upper unit semi-circle discussed above in the calculation of . As the

parametern is increased, the range covered by the argument of the sine function increases from

to . Therefore, the number of extrema in the function

increases ton. This function is plotted for several values ofn in figure 1.32 where it can be seen that

is an even function for alln odd and an odd function for alln even. When

n is even, the odd symmetry exhibited by the sine function ensures that the summation used to

calculate in equation 1.74 equals exactly 0. This brings out the important fact that a perfect

quantizer produces no even harmonics whatsoever.† The even symmetry of

whenn is odd enables the summation in equation 1.74 to be calculated

with half the original number of function evaluations. The quasi-periodic nature of the

functions plotted in figure 1.32 is reminiscent of the passband ripple of

Chebyshev filters whose characteristics are defined by the related Chebyshev polynomials.

†. The absence of even harmonics in a quantizer output spectrum should not be surprising since thequantization characteristic itself is a purely odd function of its input variable and therefore has apolynomial expansion with only odd terms.

Figure 1.31. The inverse cosine function.

-1 -.5 0 .5 1x

0

π/4

π/2

3π/4

π

aco

s(-x

)co

s1−

x−()

Ps

0 π,( ) 0 nπ,( ) ncos 1− Ti A⁄−( )( )sin


an




Equation 1.74 can be used with equation 1.71 to calculate the harmonics comprising the spectrum

of an ideal 8-bit quantizer (Fig. 1.33). The maximum harmonic distortion for lower-order harmonics

is near –72 dBc, or –9N dBc. Additionally, a slightly higher power harmonic occurs of order

approximately 800. This behavior can be compared to that of an ideal 10-bit quantizer (Fig. 1.34)

which exhibits maximum power lower-order harmonics of approximately -90 dBc, again equal to

-9N dBc. The peak harmonic, which is slightly higher in power than -9N dBc, occupies a harmonic

position just above 3000. The relative power and position of the peak harmonic in quantizer output

spectra generally follow the trends alluded to above for the specific 8-bit and 10-bit cases. In

particular, the position of the peak harmonic is closely approximated by as shown in figure

1.35 which plots the peak harmonic number versus input amplitude measured in LSBs. In the

approximation ,N refers to the maximum number of effective bits for a given input

amplitude. So, for example, an input amplitude of 16 LSBs equates to

maximum effective bits, or while an amplitude of 25 LSBs corresponds to . The

maximum harmonic power generated by an ideal quantizer is approximately-9NdBc where again

Figure 1.32. The function for several values of

n.

-1 -.5 0 .5 1x

-1

-.5

0

.5

1si

n(n*

acos

(-x)

)n

cos

1−x−()

()

sin

n 1=

n 2=

n 3=

n 4=

n 5=



π 2N×

π 2N×log2 2 16×( ) 5=

N 5= N 5.64=


N is the effective resolution assuming full loading with a sinusoidal input. Therefore,

implies that thresholds are traversed by an input sinusoid with amplitude 90.5. This

quantizer, with 181 thresholds, will exhibit identical performance to any quantizer with higher

resolution but the same input amplitude because thresholds which are not traversed by the input

waveform do not enter into the SNR or distortion calculations which limit their summations to the

range of activated thresholds. A plot of the peak harmonic distortion versus input amplitude as

expressed by maximum effective resolution (Fig. 1.36) indicates very close conformance to the

approximation -9N dBc. Also plotted in the same figure is the relative power in the third harmonic,

HD3, which conforms to the -9N dBc approximation as well.

The location of the peak distortion product at harmonic number arises because of

the quasi-periodic nature of the function as next explained. The power in

any distortion product (according to equation 1.74 which is repeated below for convenience)

depends upon the sum of samples of which varies as a function of the

harmonic number,n.

Figure 1.33. Harmonic levels for an ideal 8-bit midriser quantizer.

100

101

102

103

Harmonic Number

-100

-90

-80

-70

-60

SD

R (

dB

)

N 7.5=27.5 181=

π 2N×




(1.81)

To maximize the sum comprising , all of the samples, , should be at or near a peak of

. Two examples which illustrate this principle are depicted in figure 1.37

where and its samples are plotted for the cases whose peak

harmonic is number 47 and whose peak occurs at . Notice that in each case nearly

all of the samples occur at or near a function extrema. The condition required for such sample

placement, where the samples are located at the uniformly spaced locations , is that the

sample after the abscissa midpoint equal the sample at the abscissa midpoint. That is,

(1.82)

Figure 1.34. Harmonic levels for an ideal 10-bit midriser quantizer.

100

101

102

103

104

Harmonic Number

-105

-100

-95

-90

-85S

DR

(d

B)

an2Qπn

− ncos 1− Ti

A−( )( )sin

i J=

K

∑=

an J i K≤ ≤ncos 1− Ti A⁄−( )( )sin

ncos 1− Ti A⁄−( )( )sin N 4=N 5= n 99=

Ti A⁄−

ncos 1− TM 2⁄ 1+−A

( )( )sin ncos 1− TM 2⁄−A

( )( )sin=


This expression can be simplified by using the ideal values of and .

(1.83)

Taking the inverse sine of both sides of equation 1.83 introduces an ambiguity characterized by the

integerm which specifies by how many periods the arguments of the two sinusoids differ. The

resultant condition for peak distortion becomes

(1.84)

Figure 1.35. Peak harmonic number versus analog input amplitude.

0 50 100 150 200 250Input Amplitude (LSBs)

0

200

400

600

800

Pea

k H

arm

on

ic N

um

ber

Peak HarmonicApproximate PeakApproximation, π 2N×

Peak Harmonic Number

TM 2⁄ 1+ TM 2⁄

ncos 1− 1A

( )( )sin ncos 1− 0A

( )( )sin=

nπ2

( )sin=

ncos 1− 1A

( ) nπ2

m2π+=


which simplifies to

. (1.85)

Therefore,

(1.86)

where the approximation used relies upon forx small, a condition which holds for most

values ofA. If full loading is assumed,A can be expressed in terms of the quantizer resolution by

using the relationship which rearranges to give . Using

Figure 1.36. Peak harmonic power for ideal midriser quantizer.

1 2 3 4 5 6 7 8Quantizer Resolution (Bits)

-80

-70

-60

-50

-40

-30

-20

-10

0P

eak

Har

mo

nic

Po

wer

(d

Bc)

Peak Harmonic Power3rd Harmonic Power9N Approximation

1A

mn

2ππ2

+( )cos=

mn

2π( )sin=

n m2π

sin 1− 1 A⁄( )m

2π1 A⁄≅ m2πA= =

xsin x=

2N 2A 1+= A 2N 1−( ) 2⁄ 2N 2⁄≅=


this expression forA in equation 1.86 gives the final condition for maximum distortion:

(1.87)

wherem is any nonzero integer. Since the Fourier coefficients depend on the reciprocal ofn as

Figure 1.37. The function evaluated at for

peak harmonics. (lower) . (upper) .

-1 -.5 0 .5 1x

-1

-.5

0

.5

1

sin

(47a

cos(

x))

-1

-.5

0

.5

1

sin

(99a

cos(

x))

ncos 1− x−( )( )sin x Ti A⁄=N 4 n, 47= = N 5 n, 99= =

n m2π 2N

2m π2N= =

an


well as the sum of the samples of the function , the minimum value ofn

which satisfies equation 1.87 will give the largest distortion power. Therefore, yields the

highest harmonic power resulting in

(1.88)

as predicted empirically from the plots of quantizer distortion spectra. Notice that local distortion

maxima will occur at multiples of as predicted by equation 1.87. Such maxima are easily

noticeable in figure 1.34 where the peak harmonic number is just over 3000 ( ) and local

maxima occur just above 6000 and 9000 corresponding tom from equation 1.87 taking on values

of 1, 2, and 3, respectively. The magnitudes of the local maxima are approximately -6 dB and -10dB

relative to the absolute maximum corresponding to 20log(1/2) and 20log(1/3) as expected.

Martin and Secor [10] have shown that the relative power of the 3rd harmonic output from

a fully loadedN-bit A/D, -9N dBc, can be predicted from the Fourier series expansion of the

quantization error emanating from the converter in response to a sinusoidal input. The analysis

relies upon an identity which expresses the Fourier coefficients in terms of Bessel functions with

known approximations. Note that the 3rd harmonic is found empirically to lie within a few decibels

of the peak harmonic for most cases (see figure 1.36) so that the -9N dBc approximation for

also serves as a good approximation for peak harmonic power. For a fully loaded quantizer the result

is

(1.89)

which when expressed in decibels simplifies to

(1.90)

When the quantizer is less than fully loaded, equation 1.89 can be generalized by expressing the

number of quantization codes output from the converter as a function of the input amplitude, ,

rather than as a function of the quantizer resolution, . That is, in equation 1.89 is replaced by


m 1=

nmaxHD π 2N×=

nmaxHD

π 210×

HD3

HD3

P3

P1

1

2N( )3

≈ 2 3N−= =

HD3 10P3

P1 log 10 2 3N−( )log≈ 30− N 2( )log 9− NdBc= = =

A

N 2N


giving

(1.91)

Alternatively, the input amplitude can be expressed with the loading factor, LF (equation 1.9), as

(1.92)

This expression can be substituted into the first line of equation 1.91 giving

(1.93)

Notice that if the loading factor is expressed in decibels (i.e. ) then 1.93

further simplifies to

(1.94)

Equation 1.94 gives the very simple and important result that the 3rd harmonic (empirically seen to

be near the highest-power harmonic) can be approximated by -9N dBc at full loading

( ). Also, the distortion degrades by 1.5 dB for each 1 dB decrease in the

loading factor. This relationship leads to the counter-intuitive but correct conclusion that

distortion increases for decreasing input signal power. The surprising correlation between

distortion and signal power can be justified qualitatively by noting that the quantization

error remains bounded by one quantization step,Q, regardless of input amplitude.

Therefore, the fixed distortion power is a larger fraction of smaller input signals than of

2A Q⁄

HD3 101

2A Q⁄( ) 3 dBclog≈

30 A Q⁄( )log 30 2( )log+[ ] dBc−=30 A Q⁄( )log 9+[ ] dBc−=

AQ

2NLF

2=

HD3 101

2A Q⁄( ) 3 dBclog≈

10 22NLF( )3−dBclog=

9N 30 2( ) 30 LFlog+log+[ ] dBc−=9N 4.5 30 LFlog+ +[ ] dBc−=

LF indB 20 LFlog=

HD3 9N 4.5 1.5 LFindB+ +[ ] dBc−≈

LF 3dB−=


larger input signals; and harmonic distortion degrades for lower level inputs

correspondingly.

The above results for quantizer distortion spectra assume ideal quantization characteristics

described by uniform threshold placement. Real quantizers will exhibit imperfections in threshold

locations which are generally characterized statistically or by a polynomial expansion which

includes higher-order terms than the linear expansion describing the ideal thresholds. The effect of

such non-idealities on quantizer output spectra can be ascertained by studying their corresponding

impact on the summations which determine the Fourier coefficients, , as detailed in equation 1.74

and depicted in figure 1.32. First, since random perturbations of the ideal thresholds destroy the

symmetry of the samples of , the even-order coefficients no longer sum to

exactly zero. Therefore, even harmonics are generated by non-ideal quantizers.† Second, the

relative significance of higher-order harmonics is generally reduced because these terms become

large only when a specific relationship holds between threshold placement and peaks of the function

. Such alignment is highly unlikely in the presence of random threshold

perturbations. These two assertions are borne out by the example below (Fig. 1.38) which depicts

the output spectrum for an 8-bit quantizer having Gaussian distributed threshold errors with

standard deviation equal to one quarter of an LSB. Clearly the even-order harmonics are significant

and the higher-order terms no longer limit the spurious-free dynamic range (SFDR). The dominant

harmonic, however, remains near the predicted value of -9N dBc.

As described in section 10.2, the effect of deterministic threshold perturbations on the

spectra of quantized signals remains an important area where better understanding is needed.

Certain A/D converter architectures give rise to predictable threshold errors which ultimately limit

linearity; however, determining distortion spectra based upon these errors is still impractical. For

example, bipolar flash converters typically exhibit threshold errors caused by bias currents flowing

through a resistive reference-generation ladder. This effect, sometimes called “reference bowing”,

is predictable, but its effect on the converter output spectrum is difficult to ascertain. Also,

multistage A/D converters with imperfect matching between stages exhibit threshold placement

with periodic deviations from the ideal. Again, the threshold locations are predictable and even

admit a simple polynomial expansion; however, the concomitant effect on the converter’s spectrum

†. As in the case of an ideal quantizer, this result should not be surprising since threshold errorsdestroy the odd symmetry of the quantization characteristic upon which a polynomial expansioncomposed of purely odd harmonics is based.

an




is difficult to determine in analytic form. Development of techniques for predicting such effects

would prove invaluable for high-performance data converter design.

1.3.3 Fundamental Limits to Performance

Many factors impact overall system operation and can limit performance below the ideal

predicted in the previous section. Several such factors which present limits on A/D converter

performance will now be discussed.

In a 50Ω system, thermal noise induced by the source resistance limits A/D converter

resolution to a sub-ideal value which can be calculated if the system bandwidth, , and signal

amplitude, , are known [11]. The noise power available from the source resistance is

(1.95)

Figure 1.38. Harmonic levels for an 8-bit midriser quantizer with 1/4 LSB rmsthreshold errors.

100

101

102

103

Harmonic Number

-100

-90

-80

-70

-60

SD

R (

dB

)

∆f

Vfsr 2⁄

Pn kT∆f=


wherek is Boltzmann’s constant,T is the temperature in degrees Kelvin, and as previously

defined is the bandwidth of the system. The maximum signal power is

(1.96)

where R is the source resistance and full-scale quantizer loading is assumed. The maximum

achievable SNR of an A/D converter operating under such circumstances is:

. (1.97)

By using this expression for SNR in equation 1.20 the maximum attainable quantizer resolution as

limited by thermal noise is seen to be

. (1.98)

For a given quantizer input range, , achievable resolution, , is inversely proportional to

bandwidth and absolute temperature as shown in figure 1.39. As can be seen from this graph, 10–

bit resolution is within the thermal limit for bandwidths well above the 50MHz design goal.

Aperture jitter, which is the noise–induced uncertainty in the otherwise periodic sampling

interval, also places a fundamental limit on achievable resolution [11], [12], [13], [14] for the

following reason. If a signal is changing in time with a maximum slew rate equal toS, and its value

is to be determined with accuracydV, then the sampling instant,T must be defined with accuracy

dT (Fig. 1.40 ) such that

(1.99)

where the timing uncertainty,dT, is referred to as the aperture jitter, .If the A/D converter

requiresN bit resolution, then to ensure amplitude error less than±1/2 LSB, must be limited

∆f

Ps12

Vfsr

2( )

21R

=

SNRThermal

12

Vfsr

2( )

21R

kT∆f

Vfsr2

8kTR∆f= =

Neff log223

Vfsr2

8kTR∆f×

1 2⁄

=

Vfsr Neff

TdVdS

≤

τjitter

Vd


such that

. (1.100)

The maximum slope of a sinusoidal input signal of amplitude and frequency is

resulting in

. (1.101)

This constraint shows the maximum aperture jitter consistent withN–bit resolution and is plotted

Figure 1.39. Thermal limit to achievable resolution.

1 10 100 1000Bandwidth (MHz)

12

14

16

18

20

Res

olu

tio

n (

bit

s)

T = -55CT = 25CT = 125C

Rsource =50Ω

Vfsr =.25V

Vfsr =1.0V

Vfsr =0.5V

Vd12

2Vfs

2N≤

Vfs

2N=

Vfs finS 2πfinVfs=

τjitter Td= VdS

Vfs2

N−

2πfinVfs=≤ 2 N 1+( )−

πfin=


versus bandwidth, , for various values of resolution,N, in figure 1.41.

Figure 1.40. Aperture uncertainty causes amplitude errors.

Figure 1.41. Maximum aperture jitter consistent with 1/2 LSB errors forvarious values of resolution.

dV

dT

Vfs

Vfsr 2Vfs=

V t( ) Vfs 2πfint( )sin=

Slope V t( ) td⁄d=

V− fs

Q 2Vfs 2N⁄=

Vd

td

T0

fin

0.1 1 10 100 1000Analog Input Bandwidth (MHz)

0.1

1

10

100

1000

Ap

ertu

re J

itte

r (p

s)

N=2

4

6

8

10

12

14

N=16


Alternatively, equation 1.101 may be solved forN in terms of giving

. (1.102)

This relationship, plotted in figure 1.42 for various values of , shows that to achieve 10

effective bits of resolution, must be kept well below 10ps; and to maintain adequate margin

for this parameter a value close to 1ps is desirable. This constraint on acceptable jitter mandates use

of a track-and-hold circuit preceding the 10-bit quantizer and further implies that on-chip clock

buffer circuitry must be designed specifically to prevent degradation of the phase noise from that

presented to the A/D converter from outside clock and signal sources.

Unavoidable threshold level errors caused by device mismatches also reduce maximum

achievable SNR. The effect of such imperfections on the quantization error waveform is shown in

Figure 1.42. Maximum attainable resolution limited by aperture jitter.

τjitter

Neff log21

π τjitter fin( ) 1−≤

τjitter

1 10 100 1000Analog Input Bandwidth

0

5

10

15

20

Max

imu

m A

ttai

nab

le E

ffec

tive

Bit

s

tap=1pstap=10pstap=100pstap=1ns

τjitter = 1ps

10ps

100ps

τjitter = 1ns

τjitter


figure 1.22 which is repeated here for convenience (Fig. 1.43). As seen in this figure, threshold

errors increase the maximum amplitude and the variance of the quantization error waveform

thereby increasing the power in the noise component of the SNR equation. To determine the

quantization noise power in the presence of threshold errors, the quantizer error is now studied in

more detail. The quantization error, , represents the difference between the quantizer output,

, and the quantizer input,x, as defined in equation 1.11 and repeated here:

(1.103)

The waveform , and hence , is determined solely by the thresholds ,

which differ from the ideal thresholds, , according to

(1.104)

Figure 1.43. Quantization error waveforms. (a) Ideal quantizer. (b) Quantizerwith threshold level errors.

U x( )Q 2⁄

Q 2⁄−

x

-FSR/2

FSR/2

U x( )Q 2⁄

Q 2⁄−

x

-FSR/2

FSR/2

(a)

(b)

U x( )

Q x( )

U x( ) Q x( ) x−=

Q x( ) U x( ) M 1− Ti

i 1 … M 1−, ,= Ti*

εk Tk Tk*− ∆−=


where is the quantizer offset. The quantization error, ,equals zero when the input is equal

to the output. Since the quantizer output takes on theM discrete values ,

the quantization error vanishes for theM values of input equal to . These relationships are

depicted succinctly for one quantizer step in figure 1.44. The noise power emanating from the

quantizer can be calculated by dividing the input range into a discrete set of subranges and

determining the variance of each corresponding output waveform. If the subranges comprise the set

then,

(1.105)

Figure 1.44. Segment of quantization error waveform with non-zerothreshold errors, .

∆ Q x( )Qj

* j, 0 … M 1−, ,=Qj

*

Qj 1−*

Qj*Tj

*Tj

εj

Q 2⁄

Q 2 εj+⁄

Q− 2⁄

Q− 2 εj+⁄

x

U x( )

Qj 1−* x−

Qj* x−

εj

Aj j, 1 … L, ,=

σn2 E U x( ) 2 =

Ej 1=

L

∑= U x( ) 2 x Aj∈ Px x x Aj∈( )


If the subranges, , are taken to be the regions between adjacent nulls in the quantization error,

, and further, the input is assumed uniformly distributed on each such interval, then the noise

due to thej-th interval, , can be calculated according to the following equation derived from

figure 1.44.

(1.106)

which can be simplified by using the substitution in both integrals and recalling

that to obtain

(1.107)

The total quantizer output noise power, , is calculated by using this result for in equation

1.105.

(1.108)

Aj

U x( )σnj

2

σnj2 E U x( ) 2 x A∈ j =

E= U x( ) 2 Qj 1−* x Qj

*≤<

1Q

Qj 1−* x−( ) 2

xd Qj x−( ) 2 xdTj

Qj*

∫+Qj 1−

*

Tj

∫=

y x Qj 1−*−=

Qj* Qj 1−

*− Q=

σnj2 1

Qy−( ) 2 yd Q y−( ) 2 yd

Q 2 εj+⁄

Q

∫+0

Q 2 εj+⁄

∫=

1Q

= y2 yd Q2 2Qy−( ) ydQ 2 εj+⁄

Q

∫+0

Q

∫1Q

= 13

y30

QQ2y Qy2−( )

Q 2 εj+⁄Q

+

1Q

= 13

Q3 Q3 2 Q2− εj⁄− Q Q2 4 Qεj εj2+ +⁄( )+

Q2

12εj

2+=

σn σnj

σn2 σnj

2 Px x x Aj∈( )j 1=

L

∑=


which can be further simplified if a uniformly distributed input is again assumed.

(1.109)

where is the rms threshold error as defined in equation 1.6. The first term on the right side of

equation 1.109 is the quantization noise of an ideal quantizer as derived in equation 1.12. The

second term is the added noise power brought on by imperfect placement of thresholds. This new

expression for output noise power can be used in place of the simpler expression in

equations such as 1.14 and 1.17 to predict SNR for non-ideal quantizers. The preceding derivation

assumes that the input signal exhibits a uniform probability density function. For many inputs this

assumption is unjustified and more exhaustive analysis must be performed to obtain accurate

predictions of quantizer performance under non-ideal conditions. In such cases, the techniques of

section 1.3.2 can be applied with the actual threshold levels, , used in place of the ideal values,

, to accurately predict SNR performance.

Comparator regeneration time also places a fundamental limit on achievable resolution

[11], [15], [16] for the following reason. If a comparator is given a finite time to regeneratively

produce a logic-level output, then for some range of differential input values near zero, the

comparator output will not be large enough to be unambiguously interpreted by succeeding

encoding logic. This logic can therefore produce erroneous output codes which increase the noise

power in the quantizer output waveform thereby diminishing SNR. Such coding errors have been

called conversion errors, rabbit errors, sparkle codes, and metastability errors. The nature of the

digital output produced under conditions of metastability errors depends greatly on the output

coding format used. With most forms of binary coding, metastability errors manifest themselves as

output code errors which can be modelled as a randomN-bit word. The power contributed to the

quantizer output noise in this case is:

(1.110)

Note that this result follows directly from figure 1.23 and equation 1.12 which predict the quantizer

output noise to be for outputs uniformly distributed on . In the present

σn2 1

Lσnj

2

j 1=

L

∑=

Q2

12σe

2+=

σe

Q2 12⁄

Ti

Ti*

E n2 ConversionError 2NQ( )

2

12=

Q2 12⁄ Q 2 Q 2⁄,⁄−( )


case, the output (under the conditions of a metastability error and binary coding) is presumed to be

uniformly distributed on . Equation 1.110 follows directly. The output noise

due to metastability errors becomes

(1.111)

where is the probability of a metastability error.

If Gray coding is used rather than binary, metastability errors manifest themselves as a

single bit error in an otherwise accurate output codeword. This beneficial effect arises because in

Gray coded A/D converters each comparator influences oneand only one output bit. Therefore, a

metastable comparator causes the corresponding bit to become indeterminate, but all other bits

behave correctly (ignoring the unlikely event of two metastable comparators during one

conversion). In fact, this characteristic is the chief rationale for implementing Gray encoding in A/D

converters. When a metastability error gives rise to an erroneous output bit, the amount of noise

added to the output corresponds to an amplitude error equal to one quantizer step,Q; however, with

probability 1/2 the bit in question will assume the correct value. Therefore, the expected mean-

square noise given a metastability error is:

(1.112)

so the noise power due to metastability errors in Gray coded converters becomes

(1.113)

which is less than the noise power in a binary converter (equation 1.111) by the factor . This

factor represents an extreme noise reduction for even modest resolution A/D converters.

The maximum SNR with metastability errors can be calculated by using the preceding

expressions for noise power with equation 1.17 which gives SNR as a function of input amplitude

and quantizer step-size.

2NQ 2 2NQ 2⁄,⁄−( )

σn2 E n2 MetastabilityError PME=

2NQ( )2

12PME= Q2

1222N× P

ME=

PME

E n2 MetastabilityError 12

Q2 02+( )=

σn2 Q2

2PME

Q2

126PME×= =

22N 6⁄


(1.114)

where full loading ( ) has been assumed for maximum SNR. By replacing the

denominator of equation 1.114 which is the noise due to quantization with the noise expressions

developed for metastability errors (equations 1.111 and 1.113) the maximum achievable SNR given

metastability errors results. For binary encoding:

(1.115)

and for Gray encoding:

(1.116)

where the subscript ME modifying SNR distinguishes the noise as that caused by metastability

errors. Equation 1.20 can be used to convert the above SNR expressions into effective bits. For

binary encoding:

(1.117)

and for Gray encoding

(1.118)

The probability of a metastability error depends upon the statistics of the input signal, but if a

SNRQA2 2⁄

Q2 12⁄

2N 2⁄( )2Q2 2⁄

Q2 12⁄22NQ2 8⁄Q2 12⁄

= = =

A 2N 2⁄( ) Q×=

SNRME22NQ2 8⁄

Q2 12⁄( ) 22NPME×3

2PME= =

SNRME22NQ2 8⁄

Q2 12⁄( ) 6PME×22N

4PME= =

NeffME

12

log2

1PME

( )=

12

−= log2

PME( )

NeffME

12

log2

22N

6PME =

log= 22N

6 1

2log

2PME( )−

N= 12

log2

PME( )− log2 6( )−


uniformly distributed input is assumed, is given by [woodward]

(1.119)

where is the minimum amplitude voltage which will unambiguously be interpreted as an

appropriate logic level (so represents the range of ambiguous voltages),A is effective gain of

a comparator at the end of the latch mode, andQ is the quantizer step size. is seen to be the

ratio of the ambiguous voltage range (referred to the comparator input) divided by total input range

seen by the same comparator. The effective comparator gain,A, which is dependent upon the

dynamic comparator response and the time allowed to regeneratively establish an output state can

be described as

(1.120)

where is the DC gain of the comparator and is the time-constant (assumed first order) which

governs the comparator response during latch mode. The probability of metastability then becomes

(1.121)

where t, the amount of time the comparator is allowed to regenerate, is governed by the A/D

converter sample rate, . The term is on the order of 10 for reasonable values of ,

, andQ. Additionally, is ideally equal to the reciprocal of , the radian unity gain cut-off

frequency of the transistors comprising the latch; however in practical circuits is usually several

times this value:

(1.122)

Equation 1.121 can be used with equation 1.117 to predict maximum effective resolution as limited

PME

PME

2VL

AQ=

VL

2VL

PME

A A0et τ⁄=

A0 τ

PME

2VL

A0Qe

t τ⁄−=

fs 2VL A0Q⁄ VL

A0 τ ωt

τ

τ 52πft

≅


by metastability errors with binary encoding.

(1.123)

If the time allowed for regeneration,t, is equal to half the sample period, , and the input

bandwidth of the A/D converter is limited by Nyquist’s condition ( ) then

t in equation 1.123 can be replaced by resulting in

(1.124)

where is the natural logarithm function. as calculated by equation 1.124 is displayed

graphically in figure 1.45 which indicates that for an effective resolution of 10-bits and an input

bandwidth of 50MHz, the comparator time-constant,τ, must be less than 300 ps. The achievable

resolution for Gray encoding can be calculated in a similar fashion to equation 1.124 giving

(1.125)

where N is the number of bits in the Gray-encoded output word. Notice that the achievable

resolution as limited by metastability errors in this case is greater than that achievable in the binary

case so long as ; that is, for all resolutions of practical interest. For a Gray

encoded A/D converter to achieve 10 bits of resolution with a 50MHz input bandwidthτ can be

slightly longer than 1ns, a factor of three higher than the binary encoded configuration.

Alternatively, with the same comparator time constant the Gray converter exhibits three times the

NeffME

12

log2 PME( )−=

12

log2

2VL

A0Qe

t τ⁄−

−=

12

log2

2VL

A0Q − t

2τ log2e+=

Ts 2⁄fin fs 2⁄≤ 1 2Ts( )⁄=

1 4fin( )⁄

Neff

log2e

8finτ12

log2

2VL

A0Q −=

18ln 2finτ= 1

2log2

2VL

A0Q −

ln x( ) Neff

Neff log22N

6 log2e

8finτ12

log2

2VL

A0Q −+=

N1

8ln 2finτ+= 12

log2

2VL

A0Q − log2 6( )−

N log2 6( )> 1.29=


bandwidth as the binary converter.

In some applications, notably video signal processing, SNR is not the most important

measure of performance degradation due to metastability errors. Rather, peak error is the metric

used for such characterization because large code errors when reconstructed via D/A conversion

appear on a video monitor as noticeable pixel amplitude discontinuities. These momentary

discontinuities, a white pixel on a dark background or vice-versa, seem to the human visual system

like sparkles–hence the name sparkle codes. Gray encoding helps greatly in this regard by limiting

the maximum metastability-induced error to one LSB.

Figure 1.45. Achievable resolution as limited by metastability errors.

10 100 1000Input Bandwidth (MHz)

0

5

10

15

20A

chie

vab

le R

eso

luti

on

(B

its)

2VL

AoQ20=

τ 100ps=

200ps

500ps

τ 1000ps=


References

[1] A. Macovski,Medical Imaging Systems. Prentice–Hall, 1983.

[2] G. S. Kino,Acoustic Waves: Devices, Imaging, and Analog Signal Processing. Prentice–Hall, 1987.

[3] D. H. Sheingold, ed.,Analog–Digital Conversion Handbook. Prentice–Hall, third ed.,1986. The Engineering Staff of Analog Devices.

[4] Y. Ninomiya, “HDTV broadcasting systems,”IEEE Communications Magazine, vol. 29,pp. 15–22, Aug. 1991.

[5] K. Rush and P. Byrne, “A 4GHz 8b data acquisition system,” inInternational Solid StateCircuits Conference, pp. 176–177, IEEE, Feb. 1991.

[6] S. Swierkowski, D. Mateda, G. Cooper, and C. McConaghy, “A sub-200 picosecond GaAssample-and-hold circuit for a Multi-Gigasample/Second integrated circuit,” inInternation-al Electron Device Meeting, pp. 272–275, IEEE, 1985.

[7] W. R. Bennett, “Spectrum of quantized signals,”Bell System Technical Journal, vol. 27,pp. 446–472, July 1948.

[8] A. Gersho, “Principles of quantization,”IEEE Transactions on Circuits and Systems, vol.CAS-25, pp. 427–436, July 1978.

[9] S. Max, “Quantizing for minimum distortion,”IRE Transactions on Information Theory,vol. IT-6, pp. 7–12, Jan. 1960.

[10] D. R. Martin and D. J. Secor, “High speed analog–to–digital converters in communicationsystems: Terminology, architecture, theory, and performance,” tech. rep., TRW ElectronicSystems Group, Redondo Beach, CA, Nov. 1981.

[11] L. E. Larson, “High-speed analog-to-digital conversion with GaAs technology: Prospects,trends and obstacles,” inInternational Symposium on Circuits and Systems, pp. 2871–2878, IEEE, 1988.

[12] R. J. van de Plassche and P. Baltus, “An 8-bit 100-MHz full Nyquist analog-to-digital con-verter,” IEEE Journal of Solid State Circuits, vol. SC-23, pp. 1334–1344, Dec. 1988.

[13] T. Wakimoto, Y. Akazawa, and S. Konaka, “Si bipolar 2-GHz 6 bit flash A/D conversionLSI,” IEEE Journal of Solid State Circuits, vol. SC-23, pp. 1345–1350, Dec. 1988.

[14] M. Shinagawa, Y. Akazawa, and T. Wakimoto, “Jitter analysis of high-speed sampling sys-tems,”IEEE Journal of Solid State Circuits, vol. SC-25, pp. 220–224, Feb. 1990.

[15] C. E. Woodward, K. H. Konkle, and M. L. Naiman, “A monolithic voltage-comparator ar-ray for A/D converters,”IEEE Journal of Solid State Circuits, vol. SC-10, pp. 392–399,Dec. 1975.

[16] B. Zojer, R. Petschacher, and W. A. Luschnig, “A 6-Bit/200-MHz full Nyquist A/D con-verter,” IEEE Journal of Solid State Circuits, vol. SC-20, pp. 780–786, June 1985.

[17] M. K. Mayes and S. W. Chin, “A multistep A/D converter family with efficient architec-ture,” IEEE Journal of Solid State Circuits, vol. SC-24, pp. 1492–1497, Dec. 1989.


[18] M. P. Kolluri, “A 12-bit 500-ns subranging ADC,”IEEE Journal of Solid State Circuits,vol. SC-24, pp. 1498–1506, Dec. 1989.

[19] Y. Sugimoto and S. Mizoguchi, “An experimental BiCMOS video 10-bit ADC,”IEEEJournal of Solid State Circuits, vol. SC-24, pp. 997–999, Aug. 1989.

[20] T. Shimizu, M. Hotta, K. Maio, and S. Ueda, “A 10-bit 20-MHz two-step parallel A/D con-verter with internal S/H,”IEEE Journal of Solid State Circuits, vol. SC-24, pp. 13–20, Feb.1989.

[21] S. H. Lewis and P. R. Gray, “A pipelined 5-Msample/s 9-bit analog-to-digital converter,”IEEE Journal of Solid State Circuits, vol. SC-22, pp. 954–961, Dec. 1987.

[22] S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr., R. Ramachandran, and T. R. Viswanathan,“A 10–b 20–Msample/s analog-to-digital converter,”IEEE Journal of Solid State Circuits,vol. SC-27, pp. 351–358, Mar. 1992.

[23] R. Petschacher, B. Zojer, B. Astegher, H. Jessner, and A. Lechner, “A 10-b 75-MSPS sub-ranging A/D converter with integrated sample and hold,”IEEE Journal of Solid State Cir-cuits, vol. SC-25, pp. 1339–1346, Dec. 1990.

[24] R. E. J. van de Grift, I. W. J. M. Rutten, and M. van der Veen, “An 8 bit video ADC incor-porating folding and interpolation techniques,”IEEE Journal of Solid State Circuits, vol.SC-22, pp. 944–953, Dec. 1987.

[25] M. Hotta, T. Shimizu, K. Maio, K. Nakazato, and S. Ueda, “A 12-mW 6-b video-frequencyA/D converter,”IEEE Journal of Solid State Circuits, vol. SC-22, pp. 939–943, Dec. 1987.

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[27] Y. Akazawa, A. Iwata, T. Wakimoto, T. Kamato, H. Nakamura, and H. Ikawa, “A400MSPS 8b flash AD conversion LSI,” inInternational Solid State Circuits Conference,pp. 98–99, IEEE, Feb. 1987.

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Chapter 2

Pipelined Architecture

2.1 Architectural Comparison

Several architectures were investigated to ascertain their suitability for implementing a 10-

bit, 100 Msps, low-power data converter. The following sub-sections present the results of this

study, highlighting those features which pertain to selection of an appropriate architecture for this

project. This discussion is not intended as an exhaustive description of A/D converter techniques.

For such a treatment, the reader is referred to the text by Sheingold, [3], and the review paper by

Gordon, [2].

2.1.1 Flash Converters

Traditionally, high–speed A/D converters have relied upon the parallel or flash architecture

(Fig. 2.1) wherein the analog input signal is simultaneously compared to every threshold voltage of

the ADC by a bank of comparator circuits [15], [4]. The threshold levels are usually generated by

resistively dividing one or more references into a series of equally-spaced voltages which are

applied to one input of each comparator. The collection of digital outputs from this comparator bank

is called athermometer code because every comparator output below some point along the array is

a logic “1” (corresponding to the mercury-filled portion of a thermometer) while all comparator

outputs above this position are logic “0” (corresponding to the empty portion of a thermometer).

80 Chapter 2 Pipelined Architecture

The thermometer code is easily encoded into a binary output word with an array of simple logic

gates and a read-only-memory (ROM). Although conceptually simple, and capable of very high-

speed operation, the flash architecture suffers from several significant deficiencies described next.

In parallel ADCs, one comparator is required for each threshold of the converter. Thus, the

total number of comparators required is , where is the resolution of the ADC. Because

this quantity grows exponentially with resolution, the required number of comparators is quite

large, even for medium resolution components such as that considered here. All of the drawbacks

of flash A/D converters stem from this exponential dependence of comparator count on resolution.

Thus, increased ADC resolution leads to dramatic growth in the required number of comparators

which in turn causes the following detrimental effects:

Figure 2.1. Flash or parallel A/D converter topology.

N-bit DigitalOutputEncoding

Logic

2 -1Comparators

N-Vref

+Vref Vin

ThermometerCode

2N 1− N

2.1 Architectural Comparison 81

• Large die size which implies high cost

• Large device count leading to low yield

• Complicated clock and signal distribution with significant capacitive loading (both

device and parasitic)

• Large input capacitance requiring high power dissipation in the T/H driving the A/D

converter and degrading dynamic linearity

• High power supply noise due to large digital switching current

• Significant errors in threshold voltages caused by comparator input bias current

flowing through the resistive reference ladder

Although the flash topology is very effective for lower resolution converters [5], [25], [7],

[16], [9], [10], [13], [12], [13], and has been used widely to implement 8-bit ADCs [27], [15], [16],

[17], [18], [19], [4], [20], [21], [22], [23], [24], the above combination of factors make

implementation of flash converters above 8-bits very difficult, especially if low power dissipation

is required. Therefore, the fully parallel architecture was rejected for this project.

2.1.2 Feedback or Multi-pass Converters

The feedback, or multi-pass, A/D converter architecture reduces complexity compared to

the flash arrangement by utilizing comparators multiple times during each quantization [25], [26],

[17], [28], [29], [30]. In this architecture (Fig. 2.2), the full N-bit digitization process is divided into

a series of lower resolution, m-bit quantizations. Each of these steps begins by amplifying the

incoming signal appropriately, followed by a coarse m-bit quantization. The digital result from this

operation is applied to a special accumulator called a Successive Approximation Register (SAR),

the output of which drives an N-bit D/A converter. The analog output from the DAC subtracts from

the input signal to form a residue signal which is ready for the next pass through the feedback loop.

The N-bit resolution obtainable with this arrangement is governed by where is the

resolution of the coarse quantizer used, and is the number of passes around the loop required to

produce each N-bit output code. The gain of the amplifier preceding the m-bit quantizer must be

increased at each successive pass around the feedback loop to ensure that the coarse quantizer is

driven with the proper amplitude. The gain required to meet this condition is

N mp= m

p


(2.1)

where is the resolution of the coarse quantizer and is the number of the pass through the loop.

For example, on the 3rd pass through a loop with a 4-bit quantizer, the amplifier gain should be

. Similarly, the digital words emanating from the coarse quantizer are

multiplied by the same factor inside the SAR (this weighting applied to incoming words

distinguishes the SAR from a simple accumulator).

When the coarse quantizer resolution, , is unity, the quantizer itself reduces to a

comparator and the amplifier can therefore, be eliminated. This simplified feedback converter (Fig.

2.3) is called a successive approximation A/D converter and represents the lower bound on

feedback ADC complexity for a given resolution [31]. Conversely, when the coarse quantizer

resolution, , equals the full ADC resolution, , the SAR and reconstruction DAC become

unnecessary, and the feedback architecture reduces to a flash implementation. Therefore, the

feedback A/D converter architecture is a canonical structure, equivalent to a flash converter when

and ; and equivalent to a successive approximation converter when and

. Clearly, intermediate values between these extremes represent different trade-offs between

complexity and speed of operation.

Figure 2.2. Feedback or multi-pass A/D converter topology.

N-bit Digital Output

SwitchableGain Stage

InputSignal

N-bit DAC

-

A =2V

m(p-1)

m

N Successive Approximation

Register(SAR)

m-bit Quantizer

ResidueSignal

ReconstructedReplica

AV 2m p 1−( )=

m p

AV 24 3 1−( ) 256= =

m

m N

m N= p 1= m 1=

p N=


The feedback A/D converter architecture can offer significant hardware savings compared

to a flash implementation because the coarse quantizer resolution, , can be much smaller than the

converter resolution, . However, the feedback implementation suffers from several drawbacks

reducing its suitability for the present application including the following:

• Requires passes to generate full N-bit output word, thus limiting

maximum throughput rate

• Requires N-bit accurate DAC

• Requires switchable gain amplifier which can be very difficult to realize in practice

Largely because of the limitation on maximum throughput rate, the feedback architecture was

rejected for this project.

2.1.3 Feedforward Converters

[32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [20] [43] [44] [45] [46] [47] [18] [23] [19]

[51] [52] [53] [54] [55] [22]

By employing a cascade of coarse quantizer stages, the feedforward ADC topology (Fig.

2.4) mitigates the throughput limitations which constrain feedback converters. Each stage

Figure 2.3. Successive approximation A/D converter topology.

Vin

N-bit DigitalOutput

N-bitDAC

SuccessiveApproximation

Register(SAR)

m

N

p N m⁄=


comprising the feedforward A/D performs the same operations found in the feedback architecture,

namely: coarse quantization, conversion back to analog format via D/A conversion, subtraction

from the input signal to form a residue, and amplification. Rather than applying these operations

times in succession as in the feedback topology, stages are cascaded to produce the same effect.

The digital data from each of the quantization stages must be suitably weighted before the words

are summed to form the N-bit digital output. (This mechanism is akin to the weighting applied by

the SAR in the feedback arrangement.)

Several advantages accrue from this cascade arrangement. The architecture is inherently

faster than the feedback topology, no switchable gain amplifier is required, and digital error

correction is possible to make accuracy virtually independent of threshold errors within the

constituent coarse quantizers. However, two chief disadvantages compromise the suitability of this

scheme for high-speed operation. First, since the feedforward converter utilizes stages similar in

complexity to the entire feedback ADC, its complexity is also approximately times the

complexity of the feedback case. Second, since each signal must ripple through a cascade of sub-

stages, the net throughput is only marginally greater than in the feedback architecture. The pipelined

Figure 2.4. Feedforward A/D converter topology.

VinStage 1 Stage pStage i

+

_

-bitADC

mi -bitDAC

mi

bits of N-bitdigital output

mi

miA =2V

p

p

p

p

p

p


A/D topology, described next, circumvents this settling problem.

2.1.4 Pipelined Feedforward Converters

The pipelined feedforward A/D converter architecture (Fig. 2.5) alleviates the throughput

limitations associated with the un-pipelined feedforward case by placing a T/H at the input of each

of the stages comprising the converter. In this way, while stage 1 is processing an input sample,

stage 2 processes the preceding sample, stage 3 processes the sample before that, and so on; such

that all stages process one sample per clock cycle. Although this operation produces a delay or

latency of sub-conversions before producing a valid output code, the throughput of the system is

equal to that of each processing cell and can be significantly higher than the corresponding

throughput of any of the converters discussed previously. The pipelined feedforward architecture

combines the advantages of high throughput demonstrated by flash converters along with low

complexity, power dissipation and input capacitance characteristic of feedforward converters. The

sole disadvantage associated with the pipelined approach is the requirement for T/H circuits

which can be very difficult to implement monolithically. Since analog switches (fundamental to T/H

Figure 2.5. Pipelined A/D converter topology.

VinStage 1 Stage pStage i

+

_

-bitADC

mi -bitDAC

mi

bits of N-bitdigital output

mi

miA =2VT/H

p

p

p


operation) are difficult to implement using bipolar components (as discussed in chapter 3) most

pipelined A/D converters have utilized CMOS semiconductor processes [57], [58], [21], [60], [61],

[26], [63], [64], [65]. However, the benefits of the pipelined architecture, high-throughput combined

with low complexity, provide compelling motivation to utilize this topology. If monolithic T/H

circuits with suitable performance can be developed, the pipelined A/D topology provides the

technique for extending high-throughput, high-resolution conversion beyond those limits currently

attainable.

2.1.5 Folding Converters

A folding A/D converter (Fig. 2.6) operates in a similar manner to a feedforward ADC by

coarsely quantizing the incoming signal and generating a residue signal for further quantization by

a lower resolution succeeding stage. However, in a folding converter, the residue signal is formed

by a special analog circuit (the Analog Folding Block highlighted in figure 2.6) which operates

simultaneously with the coarse quantizer [66], [45], [67], [68], [69], [24], [71], [72], [73], [12], [75],

[52]. This arrangement obviates the need for a T/H between the coarse and fine quantizer by

forming the residue signal without going through an A/D-D/A combination with its concomitant

clock delay. The folding converter depicted in figure 2.6 corresponds to a 2-stage feedforward

implementation with a -bit coarse quantizer and an -bit fine quantizer, where

Figure 2.6. Folding A/D converter topology.

Vin


Logic

(log F)-bit

ADC2

(N-log F)-bit

Flash ADC

(2 / F Comparators)

2

N

Analog Folding BlockVout

Vincycle

1cycle

2cycleF-1

cycleF

cycle3

FineQuantizer

CoarseQuantizer

ResidueSignal

log2F N log2F−( )


is the number of periods orfolds in the transfer function of the analog folding block. This analog

cell, details of which are described in chapter 6, performs the function of the DAC and the

subtraction element from the feedforward architecture described previously, but does so in an un-

clocked manner enabling simultaneous operation of the coarse and fine quantizers. Since the folding

A/D architecture offers low complexity along with potentially high-speed operation, this topology

remains as a viable candidate for the 10-bit, 100 Msps converter designed here.

2.1.6 Algorithmic (Cyclic) Converters

[32] [38] [77] [78] [79] [80] [76] [61] [26] [81] [53] [82]

A canonical ADC structure similar in form to the successive approximation topology is the

algorithmic A/D converter (Fig. 2.7) which is sometimes referred to as a cyclic converter [76], [38].

In this arrangement, conversion begins by comparing the input signal to a mid-scale value. If the

input exceeds this mid-scale reference, the reference is subtracted from the input, and the result is

amplified by 2 in preparation for further processing. This procedure is performed once for each bit

of resolution required in the A/D conversion with the comparator output on the pass

representing the MSB of the resulting codeword. An input multiplexor and T/H are necessary

to coordinate signal flow and timing within the converter. Although extremely simple and

potentially very accurate, the cyclic topology is not suitable for high-speed operation because of the

Figure 2.7. Algorithmic A/D converter topology.

F

+

-

Vref/2

Comparator

Amplifier

Vin

Vref/2

+

-

Serial Output

Bit-stream

S/H

X2

p-th

p-th


multiple comparisons necessary during each conversion.

As in the transformation from the feedback to the feedforward architecture, several

algorithmic structures can be placed in cascade to form a converter with higher complexity but

accompanied by an attendant increase in maximum throughput rate. Such a topology has been

termed a bit-serial A/D converter (Fig. 2.8) but is actually a special case of the pipelined

feedforward architecture constructed from 1-bit stages. This conversion technique is very attractive

because it is simple and can be easily extended to higher resolutions by adding more identical

stages. However, since each stage requires a T/H circuit, the bit-serial approach has been largely

limited to CMOS implementations [58], [21].

2.1.7 Architecture Selection

Table 2.1 includes a summary comparison among the architectures described above. Based

on the relative advantages of these competing approaches, the topology for a 10-bit, 100 Msps low-

power A/D was selected. A flash architecture was rejected because its power dissipation for a 10-

bit implementation would exceed the 750 mW goal unless extremely low bias levels are used. Such

Figure 2.8. Bit serial A/D converter topology.

VinStage 1 Stage pStage m

+

Vref/21-Bit

Output

-

Vref/2

X2S/H


low bias levels compromise comparator settling time, thus reducing maximum achievable sample-

rate. In contrast, the feedback architecture, although capable of low power operation, was deemed

too slow to meet the 100 MHz sample-rate requirement. Likewise, because of its sequential nature

of operation, the algorithmic topology was rejected for inadequate speed. Although capable of

somewhat faster operation than the feedback or algorithmic architectures, the feedforward approach

was deemed too slow for the demanding 100 Msps operating speed required. The remaining

candidate converter types include the pipelined feedforward structure and the folding

implementation. Both of these conversion methods show promise, however, as will be

QuantizerArchitecture

Advantages Disadvantages

Flashor

Parallel

Very fast

Basically linear & monotonic

No D/A required

Very high transistor count

Very high power dissipation

Resolution limited by input rangeand transistor mismatch

High input capacitance

Feedbackor

Multi-pass

Low transistor count

Single input T/H required

Error correction possible

Feedback reduces maximum sam-ple rate

Subtraction element required

Switchable gain amplifier required

D/A required

FeedforwardModerate transistor count


Low input capacitance

Moderate sample rate

PipelinedFeedforward

Very high speed



Multiple T/H circuits required

Folding

High speed

Low transistor count

Folding circuit replaces coarsequantizer and D/A


Resolution limited

Folding circuit cannot realize idealtransfer function

T/H required for high input fre-quencies

Conceptually complex

Difficult to layout

Algorithmicor

Cyclic

Very low transistor count

Low power

Low speed

Table 2.1. Comparison among several A/D converter architectures.


demonstrated in the next section, the folding A/D converter in incapable of attaining 10-bit

resolution without trimming. Therefore, a hybrid approach using a pipelined feedforward

architecture with a constituent fine quantizer base on a folding topology was selected. The details

of this architecture and rationale for its selection are discussed next.

2.2 10–Bit High –Speed Converter Topology

A folding A/D converter promises low-power dissipation and is capable of high operating

speed; however, mismatches in transistor within the analog folding block can lead to

unacceptable threshold errors caused by perturbations in the resultant residue waveform from the

ideal. These level errors manifest themselves as degradations in achievable SNR (see section 1.3.3

and equation 1.109) or alternatively as decreases in circuit yield given a maximum INL

specification. If the cycle transitions of a folding characteristic such as that depicted in figure 2.6

are perturbed by transistor mismatches, the resultant ADC thresholds will be similarly

modified. Equation 1.109 predicts that when calculating the effect of such errors on A/D signal-to-

noise ratio, the variance of the threshold errors adds to the quantization noise power. Comparing the

expected SNR of a folding A/D converter including the effects of mismatches with the

maximum achievable SNR gives the expected SNR degradation from ideal (Fig. 2.9). SNR

degradation is plotted in figure 2.9 for combinations of two parameters, and . is the

number of folds in the analog residue waveform generated by the analog folding block, and

is the voltage spacing between adjacent cycle transitions in the folding characteristic. For all

combinations of these two parameters and assuming , the standard deviation of

mismatch, is approximately ; SNR degradation is or less for ADC resolutions

less than or equal to 8 bits. However, SNR degradation becomes much more significant in the higher

resolution converters, and . In the 9-bit case, SNR degradation is probably

acceptable for some combinations of and ; however in the 10-bit case, SNR degradation is

unacceptably large for all combinations of these parameters. Alternatively, the detrimental effect of

transistor mismatch on folding A/D performance can be measured by circuit yield. Figure 2.10

depicts ADC yield normalized to maximum allowable INL for the circuit parameters and ,

and for several values of converter resolution, . For typical values of (about 1/2 mV) and

maximum INL (about 1/2 LSB), circuit yield is below 50% in all cases except ,

VBE

VBE

VBE

F VTap F

VTap

σVBEVBE

1 2mV⁄ 1 2dB⁄

N 9= N 10=

F VTap

VBE

F VTap

N σVBE

F 16=

2.2 10–Bit High–Speed Converter Topology 91

. Note by contrast, that for and , yield is virtually 100% for all

combinations of and . Intuitively, this condition arises because the converter full-scale

range is determined by

(2.2)

(see figure 2.6). Therefore, the threshold spacing, , is given by

(2.3)

This voltage must be large compared with to prevent significant threshold errors implying that

should be increased to mitigate the effects of transistor mismatch. However, cannot be

Figure 2.9. SNR degradation in folding A/D converters due to

mismatches. Quantizer resolution indicated on plot.

0 .25 .5 .75 1σVbe (mV)

-2

-1.5

-1

-.5

0

SN

R D

egra

dat

ion

(d

B)

F=8, VTap=64mVF=8, VTap=128mVF=16, VTap=64mVF=16, VTap=128mV

-2

-1.5

-1

-.5

0

SN

R D

egra

dat

ion

(d

B)

0 .25 .5 .75 1σVbe (mV)

N=7 N=8

N=9 N=10

Vbe

Vbe

VTap 128mV= N 7= N 8=

F VTap

VFSR F VTap×=

Q

QVFSR

2N

F VTap×

2N= =

σVBE

VFSR F


made arbitrarily large without unduly loading the T/H circuit which must drive the A/D converter.

Likewise, is constrained to a small range of values because it must be a small multiple of ,

the thermal voltage, for proper operation of the folding circuits envisioned. (These two points will

be made more clear when folding circuits are describe in detail in chapter 6). Therefore, is

limited to a maximum value of approximately

(2.4)

The quantizer step-size, , then becomes 2 mV: not large enough relative to to make

Figure 2.10. Yield in folding A/D converters for 8 (lower) or 16 (upper) foldsper stage. is 64 mV (left) or 128 mV (right). The normalization of the

independent variable to INL refers to maximum specified INL above which pointa converter fails the performance test, e.g. if maximum specified INL is1/2 LSB, and is 1/2 mV; then the appropriate value on the independent

axis for determining yield is 1.

0 1 2 3 4 5σVbe /INL (mV/LSB)

0

10

20

30

40

50

60

70

80

90

100

Yie

ld (

%)

0

10

20

30

40

50

60

70

80

90

100Y

ield

(%

)

0 1 2 3 4 5σVbe /INL (mV/LSB)

N=10

N=9

N=8

N=7

N=10

N=9

N=8

N=10

N=9

N=8

N=7

N=10

N=9

N=8

N=7

F=16VTap=128mV

F=16VTap=64mV

F=8VTap=128mV

F=8VTap=64mV

VTap

σVBE

VTap VT

VFSR

VFSR F VTap×=

16= 128mV×2.048V=

Q σVBE


transistor mismatch effects negligible.

The preceding discussion along with the data in figures 2.9 and 2.10 indicate that without

trimming, a 10-bit folding A/D converter will exhibit very low yield coupled with degraded SNR

because mismatches significantly perturb threshold positions from their ideal locations.

Therefore, the second acceptable topology, the pipelined feedforward approach, was selected as the

architecture for this project. However, since the folding A/D implementation offers significant

performance advantages over other approaches for medium-resolution applications, a folding

converter was selected to realize the fine quantizer. The resulting ADC architecture (Fig. 2.11)

comprises a 2-stage pipelined feedforward converter with an input T/H circuit and an interstage T/H

circuit. The coarse quantizer drives a reconstruction DAC whose output is subtracted from the held

input to form a residue signal. This residue is amplified appropriately and then digitized by afolding

fine quantizer. The linearity required from the components of this circuit are indicated in figure 2.11.

Both T/H circuits must exhibit linearity consistent with 10-bit operation. Similarly, the DAC and

subtracter must be linear to this level. However, owing to the benefits of digital error correction, the

coarse quantizer needs linearity only consistent with its resolution, , not the full 10-bit resolution

of the converter [58], [21]. The amplifier and fine quantizer must exhibit linearity consistent with

bits, as expected.

As will be discussed in chapter 3, implementing T/H circuits in bipolar technology proves

Figure 2.11. Typical 2 stage pipelined A/D converter.

VBE

n2-bitFolding &

InterpolatingFine

Quantizer

N-bitDigitalOutput

Vin

First Stage Second Stage

Combining Logic

Error Correction,Encoding, and

Output Registers

DelayRegister

Required linearity: = N bit = n1 bit= n2 bit

+

-

n1-bitDAC

S/H1

S/H2

n1-bitFlash Coarse

Quantizer

X2(n1-1)

n1

n2


to be very difficult and requires significant power dissipation, particularly when wide dynamic

range is necessary. Therefore, a modification to the typical pipelined architecture which reduces the

required linearity of the second (or interstage) T/H was devised. This modification entails moving

the interstage T/H to a location after the subtraction element (Fig. 2.12) where its linearity need only

match that of the quantizer which it drives. The corresponding timing changes necessary to

implement this modification are next described.

2.2.1 Timing Scheme for Pipelined Converter

In a conventional pipelined feedforward ADC (Fig. 2.13), the coarse quantizer and the

interstage T/H share inputs. These two elements also operate in-phase, meaning that during one

clock phase both elements track their mutual input, and during the other clock phase the T/H freezes

its output while the coarse quantizer switches its output to a new digital code. The timing signals

necessary to produce this behavior are included in figure 2.13, and the resultant output signals from

each of the converter blocks are shown in figure 2.14. From these diagrams the throughput delay is

seen to be 1.5 clock periods.

In the modified pipelined architecture, the interstage T/H is relocated after the subtracter

circuit; therefore, the system timing is altered correspondingly (Fig. 2.15). In this arrangement, the

Figure 2.12. Alternative implementation of 2-stage pipelined A/D converter.

n2-bitFolding &

InterpolatingFine

Quantizer

S/H2

N-bitDigitalOutput

Vin


Combining Logic

S/H1

n1-bitDAC

+

-


Output Registers

DelayRegister

Required linearity: = N bit

X2(n1-1)

= n1 bit= n2 bit

n1-bitFlash Coarse

Quantizer

n2-bit


coarse quantizer and interstage T/H donot share a common input, nor do they operate in-phase.

Rather, the input T/H and the coarse quantizer operate in-phase so that both elements operate in

track mode simultaneously. Therefore, the coarse quantizer’s digital output word tracks the

dynamic input signal (Fig. 2.16), and the DAC analog output forms a real-time (albeit coarse)

replica of the input. The dynamically changing DAC output subtracts from the active output of the

first T/H to form the residue signal which drives the interstage T/H. The throughput delay in this

arrangement is 1.5 clock periods as in the conventional case. Since the input T/H and the coarse

quantizer operate in track mode simultaneously, the coarse quantizer must digitize a dynamic signal

rather than a static one. The coarse quantizer is therefore susceptible to the finite aperture time

effects described in section 1.3.3. Two factors mitigate these effects which would normally degrade

coarse quantizer linearity severely. First, the resolution of the coarse quantizer is quite low (only 4

bits as will be seen shortly) so that large aperture-time induced errors are tolerable. And second, the

clock to the coarse quantizer is retarded by 1 ns to allow the T/H output to settle before quantization

begins.

Figure 2.13. Conventional timing scheme for pipelined A/D converter.

Vin

DigitalOutput

ADC 2

ADC 1

ErrorCorrect

&LatchOut

T/H 1

Φ1

Φ1

Φ1 Φ1

DELAY(Master)

DAC

Φ1

T/H 2

Φ1

T/H 1

T/H 2

ADC 1

ADC 2

DELAYMaster

Output

T H T TH H

T H T THH

RT T TRR

Φ1 Φ1 Φ1Φ1 Φ1 Φ1

R=RegenerateT = Track H = Hold

5ns 5ns

RT T TRR

RT T TR R

RT T TR R


This rather unconventional clocking arrangement is motivated by the desire to replace the

interstage T/H requiring 10-bit linearity with a simpler and lower power T/H requiring only

linearity. The new scheme does not degrade converter linearity because the coarse quantizer is very

low resolution, only 4 bits, and because the coarse quantizer clock signal is delayed slightly to allow

adequate settling before quantization. The low resolution coarse quantizer is made possible because

the fine quantizer which uses the folding architecture is particularly efficient, realizing 7 bits of

resolution with roughly the same number of transistors and power dissipation as the 4-bit coarse

quantizer.

2.3 Pipelined Feedforward Partitioning

In a pipelined feedforward A/D implementation without error correction, the converter

resolution equals the sum of the resolutions of the individual stages. If error correction is used, the

converter resolution diminishes by the amount of redundancy (in bits) used for the correction. In the

present design, one bit of error correction or overrange is used so the sum of the resolutions of the

individual stages must equal 11. The next sub-sections describes the rationale behind the

Figure 2.14. Output signals from converter elements in pipelined A/Demploying conventional timing scheme.

T/H 1Output

ADC 1Output

T/H 2Output

ADC 2Output

DelayOutput

LatchOutput

n n+1 n+2n-1

n-1 n n+1

n-2 n-1 n n+1

n-2 n-1 n

n-1 n n+1

DACOutput

n-1 n n+1

n-2 n-1 n n+1

m2-bit

2.3 Pipelined Feedforward Partitioning 97

partitioning of this total resolution between the coarse and fine quantizers.

Most feedforward converters use substantially identical architectures for each constituent

quantizer. Therefore, dividing the complexity evenly between stages reduces the total complexity

of the A/D converter. Since in this project a very efficient folding converter is used as the fine

quantizer, evenly partitioning the resolution among stages does not minimize device count. Rather,

a distribution with a very low resolution coarse quantizer followed by a higher resolution folding

fine quantizer yields lower complexity.

Circuit yield and expected performance also play a role in selecting the partitioning of

resolution among stages. Some selections are more sensitive to errors induced by device

mismatches and are therefore less robust than other partitionings. Optimized converter partitioning

minimizes device count (hence power dissipation and die size) without degrading yield or expected

performance given device mismatches.

Figure 2.15. Modified timing scheme for pipelined A/D converter.

T/H 1

T/H 2

ADC 1

ADC 2

DELAYMaster

Output

T H

R

T TH H

T H T THH

T T TR

RT T TR R

RT T TRR

RT T TRR

Φ1 Φ1 Φ1Φ1 Φ1 Φ1

R=RegenerateT = Track H = Hold

1ns 5ns 5ns

Vin

DigitalOutput

T/H 2 ADC 2

ADC 1

DACDELAY STAGE

ErrorCorrect

&LatchOut

T/H 1

Master Slave

Φ1

Φ1

Φ1Φ1 Φ1

Φ1Φ1


2.3.2 Hardware Complexity (Parts and Power)

The number of transistors in a flash quantizer is proportional to the number of comparators

required, , where the proportionality constant equals the number of transistors necessary for

each comparator (including associated circuitry such as a preamplifiers and logic gates for

encoding). Likewise, the number of transistors required for a folding quantizer equals the sum of

the transistors comprising the analog folding block, the coarse quantizer, and the fine quantizer (see

Fig. 2.6). The analog folding block and the coarse quantizer complexity depend only upon , the

number of periods in the folding characteristic, and not upon , the quantizer resolution, whereas

the fine quantizer complexity is proportional to . Therefore, the total complexity of an

folding quantizer equals a constant proportional to plus a term proportional to .

The above results are summarized in figure 2.17 which plots total complexity (as measured

by transistor count) of a 10-bit 2-stage feedforward A/D converter consisting of a flash coarse

quantizer and a folding fine quantizer and assuming one bit of overrange for error correction. This

Figure 2.16. Output signals from converter elements in pipelined A/Demploying modified timing scheme.

T/H 1Output

ADC 1Input

T/H 2Output

ADC 2Output

DelayOutput

Latch Output

n n+1 n+2n-1

n-1 n+1n n+2

n-1 n n+1

n-2 n-1 n n+1

n-2 n-1 n n+1

n-2 n-1 n

DACOutput

n-1 n n+1 n+2

2N 1−

F

N

2N F⁄ N-bit

F 2N F⁄


plot shows that ADC complexity is minimized if the first quantizer is selected to have 4-bit

resolution. This is a broad minimum, however, so 3-bit and 5-bit coarse quantizers also produce low

total converter complexity. As will be shown in the next sub-section, the 3-bit coarse quantizer

partitioning is overly sensitive to component mismatching producing inadequate yield and

excessive threshold errors. Therefore, only the partitionings based on 4-bit and 5-bit coarse

quantizers are considered further. The A/D converter utilizing a 5-bit coarse quantizer (called the 5-

6 partitioning) is depicted in figure 2.18 which indicates the linearity requirements of each

component. The contending architecture based on a 4-bit coarse quantizer (the 4-7 partitioning) is

depicted in figure 2.19. Since the 4-7 approach exhibits lower complexity than the 5-6 partitioning,

the former should be utilized unless sensitivity to component mismatches proves otherwise.

2.3.3 Performance (Yield and SNR)

The 4-7 and 5-6 partitionings exhibit different sensitivities to component mismatches.

Figure 2.17. Comparison of A/D converter complexity versus fine quantizerresolution.

1 2 3 4 5 6 7 8 9 10

First Quantizer Resolution

102

103

104

Tran

sist

or C

ount

First Quantizer

10-Bit A/D

Second

Assumes 1-Bit Overrange

(8 Folds) Quantizer


These sensitivities can be ascertained by simulation, and an optimum partitioning can be selected

based upon the results. Component mismatches which affect ADC performance include DAC

current source error, coarse quantizer INL, fine quantizer INL, fine quantizer gain error, and DAC

gain error. The effects of each of these error sources is investigating by simulating the ADC transfer

function in the presence of the specified error. The threshold perturbations due to the error source

can then be quantified by specifying the resultant A/D converter SNR.

Figure 2.18. 5-6 pipeline partitioning.

Figure 2.19. 4-7 pipeline partitioning.

Vin

10-bitDigitalOutput


Combining Logic

+

-


Output Registers

DelayRegister

Required linearity: = 10 bit = 5 bit= 6 bit

S/H1

5-bitDAC

5-bitFlash Coarse

Quantizer

S/H2

6-bitFolding &

InterpolatingFine

Quantizer

X16

Required linearity: = 10 bit

Vin

10-bitDigitalOutput


Combining Logic

+

-


Output Registers

DelayRegister

= 4 bit= 7 bit

S/H1

4-bitDAC

4-bitFlash Coarse

Quantizer

S/H2

7-bitFolding &

InterpolatingFine

Quantizer

X8


DAC current source matching is largely determined by resistor matching which is usually

expressed by the standard deviation of resistor mismatch normalized to the mean resistance value.

That is, for resistors with mean value , and standard deviation , the resistor mismatch is

expressed in percent. In a well-controlled monolithic process is usually a small

fraction of 1%. The effect of DAC current source matching was determined via Monte Carlo

analysis where, for a large number of test cases, a random distribution is selected for the DAC

current source values. The resultant ADC transfer function is calculated, and SNR based upon

threshold errors is determined. The distribution of SNR values associated with the ensemble is then

specified by its ensemble average or yield, the percentage of test cases where SNR is above some

specified value (in this case 59 dB). The dependence of A/D converter SNR on DAC current source

mismatch (Fig. 2.20) is stronger for the 4-7 partitioning than for the 5-6 partitioning. However, the

anticipated resistor mismatch in Tektronix’ SHPi process is approximately 0.1%. At this value of

, the difference in expected SNR between the two cases is negligible.

Coarse quantizer INL is largely due to transistor mismatches and is specified by its rms

value in LSBs. The effect of this error source on converter SNR was investigated with the same

method used for DAC current source mismatch phenomenon. Owing to the digital error correction

used in the proposed topologies, coarse quantizer INL less than 1/2 LSB in magnitude does not

affect A/D converter SNR (Fig. 2.21). Since 1/2 LSB rms INL is easily obtainable for both the 4-

bit quantizer and the 5-bit quantizer cases, coarse quantizer INL will not substantially impact

overall A/D converter performance.

Fine quantizer INL was investigated in identical manner to coarse quantizer INL resulting

in the plots included in figure 2.22 which indicate that SNR sensitivity to fine quantizer INL is

identical for the 4-7 and 5-6 partitionings. However, since a specified INL in a 6-bit fine quantizer

is more readily obtained than in a 7-bit quantizer, this data indicates that the 5-6 partitioning is more

robust in this regard.

For the feedforward topology to operate correctly, the input-referred full-scale-output from

the DAC must equal the full-scale input to the coarse quantizer. Likewise, the full-scale output from

the amplifier block must equal the full-scale input to the fine quantizer. Mismatches in these settings

introduce systematic errors into the ADC transfer function.

µR σR

σR µR⁄ σR µR⁄

σR µR⁄


If the DAC full-scale-output is set incorrectly; that is, if its gain is erroneous, threshold

errors result which degrade SNR. Such threshold errors are a deterministic function of the DAC

gain error and can be calculated via simulation. A/D converter SNR, calculated in this manner, is

plotted for a range of gain errors in figure 2.23. This figure indicates that SNR degradation for the

4-7 partitioning is a stronger function of DAC gain error than for the 5-6 partitioning. However, for

DAC gain errors of approximately 1%, the degradation is less than 2 dB and the discrepancy

between the 4-7 partitioning and the 5-6 is even less.

Figure 2.20. 10 bit A/D converter yield (upper) and mean SNR (lower) versussegmented DAC current source mismatch for both 4-7 and 5-6 partitioning.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0DAC Current Source Matching (%)

54

55

56

57

58

59

60

61

62

Mea

n S

NR

(d

B)

0

10

20

30

40

50

60

70

80

90

100

AD

C Y

ield

at

59 d

B (

%)

n1=4n2=7

n1=5n2=6

n1=4n2=7

n1=5n2=6


Fine quantizer gain errors are treated in a manner analogous to DAC gain errors.

Simulations of this deterministic phenomenon indicate that the sensitivity of the 4-7 topology to this

effect is greater than the 5-6 case (Fig. 2.24). Again, however, the difference in sensitivities is small

for the range of mismatches anticipated which is approximately 1%.

To assess the cumulative effect of component mismatches on SNR, Monte Carlo

simulations varying all of the above error sources were performed. The resulting histograms of SNR

Figure 2.21. 10 bit A/D converter yield (upper) and mean SNR (lower) versuscoarse quantizer INL for both 4-7 and 5-6 partitioning.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Coarse Quantizer INL (Bits)

40

45

50

55

60

65

Mea

n S

NR

(d

B)

0

10

20

30

40

50

60

70

80

90

100

AD

C Y

ield

at

59 d

B (

%)

n1=4n2=7 n1=5

n2=6

n1=5n2=6

n1=4n2=7


give insight into the expected operation of the 4-7 and 5-6 partitioned A/D converters. These

histograms (Fig. 2.25) indicate that for the component mismatches anticipated, the expected SNR

for the 5-6 partitioning will be clearly superior to that for the 4-7 partitioning. However, the 4-7

partitioned samples indicate adequate performance with nearly all samples exhibiting SNR equal to

59 dB or greater.

Figure 2.22. 10 bit A/D converter yield (upper) and mean SNR (lower) versusfine quantizer INL for both 4-7 and 5-6 partitioning.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Fine Quantizer INL (Bits)

56

57

58

59

60

61

62

Mea

n S

NR

(d

B)

0

10

20

30

40

50

60

70

80

90

100

AD

C Y

ield

at

59 d

B (

%)

n1=5n2=6

n1=4n2=7

n1=5n2=6

n1=4n2=7


Because the 4-7 partitioning offers a significant complexity advantage over the 5-6

partitioning and delivers adequate insensitivity to expected component mismatches, this topology

was selected over the more robust 5-6 approach. The final 10-bit A/D converter architecture (Fig.

2.26) consists of a pipelined feedforward topology with a 4-bit coarse quantizer and a 7-bit folding

fine quantizer. The interstage T/H is located after the subtracter element so that it needs to exhibit

linearity consistent with 7-bit quantization. The input T/H and the coarse quantizer operate in track

Figure 2.23. 10 bit A/D converter SNR (upper) and gain error (lower) versusDAC gain error for both 4-7 and 5-6 partitioning.

-10 -8 -6 -4 -2 0 2 4 6 8 10DAC Gain Error (%)

-10

-5

0

5

10

AD

C G

ain

Err

or

(%)

44

46

48

50

52

54

56

58

60

62

SN

R (

dB

)

n1=4n2=7

n1=5n2=6

n1=5n2=6

n1=4n2=7


mode simultaneously to enable this placement of the interstage T/H. Consequently, the coarse

quantizer sample clock is retarded by 1 ns relative to the other A/D clocks to allow for adequate

settling from the input T/H before coarse quantization. The one bit of overrange is used for error

correction so that coarse quantizer threshold errors less than 1 LSB will not affect the A/D converter

linearity.

Figure 2.24. 10 bit A/D converter SNR (upper) and gain error (lower) versusfine quantizer gain error for both 4-7 and 5-6 partitioning.

-10 -8 -6 -4 -2 0 2 4 6 8 10Fine Quantizer Gain Error (%)

-0.05

-0.04

-0.03

-0.02

-0.01

0.00

0.01

0.02

0.03

0.04

0.05

AD

C G

ain

Err

or

(%)

44

46

48

50

52

54

56

58

60

62

SN

R (

dB

)

n1=4n2=7

n1=5n2=6

n1=5n2=6

n1=4n2=7


References


Figure 2.25. Histogram of A/D converter SNR for 4-7 (upper) and 5-6 (lower)partitionings.

58.0 58.5 59.0 59.5 60.0 60.5 61.0 61.5 62.0SNR (dB)

0

10

20

30

40

50

60

70

Nu

mb

er o

f O

ccu

rren

ces

0

5

10

15

20

25

30

35

40

Nu

mb

er o

f O

ccu

rren

ces

n1=4, n2=7Gain Error = 0.25%Offsets = 2 mVINL1 = 1/32 LSBINL2 = 1/4 LSBDAC Error = 0.2%

n1=5, n2=6Gain Error = 0.25%Offsets = 2 mVINL1 = 1/16 LSBINL2 = 1/8 LSBDAC Error = 0.2%


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Vin

10-bitDigitalOutput

Required linearity: = 10 bit = 7 bit = 4 bit


Combining Logic

T/H2

X8

Folding &Interpolating

SecondQuantizer

7-Bit


Output Registers

DelayRegister

T/H1

DAC

4-BitFlash FirstQuantizer

4-Bit


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Chapter 3

Sample-and-Hold Design

The function and specification of Sample-and-Hold (S/H) circuits was discussed in section

1.3.1. The hardware implementations of such devices which are also referred to as Track-and-Hold

(T/H) circuits or Sample-and-Hold Amplifiers (SHAs) will now be described. A T/H circuit

comprises five elements; an input preamplifier, a sampling switch, a storage element which is

assumed to be a capacitor†, an output amplifier or postamplifier, and a clock buffer (Fig. 3.1a). The

preamplifier presents a high or well-controlled impedance to the signal source while maintaining a

low output impedance for rapidly charging and discharging the storage or hold capacitor.

Additionally, the preamplifier can provide gain to maximize the dynamic range of the stored signal.

The sampling switch, when closed, enables the preamplifier to drive the stored signal on the hold

capacitor; and, when open, disconnects the hold capacitor from the preamplifier preserving a

constant stored signal equal to the value at the instant the switch was opened. The postamplifier

presents a high impedance to the hold capacitor to minimize leakage of the stored charge and drives

succeeding circuitry with a (possibly amplified) replica of the held signal. Frequently, the

postamplifier exhibits low output impedance thus ensuring adequate frequency response and

distortion characteristics when driving capacitive loads. The clock buffer facilitates switch

operation by providing suitable logic signals in response to the incoming clock. Such buffering

†. T/H circuits which employ inductors as storage elements are possible in theory but for a varietyof reasons have proven impractical. Superconducting coils have been investigated for this purpose.

116 Chapter 3 Sample-and-Hold Design

requires adequate gain and frequency response without unduly exacerbating clock timing jitter. This

operation is depicted graphically in figure 3.1b.

Each of the elements described above can be easily implemented in a standard bipolar

integrated circuit technology (such as Tektronix’ SHPi) with the exception of the sampling switch.

High-performance switches are particularly difficult to realize in bipolar processes, and the

availability of native integrated circuit switches in MOS technologies provides compelling

motivation to use such processes when analog switching is necessary. The inferior capabilities of

MOS devices in high-speed, high-accuracy applications; however, limits the utility of this option.

Complementary processes combining both bipolar and MOS devices (BiCMOS) provide an

adequate solution, but these processes are currently rare and expensive. Therefore, utilization of a

high-performance bipolar switch is imperative. Such a circuit will be discussed in detail next.

3.1 Sampling Bridge Topology and Operation

The basis of almost all analog switches implemented in bipolar IC technologies is the diode

sampling bridge (Fig. 3.2) which provides a low impedance between input and output when

conducting, high isolation when not conducting, and very fast switching between the conducting

and non-conducting states. This architecture has been widely used in sampling applications for

many years owing to its simplicity and speed of operation [6], [7], [8]. The diode-bridge switch is

Figure 3.1. Track-and-hold building-blocks (a) and operation (b).

InputBuffer

OutputBuffer

ClockBuffer

SamplingSwitch

Track/HoldCommand

HoldCapacitor

Vin Vout

time

AmplitudeAcquisition

timeTracktime

Settlingtime

time

A/DConversion

time

Track/HoldCommand

Vin

Vout

Hold Sample Hold

Hold Track Hold Track

(a) (b)

3.1 Sampling Bridge Topology and Operation 117

virtually a necessity in bipolar semiconductor technologies lacking field-effect transistors (FETs)

and has been popular in silicon technologies [9], [8], [10], [11], [12] and more recently in Gallium-

Arsenide (GaAs) Heterojunction Bipolar Transistor (HBT) technologies [13], [14]. The diode-

bridge has frequently been used even in some technologies with native FET devices [15], [16], [17],

[18] because of its superior switching properties, but the emerging preeminence of CMOS

technology has driven many workers to pursue high performance track-and-hold circuits based

upon CMOS switches [19], [20], [21], [22], [23], [24], [25]. Others have developed switches in

bipolar technologies without diode-bridges [26], [27], [23] or have utilized FET switches in more

exotic technologies such as GaAs [29], [30]. The diode-bridge switch offers speed and precision

advantages over most other approaches but suffers from some disadvantages which must be

contended with to develop high-performance T/H circuits. These drawbacks will be discussed in the

next several sections.

The preamplifier and postamplifier in figure 3.2 are simple emitter follower buffers, but

any type of amplifier fulfilling the characteristics described in the preceding introduction will

suffice. Selection of amplifier topologies for these functions depends upon practical considerations

such as linearity, power dissipation, frequency response, complexity, etc. Since this section details

operation of the diode bridge itself, the pre- and postamplifiers comprising the track-and-hold in

figure 3.3 are depicted as ideal elements for simplicity while the bridge drive circuitry consists of a

Figure 3.2. Prototype diode bridge track-and-hold circuit with emitter followerpreamplifier and postamplifier.

D1 D2

D3 D4 CH

Vout

Vin

Preamplifier Diode Bridge Postamplifier


differential transistor pair and ideal current sources. The circuit operates in the following manner.

When in track mode, transistor Q2 conducts all of the diff-pair current causing and

. Consequently, each of the diodes D1 through D4 conducts causing their

small-signal impedances to be very low, . The preamplifier can therefore charge or

discharge the hold capacitor, , through the small impedance

enabling to track . Conversely, in hold mode transistor Q1 conducts the diff-pair current

resulting in and . In this case diodes D1 through D4 conduct no current

thereby interposing a large (ideally infinite) small-signal impedance between the preamplifier and

the hold capacitor. Diodes D5 and D6 conduct pinning the top and bottom of the bridge at

and respectively where is some convenient bias voltage and is the

forward diode voltage drop. In this state the output is effectively isolated from the input. Although

fairly simple and capable of faithfully replicating analog switch operation, this topology suffers

from several drawbacks which limit performance and which will be discussed in detail next.

The nature of diode bridge operation during track mode is quite complicated and will be

elaborated upon with reference to figure 3.4 which shows a diode bridge with ideal current drive.

When the current sources in figure 3.4 are at value zero, all 4 diodes conduct no current and the

Figure 3.3. Diode-bridge track-and-hold with differential pair controllingbridge current.

Vin

Hold Track

VoutVCTX1 X1

I1 I2

D1

D3 D4

D2

D5

D6

Q1 Q2

2IBridge

CH

IBridge

IBridge

I1 0=

I2 2IBridge= I Bridge 2⁄

I Bridge 2VT⁄

CH rd1 rd2+( ) rd3 rd4+( )

Vout Vin

I1 2IBridge= I2 0=

I Bridge

VCT VD− VCT VD+ VCT VD


output terminal is isolated from the input terminal as described previously. When the current

sources are at value , circuit operation depends upon the exponential relationship between

diode voltage and current:

(3.1)

where is the diode saturation current, is the diode area and is the thermal voltage, ,

which equals approximately 26mV at room temperature. Performing KVL around the loop of

diodes gives

(3.2)

which through the use of equation 3.1 becomes

(3.3)

If all of the terms are assumed to be identical (the area parameters through can be

suitably modified to account for any mismatches in saturation current) equation 3.3 can be

Figure 3.4. Diode-bridge switch.

D4D3

D2D1

Vin Vout

0

IBias

0

IBias

I Bias

ID ISAeVD VT⁄

ISAeVD VT⁄= =

IS A VT kT q⁄

VD1 VD3+ VD2 VD4+=

VTlnID1

A1ISVTln

ID3

A3IS+ VTln

ID2

A2ISVTln

ID4

A4IS+=

IS A1 A4


simplified to

(3.4)

where is defined as the ratio of areas as shown.† If all diode areas are equal mandating

equation 3.4 becomes

(3.5)

Performing KVL around the upper (lower) half of the diode ring gives a constraint on and

( and ):

(3.6)

Using the diode I-V characteristic (Eq. 3.1) in the first equation above yields

(3.7)

where the last simplification assumes . Solving for gives

(3.8)

†. This surprisingly simple result is representative of all circuits in which a set ofelements with exponential I-V characteristics form a closed voltage loop. Theabove relationship arises because the elements’transconductances arelinear func-tions of their branch currents. Such topologies have therefore been dubbedtrans-linear circuits [1] and have seen widespread use in analog multipliers, dividers,and other function generators [2], [3], [4], [5].

ID1ID3

ID2ID4

A1A3

A2A4λ= =

λ λ 1=

ID1ID3 ID2ID4=

VD1 VD2

VD3 VD4

Vin Vout− VD2 VD1−=

Vin Vout− VD3 VD4−=( )

Vin Vout− VTlnID2

A2ISVTln

ID1

A1IS−=

VTlnID2

ID1

A1

A2=

VTlnID2

ID1=

A1 A2= ID2

ID2 ID1eVin Vout−( ) VT⁄=


An additional constraint is found by performing KCL at the top of the diode bridge producing

(3.9)

Equations 3.8 and 3.9 can be solved for and .

(3.10)

The differential current can be easily found as well

(3.11)

According to equation 3.6, and are related to in the same manner as and

respectively; therefore, , , and can be found by analogy to equations 3.10

and 3.11.

(3.12)

The following two equivalencies stemming from equation 3.10 and 3.12 should be noted:

(3.13)

and can be used to determine in terms of (where and are defined to flowinto the

ID1 ID2+ IBias=

ID1 ID2

ID1 IBias1

eVin Vout−( ) VT⁄

1+=

ID2 IBiase

Vin Vout−( ) VT⁄


1+=

ID2 ID1−

ID2 ID1− IBiase

Vin Vout−( ) VT⁄1−


1+=

IBias

Vin Vout−2VT

tanh=

VD4 VD3 Vin Vout− VD1

VD2 ID3 ID4 ID3 ID4−

ID3 IBiase

Vin Vout−( ) VT⁄


1+=

ID4 IBias1


1+=

ID3 ID4− IBias

Vin Vout−2VT

tanh=

ID1 ID4=

ID2 ID3=

Iout I in I in Iout


diode bridge at the input and output nodes respectively),

(3.14)

Alternatively, equation 3.11 and 3.13 can be used to solve for

(3.15)

Equation 3.15 predicts that is a function of which implies that the diode bridge

behaves identically to a non-linear resistor placed between the input and output ports. The

incremental value of this conductance which depends upon the applied voltage can be found by

differentiating equation 3.15 with respect to .

(3.16)

or alternatively

(3.17)

Comparing this expression to that generated via small-signal analysis is instructive. In the small-

signal equivalent circuit of the diode bridge in track mode (Fig. 3.5b) each diode is replaced by ,

the diode small-signal resistance, which is equal to . Since each diode is nominally biased

at , becomes . The combination of the 4 resistors in figure 3.5b is

equivalent to one resistor of value spanning from input to output also of value . The large-

I in ID3 ID1−=

ID2 ID4−=

Iout−=

I in

I in ID3 ID1−=

ID2 ID1−=

IBias

Vin Vout−2VT

tanh=

I in Vin Vout−

Vin Vout−

gBridgeI V( )( )d

Vd

IBiasV

2VT( )tanhd

Vd= =

IBiassech2V

2VT( ) 1

2VT=

IBias

2VTsech2

V2VT

( )=

rBridge

VT

IBias 2⁄ cosh2 V2VT

( )=

rd

VT ID⁄IBias 2⁄ rd VT IBias 2⁄( )⁄

rd rd


signal model shown in figure 3.5a gives identical results; that is, a resistance of value

when the voltage difference between input and output is (since

). The large-signal non-linear model more accurately predicts bridge behavior for

with an attendant increase in complexity.

Intuitively, the bridge operates by steering the bridge bias current under control of the

applied voltage. When equals the bridge is balanced with equal current

flowing in all diodes and (Fig. 3.6a). If , diodes D2 and D3 experience

Figure 3.5. Diode-bridge models in track mode. (a) Large-signal model. (b)Small-signal model.

Figure 3.6. Diode bridge operation in track mode. (a) t. (b)

. (c) .

req rd

V1 V2−VT

cosh= rd

VT

IBias 2⁄=

req

rd

V1 V2 V1 V2

rd

rdrd

(a) (b)

VT IBias 2⁄( )⁄ 0

0( )cosh 1=Vin Vout− 0≠

Vout Vin IBias 2⁄

I in Iout 0= = Vin Vout>

D4D3

D2D1

Vin VoutD4D3

D2D1

Vin VoutD4D3

D2D1

Vin Vout

(a) (b) (c)

Vin Vout=Vin Vout> Vin Vout<


larger voltage drops and consequently conduct more current than D1 and D4 resulting in current

being drawn from the input node and delivered to the output (Fig. 3.6b). Conversely, if ,

diodes D1 and D4 conduct more strongly than D2 and D3 with current sunk by the input and sourced

by the output (Fig. 3.6c). In each of these cases and . Also, when one

current exceeds another, it does so by the factor .

The diode-bridge as described above forms the basis of a practical switch which is

supported by a preamplifier and postamplifier as well as circuitry to provide the bridge with the

appropriate pulsed bias current. A block diagram of such a configuration is shown in figure 3.7

which also includes a differential realization incorporating two bridges and differential pre- and

post-amplifiers. Differential implementations enjoy several advantages over single-ended

approaches including: rejection of common-mode errors such as power supply modulation and

unwanted signals coupled onto differential signal nodes; elimination (ideally) of all even order

distortion products; improved dynamic range since signal power quadruples (due to the doubled

signal amplitude compared to the single-ended case) while noise power only doubles; and the

availability of both signal polarities which can frequently be used advantageously to improve

linearity or operating speed. These benefits are countered by the disadvantages that the differential

approach requires more components (and hence die area) and consumes more power than a single-

Figure 3.7. T/H topologies. (a) Single-ended. (b) Differential.

Vin Vout<

ID1 ID4= ID2 ID3=


BridgeDriver

+_ _+

BridgeDriver

(a) (b)

3.2 Error Sources in Diode Sampling Bridges 125

ended implementation. For the present application, the advantages accrued by the differential

approach outweigh the disadvantages; therefore, the more complicated method was used as will be

detailed in section 3.3.

3.2 Error Sources in Diode Sampling Bridges

T/H performance and hence A/D performance are limited by the operation of the diode-

bridge circuit. Understanding the factors constraining their behavior is therefore crucial to

developing bridges with optimum specifications. The next several sections analyze the various error

sources which impinge upon diode-bridge T/H operation.

3.2.1 Aperture Jitter

Random variations in the otherwise periodic sampling interval caused by electronic noise

will limit A/D converter performance because temporal errors in the sampling instant manifest

themselves as equivalent amplitude errors at the quantizer output [10], [15], [16], [13], [14].

Whereas the explanation of this effect in section 1.3.3 predicted performance bounds as limited by

1/2 LSB amplitude errors, the present analysis predicts SNR degradation based upon the statistics

of the signal and the sampling clock phase noise. If a T/H circuit operates with a sampling period

where is a zero–mean Gaussian random variable such that

(3.18)

and an analog input signal , then the voltage error due to the timing jitter

is the product of the derivative of the input signal (with respect to time) and the jitter (Fig. 3.8). This

relationship can be expressed using the notation of figure 3.8:

(3.19)

In this equation, arbitrary input amplitude, , is assumed rather the full-scale amplitude assumed

T Tnom τjitter+= τjitter

P τjitter( ) 1

2πστ2e

τj i tter2 2στ

2⁄−=

Vin t( ) A ωint( )sin=

∆VVind

tdτjitter=

Aωin ωint( ) τcosjitter

=

A


in figure 3.8. The noise power due to jitter is

(3.20)

where the expectation is calculated over all values of such that and over all

Figure 3.8. Aperture jitter gives rise to amplitude error.

dV

dT

Vfs

Vfsr 2Vfs=

V t( ) Vfs 2πfint( )sin=

Slope V t( ) td⁄d=

V− fs

Q 2Vfs 2N⁄=

Vd

td

T0

σjitter2 E ∆V =

t 0 t T≤ ≤ 1 fin⁄=


values of . (In the equations below, is replaced by for simplicity.)

(3.21)

The above differs from Wakimotoet al [13] but agrees with Martin and Secor [10]. The SNR due

to timing jitter is

(3.22)

which isindependent of the input signal amplitude. For a given time jitter, , the phase error,

, is

(3.23)

τjitter τjitter τ

σjitter2 1

T∆V( ) 2P τ( ) τ tdd

∞−

∞

∫0

T

∫=

1T

Aωin ωint( ) τcos[ ] 2P τ( ) τ tdd∞−

∞

∫0

T

∫=

1T

Aωin ωint( )cos[ ] 2 t τ2P τ( ) τd∞−

∞

∫d0

T

∫=

1T

Aωin ωint( )cos[ ] 2 t τ2P τ( ) τd∞−

∞

∫d0

T

∫=

Aωin( ) 2

Tωint( )cos2 t στ

2×d0

T

∫=

Aωin( ) 2

2στ

2=

2 Aπfinστ( ) 2=

SNRjitter

σS2

σjitter2

A2 2⁄2 Aπfinστ( ) 2

= =

1

2πfinστ( ) 2=

τjitter

θclock

θclock ωclockτjitter=


where is the radian clock frequency. Therefore,

(3.24)

Using this expression in equation 3.22, the SNR due to jitter becomes

(3.25)

or in decibels

(3.26)

Under Nyquist conditions where this expression simplifies to

(3.27)

This very simple result is independent of input amplitude predicting SNR degradation

solely in terms of sample clock spectral purity as specified by phase noise. To attain 62 dB SNR

(consistent with 10 effective bits of resolution), equation 3.27 constrains the standard deviation of

the integrated phase noise to be less than 1.6 milliradians. At 100 MHz clock rates this phase noise

translates to 2.5ps standard deviation of jitter (using equation 3.24). Since this noise source will

combine in a root-mean-square fashion with the quantization noise, total SNR will decrease by 3 dB

under such circumstances. To maintain total SNR including effects of clock jitter and quantization

at an acceptable level, SNR due to jitter alone must be reduced to a fraction of the above levels. To

assess the combined effects of clock jitter and quantization noise, equation 3.22 can be modified to

include both error sources resulting in:

ωclock

σθ ωclockστ=

SNRjitter1

2πfinστ( ) 2

1

ωin

ωclockσθ

2

= =

SNRjitter 20ωclock

ωin 20 σθ( ) dBlog−log=

20fclock

fin 20 σθ( ) dBlog−log=

fclock 2fin≥

SNRjitter 20 2( ) 20 σθ( ) dBlog−log=

6 20 σθ( ) dBlog−=


(3.28)

Expressed in decibels this equation becomes

(3.29)

where the last equality assumes . Equations 3.27 and 3.29 are plotted in figure 3.9

from which can be read for a given quantizer resolution,N, and desired SNR. =.5

milliradians ( =0.8ps at =100 MHz) is reasonable for a 10-bit quantizer.

Phase noise or sample jitter exists on the clock signal driving the T/H but is increased by

electronics within the clock buffer and bridge driver circuitry. A typical bridge drive

implementation (Fig. 3.3) utilizes a differential transistor pair (Q1,Q2) to control the bridge current.

The phase noise in equations 3.26 and 3.27 is that at the collectors of the differential pair.

Consequently, noise contributions from the differential pair and from the preceding clock buffer

must be referred to the collector nodes when calculating SNR loss. Such performance degradation

constrains the clock buffer design and will be addressed in more detail in section 3.3.3.

3.2.2 Small –Signal Bandwidth

Small-signal operation of the diode-bridge in track mode was discussed in some detail in

section 3.1. Here the bandwidth of a track-and-hold based upon a bridge switch will be determined.

The small-signal equivalent circuit of such a S/H in track mode (Fig. 3.10) replaces each diode with

a resistor, , of value . Because the bridge is modelled by two Tee networks in

parallel the simplified circuit of figure 3.10b can be used to determine its frequency response. In the

SNRj Q+

σS2

σjitter2 σQ

2+A2 2⁄

2 Aπfinστ( ) 2 2A 2N⁄( )2

12⁄+= =

1

2πfinστ( ) 2 2 3⁄( ) 2 2N−+=

1

ωin

ωclockσθ

2

2 3⁄( ) 2 2N−+

=

SNRj Q+ 10ωin

ωclockσθ

2

2 3⁄( ) 2 2N−+

log−=

10 σθ2 4⁄ 2 3⁄( ) 2 2N−+( )log−=

ωclock 2ωin=σθ σθστ fclock

rd VT I Bridge 2⁄( )⁄


analysis which follows the variables and from figure 3.10b will be written as and

respectively to clarify the notation. Care will be taken to appropriately accommodate this change in

notation once the desired results have been derived. The output voltage, , is developed through

an impedance divider from node 1.

(3.30)

is in turn developed through an impedance divider from :

(3.31)

Figure 3.9. SNR as limited by clock jitter and quantization noise. Quantizerresolution labelled on curves.

10-5

10-4

10-3

10-2

10-120

40

60

80

100

120S

NR

(d

B)

1 10 100.1.01σθ(radians)

N=4

5

6

16

15

14

13

12

11

10

9

8

7

SNRjitter 6 20 σθ( ) dBlog−=

rd′ RL′ rd RL

Vout

Vout

V1

1sCH

1sCH

rd+

11 srdCH+= =

V1 Vin

V1

Vin

Z1

rd Z1+=


where is the impedance seen from node 1 to ground.

(3.32)

Figure 3.10. Small-signal models of diode-bridge in track mode. (a) Fullmodel. (b) Simplified model when parallel networks are combined.

X1 X1

CH

RL

RL

rdrd

rdrd

Vin Vout

X1 X1

CH

Vin VoutV1

rd’

RL’

rd’

rdrd’ = /2

RLRL’ = /2

(a)

(b)

Z1

Z1 RL rd1

sCH+( ) RL

1 srdCH+( )1 s RL rd+( ) CH+( )= =


can therefore be simplified to:

(3.33)

And the track mode small-signal transfer function becomes

(3.34)

To account for the notational change introduced earlier and must be replaced by and

V1 Vin⁄

V1

Vin

RL

1 srdCH+( )1 s RL rd+( ) CH+( )

rd RL

1 srdCH+( )1 s RL rd+( ) CH+( )+

=

RL 1 srdCH+( )rd 1 s RL rd+( ) CH+( ) RL 1 srdCH+( )+=

RL 1 srdCH+( )

RL rd+( ) sCH 2RLrd rd2+( )+

=

RL

RL rd+( )1 srdCH+( )

1 sCH rd

RLrd

RL rd++ +

=

Vout

Vin

Vout

V1

V1

Vin=

11 srdCH+( )

RL

RL rd+( )1 srdCH+( )

1 sCH rd

RLrd

RL rd++ +

=

RL

RL rd+( )1

1 sCH rd

RLrd

RL rd++ +

=

rd RL rd 2⁄


respectively giving

(3.35)

where the last approximation assumes . Since is a very low resistance (less than

in most cases) this assumption is well justified. Also, since the hold capacitance, , is generally

much larger than the device intrinsic capacitances, the single-pole approximation of equation 3.35

is valid. Therefore, to a very close approximation, the diode-bridge will exhibit unity-gain at low

frequency and a single-pole roll-off with time-constant, . For values of bridge

current on the order of 1 mA and hold capacitances of a few pF, bandwidths near 1 GHz are

attainable. Therefore, small-signal frequency response is rarely a limiting factor for diode-bridge

T/H performance.

3.2.3 Preamplifier Track –Mode Distortion

Dynamic distortion arises in the preamplifier and sampling bridge during track mode

because these elements must supply dynamic current to circuit capacitors (parasitic and non-

parasitic) at the frequency of the input to the T/H. Conversely, the postamplifier need not exhibit

good linearity in track mode but must settle to a relatively distortion-free value during hold mode.

In fact, this state of affairs is the motivation for preceding A/D converters with sample-and-hold

circuits. Only the preamplifier and switch need to exhibit dynamic linearity. All subsequent

components, including the postamplifier, comparators, and any other signal processing circuitry can

have very poor dynamic linearity so long as they settle within the allotted time to an appropriate DC

value. Since fast settling and good DC linearity are much easier to achieve than dynamic

linearity†considerable savings in power and circuit complexity can be achieved by isolating the

RL 2⁄

Vout

Vin

RL

RL rd+( )1

1 sCH

rd

212

RLrd

RL rd++ +

=

1

1rd

RL+

1

1 sCH

rd

21

1

1rd

RL+

+

+

=

11 sCHrd+≈

RL rd» rd 50ΩCH

τBridge rdCH=


required dynamic performance to the preamplifier and switch. These elements can then be suitably

optimized to realize the desired performance with a net savings in power and circuit complexity.

This section analyzes the dynamic distortion which affects the preamplifier and bridge during track

operation.

Figure 3.11 depicts schematically the prototype preamplifier used for this study which is an

emitter follower with an ideal current source and capacitive load. Computer simulations assessed

the dynamic performance of this topology for various values of input amplitude and frequency, bias

current, and load capacitance. Inspection of the resulting data (plotted in figure 3.12) reveals the

following empirical relationship between total harmonic distortion (THD)† and the various circuit

parameters.

(3.36)

A theoretical basis can be found for this expression as follows. At the quiescent operating point the

†. This statement is only true for frequencies which are significant relative to the time-constants ofthe circuit under consideration. The term dynamic in this context, therefore, implies operation atsuch frequencies.†. THD is taken to be the sum of the output power from all harmonics divided by the output powerin the fundamental and is usually expressed in decibels.

Figure 3.11. Emitter follower preamplifier with capacitive load used tosimulate dynamic distortion.

Vout

CLoad

IBias

50Ω

50Ω

Vin

=Asin tωinVsrcVsrc A ωintsin=

THD 40finCLoad

IBias 20 A 18dB−log+log=


input and output voltages are related by

(3.37)

where the subscript denotes the quiescent value. At any other operating point the more general

relationship holds:

(3.38)

Figure 3.12. Simulated THD of the emitter follower preamplifier withcapacitive load versus load capacitance, , bias current, , amplitude,

, and input frequency, . In each case, the parameter is varied in a 1, 2, 5,

10 pattern which approximates exponential spacing (i.e. each value is abouttwice the previous one) while maintaining integer values.

0.01 0.1 1Amplitude (Volts)

-100

-90

-80

-70

-60

-50

-40

TH

D (

dB

)

0.1 1 10Load Capacitance (pF)

-100

-90

-80

-70

-60

-50

-40

TH

D (

dB

)

10 100 1000Frequency (MHz)

0.1 1 10Bias Current (mA)

IBias 1mA=

fin 50MHz=

A 500mV=

A 250mV=

fin 50MHz=

CLoad 0.1pF=

CLoad 1pF=

IBias 1mA=

fin 50MHz=

CLoad 1pF=

10pF

IBias 1mA=

A 256mV=

CLoad 0.1pF=

CLoad 1pF=

A 50mV=

CLoad IBias

A fin

VoutQVinQ

VBEQ−=

Q

Vout Vin VBE−=


Subtracting equation 3.37 from equation 3.38 gives

(3.39)

where is the incremental value of ; that is, its change from the quiescent condition.

Expressing in terms of the transistor current gives

(3.40)

where is the load impedance at the output of the emitter follower. By defining the parameter

this expression further simplifies to

(3.41)

For clarity the terms can be replaced by giving

(3.42)

This expression can be expanded through use of the identity

(3.43)

to give

(3.44)

∆Vout ∆Vin ∆VBE−=

∆V V

∆VBE

∆Vout ∆Vin VTlnIC

ICQ −=

∆Vin VTlnICQ

∆IC+

ICQ −=

∆Vin VTln 1∆Vout ZL⁄

ICQ

+ −=

ZL

VB ICQZL IBiasZL= =

∆Vout ∆Vin VTln 1∆Vout

VB+

−=

∆V V

Vout Vin VTln 1Vout

VB+

−=

ln 1 x+( ) x12

x2 13

x3 14

x4− …+ +−=

Vout Vin VT

Vout

VB

12

Vout

VB

2

− 13

Vout

VB

3

…−+−=


or after rearrangement

(3.45)

This relation expresses as nonlinear function of . To express in terms of series

inversion is performed with the following useful formulae.

(3.46)

This procedure gives

(3.47)

which upon rearrangement becomes

(3.48)

This polynomial expansion of as a function of can be related to harmonic distortion by

Vin 1VT

VB+

Vout VT

12

Vout

VB

2

− 13

Vout

VB

3

…−++=

Vin Vout Vout Vin

if y a1x a2x2 a3x3 …+ + +=

then x A1y A2y2 A3y3 …+ + +=

where A11a1

= A2

a2

a13

−=

A31

a15

2a22 a1a3−( )=

A41

a17

5a1a2a3 a12a4 5a2

3−−( )=

Vout1

1 VT VB⁄+( ) Vin1

1 VT VB⁄+( )312

VT

VB2

Vin2+ +=

11 VT VB⁄+( )

516

VT2 2VTVB−( )

VB4

Vin3 …+ +

Vout1

1 VT VB⁄+( ) Vin1

1 VB VT⁄+( )312

VB

VT2

Vin2+ +=

11 VB VT⁄+( )

516

VBVT

2VB2−( )

VT4

Vin3 …+ +

Vout Vin


making the following observations. Ify can be expressed as a polynomial expansion inx

(3.49)

andx is a sinusoidal function of time, , theny can be expanded as

(3.50)

The last expression in equation 3.50 can be simplified by noting that for weakly non-linear functions

of the type under consideration, higher order coefficients are small compared to and . Under

this assumption equation 3.50 becomes

(3.51)

From this relationship, the ratio of second harmonic amplitude to the fundamental amplitude can be

easily calculated in terms of the coefficients of the original polynomial expansion:

(3.52)

y a0 a+1x a2x2 a3x3 …+ + +=

x t( ) A ωt( )sin=

y t( ) a0 a+1A ωt( )sin a2A2 ωt( )sin2 a3A3 ωt( )sin3 …+ + +=

a0 a+1A ωt( )sin a2A2 1 2ωt( )cos−

2+ +=

a+ 3A3 3 ωt( )sin 3ωt( )sin−4

…+

a0

a2A2

2+

a1A

34

a3A3+( ) ωt( )sin+ +=

a2A2

2− 2ωt( )cos

a3A3

4− 3ωt( )sin …+

a0 a1

y t( ) a0 a1A ωt( )sina2A2

2− 2ωt( )cos

a3A3

4− 3ωt( )sin …++≈

HD2amplitudeof2ndharmonicamplitudeoffundamental

a2A2

2a1A

= =

12

a2

a1A=


similarly

(3.53)

Higher order distortion products, , can be found in like manner. Using the coefficients for the

polynomial expansion of from equation 3.48 in the expressions for and gives

(3.54)

and

(3.55)

These distortion products can be calculated in terms of circuit parameters by noting that

and recalling that . With capacitive loading . Therefore,

(3.56)

HD 3amplitudeof3rdharmonicamplitudeoffundamental

a3A3

4a1A

= =

14

a3

a1A2=

HDn

Vout HD2 HD3

HD212

1 2⁄( ) VB VT2⁄

1 VB VT⁄+( ) 31 VT VB⁄+( ) A=

14VT

A

1 VB VT⁄+( ) 2=

HD314

1 6⁄ VBVT 2VB2−( ) 1 VT

4⁄( )

1 VB VT⁄+( ) 51 VT VB⁄+( ) A2=

1

24VT2

1 2VB VT⁄−( )

1 VB VT⁄+( ) 4A2=

VB VT»

VB IBiasZL= VB IBias ωinCLoad( )⁄=

HD21

4VT

A

1 VB VT⁄+( ) 2

VT

4A

VB2

≈=

VT

4

ωinCLoad

IBias

2

A=

π2VT

finCLoad

IBias

2

A=


or in decibels

(3.57)

Note that this expression is identical in form to that in equation 3.36 which empirically predicted

THD based upon computer simulations. The sole discrepancy between the two is a 6 dB constant

term which arises because the amplitude,A, in equation 3.36 refers to the applied signal which is

attenuated by 6 dB before reaching the input to the emitter follower. Therefore, equation 3.57

accurately predicts dynamic distortion for a capacitively loaded emitter follower. Further, since the

empirical THD matches the theoretical , total distortion is dominated by the second order

component which can be largely cancelled if a differential structure is used. The third-order

distortion can be calculated easily as well.

(3.58)

and in decibels

(3.59)

The above simple expressions for HD2 and HD3 can be used to design a T/H input preamplifier

which meets distortion specifications while dissipating minimum power. Normally, complicated

mathematical techniques such as Volterra series must be employed to predict dynamic distortion

HD2 40finCLoad

IBias log 20 Alog 20 π2VT( ) dBlog+ +=

40finCLoad

IBias log 20 Alog 11.8dB−+=

HD2

HD31

24VT2

1 2VB VT⁄−( )

1 VB VT⁄+( ) 4A2 VT

121

VB3

A2−≈=

HD3

VT

12

ωinCLoad

IBias

3

A2≈

2π3VT

3

finCLoad

IBias

3

A2=

HD3 60finCLoad

IBias log 40 Alog 20

2π3VT

3

dBlog+ +=

60finCLoad

IBias log 40 Alog 5.4dB−+=


requiring extensive analysis and simulation while affording little design insight. The method used

above accurately extends from the simpler DC case to predict high-frequency distortion

characteristics because one dominant storage element of constant value (in this case the hold

capacitor) influences circuit behavior at frequencies well below those where the intrinsic device

capacitances become important. This technique wouldnot accurately predict performance in RF

systems where the non-linear device capacitances are important at frequencies of interest.

3.2.4 Diode Bridge Track –Mode Distortion

Two phenomena adversely affect linearity of the diode bridge itself. Firstly, the finite

impedances with which the bridge must inevitably be biased cause the quiescent current to vary

with input signal, and secondly, the dynamic current which charges the hold capacitor enabling the

output signal to track the input also perturbs the bridge operating point in a signal-dependent

manner. These effects will be discussed separately.

In an ideal biasing arrangement, such as that depicted in figure 3.4, perfect sources supply

the operating current to the diode bridge. In actual implementations, circuit elements with finite

impedance will drive the top and bottom nodes of the bridge. These impedances allow signal current

to flow through and perturb balance of the bridge diodes in response to voltage variations at the

bridge input. A large-signal model of the diode bridge in track mode including finite biasing

impedances (Fig. 3.13) shows the relationships among these quantities. Here an approximation has

been made that the incremental voltage seen at the top and bottom of the bridge is equal to the

incremental input voltage. Using the result from section 3.1 that (Eq. 3.5), the

diode currents can be related as follows:

(3.60)

This equation expands to give

(3.61)

ID1ID3 ID2ID4=

IBias

2∆I

∆Vin

ZB−+

IBias

2∆I

∆Vin

ZB+ +

IBias

2∆− I( )

IBias

2∆− I( )=

IBias

2∆I+( )

2 ∆Vin

ZB

2

−IBias

2∆− I( )

2

=


which can be solved for .

(3.62)

where . At the quiescent point the output voltage can be expressed as the sum of the

Figure 3.13. Large-signal model of diode bridge in track mode with finite biasimpedances, .

IBias

2∆I

∆Vin

ZB−+

ZB ZB

2IBias

Vin ∆Vin+ Vout ∆Vout+

2∆Vin ZB⁄

IBias

2∆− I

IBias

2∆− I

IBias

2∆I

∆Vin

ZB+ +

IBias

∆Vin

ZB−IBias

∆Vin

ZB−

D1 D2

D4D3

ZB

∆I I Bias⁄

IBias

2∆I+( )

2 ∆Vin

ZB

2

−IBias

2∆− I( )

2

=

IBias

2∆I+( )

2 IBias

2∆− I( )

2

−∆Vin

ZB

2

=

2IBias∆I∆Vin

ZB

2

=

∆IIBias

12

∆Vin

IBiasZB

212

∆Vin

VB

2

= =

VB IBiasZL=


input voltage and two diode voltage drops which are known functions of the diode currents.

(3.63)

At any other operating point the more general expression can be written:

(3.64)

Subtracting these two equations (and using ) gives the relationship between the

incremental variables

(3.65)

Using the result of equation 3.62, , and dropping the notation for

simplicity gives

(3.66)

Again, the polynomial expansion of can be employed advantageously to express

VoutQVinQ

− VBE4QVBE3Q

−=

Vout Vin− VBE4 VBE3−=

V VQ ∆V+=

∆Vout ∆Vin− ∆VBE4 ∆VBE3−=

VTlnIBias 2⁄ ∆I−

IBias 2⁄ VTln

IBias 2⁄ ∆I ∆Vin ZB⁄+ +IBias 2⁄

−=

VTlnIBias 2⁄ ∆I−

IBias 2⁄ ∆I ∆Vin ZB⁄+ + =

VTln1 2∆I I Bias⁄−

1 2∆I I Bias⁄ 2∆Vin VB⁄+ + =

2∆I I Bias⁄ ∆Vin VB⁄( ) 2= ∆

Vout Vin− VTln1 Vin VB⁄( ) 2−

1 Vin VB⁄( ) 2 2Vin VB⁄+ + =

VTln1 Vin VB⁄+( ) 1 Vin VB⁄−( )1 Vin VB⁄+( ) 1 Vin VB⁄+( )=

VTln1 Vin VB⁄−( )1 Vin VB⁄+( )=

ln 1 x+( ) Vout


as a polynomial function of .

(3.67)

The absence of even-order components in the last expression in equation 3.67 implies that the finite

impedances of the bias current sources give rise to only odd-order distortion products. The

dominant 3rd-order component is

(3.68)

Where the approximation above assumes , a condition which always holds in practice,

and the sign of the result can be ignored since only relative amplitudes are of interest. Recalling that

Vin

Vout Vin VT

Vin

VB−

1

2

Vin

VB−

2

− 13

Vin

VB−

314

Vin

VB−

4

− …+ ++=

V− T Vin

VB 1

2

Vin

VB

2

− 13

Vin

VB

314

Vin

VB

4

− …+ +

Vin 2VT−Vin

VB 1

3

Vin

VB

315

Vin

VB

5

…+ + +=

12VT

VB−

Vin 2VT− 1

3

Vin

VB

315

Vin

VB

5

…+ +=

HD314

a3

a1A2=

14

2 3⁄− VT VB3⁄( )

1 2VT VB⁄−[ ] A2=

14

2 3⁄− VT VB3⁄( ) VB 2VT⁄( )

VB 2VT⁄ 1−[ ] A2=

1−12

1 VB2⁄

VB 2VT⁄ 1−[ ] A2=

1−12

≈1 VB

2⁄VB 2VT⁄ A2

VT

6− 1

VB3

A2=

VB 2VT»


, the distortion becomes

(3.69)

or in decibels

(3.70)

In most cases is resistive in nature, either because it is implemented with an actual resistor

connected to an appropriate voltage supply or because the active current source exhibits a small

parasitic output capacitance. Therefore, odd-order distortion products due to finite current source

output impedances exist even at low frequencies and must evaluated to ensure they are acceptably

low.

Similarly to the output impedances discussed above, finite impedance at the bridge output

causes signal current to flow through the bridge, thereby modifying the quiescent currents and

leading to distortion. The incremental currents flowing in this situation (Fig. 3.14) again adhere to

the constraint of equation 3.5 resulting in the following relationship:

(3.71)

This expression can be solved for as follows:

(3.72)

VB IBiasZB=

HD3

VT

61

IBiasZB( )

3

A2=

HD3 40 A 60−log IBiasZB( ) 20 VT 6⁄( )log dB+log=

40 A 60−log IBiasZB( ) 47.26− dBlog=

ZB

IBias

2∆I+( )

IBias

2∆I ∆I in+ +( )

IBias

2∆− I( )

IBias

2∆− I ∆Iout+( )=

∆I

IBias∆IIBias

2∆I in ∆I∆I in+ + IBias− ∆I

IBias

2∆Iout ∆− I∆Iout+=

2IBias∆I ∆I ∆I in ∆Iout+( )+IBias

2∆Iout ∆I in−( )=

∆I

IBias

2∆Iout ∆I in−( )

2IBias ∆I in ∆Iout+( )+=


As in the previous cases the incremental input and output voltages are simply related

(3.73)

Using the expression for found in equation 3.72 and dispensing with the cumbersome

Figure 3.14. Diode bridge with current perturbations caused by dynamiccurrent into .

IBias

2∆I+

IBias

Vin ∆Vin+ Vout ∆Vout+

IBias

2∆− I

IBias

2∆− I ∆Iout+

IBias

2∆I ∆I in+ +

IBias

∆Iout∆I in

CH

D1 D2

D3 D4

CH

∆Vout ∆Vin− ∆VBE1 ∆VBE2−=

VTlnIBias 2⁄ ∆I+IBias 2⁄ ∆− I

=

VTln1 2∆I I Bias⁄+1 2∆I I Bias⁄−

=

∆I ∆


notation the above equation becomes

(3.74)

Performing KCL on a closed surface enclosing all four bridge diodes leads to the conclusion that

. Note also that in turn is constrained by the impedance connected between the

bridge output and ground, temporarily called , to be ; that is, .

Therefore, equation 3.74 produces

(3.75)

where . The right hand side of equation 3.75 is identical in form to the right hand

side of equation 3.66 and therefore admits the same polynomial expansion arrived at in equation

3.67. The resulting relationship is

(3.76)

which upon rearrangement expresses as a polynomial function of

(3.77)

This equation can be inverted to give in terms of using the series inversion formulae

Vout Vin− VTln

1Iout I in−

2IBias Iout I in+++

1Iout I in−

2IBias Iout I in++−

=

VTln2IBias 2Iout+2IBias 2I in+

=

VTln1 Iout IBias⁄+1 I in IBias⁄+

=

I in Iout−= Iout

ZL V− out ZL⁄ Iout Vout ZL⁄−=

Vout Vin− VTln1 Vout VB⁄−1 Vout VB⁄+

=

VB IBiasZL=

Vout Vin− VTln1 Vout VB⁄−1 Vout VB⁄+

=

2VT−Vout

VB 1

3

Vout

VB

315

Vout

VB

5

…+ + +=

Vin Vout

Vin Vout 2VT+Vout

VB 1

3

Vout

VB

315

Vout

VB

5

…+ + +=

Vout Vin


described earlier (Eq. 3.46).

(3.78)

Since contains no even-order powers of , no even-order harmonics are generated from the

bridge due to output current flow. The dominant odd-order harmonic, the third, is

(3.79)

where the approximation relies upon which usually holds in practical implementations.

Substituting for yields

(3.80)

Vout1

1 2VT VB⁄+( ) Vin1

1 2VT VB⁄+( )4

− 23

VT

VB3

Vin3 …−=

Vout Vin

HD314

11 2VT VB⁄+( )

4

− 23

VT

VB3

11 2VT VB⁄+( )

A2=

14

− 11 2VT VB⁄+( )

323

VT

VB3

A2=

HD316

VT

VB3

A2≈

VB VT»

IBias ωinCH( )⁄ VB

HD3

VT

6

ωinCH

IBias

3

A2=

4π3VT

3

finCH

IBias

3

A2=


or in decibels

(3.81)

3.2.5 Finite Aperture Time

Ideally, the track-to-hold transition occurs instantaneously at the sampling moment

implying that the bridge diodes are switched from the conducting state to the non-conducting state

spending no time in any intervening partially conducting mode. In a real T/H, such a discontinuity

is impossible, and the bridge diodes spend some finite time in transition between these conditions.

Two significant effects arise from the non-zero transition oraperture time. First, high-frequency

signals are attenuated because the resultant output signal is averaged during the aperture window.

This averaging operation is linear but acts as a low-pass filter imposing a limit on the frequency

response of the bridge. Second, the time-varying nonlinear impedance of the diode bridge

introduces distortion into the held signal. These two effects will be discussed separately.

Ignoring the nonlinear aspects of the switching process, the diode bridge can be modelled

as a time-varying linear resistor, , which charges the hold capacitor, (Fig. 3.15). If the

bridge bias currents (Fig. 3.4) switch linearly from their nominal values, , to over an aperture

Figure 3.15. Linear, time-varying model of diode bridge and hold capacitorused for finite aperture analysis.

HD3 60finCH

IBias 40 A 20

4π3VT

3

dBlog+log+log=

60finCH

IBias 40 A 0.6dB+log+log=

rd t( ) CH

rd t( )

CH

Vin t( ) Vout t( )

Io 0


time (Fig. 3.16a), the bridge resistance will increase from its nominal value to infinity over the

same period (Fig. 3.16b). The bridge current and small-signal resistance can be described

analytically as:

(3.82)

and

(3.83)

Alternatively, the bridge can be described by its conductance which is

(3.84)

This function is not plotted but is a scaled version of the bridge current, , shown in figure

3.16a. The differential equation which governs the bridge turn-off behavior can be derived by

Figure 3.16. Response of bridge current (a) and small-signal bridgeresistance (b) over finite aperture time.

tA

I(t)

t0 tAAperture Time

IO

t0 tA

IO

2VT

(t)rd

(a) (b)

IBridge t( ) Io 1 t tA⁄−( )=

rd t( )2VT

IBridge t( )2VT

Io 1 t tA⁄−( )= =

gBridge t( )IBridge t( )

2VT

Io 1 t tA⁄−( )2VT

= =

IBridge t( )


applying KCL to the output node of the RC circuit shown in figure 3.15 giving

(3.85)

which upon rearrangement results in

(3.86)

The above relationship is a linear time-varying differential equation whose time-varying aspect is

reflected by the coefficients which are not constant but which change according to the

diode small-signal resistance, . These time-constants can be parameterized by their value at

time which is and which is the reciprocal of the bridge –3 dB radian

bandwidth during track mode:

(3.87)

Equation 3.86, along with the constraint on bridge resistance, ,

can be solved numerically for an input sinusoid of given frequency and phase,

, yielding an output voltage at which represents the held

signal corresponding to the sample at the relative phase between the input sinusoid and the

sampling clock. By performing this analysis for several equally-spaced phases along the input

waveform a set of output voltages representing a sampled sinusoid results. The Fourier transform

of this sampled signal gives the output amplitude and phase at frequency . Assembling these

results for many values of , the frequency response of the system is found. Figure 3.17 displays

the results of such analysis compared with the simple single-pole frequency response of the bridge

in track mode for several values of the normalized parameter . The frequency response

curves including the effects of finite aperture time follow closely the single-pole response until

; that is, until the aperture time is one fifth the period of the input signal. Beyond this

frequency the sampling gain drops rapidly exhibiting a null at which appears because

the input sinusoid is integrated over exactly one period ( ). Additional nulls exist

whenever equals an integer value, since the input signal is then integrated over an integer

number of periods thereby generating output equal to zero. Figure 3.17 shows that for reasonable

Vin t( ) Vout t( )−rd t( ) CH td

d Vout t( )=

Vout t( )d

td1

rd t( ) CHVout t( )+ 1

rd t( ) CHVin t( )=

rd t( ) CH

rd t( )t 0= τo 2VT Io⁄( ) CH=

ωtrack ω 3dB−1τo

Io

2VTCH= = =

rd t( ) 2VT Io 1 t tA⁄−( )[ ]⁄=

Vin t( ) A ωint φ+( )sin= t ∞=φ

ωin

ωin

ωtrack tA×

f tA× 1 5⁄≈f tA× 1=

tA 1 f⁄ T= =f tA×


frequency response the following conditions must prevail:

(3.88)

and

(3.89)

where is the desired operating frequency of the track-and-hold. must be much larger than

, otherwise significant attenuation occurs (even in track mode) since at

signal attenuation is unacceptable (3 dB). For a desired operating frequency, , equal to 50 MHz,

equations 3.88 and 3.89 mandate that and . The first of

Figure 3.17. Frequency response induced by finite aperture time assuminga linear small-signal bridge model. Upper curves represent frequency responsewith constant bridge resistance, . Lower curves include

the effect of bridge turn-off governed by .

.01 .1 1 10f * tA

-80

-60

-40

-20

0M

agn

itu

de

(dB

)

ωTrack * tA = 1/32 1/16 1/8 1/4

rd t( ) rd 2VT Io⁄= =rd t( ) 2VT Io 1 t tA⁄−( )[ ]⁄=

tA1

10fin<

ωtrack ωin» 2π fin×=

fin ωtrack

2π fin× ωtrack 2π f× in=fin

tA 2ns≤ ftrack 50MHz 500MHz≈»


these constraints generally does not pose a difficult problem for a modern silicon bipolar process

like Tektronix’ SHPi. The second constraint places a lower limit on the bridge bias current required

for a given value of hold capacitance, . That is,

(3.90)

In the preceding analysis, a simple ramp was assumed for the bridge current waveform;

however, the exact form of the turn-off mechanism is not critical so that if different switching

characteristics are used (e.g. exponential decay rather than linear decay of the bridge current)

qualitatively similar results obtain.

The nonlinear effects of finite aperture time are more deleterious than the simple band-

limiting phenomenon just described [6], [7], [15], [16]. The large-signal behavior of a diode bridge

during the turn-off transient can be analyzed with the aid of equations 3.14 and 3.15 from section

3.1 which apply to figure 3.18a. These equations predict the bridge transfer characteristics during

track mode and are repeated here:

Figure 3.18. Large-signal model for simulating finite aperture effects.

CH

ωtrack1τo

Io

2VTCHfin»= =

Io 2VTCHfin»∴

I(t)

t00 tAAperture Time

IO

I(t)

Vin(t)Vout(t)

I(t)

CH

CHdVout

dt

(a) (b)


(3.91)

When combined, the two lines in equation 3.91 predict the output current as a non-linear function

of the input and output voltages. (By the associated reference convention both and are

assumed to flowinto the diode bridge in figure 3.18a.)

(3.92)

The output current is further constrained by the hold capacitor to be

(3.93)

Equations 3.92 and 3.93 combine to give

(3.94)

Since is not constant but decreases from to over the aperture time, , according to

(Fig. 3.18b), equation 3.94 becomes

(3.95)

which is the non-linear, time-varying differential equation governing bridge turn-off with finite

aperture time and a linearly ramped current decay. This equation depends explicitly on the aperture

time, , and the bridge slew-rate, ; and implicitly upon the input sinusoid amplitude, ,

and frequency, (through the definition of assumed here to be a sinusoid). Intuitively, the

nonlinear nature of the bridge gives rise to distortion because in the presence of a non-zero hold

capacitor, the bridge output voltage will not equal the bridge input. The bridge output current is a

nonlinear function of this voltage difference and integrates on the hold capacitor resulting in a held

voltage which is a nonlinear function of the input signal. This phenomenon (described in section

I in IBias

Vin Vout−2VT

tanh=

and

Iout I in−=

I in Iout

Iout IBias

Vin Vout−2VT

tanh−=

Iout C− H

Voutd

td=

Vout t( )d

td

IBias

CH

Vin t( ) Vout t( )−2VT

tanh=

IBias Io 0 tAIBias Io 1 t tA⁄−( )=

Vout t( )d

td

Io

CH

Vin t( ) Vout t( )−2VT

1 t tA⁄−( )tanh=

tA Io CH⁄ A

fin Vin t( )


3.2.4 with reference to figure 3.14) is further exacerbated by the diminution of the bridge bias

current over the aperture window. Equation 3.95 describes both of these effects and can be solved

numerically for input sinusoids of various phases and frequencies (as in the case above where the

band-limiting effects of finite aperture time were investigated). Fourier transforms calculate the

harmonic content of the resultant sampled output waveforms from which total-harmonic-distortion

(THD) can be easily ascertained. Results from such analysis agreed very closely with those obtained

via SPICE circuit analysis and are plotted in figure 3.19 as functions of the circuit parameters

mentioned above; , , , and . The THD curves in figure 3.19 can be seen

empirically to follow the relationship

(3.96)

within a few decibels over all regions of interest. This expression rearranges giving a form

containing normalized parameters:

(3.97)

Equations 3.96 and 3.97 can be used as guides when designing diode bridge switches and selecting

circuit parameters which govern bridge operation.

3.2.6 Hold Pedestal

While the bridge diodes are conducting during track mode, they store charge on both their

depletion capacitance and their diffusion capacitance. After the bridge switches to hold mode and

all transients settle, the bridge diodes conduct no current† with their terminal voltages determined

by a mechanism dependent upon the particular implementation of the switch. Regardless of the

particular diode terminal voltages in this state, reduced charge is stored on the depletion

capacitance, and the diffusion storage is zero. The difference in charge stored during track mode

and hold mode is therefore expelled from each diode during the turn-off transient. If the charges

expelled from the two diodes connected to the hold capacitor are not equal, the net charge injected

onto that capacitor imparts an output voltage perturbation calledhold step or hold pedestal which,

†. The diodes can still conduct a small displacement current owing to their non-zero junction capac-itance. This effect is ignored here but will be discussed in section 3.2.7 which addresses bridgefeedthrough in hold mode.

tA Bslew Io CH⁄= A fin

THD 40 Alog 60 finlog 30 tAlog 30 Io CH⁄( )log 30+−+ +[ ] dB=

THD 40 Alog 60 fintA( )log 30Io

CH tA

log 30+ + + dB=


if non-linearly dependent upon the input signal, introduces distortion into the sampled output

stream. This distortion mechanism can be analyzed by determining the diode operating voltages

Figure 3.19. Simulated THD due to finite aperture time as a function of inputamplitude, , input frequency, , aperture time, , and bridge slew rate,

. Parameters are swept in a 1, 2, 5, 10 fashion to approximate an

exponential sweep with integer values.

.1 1Amplitude (Volts)

-100

-90

-80

-70

-60

-50

-40

TH

D (

dB

)

.01 .1 1fin * ta

-100

-90

-80

-70

-60

-50

-40

TH

D (

dB

)

.01 .1 1Bslew * ta (Volts)

-100

-90

-80

-70

-60

-50

-40T

HD

(d

B)

.1 1Amplitude (Volts)

.01 .1 1fin * ta

.01 .1 1Bslew * ta (Volts)

I0 CH⁄( ) tA 1=

0.01

fintA 0.1=

fintA 0.025=

I0 CH⁄( ) tA 0.1=

1

I0 CH⁄( ) tA 0.1=

A 0.256=A 1=

I0 CH⁄( ) tA 1=

A 0.1=

A 0.256= fintA 0.025=

A 1=0.1

A 0.1=

fintA 0.01=

1

A fin tAI0 CH⁄


before and after the track-to-hold transition. In a typical embodiment (Fig. 3.20a), the diode bridge

is turned off by reversing the polarity of the bias current, thereby forcing this current to flow through

two auxiliary diodes which in turn reverse bias the bridge diodes. While tracking, diodes D1

through D4 conduct nominally equal currents corresponding to the bias voltage (point 1 on

the diode small-signal depletion capacitance curve of figure 3.20b). During hold mode the bridge

current forward biases the two auxiliary diodes which now control the upper and lower bridge node

voltages. If the auxiliary diodes have twice the area as the bridge diodes†, then the upper bridge

node moves to Volts and the lower bridge node to Volts. Therefore, the voltage across

D4 becomes while D2 sees Volts (figure 3.20b points 2 and 3 respectively).

Notice that in the implementation depicted in figure 3.20a the maximum allowable input amplitude

is . If the input signal exceeds this value, diodes D1 and D3 will become at least slightly forward

biased severely reducing the isolation provided by the bridge in the hold mode. If larger signal

†. This constraint ensures that the auxiliary diodes operate at the same current density in hold modeas do the bridge diodes in track mode. Without this restriction, the auxiliary diodes’ forward biaspotential will be lower than bridge diodes’ by Volts. This difference does not materially

affect the analysis or results presented here. In fact, the auxiliary diodes are usually made largerthan the bridge diodes for another reason – to reduce parasitic resistance which increasesfeedthrough during hold mode.

Figure 3.20. Charge injection at bridge turn-off gives rise to hold pedestaldistortion. (a) Typical bridge circuit showing auxiliary diodes which controlbridge bias voltages in hold mode. (b) Diode small-signal capacitance-voltagecharacteristic.

Cj

Cjo

0-Vd

-Vout

-Vd

+Vout-V

d

+Vd

1

23

D1 D2

D3 D4 CH

VoutVin

(a) (b)

V+ d

VTln2

Vd− Vd+

Vout Vd− Vd Vout−−

Vd


swings are required, multiple diodes in series can replace each auxiliary diode.

Since the diode capacitance-voltage characteristic is a small-signal quantity, the difference

in stored charge at two operating points can be calculated by integrating the C-V function between

the voltages of interest.

(3.98)

Therefore, the net charge injected onto the hold capacitor which is the difference between the

charges injected by diodes D1 and D4 can be expressed as

(3.99)

where the C-V curves of diodes D2 and D4 are assumed identical, i.e.

. The last integral in equation 3.99 represents the shaded area

under the C-V curve in figure 3.20b. The diode diffusion capacitance does not contribute to

because the stored diffusion charge due to diodes D2 and D4 is nominally equal and will therefore

sum to zero at the output node. Any small differences in this charge due to device mismatches result

in a signal independent pedestal which disturbs every output sample and therefore appears as an

offset component of the T/H circuit. In the absence of other error sources, the injected charge, ,

Cj V( ) QdVd

≡

Qd Cj V( ) Vd=

QdQ1

Q2

∫ CjV1

V2

∫ V( ) Vd=

∆Q Q2 Q1− CjV1

V2

∫ V( ) Vd= =

Qinj ∆QD4 ∆QD2−=

Cj4Vd

V− d Vout+

∫ V( ) Vd Cj2Vd

V− d Vout−

∫ V( ) Vd−=

CjV− d Vout−

V− d Vout+

∫ V( ) Vd=

Cj2 V( ) Cj4 V( ) Cj V( )= =Qinj

Qinj


will prevent the held output from equalling the input according to

(3.100)

so that the input signal can be expressed as a function of the output signal:

(3.101)

Notice that is a purely odd function of regardless of the nature of since

(3.102)

Therefore, by inspection of the formulae for series inversion (Eq. 3.46), will also be an odd

function of and only odd-order harmonics can arise from the hold pedestal phenomenon. This

claim is invalid if component mismatches are encountered such that .

Nonetheless, reasonable component matching should minimize even-order distortion products.

can be expressed as a polynomial function of by forming the Taylor series

expansion of the relationship found in equation 3.101. That is,

(3.103)

Vout Vin

Qinj

CH−=

Vin Vout

Qinj

CH+=

Vout1

CHCj

V− d Vout−

V− d Vout+

∫ V( ) Vd +=

Vin Vout Cj V( )

Vin Vout−( ) V− out1

CHCj

V− d Vout+

V− d Vout−

∫ V( ) Vd +=

Vout− 1CH

− CjV− d Vout−

V− d Vout+

∫ V( ) Vd =

V− in Vout( )=

Vout

Vin

Cj2 V( ) Cj4 V( )≠

Vin Vout

Vin a1Vout a2Vout2 a3Vout

3 …+ + +=

where

an1n! Vout

n

n

dd Vin Vout( )

Vout 0==


can be found directly from equations 3.101 and 3.103 by recalling Leibnitz’ Rule:

(3.104)

Applying Leibnitz’ Rule to equation 3.101 gives

(3.105)

So that

(3.106)

a1

if

ϕ x( ) f t x,( ) tda x( )

b x( )

∫=

then

xdd ϕ x( )

x∂∂ f t x,( ) td

a x( )

b x( )

∫ f b x( ) x,[ ]xd

d b x( ) f a x( ) x,[ ]xd

d a x( )−+=

Voutd

dVin 11

CH Voutdd C V( ) Vd

Vd− Vout−

Vd− Vout+

∫ ++=

1CH

+ C Vd− Vout+( ) 1( ) C Vd− Vout−( ) 1−( )−[ ]

11

CH+ C Vd− Vout+( ) C Vd− Vout−( )+[ ]=

a1 Voutd

dVin=Vout 0=

11

CH+ C Vd−( ) C Vd−( )+[ ]=

1 2C Vd−( )

CH+=


The higher order derivatives can be found in a straightforward manner.

(3.107)

All even coefficients of the polynomial expansion of are therefore zero as noted earlier, and the

odd coefficients become

(3.108)

If the diode small-signal capacitance can be described by where

(3.109)

Voutn

n

d

d Vin 1CH Vout

n 1−( )

n 1−( )

d

d C Vd− Vout+( )Vout

n 1−( )

n 1−( )

d

d C Vd− Vout−( )+=

1CH

dn 1−( )

C Vd− Vout+( )

Vd− Vout+( )dn 1−( )

Vd− Vout+( )d

Voutd

n 1−

+=

1CH

+d

n 1−( )C Vd− Vout−( )

Vd− Vout−( )dn 1−( )

Vd− Vout−( )d

Voutd

n 1−

1CH

dn 1−( )

C Vd− Vout+( )

Vd− Vout+( )dn 1−( ) 1( ) n 1− d

n 1−( )C Vd− Vout−( )

Vd− Vout−( )dn 1−( ) 1−( ) n 1−+=

0 forneven

2CH

dn 1−( )

C Vd− Vout+( )

Vd− Vout+( )dn 1−( ) fornodd

=

Vin

an1n! Vout

n

n

dd Vin Vout( )

Vout 0==

1n!

2CH

dn 1−( )

C Vd− Vout+( )

Vd− Vout+( )dn 1−( )

Vout 0=

=

1n!

2CH

dn 1−( )

C V( )

Vdn 1−( )

V Vd−=

=

Cj V( )

Cj V( ) QdVd

Cjo

1V

VBI−( )

m= =


where is the zero-bias capacitance, is the built-in potential usually near 0.7 Volts, andm

is a factor equal to about 1/2 which depends upon the junction doping profile, then the odd

coefficients can be expressed as:

(3.110)

where is the Gamma or generalized factorial function. With the coefficients known for the

polynomial expansion of in terms of , the series can be inverted using the formulae listed

in equation 3.46 to give

(3.111)

where

(3.112)

and

(3.113)

The expressions for and can be used to calculate the gain and third harmonic distortion

Cjo VBI

an1n!

2CH

dn 1−( )

C V( )

V( )dn 1−( )

V Vd−=

=

2n!

Cjo

CH

m m 1+( ) … m n 2−+( )

VBIn 1−

1

1 Vd VBI⁄+( ) m n 1−+=

2n!

Cjo

CH

Γ m n 1−+( )Γ m( )

1

VBIn 1−

1

1 Vd VBI⁄+( ) m n 1−+=

Γ x( )Vin Vout

Vout A1Vin A2Vin2 A3Vin

3 …+ + +=

A11a1

1

1 2C Vd−( )

CH+

1

1 2Cjo

CH

1

1 Vd VBI⁄+( ) m+

= = =

A3

2a2 a1a3−

a15

a3

a14

−= =

13

Cjo

CH

m m 1+( )

VBI2

1

1 Vd VBI⁄+( ) m 2+

1 2Cjo

CH

1

1 Vd VBI⁄+( ) m+

4−=

A1 A3


component due to hold pedestal. If , simplifications in the resulting equations arise.

(3.114)

where the last expression is based upon the binomial expansion and the assumption that

which is well founded in practical circuits sincem is a constant near 1/2 and

is usually more than an order of magnitude greater than .

(3.115)

If m is assumed to equal 1/2, and is 750mV (3/4 V) then the equations for gain and third order

distortion further simplify to

(3.116)

Vd VBI≈

AV A11

1 2Cjo

CH

1

1 Vd VBI⁄+( ) m+

= =

1

1Cjo

CH2 1 m−( )+

≈

1Cjo

CH− 2 1 m−( )≈

CH Cjo» 2 1 m−( ) CH

Cjo

HD314

A3

A1A2=

14

13

Cjo

CH

m m 1+( )

VBI2

1

1 Vd VBI⁄+( ) m 2+

1 2Cjo

CH

1

1 Vd VBI⁄+( ) m+

3A2−=

HD3112

Cjo

CH

m m 1+( )

VBI2

1

2m 2+

1Cjo

CH2 1 m−( )+

3A2≈

112

Cjo

CH

m m 1+( )

2m 2+1

VBI2

A2≈

VBI

AV 1 2Cjo

CH−=


and

(3.117)

or in decibels

(3.118)

and

(3.119)

The accuracy of this analysis is demonstrated in figure 3.21 which plots gain and as

calculated analytically and as predicted by SPICE. The top plot in the figure compares SPICE

results with those obtained by included many higher-order terms in the polynomial expansion and

series inversion of equation 3.101, while the bottom plot uses the simpler approximations from

equations 3.114 and 3.115. Note that in all cases the predicted performance is within a few decibels

of the simulated result, thereby ensuring fast but accurate prediction of distortion due to the hold

jump phenomenon.

If excessive distortion or gain loss results from hold pedestal, a unity-gain amplifier driving

the bridge center tap from the output node (Fig. 3.22a) can reduce the effects to a possibly

acceptable level [15], [16], [10]. Analysis of hold pedestal with feedback proceeds as in the case

without feedback with the modification that the center-tap voltage is no longer grounded but is

assumed to be a function of the output voltage. In this case, diodes D2 and D4 switch between the

HD31

36 2

Cjo

CHA2=

AV 20 1 2Cjo

CH−

log 20ln 1 2

Cjo

CH−

ln 10dB⁄= =

20ln 10

≈ 2Cjo

CH−

dB

12.3Cjo

CHdB−≈

HD3 40 Alog 20Cjo

CH log 20

1

36 2( ) dBlog+ +=

40 Alog 20Cjo

CH log 34.1− dB+=

HD3


track mode with each biased at , and hold mode where D2 is biased at

Volts and D4 at Volts. The feedback amplifier is assumed for simplicity to be

memoryless with a linear transfer function described by its output-referred offset, , and its gain,

, which is ideally unity. Therefore, , and the diode voltages in hold mode

become and as shown

in figure 3.22b. The equation governing the pedestal (analogous to equation 3.101) is therefore

Figure 3.21. Comparison between distortion due to hold pedestal predictedby analysis and simulation (upper); and between distortion predicted by simpleapproximations and simulation (lower).

-140

-120

-100

-80

-60

-40

-20

0

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Cjo/Ch

dBc

T/H Harmonics Due to Hold Jump (SPICE & Analysis)

Av

HD3

HD5

-80

-70

-60

-50

-40

-30

-20

-10

0

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

T/H Harmonics Due to Hold Jump (SPICE & Approximations)

Cjo/Ch

dBc

Av

SPICE

SPICE

HD3

Approximation

Approximation

V+ d VCT Vd−( ) Vout−

Vout VCT Vd+( )−

Voff

α VCT Voff αVout+=

VD2 Vd− Voff 1 α−( ) Vout−+= VD4 Vd− Voff− 1 α−( ) Vout+=


(3.120)

This equation can be slightly modified to attain the same form as equation 3.101 so that the

coefficients of the Taylor series expansion, found for the case of a grounded center tap node, can be

applied directly to the present case.

(3.121)

Figure 3.22. A bootstrapped bridge center-tap reduces hold pedestaldistortion. (a) Unity-gain buffer drives bridge center-tap from output node. (b)Diode C-V characteristic still determines residual charge injection.

D1 D2

D3 D4 CH

VoutVin

AV

Cj

Cjo

0-V

d

+Vd

1

23

-Vd

(1-A )V

-Vout

-Vd

(1-A )V

+Vout

(a) (b)

Vin Vout

Qinj

CH+=

Vout1

CHCj

V− d Voff Vout 1 α−( )−+

V− d Voff− Vout 1 α−( )+

∫ V( ) Vd +=

Vin Vout1

CHCj

V− d Voff Vout 1 α−( )−+


∫ V( ) Vd +=

Vin αVout Voff−− Vout αVout Voff−− 1CH

CjV− d Voff Vout 1 α−( )−+


∫ V( ) Vd +=

Vin αVout Voff−− Vout 1 α−( ) Voff− 1CH

CjV− d Voff Vout 1 α−( )−+


∫ V( ) Vd +=

Vx1

CHCj

V− d Vx−

V− d Vx+

∫ V( ) Vd +=


where and the right hand side of the last equation in 3.121 is identical

in form to equation 3.101. Since the coefficients, , of the Taylor series expansion of this form are

known (Eqs. 3.106 and 3.108), The expansion in terms of can be written immediately:

(3.122)

If is negligibly small, then becomes and 3.122 can be written

(3.123)

So the Taylor series coefficients for the expansion of as a function of are

(3.124)

Vx Vout 1 α−( ) Voff−=an

Vx

Vin αVout Voff−− a1Vx a2Vx2 a3Vx

3 …+ + +=

1 2Cj Vd−( )

CH+

Vx

1n!

2CH

dn 1−( )

Cj V( )

Vdn 1−( )

V Vd−=

Vxn

n 3=nodd

∞

∑+=

Voff Vx Vout 1 α−( )

Vin αVout− 1 2Cj Vd−( )

CH+

Vx

1n!

2CH

dn 1−( )

Cj V( )

Vdn 1−( )

V Vd−=

Vxn

n 3=nodd

∞

∑+=

1 2Cj Vd−( )

CH+

1 α−( ) Vout +=

1n!

2CH

dn 1−( )

Cj V( )

Vdn 1−( )

V Vd−=

1 α−( ) Vout[ ] n

n 3=nodd

∞

∑+

Vin 1 2 1 α−( )Cj Vd−( )

CH+

Vout= +

1n!

2 1 α−( ) n

CH

dn 1−( )

Cj V( )

Vdn 1−( )

V Vd−=

Voutn

n 3=nodd

∞

∑+

Vin Vout

a1 1 2 1 α−( )Cj Vd−( )

CH+=

an1n!

2 1 α−( ) n

CH

dn 1−( )

Cj V( )

Vdn 1−( )

V Vd−=

=n 3≥nodd


If the diode capacitance-voltage relationship, , is described by equation 3.109, then the

coefficients become

(3.125)

With the coefficients known for the polynomial expansion of in terms of , the series can

be inverted using the formulae listed in equation 3.46 to give

(3.126)

where

(3.127)

and

(3.128)

The expressions for and can be used to calculate the gain and third harmonic distortion

Cj V( )

a1 1 2 1 α−( )Cjo

CH

1

1 Vd VBI⁄+( ) m+=

an2n!

Cjo

CH

Γ m n 1−+( )Γ m( )

1

VBIn 1−

1 α−( ) n

1 Vd VBI⁄+( ) m n 1−+=n 3≥nodd

Vin Vout

Vout A1Vin A2Vin2 A3Vin

3 …+ + +=

A11a1

1

1 2 1 α−( )Cjo

CH

1

1 Vd VBI⁄+( ) m+

= =

A3

2a2 a1a3−

a15

a3

a14

−= =

13

Cjo

CH

m m 1+( )

VBI2

1 α−( ) 3

1 Vd VBI⁄+( ) m 2+

1 2 1 α−( )Cjo

CH

1

1 Vd VBI⁄+( ) m+

4−=

A1 A3


component due to hold pedestal. If , simplifications in the resulting equations arise.

(3.129)

where the last expression is based upon the binomial expansion and the assumption that

which is well founded in practical circuits.

(3.130)

If m is assumed to equal 1/2, and is 750mV (3/4 V) then the equations for gain and third order

distortion further simplify to

(3.131)

Vd VBI≈

AV A11

1 2 1 α−( )Cjo

CH

1

1 Vd VBI⁄+( ) m+

= =

1

1 1 α−( )Cjo

CH2 1 m−( )+

≈

1 1 α−( )Cjo

CH− 2 1 m−( )≈

CH 1 α−( ) Cjo» 2 1 m−( )

HD314

A3

A1A2=

14

13

Cjo

CH

m m 1+( )

VBI2

1 α−( ) 3

1 Vd VBI⁄+( ) m 2+

1 2 1 α−( )Cjo

CH

1

1 Vd VBI⁄+( ) m+

3A2−=

HD3112

Cjo

CH

m m 1+( )

VBI2

1 α−( ) 3

2m 2+

1 1 α−( )Cjo

CH2 1 m−( )+

3A2≈

112

Cjo

CH

m m 1+( )

2m 2+1 α−( ) 3

VBI2

A2≈

VBI

AV 1 2 1 α−( )Cjo

CH−=


and

(3.132)

or in decibels

(3.133)

and

(3.134)

Notice that both gain loss (in dB) and third harmonic distortion are greatly reduced by the presence

of the term. Also, if , then and as desired.

If is not negligible but is very near unity then and

(3.135)

HD31

36 21 α−( ) 3Cjo

CHA2=

AV 20 1 2 1 α−( )Cjo

CH−

log=

20ln 10

−≈ 2 1 α−( )Cjo

CHdB

12.3 1 α−( )Cjo

CHdB−≈

HD3 40 Alog 20Cjo

CH log 60 1 α−( )log 20+ 1

36 2( ) dBlog+ +=

40 Alog 20Cjo

CH 60 1 α−( )log+log 34.1− dB+=

1 α−( ) α 1= AV 0dB= HD3 ∞− dB=

Voff α Vx Voff−=

Vin Vout Voff−− a1Vx a2Vx2 a3Vx

3 …+ + +=

1 2Cj Vd−( )

CH+

Voff−( ) +=

1n!

2CH

dn 1−( )

Cj V( )

Vdn 1−( )

V Vd−=

Voff−( ) n

n 3=nodd

∞

∑+

Vout Vin 2Cj Vd−( )

CHVoff

1n!

2CH

dn 1−( )

Cj V( )

Vdn 1−( )

V Vd−=

Voffn

n 3=nodd

∞

∑+ +=


In this case the held sample, , equals the input plus an offset term which is the indicated

function of the auxiliary amplifiers output offset voltage, . Therefore, hold pedestal with unity

gain feedback to the bridge center tap results in an offset error at the bridge output but no gain error

or distortion.

3.2.7 Feedthrough

When the sampling bridge is in hold mode, current is prevented by appropriate means from

flowing through the bridge diodes so that ideally the bridge impedance becomes infinite, thereby

isolating the hold capacitor from the input signal. Because of non-idealities in the bridge diodes,

notably finite junction capacitance, the isolation is not complete. The extent to which the input

signal affects the held output voltage in hold-mode is characterized byfeedthrough which is the gain

of the bridge, ideally zero, and which is usually expressed in decibels. In a typical diode bridge

(shown with its concomitant switching circuitry in figure 3.23) all bias current is caused to flow in

the auxiliary diodes thereby forcing current in the bridge diodes to zero. In the example shown,

, , , and .

Figure 3.23. Diode-bridge track-and-hold with differential pair controllingbridge current. Diodes D5 and D6 conduct during hold-mode while diodes D1through D4 are cut-off.

Vout

Voff

Vin

Hold Track

VoutVCTX1 X1

I1 I2

D1

D3 D4

D2

D5

D6

Q1 Q2

2IBridge

CH

IBridge

IBridge

I1 2IBridge= I2 0= ID5 ID6 IBridge= = ID1 ID2 ID3 ID4 0= = = =


Therefore, the bridge diodes’ small-signal resistance, , becomes very large and the auxiliary

diodes’ small-signal resistance becomes small. The bridge and auxiliary diodes now form a voltage

divider severely attenuating signals as they pass from input to output. Because of the diode junction

capacitance in parallel with the small-signal resistance this attenuation characteristic is frequency

dependent. A small-signal model of the switch in hold mode (Fig. 3.24a) includes all of the

significant circuit elements necessary to analyze the nature of hold-mode behavior. Note that

distortion in this mode is unimportant since any signal at the bridge output is unwanted; and since

the bridge output is greatly attenuated leading to signals which are largely distortion free. Therefore,

small-signal models adequate describe circuit behavior in hold mode. The bridge model (Fig. 3.24a)

includes , the diode small-signal junction capacitance, for those diodes which are non-

conducting, and , the diode small-signal resistance, for those diodes which are conducting during

hold mode. Also included in the model is an amplifier with gain and output resistance

feeding its signal from the bridge output to the bridge center tap. These parameters can be set to zero

if the bridge center tap is grounded directly rather than driven by an amplifier. Bridge feedthrough

Figure 3.24. Small-signal models of bridge in hold mode. (a) Model includingall components. (b) Equivalent model simplified through symmetry.

VT ID⁄

Av

(a)

Cd Cd

Cd Cd

rd

rd

r0 CH

Vin Vout

Av Vout

Vin

(b)

dC2Cd2VTop

CH

VFB

r0

rd /2

Cd

rd

AV ro


analysis proceeds by noting that this model includes identical elements mirrored above and below

a horizontal line of symmetry. By combining in parallel those elements which by symmetry are seen

to exhibit identical node voltages, the simplified network of 3.24b results which can be solved most

easily by nodal analysis. The 3 equations which govern circuit operation are:

(3.136)

where . The second constraint above can be solved for in terms of and

the third constraint gives in terms of .

(3.137)

These two relations allow to be expressed solely as a function of :

(3.138)

When the above equation is combined with the first expression in 3.137 the hold mode gain results.

(3.139)

This equation indicates that the input-output transfer function exhibits a zero at DC and a pole at a

frequency dependent upon the circuit parameters. The expression for this pole frequency can be

Vin VTop−( ) s2Cd Vout VTop−( ) s2Cd VFB VTop−( ) rb⁄+ + 0=

VTop Vout−( ) s2Cd Vout− sCH 0=

VFB AVVout=

rb rd 2⁄ ro+= Vout VTop

VFB Vout

Vout

2Cd

CH 2Cd+ VTop=

VFB

2AVCd

CH 2Cd+ VTop=

Vin VTop

Vin

VTop

s2Cd CH 2Cd+( ) s4Cd CH Cd+( ) 1rb

CH 2Cd 1 AV−( )+( )+=

Vout

Vin

Cd

CH Cd+s

s2 1 AV−( ) Cd CH+4rbCd CH Cd+( )+

=

whererb

rd

2ro+=


simplified if in which case

(3.140)

Therefore, the input-output characteristic simplifies to

(3.141)

The magnitude of this transfer function is

(3.142)

which is plotted in figure 3.25. Since, is a few tens of ohms and is a few tens of femtofarads,

Figure 3.25. Small-signal frequency response of diode bridge in hold mode.

CH 2Cd»

1τft

2 1 AV−( ) Cd CH+4rbCd CH Cd+( )

14rbCd

≈=

τft 4rbCd≈

Vout

Vin

Cd

CH Cd+s

s 1 τft⁄+=

Vout

Vin s jω=

Cd

CH Cd+ω

ω2 1 τft2⁄+

=

Cd

CH Cd+1

1 1 ωτft( ) 2⁄+=

rb Cd

20 H jω( )log

Cd

Cd CH+

Cd

Cd CH+ ωτft

Vout

Vin s jω=

ω

20 dB/decade1τft

14rbCd

=


the pole frequency, , is many tens of Gigahertz; therefore, at all frequencies of interest

and the expression for feedthrough can be simplified:

(3.143)

where was assumed in the last simplification. The frequency-dependent feedthrough in

hold mode is simply:

(3.144)

Notice that hold capacitance, , is the only parameter which can be freely varied since cannot

reasonably be made smaller than about 10Ω; is a fixed device constant dependent upon the

process being used; and is a parameter of the performance goals for the circuit. Feedthrough

can be made arbitrarily low by increasing the value of which will also decrease distortion due

to hold pedestal, but at the expense of increased track mode distortion in both the preamplifier and

the diode bridge itself. If a satisfactory trade-off cannot be made with this approach and a

differential implementation is used, capacitively coupling signals from the complementary bridge

can partially cancel the residual signal at the hold capacitor affording an added degree of signal

attenuation [10]. An embodiment of this concept (Fig. 3.26) entails coupling capacitors from the top

and bottom nodes of each bridge to the output node of the complementary bridge. Cancellation of

the output signal occurs during hold mode if the value of the coupling capacitance equals the value

of the corresponding diode junction capacitance. If this condition holds, capacitor C2B couples a

signal from the top of bridge B onto hold capacitor equal in magnitude to the signal coupled

through diode D2A onto ; however, since bridge B receives an input signal complementary to

1 τft⁄ωτft 1«

Vout

Vin s jω=

Cd

CH Cd+1

1 1 ωτft( ) 2⁄+=

Cd

CH Cd+≈ ωτft( ) 2

Cd

CH Cd+ ωτft=

Cd

CH Cd+ 4rbCdω=

4rb

Cd2

CHω=

CH Cd»

Feedthroughωin( ) 4rb

Cd2

CHωin=

CH rb

Cd

ωin

CH

CHA

CHA


bridge A, the signal coupled through C2B is complementary to that coupled through D2A.

Therefore, the net coupling onto the hold capacitor is zero. Similarly, C2A cancels the coupling

through D2B; C4A cancels D4B; and C4B cancels D4A. These cancellations also operate during

track mode but since the bridge impedance is then very low, the effect is negligible. The bridge

diode bias voltages vary from track mode to hold mode and also depend upon the signal at the bridge

center taps, labelled and in figure 3.26. Diode and cross-coupling bias voltages are tabulated

for reference in table 3.1. If the bridge center taps are grounded (or more generally set to the input

Figure 3.26. Cross-coupled capacitors between complementary bridgesreduce feedthrough and hold pedestal error.

ElementTrack Mode

PotentialHold ModePotential

∆V=

D2A

D4A

D2B

D4B

C2A

C4A

Table 3.1. Bias voltages across bridge elements in track mode and hold mode.

D2A

D4A

D1A

D3A

C2A

C4A

D1BD2B

D3BD4B

C2B

C4B

CHA CHB

+Vout–Bridge A Bridge B

VA VB

VA VB

VHold VTrack−

Vd VA Vd−( ) Vin( )− VA 2Vd− Vin−

Vd Vin( ) VA V+d

( )− V− A 2Vd− Vin+

Vd VB Vd−( ) V− in( )− VB 2Vd− Vin+

Vd V− in( ) VB V+d

( )− V− B 2Vd− Vin−

Vin Vd+( ) Vin−( )− VA Vd−( ) Vin−( )− VA 2Vd− Vin−

Vin Vd−( ) Vin−( )− VA Vd+( ) Vin−( )− VA 2Vd Vin−+


common-mode voltage) then the diode bias potential in hold mode is that listed in table 3.1

evaluated with and each pair of diodes, (D2A, D4A) and (D2B, D4B), couples

from the bridge top and bottom nodes to the bridge outputs with capacitances and

. The sum of these capacitances (representing the net capacitance coupled from the

bridge top and bottom to the bridge output) will equal to a first order approximation .

Therefore, if C2A, C4A, C2B, and C4B are equal in capacitance to significant

cancellation in bridge feedthrough results. If the bridge center taps are driven with unit-gain

amplifiers from their respective bridge outputs ( and ), the resultant hold

mode bias voltage on each of diodes D2A, D4A, D2B, and D4B is . Therefore, these diodes’

junction capacitances are each and perfect feedthrough cancellation occurs if the cross-

coupling capacitors take on this same value. Mismatches in the cross-coupling capacitors from their

ideal values, , will be relatively large because the added capacitors will most likely be

implemented with metal-insulator-metal (MIM) or metal-insulator-semiconductor (MIS) structures

which do not track diode capacitance well. Simulations which predict bridge feedthrough as a

function of cross-coupling capacitance (Fig. 3.27) indicate high sensitivity to mismatches. For

example figure 3.27 indicates that a nearly 40 dB increase in feedthrough arises when the cross-

coupling capacitance deviates from the ideal value by 25%. Better matching can be obtained by

constructing the cross-coupling capacitors from diodes similar to those comprising the bridge.

Simple diodes are inappropriate because they will become forward biased interfering with normal

bridge operation so structures involving multiple diodes connected to prevent current flow are

necessary (Fig. 3.28). Such realizations incur parasitic substrate capacitances† which inevitably

detract from the achievable signal cancellation, but better matching can indeed be achieved (Fig.

3.29) The simulation leading to the data plotted in figure 3.29 replaced each coupling capacitor with

†. Substrate capacitances are significantly reduced if a fully oxide-isolated processis used or if a semi-insulating substrate such as in Gallium-Arsenide (GaAs) isused.

C2B

C4B

ElementTrack Mode

PotentialHold ModePotential

∆V=

Table 3.1. Bias voltages across bridge elements in track mode and hold mode.

VHold VTrack−

V− in Vd+( ) Vin( )− VB Vd−( ) Vin( )− VB 2Vd− Vin+

V− in Vd−( ) Vin( )− VB Vd+( ) Vin( )− VB 2Vd Vin+ +

VA VB 0= =Cj Vd Vin+−( )

Cj Vd Vin−−( )Cj Vd−( )

Cj Vd−( )

VA Vin= VB V− in=Vd−

Cj Vd−( )

Cj Vd−( )


two diodes connected in series but with opposite polarity. The figure indicates that such an

arrangement can achieve feedthrough near –100 dB even with diode area deviations of a few

percent, matching which is easily attained in most modern semiconductor processes.

The hold pedestal phenomenon described in section 3.2.6 can also be mitigated somewhat

Figure 3.27. Feedthrough versus cross-coupling capacitance normalized tooptimum value.

Figure 3.28. Cross-coupling scheme for reduced feedthrough with seriesconnected diodes as coupling elements.

.5 .75 1 1.25 1.5Cross Coupling Capacitance (normalized to optimum)

-120

-110

-100

-90

-80

-70

Fee

dth

rou

gh

(d

B)


with this cross-coupling arrangement. In this case, the charge which is cancelled is that expelled

from the bridge diodes when switched from the conducting to the non-conducting state. Figure 3.30

indicates how the cross-coupling capacitances can partially cancel the charges expelled by the

bridge diodes during bridge turn-off. For this cancellation to be complete however, the cross-

coupling elements must exhibit the same non-linear C-V characteristics as the bridge diodes and

must also experience the same voltage transitions during the turn-off transient (see for example

figure 3.20). The initial and final voltages across the diode and cross-coupling elements at the track-

to-hold transition compiled in table 3.1 are again helpful in studying such operation. The last

column of this table indicates that with , the bridge diodes experience the same

voltage transitions as do the pertinent cross-coupling elements; however neither fixed capacitors nor

series coupled diodes provide the appropriate C-V characteristic to achieve exact charge injection

cancellation. Therefore, only first-order cancellation is possible with this method, improving gain

loss due to hold pedestal but leaving distortion unaffected. If the bridge center taps are driven by

amplifiers from the respective bridge outputs such that and , then hold

pedestal is negligible anyway (recall the analysis from section 3.2.6) so this cross-cancelling

Figure 3.29. Feedthrough versus area of cross-coupled diode structurenormalized to the optimum area.

0.85 0.90 0.95 1.00 1.05 1.10Cross Coupling Diode Area (normalized to optimum)

-120

-110

-100

-90

-80

-70

Fee

dth

rou

gh

(d

B)

VA VB 0= =

VA Vout= VB V− out=


approach is unnecessary.

Although the cross-coupling scheme described here can reduce feedthrough and gain loss

from hold pedestal, its several drawbacks including sensitivity to device mismatches, added

parasitic capacitances loading the bridge, and increased layout complexity call into question the

utility of the technique; therefore, this approach was not utilized in the present design.

3.2.8 Noise

Electronic noise generated by the elements within the track-and-hold contaminates the

input signal before digitization. Therefore, this noise must be negligible compared to quantization

noise to prevent the T/H from limiting the achievable SNR of the A/D converter. Moreover, several

noise sources affect T/H operation in ways that are unique from more general purpose circuits. Such

sources which comprise T/H noise include:

• Sample clock jitter as exacerbated by noisy clock buffer electronics within the T/H

itself

Figure 3.30. Cross-coupling can partially cancel hold pedestal error bycancelling charge expelled by bridge diodes during bridge turn-off. Note thatcharge injection from a bridge diode connected to the top node of one bridge iscancelled by the cross-coupled element connected to the bottom node of thecomplementary bridge. Likewise, injection from a diode connected to thebottom of one bridge is cancelled by the cross-coupled element connected tothe top of the complementary bridge.


• Electronic noise seen at the hold capacitor during track mode

• Electronic noise which adds to the held voltage during hold mode

• Shot noise from the postamplifier bias current which is integrated on the hold

capacitor during the hold period

These sources are summarized in figure 3.31 and will be described separately below. Since the noise

sources listed are uncorrelated, the total noise power emanating from the T/H is the sum of all of

these components. Total noise from an A/D converter includes this electronic noise from the T/H

plus quantization noise so that SNR can be expressed as

(3.145)

where is the noise power added to the signal during track mode, is the noise power

Figure 3.31. Noise sources affecting track-and-hold operation.

represents the total jitter noise power on the drive signals to the diode bridgeincluding the jitter on the incoming clock and that added by the clock buffercircuitry. represents the mean-square noise voltage at the holdcapacitors. This is an approximation assuming that the dominant component isthermal noise and exists during both track mode and hold mode. causes

base shot noise which is integrated on the hold capacitor during hold modegiving rise to voltage noise.

CH

CH

Preampand

Bridge

Preampand

Bridge

Vout

kTC noise

IB

στ2Clock

Buffer

Clock -Vin

+Vin

στ2

kT C⁄

IB

SNRσSignal

2

σQ2 σJitter

2 σTrack2 σHold

2 σShot2+ + + +

=

σTrack2 σHold

2


added to the held signal during hold mode, and is the shot noise integrated on the hold

capacitor during hold mode. The components of noise power found in the denominator of equation

3.145 are now discussed with the exception of the quantization noise power, , which was

described in detail in section 1.3.2.

The effect of clock jitter on SNR was treated in section 3.2.1 from a theoretical standpoint.

Here the deleterious effects of electronic noise in the clock buffer on the incoming clock signal are

discussed. The function of the clock buffer circuitry is to provide gain and level shifting so that a

standard logic-level signal can switch the diode bridge. In so doing, noise within the buffer will

exacerbate the jitter of the sampling signal seen at the top and bottom nodes of the diode bridge.

The resultant clock noise at the bridge drive nodes (which was the subject of section 3.2.1) derives

from the slew rate of the incoming clock signal and the input-referred noise voltage of the clock

buffer according to

(3.146)

where is the standard deviation of the clock jitter at the bridge drive nodes (this entity was

called in section 3.2.1), and is the standard deviation of the input-referred clock buffer

noise voltage. Notice that this component of clock jitter power adds to the jitter power already

existing on the incoming clock signal. , the input clock signal’s slew rate, is difficult to

predict in practice so a pessimistic approximation can be made by assuming that the incoming clock

signal is a sinusoid at the clock frequency with appropriate amplitude and offset to alternate

between the expected logic levels. can then be determined analytically. Under these

conditions, equation 3.146 places an upper limit on the input-referred clock buffer noise since

(3.147)

and is known from the assumption given above, and can be selected based on

its effect on A/D SNR as detailed in section 3.2.1. , the standard deviation of the input referred

noise voltage, can be calculated using standard methods of circuit analysis and should include all

noise sources including thermal noise, shot noise, noise, etc. In the present design, thermal

noise from transistor intrinsic base resistance dominates the input-referred noise but does not

present a limit to A/D converter operation at 10 bits of resolution and 100 Msps. The clock buffer

σShot2

σQ2

στBridge

σVin

Vclockd td⁄=

στBridge

στ σVin

Vclockd td⁄

Vclockd td⁄

σVinστBridge

Vclockd

td×≤

Vclockd td⁄ στBridge

σVin

1 f⁄


circuitry will be discussed in more detail in section 3.3.3.

Noise power produced by the track-and-hold electronics during track mode (called

above) can be calculated in ordinary fashion and referred to any convenient node in

the circuit for purposes of later analysis. This noise represents perturbations which are

added to the desired signal and which are sampled and then held when the S/H switches

into hold mode. Once in hold mode, electronic noise further perturbs the held signal so that

three components contribute to the signal which is eventually quantized: the desired signal

itself, additive noise from the circuit in track mode, and additive noise from the circuit in

hold mode. Because the bias levels for many T/H circuit elements are different in track

mode than in hold mode, the noise contributions during these two states are not necessarily

equal. Further, since contributes at the time of the track-to-hold transition while

contributes at the quantization instant, the two sources are independent (assuming

for simplicity white noise). Therefore, the noise power from the two sources simply adds

to the desired signal to give

(3.148)

If the track-mode noise and the hold-mode noise are nearly equal, the total noise power added to the

signal is twice that encountered in a continuous-time circuit. Therefore, low noise design of the T/H

electronics is particularly important mandating use of extreme care to ensure optimum

performance. Although standard techniques of noise analysis pertain to calculation of the noise

power at any circuit node, and computer simulation enables rapid and accurate analysis of very

complicated circuits; determination of the noise in a very simple network serves as a crude but

illustrative example enlightening analysis of the T/H circuit discussed here. Such a simple network

is now investigated.

In a simple single-pole system consisting of a resistor driving a shunt capacitor (Fig.

3.32), the noise power spectral density output from the circuit is the low-pass filtered white,

thermal noise power spectral density from the resistor whose mean square is

. The frequency response of the system is

σTrack2

σTrack2

σHold2

σTotal2 σSignal

2 σTrack2 σHold

2+ +=

vn2 4kTR fd=


(3.149)

so that the output power spectral density becomes

(3.150)

and the mean-square noise voltage at the capacitor can be found by integration:

(3.151)

where the subscript impliestotal output noise power as distinct from output noise power

spectral density. By substituting , this integration simplifies to

(3.152)

which is easily solved to give

(3.153)

Figure 3.32. Single-pole RC low pass filter for analysis of kT/C noise.

R

Cvn2 4kTR∆f=

Vout

Vout s( )Vin s( )

11 sRC+=

Vout2 Vin

2

1 ω2R2C2+4kTR fd

1 ω2R2C2+= =

VoT2 Vout

2

0

∞

∫ 4kTR

1 ω2R2C2+fd

0

∞

∫ 4kTR

1 2πfRC( ) 2+fd

0

∞

∫= = =

oT

x 2πfRC=

VoT2

2kT( ) Cπ( )⁄

1 x2+xd

0

∞

∫2kTπC

1

1 x2+xd

0

∞

∫= =

VoT2 2kT

πC

1

1 x2+xd

0

∞

∫2kTπC

π2

× kTC

= = =


This equation implies that the integrated mean-square noise voltage arising from any single-pole

RC network is regardless of the resistor value and bandwidth of the system. Or stated more

simply, the RMS noise voltage is .

By generalizing the results of the above analysis, it can be shown that in anypassive circuit

where noise arises exclusively from thermal sources, the mean-square integrated noise voltage at

any node with shunt capacitance to ground can be conservatively approximated by where

is the shunt capacitance. Although this concept does not extend in any rigorous way to active

circuits, most practical circuits exhibit noise voltages on the order of this amount. By simulation,

the T/H circuits investigated here demonstrated mean-square noise voltages at the hold capacitor

within a factor of about 3 of for a wide range of circuit parameters. This empirical result

allows rapid approximations of circuit noise performance during preliminary design studies. Since

similar noise power levels exist at the hold capacitor in both track and hold modes, and since these

components arise from independent noise sources, the resultant contribution to the total noise from

and is twice the value quoted above; therefore, mean-square noise voltage referred

to the hold node can be approximated as . The differential aspect of the

T/H designed here affects the noise analysis. Since two identical half-circuits comprise the T/H,

noise as just describes exists at each hold capacitor. These noise sources are independent so

Figure 3.33. kT/C noise at the hold capacitors. In the differentialimplementation the two independent sources contribute to the total noisepower perturbing the held voltage, resulting in doubled noise power

compared to a single-ended version. Signal amplitude is also doubled, thusquadrupling signal power and increasing SNR by 3 dB over the single-endedcase.

kT C⁄kT C⁄

kT C⁄

C

kT CH⁄

σTrack2 σHold

2

σTrack2 σHold

2 5kT C⁄≈+

kT C⁄

Preamp&

Bridge

Preamp&

Bridge

Postamp

CH

CH

Vin

+

-

+

-VH -

+

VnT2 kT

CH=

VnT2 kT

CH=

VH


their powers add when affecting the differential held voltage, . Therefore, the mean-square

differential noise component of the held voltage is (where the subscript refers

to the total integrated mean-square noise voltage at the hold node as distinct form the noise power

spectral density). In spite of this increase in noise power, the differential implementation exhibits

superior SNR compared to a single-ended version because while the noise power doubles as shown,

the signal power quadruples (since the signal amplitude doubles and the power is proportional to

). Therefore, a differential T/H circuit is capable of increased SNR by 3 decibels over a single-

ended version.

During hold mode, base shot noise from the postamplifier integrates on the hold capacitor,

, giving rise to a noise voltage which adds to the held signal further degrading achievable SNR.

Themean square of the shot noise is where is the electron charge and is

the base current flowing to the input transistor of the postamplifier. When integrated over the

hold period, (where is the sample rate of the converter), the resultant mean-square

noise voltage on the hold capacitor, , is†

(3.154)

†. My thanks to Aaron Buchwald for deriving this result.

Figure 3.34. Base shot noise integrates on the hold capacitors during thehold interval adding a noise component to the held voltage.

VH

VHT2 2kT C⁄= HT

A2

CH

Ib

Ibias

VHeld+

Ib

Ibias

_VHeld

CH CH

in2 2qIB fd= q IB

TS 1 fS⁄= fS

CH

σShot2 qIB

CH2 fS

=


Since the shot noise source is independent from the others previously described, this noise power

adds to the total signal power which is eventually quantized. Notice that increased hold capacitance,

, decreases the shot noise contribution as does decreased postamplifier input bias current, .

The integrated shot noise component decreases with increasing sample rate, , since the noise

current spends less time integrating on the hold capacitor forming a noise voltage. Only and

are parameters under designer control which affect the integrated shot noise. Therefore, these

factors must be chosen judiciously to keep acceptably small.

3.2.9 Droop

Input bias current flowing to the postamplifier during hold mode depletes the hold capacitor

of charge resulting in a change in the held voltage calleddroop(Fig 3.35a). The held voltage varies

with the postamplifier input current according to:

(3.155)

where is the postamplifier input current. If is constant, the held voltage changes at a fixed slew

rate (Fig.3.35b), and in a T/H circuit operating at sample rate the voltage deviation

Figure 3.35. Postamplifier input bias current causes droop on hold capacitor.

CH IB

fSCH IB

σShot2

Ib

Ibias

V Held

time

V HeldSlope= / CHIb

0

CH

(a) (b)

VHeld t( )d

td

Ib

CH−=

Ib Ib

fS 1 TS⁄=


during the hold period becomes

(3.156)

If the input bias current, , is truly constant, then will not vary from sample to sample,

and therefore will not affect operation of the T/H except by adding an offset to the stream of held

samples. This offset must be kept reasonably small to prevent bias problems in succeeding circuitry

but does not hinder performance in any other way. If, however, the postamplifier input bias current

depends upon the held signal then equation 3.155 modifies to

(3.157)

where indicates the functional dependence of on . For a known function,

, equation 3.157 can be solved for , the held voltage at the end of the hold

mode. If is a linear function of , say

(3.158)

then can be solved for analytically using equation 3.157:

(3.159)

∆VHeld

Ib

CH− ∆t

Ib

CH−

TS

2= =

Ib ∆VHeld

VHeld t( )d

td

Ib VHeld t( )( )CH

−=

Ib VHeld( ) Ib VHeld t( )Ib VHeld( ) VHeld TS 2⁄( )

Ib VHeld t( )

Ib αVHeld t( )=

VHeld TS 2⁄( )

VHeld t( )d

td

αVHeld t( )CH

−=

VHeld t( )d

VHeld t( )α

CHtd−=

VHeld t( )d

VHeld t( )Vo

VHeld TS 2⁄( )

∫α

CHtd

o

TS 2⁄

∫−=

lnVHeld TS 2⁄( )

Vo( )

αCH

TS

2−=

VHeld TS 2⁄( ) Voe

αCH

TS

2−

=


The last line of equation 3.159 indicates that the held voltage at the end of hold mode,

, equals the initial held voltage, , multiplied by a constant factor,

. Therefore, when is a linear function of , the effect of droop is to

attenuate the stream of sampled signals from the T/H without introducing any distortion. In general,

however, dependency of on causes distortion at the T/H output because signals of

different amplitudes experience different deviations during hold mode. This potential error source

can be mitigated by ensuring that is small enough and is large enough that any distortion

resulting from droop is acceptably small.

Mandating low postamplifier input bias current, , and large hold capacitance, , as just

suggested reduces droop-induced distortion but possibly at the expense of increased settling time of

the postamplifier due to its low bias current, and at the expense of increased track-mode distortion

because of the increased dynamic load on the preamplifier. Alternatively, the natural common-mode

rejection of a differential implementation can be used advantageously to eliminate most effects of

the droop phenomenon. In a differential realization of the T/H, both held voltages will experience

nominally equal droop so that the resulting differential signal is largely (if not totally) independent

of postamplifier input bias current (Fig. 3.36). Since each side of the differential circuit still

Figure 3.36. A differential T/H implementation largely cancels droop effects.

VHeld TS 2⁄( ) Vo

exp αTS 2CH⁄−( ) Ib VHeld

Ib VHeld

Ib CH

Ib CH

V Held+

Ibias

CHIb1 CH

Ibias

-V Held

Ib2

Vol

tage

Time

slope= 0~

VHeld+

_VHeld

_VHeld+

_VHeld

Ib1slope= / CH

slope= / CHIb2

(a)

(b)


experiences a voltage drop during the hold mode equal to approximately care must be

taken to ensure that bias levels of succeeding circuitry remain suitable. Cancellation of droop effects

relies upon in figure 3.36. Otherwise, a residual differential droop signal will perturb the

held signal according to

(3.160)

If the current difference is constant, then (as in the single-ended case with constant )

will not vary from sample to sample but will merely add a fixed offset to each sample of

the output data stream. Likewise, if varies linearly with , then attenuation of the

sampled data stream results. Again, as in the single-ended case, distortion arises when is

a nonlinear function of . The chief advantage of the differential implementation regarding

droop behavior is that is usually quite small so that the slew rate of the differential output

from the postamplifier is near zero. In contrast, the postamplifier can traverse many A/D LSBs

during the hold mode if a single-ended circuit T/H is used.

3.2.10 Thermal Distortion

Power dissipated in an integrated circuit induces temperature gradients across the surface

of the silicon chip. These gradients in turn affect device operation because the underlying

semiconductor physics follow either Fermi-Dirac or Maxwell-Boltzmann distributions both of

which depend exponentially on temperature. Such temperature dependence is exhibited by, among

other things, , the saturation current of apn junction, and , the thermal voltage equal to .

These two dependencies combine to determine the temperature coefficient of thepn junction

potential under constant current conditions, , which is well known to be approximately –

2 mV/°C. This extreme sensitivity of the bipolar transistor’s operating characteristic frequently

degrades circuit operation by causing unwanted perturbations in base-emitter potentials when

temperature gradients exist. For example, thermal effects can induce offsets in comparators when

one transistor of the input differential pair operates at a different temperature than the

complementary transistor. This temperature difference can be caused by power dissipation within

the comparator itself which, in turn, depends upon the input signal to the circuit. Since dynamic

thermal behavior in silicon exhibits natural frequencies in the audio range, signal-dependent

IbTS 2CH⁄

Ib1 Ib2=

∆VHeld ∆VHeld+ ∆VHeld

−−Ib1 Ib2−( )

CH

TS

2= =

Ib1 Ib2− Ib

∆VHeld

Ib1 Ib2− ∆VHeld

Ib1 Ib2−∆VHeld

Ib1 Ib2−

IS VT kT q⁄

TCVBE


thermal gradients result in unwanted comparator hysteresis [34], [35].

To quantify the magnitude of electro-thermal interaction, the thermal resistance from a

device’s junction to the substrate, , must be known. can be calculated by solving the steady-

state thermal diffusion equation for a device of given geometry and power dissipation [36],[37].

When performed for a minimum-size SHPi transistor with a2 µm X 8 µm emitter area not

located near any adiabatic edges and dissipating 1 mW in a250 µm thick substrate, such analysis

yields a temperature contour exhibiting a 2°C temperature rise from the substrate to the emitter

center (Fig. 3.37). Therefore, for a minimum-size SHPi device, . The contour

of figure 3.37 also indicates that temperature perturbations of the substrate are localized to an area

a few times larger than the emitter itself, indicating that modest power dissipated in one device will

only marginally increase the temperature of adjacent devices. For comparison, a large device with

a 75 µm X 75 µm emitter area dissipating 200 mW also in a250 µm thick substrate shows an

increase in emitter temperature of approximately 20°C although the power density is only about

Figure 3.37. Thermal contour of minimum-size SHPi device (2 µm X 8 µmemitter area) dissipating 1 mW on a 250 µm thick substrate.

θjs θjs

θjs 2°C mW⁄=

-20

0

20

-20

0

20

0

0.5

1

1.5

2

x axis (microns)y axis (microns)

Tem

pera

ture

Ris

e (C

)


half of that in the previous case (Fig. 3.38). for this device is therefore 0.1°C/mW. Again,

significant temperature changes are limited to an area a few times larger than the emitter region.

Note that although the area of the larger device is 350 times that of the minimum device, its thermal

resistance to the substrate, , is only 20 times lower. Nonetheless, when high power dissipation

is required, larger devices are necessary for their lower thermal resistance.

Electro-thermal interaction gives rise to distortion when an electrical input signal

modulates device power. The power modulation induces temperature fluctuations within the device

resulting in electrical perturbations which distort the original signal. This phenomenon, called

thermal distortion, is particularly troublesome in precision circuits where even small deviations

from ideal performance are unacceptable. The T/H circuit under consideration represents such a

precision circuit, and even a simple emitter follower buffer comprising the preamplifier and/or

postamplifier is susceptible to excessive thermal distortion. Emitter follower device power is

determined exclusively by the input voltage since the bias current is ideally constant (Fig. 3.39).

Power dissipation in a transistor can be expressed by

Figure 3.38. Thermal contour of large device (75 µm X 75 µm emitter area)dissipating 200 mW.

θjs

-0.4-0.2

00.2

0.4

-0.4

-0.2

0

0.2

0.40

5

10

15

20

x axis (mm)y axis (mm)

Tem

pera

ture

Ris

e (C

)

θjs


(3.161)

where the approximation assumes . In an emitter follower such as depicted in figure 3.39 the

power dissipation becomes

(3.162)

If the input voltage, , changes to a new value, , then the power dissipation will

change correspondingly to

(3.163)

where any changes in are assumed to be negligible. Subtracting equation 3.162 from equation

3.163 gives the change in power, , as a function of the change in input voltage, :

(3.164)

This change in the emitter follower power dissipation will cause a change in the base-emitter

junction temperature which will in turn cause a change in . The change in can be

determined from the device thermal resistance, , and the temperature coefficient of thepn

junction potential, .

(3.165)

By substituting the expression in equation 3.164 for the incremental base-emitter voltage as

Figure 3.39. Emitter follower buffer.

IBias

Vin

VCC

Vout

PD IcVce IbVbe+=

PD IcVce IbVbe+= IcVce≈

Ic Ib»

PD IBias VCC Vout−( ) IBias VCC Vin Vbe−( )−[ ]= =

Vin Vin ∆Vin+

PD ∆PD+ IBias VCC Vin ∆Vin+( ) Vbe−[ ]− =

Vbe

∆PD ∆Vin

∆PD I− Bias∆Vin=

Vbe Vbe

θjs

TCVBE

∆Vbe TCVBEθjs ∆PD××=

∆PD


a function of the incremental input voltage results:

(3.166)

Since is an error term caused when is applied to the T/H, and since this error term must

be small compared to a quantization step, , of the following quantizer, the ratio must

smaller than . This places an upper bound on the emitter follower bias current before thermal

distortion leads to errors larger than one quantization step.

(3.167)

The last line of equation 3.167 represents a severe limitation on bias current for emitter followers

in high-resolution circuits. For example, in the T/H under consideration with ,

, and , bias current is limited to

(3.168)

This low value of bias current can be problematic when driving capacitive loads because both

bandwidth and dynamic linearity degrade with reduced bias (as explained in section 3.2.3).

Therefore, simply selecting low bias levels is not a viable method for reducing thermal distortion to

acceptable levels. Rather, techniques must be employed to enable operation at higher bias levels

without thermal distortion effects. Circuits based on negative feedback can achieve insensitivity to

thermal gradients, but this method is rejected for the present application because open-loop

∆Vbe TC− VBEθjs IBias∆Vin××=

∆Vbe

∆VinTC− VBE

θjs IBias=

∆Vbe ∆Vin

Q ∆Vbe ∆Vin⁄2 N−

∆Vbe

∆Vin2 N−<

TC− VBE θjs IBias 2 N−<

IBias2 N−

TC− VBE θjs

<

IBias1

2NTCVBE θjs

<

N 10=TCVBE

2mV °C⁄−= θjs 2°C mW⁄=

IBias1−

2NTCVBE θjs

< 1−

210( ) 2mV−°C

( )2°CmW

( )250µA≈=

3.3 Track-and-Hold Design 195

implementations offer potentially higher-speed operation. Instead, approaches are utilized which

maintain constant power dissipation in pertinent devices independent of signal level, or which

constrain signal-dependent power to be matched between complementary devices in differential

implementations [38]. Both of these techniques have been used in the T/H circuit and will be

described in detail.

3.3 Track-and-Hold Design

Sections 3.1 and 3.2 discussed operation and limitations of diode-bridge track-and-hold

circuits from a general perspective. This section describes in detail the specific circuits implemented

during this project to realize a 10-bit 100 Msps A/D converter with on-chip T/H. Two such circuits

are required in the feedforward architecture used: the first, the input T/H, tracks the 50 MHz input

signal with adequate dynamic linearity to assure 10-bit operation at 100 Msps while the second, the

interstage T/H, is required for pipelined operation of the A/D converter and requires only linearity

consistent with 7-bit quantization but must also operate at 100 Msps.

3.3.1 Preamplifier and Sampling Bridge

The input T/H circuit is based upon a diode-bridge with a differential pair current switch

and resistive loads. Both the preamplifier and postamplifier are based upon emitter followers to

achieve a simple design with high-speed performance and good linearity (Fig. 3.40). This circuit

suffers from several drawbacks which were discussed in section 3.2 and which can be at least

partially alleviated by resorting to a differential implementation. Additional circuit modifications

are required to overcome other shortcomings. The important error sources afflicting the T/H of

figure 3.40 include:

• Track mode distortion due to dynamic load current flowing through the input emitter

follower and diode-bridge and into load capacitor (these effects are analyzed in

sections 3.2.3 and 3.2.4)

• Track mode distortion caused by finite load impedances, , as described in section

3.2.4

• Thermal distortion resulting from signal-dependent power modulation in the

preamplifier and postamplifier (section 3.2.10)

CL

RL


• Excessive droop caused by postamplifier bias current discharging the hold capacitor

(section 3.2.9)

• Exacerbated hold pedestal error which arises because the bridge center-tap node is

not centered at the same voltage as the input signal. The input source is assumed to

be ground-centered with impedance. (See section 3.2.6.)

The differential circuit implemented to mitigate these errors (Fig. 3.41) includes two identical

diode-bridge switches driven by a common clock buffer, two hold capacitors connected to ground,

a differential postamplifier, and a compensation network between the complementary input emitter

followers to decrease both static and dynamic track-mode linearity. The differential nature of the

circuit naturally cancels even-order error terms including even-order distortion components and

droop. Additionally, the SNR of this approach is improved over the single-ended version because

while the noise power is doubled, so is the signalamplitude resulting in quadrupled signal power.

Aside from these advantages which accrue for all differential circuits, the available complementary

Figure 3.40. A single-ended T/H circuit based on a diode-bridge with emitterfollower preamplifier, differential pair current switch with resistive loads, andemitter follower postamplifier.

Hold Track

Vout

Vin

RL RL

CH

50Ω


signals can be used judiciously to cancel some mechanisms of distortion. The technique used here

(Fig. 3.42) reduces track mode distortion by injecting a compensation current at the emitters of the

two main emitter followers. This compensation current is generated by a transconductance cell

comprising a degenerated differential pair whose inputs are developed by an auxiliary pair of

emitter followers. The output of each auxiliary emitter follower drives the complementary input of

the transconductance cell so that the effective polarity of transconductance is inverted. The

magnitude of the transconductance is determined by the cell’s degeneration resistance, , which

is set equal to the diode-bridge load resistors, . By selecting this polarity and value of

transconductance, signal current is injected into the input node of the bridge exactly equal to that

required to flow through the parallel combination of the two bridge load resistors, , in response

to the input signal. This arrangement therefore cancels the static signal current flowing from the

main emitter follower eliminating its signal-dependent modulation and hence its static

distortion. Dynamic distortion caused by signal current flowing from the main emitter followers

into the hold capacitors is also reduced with this mechanism by connecting a shunt capacitor around

the transconductance’s degeneration resistor. The value of this capacitance should nominally equal

one half the hold capacitance, but the actual value, determined empirically via simulation, is

Figure 3.41. A differential track-and-hold implementation with linearity compensation.

CompensationNetwork

DiodeBridgeSwitch

ClockBuffer

DiodeBridgeSwitch

Track

HoldVout

DifferentialPostamplifier

X1

X1

InputBuffer

InputBuffer

Vin+

-Vin

-+

RE

RL

RL

Vbe


somewhat different to optimally cancel not only dynamic distortion from the main emitter follower,

but from other dynamic effects within the bridge as well. Because the bias and signal currents

flowing through the bridges are unaffected by this scheme, distortion arising from current

modulation in the bridge diodes (both static and dynamic) is not eliminated. These distortion

sources are analyzed in section 3.2.4, and along with finite aperture time remain as the dominant

error sources in the T/H.

In addition to generating the input signals for the compensating transconductance cell, the

auxiliary emitter followers feed a level-shifted signal to the base of a bootstrap device which

maintains a constant across the main emitter followers independent of the input signal level.

This method eliminates thermal distortion in the input devices. To reduce thermal noise which is

dominated by intrinsic base resistance in the main emitter followers, these devices are selected to

be 4 times the minimum device size, thus reducing the contribution of these noise sources by a like

factor. The center-tap nodes of the complementary bridges are biased at one diode drop below

ground potential. This voltage drop matches that of the input emitter followers so that the center-

tap nodes are biased at the common-mode voltage of the differential input signal. The preamplifiers

consisting of main and auxiliary emitter followers, the complementary diode-bridges, the

transconductance cell, and the two hold capacitors are laid out in symmetric fashion occupying an

area of approximately (Fig. 3.43).

Figure 3.42. Differential preamplifier and bridge with compensation.

Hold Track

2.5 mA

800 uA200 uA

A=4

HoldTrack

2.5 mA

800 uA 200 uA

A=4

ToPostamplifier

Vout-Vout+

RL

RLRL

RL

RE

Vin+ Vin-

Vce

600µm 500µm×


3.3.2 Postamplifier Design

The purpose of the postamplifier is to provide high input impedance with low bias current

to prevent leakage of charge from the hold capacitor during hold mode. In addition, an ideal

postamplifier should exhibit low output impedance for driving capacitive loads with low distortion

and short settling time. Of course, low power dissipation, and low-noise operation are desirable as

for any analog component. In some instances, the postamplifier also provides voltage gain, but the

first T/H in the present A/D converter does not require gain greater than unity (the voltage gain of

the postamplifier in the second T/H from this design is 2 however). A prototype postamplifier

fulfilling all of the above characteristics derives from an ideal operational amplifier (op-amp)

configured as a voltage follower (Fig. 3.44a). This circuit provides infinite input impedance, unity

gain, and zero output impedance, but is unrealizable in practice. A simple but crude approximation

to this ideal relies on a resistively loaded differential pair to form a basic one-stage op-amp (Fig.

Figure 3.43. Layout of differential preamplifier and diode bridge withfeedforward compensation.

xsam

p1

Siz

e: 5

92 x

480

mic

rons

### ## ##

## # #### ## ##### ### ###### # # ### ### #### #### ####

###### ## ####### ### ### ##### ###### ##### # #### #### # ### ## ###### # ### ## ## ### ### #

#### ##

####


3.44b). The chief limitation of this approach is the relatively low gain achievable with resistive

loading which is expressed by

(3.169)

where is the bias voltage across load resistor . Since a 5 Volt power supply is used, is

limited to about 2.5 Volts so that the maximum gain is

(3.170)

Figure 3.44. Postamplifier implementations. (a) An operational amplifierconnected as a voltage follower. (b) A differential pair configured as a voltagefollower. (c) A differential pair-based follower with enhanced performance. (d)An open-loop unity-gain postamplifier with linearity compensation.

VoutVin

(a)

(d)

Vin+ Vin-Vout- Vout+RE

RLRL

Vin Vout

Vcc

(b)

RL

Ibias

(c)

Vin Vout

X1

AuxiliaryAmplifier

LevelShiftRL

Ibias

AV gmRL

IC

VTRL

VRL

VT= = =

VRLRL VRL

AV

VRL

VT

2.5V25mV

≈ 100= =


With open-loop gain of 100, the follower’s closed-loop gain is only approximately 0.99, and the

improvements from feedback in input and output impedance are modest. The effective resistance,

, can be increased, and the amplifier gain improved proportionately, if the top node of the load

resistor is driven by a level-shifted replica of the output voltage rather than connected to the positive

power supply (Fig. 3.44c). In this arrangement, a constant bias equal to the level-shift voltage is

maintained across thus presenting an infinite impedance to the differential pair. Higher open-

loop gain and improved closed-loop performance result. If the gain of the auxiliary amplifier in

figure 3.44c is rather than 1, the effective impedance looking into the load resistor is

and the open-loop gain becomes

(3.171)

where is the value of the level-shifting voltage. Therefore, even with a non-ideal bootstrap

amplifier significant improvements in gain can be achieved. A suitable circuit for providing the

level-shifting and near-unity gain necessary in figure 3.44c is shown in figure 3.44d. This buffer

amplifier relies on a degenerated differential pair with resistive loads to attain voltage gain near

unity, and employs diode-connected transistors in its loads to enhance linearity. The load diodes

improve linearity by eliminating the dependence of amplifier gain upon transistor . The

transconductance of the degenerated differential pair is

(3.172)

where appears instead of because differential half-circuit is used for calculating the gain.

The load impedance seen in figure 3.44d is

(3.173)

so that the amplifier gain becomes

(3.174)

RL

RL

1 α− RL α⁄

AV gm

RL

αIC

VT

RL

αVRL

αVT

VLS

αVT= = = =

VLS

gm

Gm

gm

1 gm RE 2⁄( )+1

RE 2⁄( ) 1 gm⁄+= =

RE 2⁄ RE

ZL RL 1 gm⁄+=

AV G− mZL

RL 1 gm⁄+RE 2⁄( ) 1 gm⁄+−= =


If then the gain expression simplifies to

(3.175)

Since the voltage gain, , is independent of , distortion-free operation results. Finite transistor

reduces the actual gain of this amplifier to slightly less than unity for two reasons. First, losses

reduce the given above by the factor , and second, of the load diodes is lower

than that of the differential pair transistors by the same factor, , since the collector

current of the differential pair devices equals theemitter current of the diode-connected load

transistors. Equation 3.175 indicates that the buffer amplifier voltage gain is negative, however,

since the realization is fully differential, either inverting or non-inverting operation is easily

obtainable.

This differential auxiliary buffer is combined with two complementary followers from

figure 3.44c to form the T/H postamplifier (Fig. 3.45). In this implementation, each of the transistors

comprising the op-amp followers is increased in area to reduce thermal noise from intrinsic base

resistance. Additionally, the high gain achieved with the bootstrapping technique will increase the

Figure 3.45. Differential postamplifier implementation.

RL RE 2⁄=

AV

RE 2⁄( ) 1 gm⁄+RE 2⁄( ) 1 gm⁄+− 1−= =

AV gm

β βGm β β 1+( )⁄ gm

β β 1+( )⁄

Vin+ Vin-

+ Vout -

Vcc

A=4A=4 A=4 A=4


input impedance and decrease the output impedance significantly. Each transistor in the op-amp

differential pairs experiences constant so thermal distortion is eliminated (any residual thermal

effects are further reduced because of the closed-loop nature of the amplifier). The postamplifier

layout is symmetrical; is pitch aligned with the preamplifier and bridge circuits; and occupies an

area of (Fig. 3.46).

3.3.3 Clock Buffer

The clock buffer circuit provides suitable gain and level-shifting to accept a standard

Figure 3.46. Layout of differential postamplifier with feedback bootstrapping.

Vce

300µm 500µm×

###

###

##########

#

#

######

#

#

#

#

#

#

#

#

###

###

##########

######

#

#

######

#

#

######

####

####

#

#

#

#

####

#

#

##

###

####

###

#

#

#

#

#

##

###

##

##

###

#

#

####

####

#

#

#

#

#

#

#

#

#

#


emitter-coupled-logic (ECL) input signal and drive the differential pair switches which control the

complementary diode-bridge. The buffer must perform this function while adding minimal noise to

the incoming clock signal (as discussed in sections 3.2.1 and 3.2.8) and while dissipating minimal

power. The implementation used for this project (Fig. 3.47) incorporates input emitter followers to

provide high input impedance and level-shifting, a resistively loaded differential pair to provide

gain and common-mode rejection, and emitter follower output buffers to provide low output

impedance. Two series connected diodes ensure the correct common-mode bias voltage at the

output of the differential pair where on-chip capacitors filter broadband noise and prevent ringing

of the output emitter followers when driving capacitive loads. The input emitter followers are 4

times larger than minimum devices to reduce their base resistance associated thermal noise which

proves to be the dominant noise source in this amplifier. The clock buffer is pitch-aligned with the

Figure 3.47. Clock buffer schematic diagram.

-2V

Vref

Vin+

-

Vout+

-


rest of the T/H circuitry and occupies an area of (Fig. 3.48).

3.3.4 Design Summary

The differential preamplifier, complementary bridges, and differential postamplifier

combine to form the T/H circuit used for this A/D converter (Fig. 3.49) which operates from +5 V

and –5 V supplies dissipating approximately 100 mW. (The clock buffer and bias generation

circuitry are not included in figure 3.49 for simplicity but are included in the 100 mW power figure.)

The two hold capacitors are 2 pF metal-oxide-semiconductor (MOS) structures which occupy

around 10% of the T/H area which is (Fig. 3.50). The full-scale input signal

Figure 3.48. Layout of first track-and-hold clock buffer circuit.

220µm 425µm×

ckbuf Size: 220 x 424 microns

#

########

#

##

###

##

##

######

#

###

#

##

#

#

###

#

##

##

##

#

######

###

##

##

###

#

########

#

1200µm 500µm×


to the T/H is designed to have 512 mV differential amplitude. Alternatively, the full-scale range can

be specified as 1.024 V differential. Simulations indicate that for a full-scale sinusoidal input at a

frequency near 50 MHz and sampled at 100 Msps, the spectrum of the output sample stream

contains harmonics which are over 80 dB below the fundamental frequency (Fig. 3.51). The

prominent odd-order harmonic is the 3rd, located at –85.7 dBc, while the odd-order total harmonic

distortion (THD) is –84.4 dB. These figures approach the ideal distortion level of a 10-bit quantizer

which is . Because the differential architecture of the T/H rejects all even-order

distortion products, only odd components appear in the differential output spectrum. Anticipating

imperfect cancellation of even-order components due to mismatches in the T/H components, the

single-ended output spectrum was also investigated. The worst-case even-order harmonic in the

Figure 3.49. Complete track-and-hold circuit (with postamplifier shaded).The clock buffer has not been drawn for simplicity.

Figure 3.50. Layout of first track-and-hold circuit.

Vin

Vout −+

Vin

th1

S

ize:

123

2 x

480

mic

rons

###### ### # ### ## ### ## ## ## ##### ##### ## #### #### ###### #### ########## ## # ############ # ## ##### #### #### ## ####### ### #### ## ##########

####

## ####### #### ############ #### ##### ## #### ### ############## ### ####### ############ ## ######### ### ### ##### #### ### # ######## ########## # ## ########## ### #### ## ### #### ### ### ## ### ## ## ## ## #### ### ## ###

##

##

### ##### ## ######### #### ######

9N− 90dBc−=

3.4 Interstage Track–and–Hold Design 207

single-ended spectrum is the 2nd at –67 dBc. This distortion product, along with all other even-

order components, will be attenuated significantly by the common-mode rejection of the succeeding

circuits within the A/D so that the overall distortion performance of the T/H is acceptable for

application in a 10-bit converter.

3.4 Interstage Track –and–Hold Design

The second (or interstage) track-and-hold circuit receives a signal from the residue

amplifier in the A/D converter which must be quantized with 7-bit resolution. As in the first T/H,

operation at 100 Msps is required, but the input to the second T/H is not a dynamically changing

signal. Rather, the input here is a signal which steps rapidly at the hold-to-track transition (as the

reconstruction DAC switches to its new state) and then settles slowly during track mode. Therefore,

good dynamic linearity in track mode is unnecessary and only static linearity consistent with 7-bit

quantization (implying ) is required. Unlike the input T/H, gain

accuracy is critical in the interstage T/H and its design is modified accordingly.

The interstage T/H is modelled after the input T/H with slight modification as indicated in

figure 3.52. This block diagram indicates that the interstage T/H is identical to the input T/H with

the addition of two feedback amplifiers from the two output nodes to the bridge center-tap nodes.

Figure 3.51. Simulated T/H output spectrum. Fs=100 Msps, Fin=43.75 MHz.

0 1 2 3 4 5 6 7 8Harmonic

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

Rel

ativ

e A

mp

litu

de

(dB

c)

SFDR 9N 63dBc= =


These amplifiers reduce hold pedestal error which would otherwise cause unacceptable gain loss

(see section 3.2.6). The feedback amplifiers are simple, one-stage op-amps configured as voltage

followers like that depicted in figure 3.44b. When connected between bridge output and center-tap

node (Fig 3.53), these buffers significantly reduce the deleterious effects of hold pedestal. The

layout of the interstage T/H is symmetrical and occupies an area equal to

(Fig. 3.54).

The postamplifier of the interstage T/H must present a high impedance to the hold

capacitors to prevent excessive droop, and must provide voltage gain of 2 in order for the amplitude

of the residue signal to correctly align with the full-scale voltage of the fine quantizer. This gain

Figure 3.52. Second stage track-and-hold block diagram with feedback tobridge center-tap nodes to reduce gain-loss due to hold pedestal error.

CompensationNetwork

DiodeBridgeSwitch

ClockBuffer

DiodeBridgeSwitch

Track

HoldVout

DifferentialPostamplifier

X1

X1

InputBuffer

InputBuffer

X1

X1

FeedbackAmplifier

FeedbackAmplifier

-Vin

Vin+

-+

1200µm 500µm×


must be accurate to within about 1% to prevent missing codes in the A/D transfer function. The

Figure 3.53. Second track-and-hold with bootstrapped center-tap.

Figure 3.54. Layout of second T/H.

Hold Track

Vout

Vin

CH

xsam

p2

Siz

e: 2

26 x

556

mic

rons

########### ########## ## ####### #### ## # ########### # ########### ########## # ############ ## ##### ##### ## ## ##### ##### # # ############ # ########## ############ ########### #

### ## #### ######### ########## # ##########


circuit implemented here resembles that described in section 3.3.2 and shown in figure 3.44d with

the exception that the load impedances are doubled to achieve the increased gain necessary (Fig.

3.55). In this circuit, the output common-mode voltage is set by a diode reference string (D1-D3)

which supplies the bias voltage for the base of an emitter follower pull-up device (Qpull-up). Using

this method, the output common-mode voltage becomes

(3.176)

Figure 3.55. Interstage postamplifier schematic which provides high inputimpedance and voltage gain of 2. Output emitter followers are not shown forsimplicity.

Vin+ Vin-

Vcc

Ree

+Vout-Rl Rl

D1

D2

D3

Ql1A

Ql2A Ql2B

Ql1B

Qpull-up

Vcm VD1 VD2 VD3 VQpull up−− VQl1A− VQl2A− IBiasRL−+ +=

IBiasRL−=


where the last line of equation 3.176 assumes all drops are equal. Since this bias voltage is

independent of , it is also independent of the concomitant reliance on temperature. The gain of

the second postamplifier is

(3.177)

If , then this expression reduces to

(3.178)

Since the gain is independent of and hence transistor operating point, the amplifier should be

distortion-free. Mismatches in components will degrade performance from this ideal, but operation

with linearity appropriate for 7-bit quantization ( ) is

achievable. The interstage postamplifier layout is symmetrical and occupies an area equal to

(Fig. 3.56).

A replica of the interstage T/H circuit facilitates matching the A/D converter residue full-

scale amplitude to the fine quantizer full-scale amplitude. This replica circuit is identical to the

interstage T/H but scaled down to reduce power dissipation. Also, the replica circuit is locked in

track mode, so the bridge switch circuitry is eliminated. The entire interstage T/H along with its

replica, the clock buffer, and the bias circuitry occupy an area equal to (Fig.

3.57).

VBE

VBE

AV GmZL1

1gm

Ree

2+

1gmQl1A

1gmQl2A

RL+ +( )==

1

1gm

Ree

2+

= 2gm

RL+( )

Ree RL=

AV1

1gm

Ree

2+

2gm

RL+( )=

1

1gm

RL

2+

= 2gm

RL+( ) 2=

gm

SFDR 9N 9 7× 63dB= = =

225µm 300µm×

750µm 1000µm×


References

[1] B. Gilbert, “Translinear circuits: A proposed classification,”Electronics Letters, vol. 11,pp. 14–16, Jan. 1975.

[2] B. Gilbert, “A precise four-quadrant multiplier with subnanosecond response,”IEEE Jour-nal of Solid State Circuits, vol. SC-3, pp. 365–373, Dec. 1968.

[3] B. Gilbert, “A new wide-band amplifier technique,”IEEE Journal of Solid State Circuits,

Figure 3.56. Second T/H postamplifier.

sh2p

st

Siz

e: 2

24 x

285

mic

rons

########## ########## ### ###### # ## ## ######## ### ##### ## ######## ##### #### ### ######

##### ##### ##### ## # ######## ## ### # ######## ########## ##########


vol. SC-3, pp. 353–365, Dec. 1968.

[4] E. Seevinck, “Synthesis of nonlinear circuits based on the translinear principle,” inInter-national Symposium on Circuits and Systems, pp. 370–373, IEEE, 1983.

[5] E. Seevinck,Analysis and Synthesis of Translinear Integrated Circuits. Elsevier, 1988.

[6] J. R. Gray and S. C. Kitsopoulos, “A precision sample and hold circuit with subnanosecondswitching,” IEEE Transactions on Circuit Theory, vol. CT-11, pp. 389–396, Sept. 1964.

[7] I. Dostis, “Evaluation of the nonlinear distortion caused by the finite turn-off time of a Sam-ple-and-Hold-Circuit for high-speed PCM,”IEEE Transactions on Circuit Theory, vol.CT-13, pp. 94–97, Mar. 1966.

[8] G. Erdi and P. R. Henneuse, “A precision FET-Less Sample-and-Hold with high Charge-to-Droop current ratio,”IEEE Journal of Solid State Circuits, vol. SC-13, pp. 864–873,Dec. 1978.

[9] B. Astegher, A. Lechner, and H. Jessner, “A novel All-NPN sample and hold circuit,” in15th European Solid-State Circuits Conference Digest of Technical Papers, pp. 88–91,IEEE, 1989.

[10] A. J. Metz, “Sampling bridge.” U.S. Patent Number 4,659,945, Apr. 1987.

[11] K. Tanaka, F. Ishikawa, K. Abe, and K. Koma, “A 40MS/s monolithic S/H IC,” inInterna-

Figure 3.57. Second T/H with replica.

th2

S

ize:

741

x 9

81 m

icro

ns

############ ## ############# # ### ############## ####### ### #### ######### ## ## ################# # ############### ############# # ################## ## ## ########### ##### ##### ##### ##### ########### # ## ################## # ############## ############## ################ ## ### #########

## #### #### ###### # ################# ############### ## ########### ########### # ############### ### ### ################# ###### ## ###### ##### ###### ########## ##### ############### ################### ## # ######### # #### #### # ######## ### ################### ############## ######## ######### ###### #####

## ##### ####### ## # ################### # ################# # ########## # ##### ### ##### ## #### # ## ### ########### ### #### ##### ####### ## ###### ## # ### ##### # ##### ## ## ###### #### ###### ###### ######


tional Solid State Circuits Conference, pp. 190–191, IEEE, Feb. 1983.

[12] M. J. Chambers and L. F. Linder, “A precision monolithic Sample-And-Hold for video An-alog-to-Digital converters,” inInternational Solid State Circuits Conference, pp. 168–169,IEEE, Feb. 1991.

[13] G. M. Gorman, J. B. Camou, A. K. Oki, B. K. Oyama, and M. E. Kim, “High performancesample-and-hold implemented with GaAs/AlGaAs heterojunction bipolar transistor tech-nology,” in International Electron Device Meeting, pp. 623–626, IEEE, Dec. 1987.

[14] K. Poulton, J. S. Kang, J. J. Corcoran, K.-C. Wang, P. M. Asbeck, M.-C. F. Chang, and G.Sullivan, “A 2 Gs/s HBT sample and hold,” inGaAs IC Symposium, pp. 199–202, IEEE,1988.

[15] J. Corcoran, K. Poulton, and T. Hornak, “A 1GHz 6b ADC system,” inInternational SolidState Circuits Conference, pp. 102–103, IEEE, Feb. 1987.

[16] K. Poulton, J. J. Corcoran, and T. Hornak, “A 1-GHz 6-bit ADC system,”IEEE Journal ofSolid State Circuits, vol. SC-22, pp. 962–970, Dec. 1987.

[17] B. Wong and K. Fawcett, “A precision dual bridge GaAs sample and hold,” inGaAs ICSymposium, pp. 87–90, IEEE, 1987.

[18] F. Thomas, F. Debrie, M. Gloanec, M. L. Paih, P. Martin, T. Nguyen, S. Ruggeri, and J.-M. Uro, “1-GHz GaAs ADC building blocks,”IEEE Journal of Solid State Circuits, vol.SC-24, pp. 223–228, Apr. 1989.

[19] K. R. Stafford, P. R. Gray, and R. A. Blanchard, “A complete monolithic Sample/Hold am-plifier,” IEEE Journal of Solid State Circuits, vol. SC-9, pp. 381–387, Dec. 1974.

[20] P. J. Lim and B. A. Wooley, “A high-speed sample-and-hold technique using a miller holdcapacitance,”IEEE Journal of Solid State Circuits, vol. SC-26, pp. 643–651, Apr. 1991.

[21] M. Nayebi, “A 10-bit video BiCMOS track-and-hold amplifier,”IEEE Journal of SolidState Circuits, vol. SC-24, pp. 1507–1516, Dec. 1989.

[22] P. Real and D. Mercer, “A 14b linear, 250ns sample-and-hold subsystem with self- correc-tion,” in International Solid State Circuits Conference, pp. 164–165, IEEE, Feb. 1991.

[23] P. Real, D. H. Robertson, C. W. Mangelsdorf, and T. L. Tewksbury, “A wide-band 10-b20-Ms/s pipelined ADC using current-mode signals,”IEEE Journal of Solid State Circuits,vol. SC-26, pp. 1103–1109, Aug. 1991.

[24] F. Moraveji, “A 14b, 150ns sample-and-hold amplifier with low hold step,” inInternation-al Solid State Circuits Conference, pp. 166–167, IEEE, Feb. 1991.

[25] F. Moraveji, “A high-speed current-multiplexed sample-and-hold amplifier with low holdstep,”IEEE Journal of Solid State Circuits, vol. SC-26, pp. 1800–1808, Dec. 1991.

[26] R. J. van de Plassche and H. J. Schouwennars, “A monolithic S/H amplifier for digital au-dio,” in International Solid State Circuits Conference, pp. 180–181, IEEE, Feb. 1983.

[27] R. J. van de Plassche and H. J. Schouwennars, “A monolithic high-speed sample-and-holdamplifier for digital audio,”IEEE Journal of Solid State Circuits, vol. SC-18, pp. 716–722,Dec. 1983.

[28] R. Petschacher, B. Zojer, B. Astegher, H. Jessner, and A. Lechner, “A 10-b 75-MSPS sub-ranging A/D converter with integrated sample and hold,”IEEE Journal of Solid State Cir-


cuits, vol. SC-25, pp. 1339–1346, Dec. 1990.

[29] P. H. Saul, “A GaAs MESFET sample and hold switch,”IEEE Journal of Solid State Cir-cuits, vol. SC-15, pp. 282–285, June 1980.

[30] R. Bayruns, N. Scheinberg, and R. Goyal, “An 8ns monolithic GaAs sample and hold am-plifier,” in International Solid State Circuits Conference, pp. 42–43, IEEE, Feb. 1987.




[34] K.-C. Wang, P. M. Asbeck, M.-C. F. Chang, D. L. Miller, G. J. Sullivan, J. J. Corcoran, andT. Hornak, “Heating effects on the accuracy of HBT voltage comparators,”IEEE Transac-tions on Electron Devices, vol. ED-34, pp. 1729–1735, Aug. 1987.

[35] K. Poulton, K. L. Knudsen, J. J. Corcoran, K.-C. Wang, R. L. Pierson, R. B. Nubling, andM.-C. F. Chang, “Thermal design and simulation of bipolar integrated circuits,”IEEEJournal of Solid State Circuits, vol. SC-27, pp. 1379–1387, Oct. 1992.

[36] R. C. Joy and E. S. Schlig, “Thermal properties of very fast transistors,”IEEE Transactionson Electron Devices, vol. ED-17, pp. 586–594, Aug. 1970.

[37] R. D. Lindsted and R. J. Surtry, “Steady–state junction temperatures of semiconductorchips,” IEEE Transactions on Electron Devices, vol. ED-19, pp. 41–44, Jan. 1972.

[38] T. C. Hill, III, “Differential amplifier with dynamic thermal balancing.” U.S. Patent Num-ber 4,528,516, July 1985.

Chapter 4

Coarse Quantizer

4.1 4-Bit Flash Quantizer

The topology of the coarse quantizer is based upon a flash converter (Fig. 4.1) with several

modifications to improve performance and reduce power dissipation. The basic flash A/D converter

architecture is well-suited for low resolution applications such as the 4-bit coarse quantizer

envisioned here, but does exhibit some characteristics which hinder performance of the 10-bit A/D

converter including: high input capacitance, threshold perturbations due to comparator input current

flowing through the resistive reference ladder, and high power dissipation. These drawbacks are

alleviated through two techniques, use of a differential reference ladder implementation and

interpolation between comparator pre-amplifiers. These methods are detailed in the next two sub-

sections.

4.1.1 Differential Reference Ladder

In a typical flash A/D converter such as that depicted in figure 4.1 input bias current flows

into each comparator of the array. This current flows through the resistive ladder thereby causing

voltage fluctuations which perturb the nominally equally-spaced reference voltages from their ideal

positions [1]. This well-known effect is called “reference bowing” because the reference voltages

vary from their ideal positions according to a parabolic or bowed pattern. A reference generation

218 Chapter 4 Coarse Quantizer

scheme which simultaneously eliminates the reference bowing problem and provides buffering to

reduce the capacitive loading presented by the comparator array relies on a differential signal being

applied to differential emitter followers with resistive loads (Fig. 4.2) [23]. Here, the emitter

followers provide buffering, however, the nodes at the bottom of the resistive ladders must be

charged through the full ladder resistance. The distributed nature of this loading places a practical

upper limit on the number of comparators which can be driven in this manner; however for the low

resolution coarse quantizer, this settling time is adequate.

Temporarily ignoring comparator bias currents, the comparator threshold occurs when

its differential input is zero which implies that

(4.1)

Figure 4.1. Flash or parallel A/D converter topology.


Logic

2 -1Comparators

N-Vref

+Vref Vin

ThermometerCode

kth

Vk VN k−=

4.1 4-Bit Flash Quantizer 219

The node voltages and can be defined in terms of the input voltage and the voltage drops

across the resistive ladder:

(4.2)

where is defined by . If , then equation 4.2 simplifies to

(4.3)

Figure 4.2. Differential reference ladder with comparators.

V0

V1

V2

VN 2−

VN 1−

VN

V0

V1

V2

VN 2−

VN 1−

VN

Vin

Vin

+-

+-

+-

+-

+-

+-

C0

C1

C2

CN 2−

CN 1−

CN

ILadder

ILadder

RTap

RTap

RTap

RTap

Q1

Q2

Vk VN k−

Vin VBE1 kVTap−− V− in VBE2 N k−( ) VTap−−=

VTap VTap ILadderR= VBE1 VBE2=

2Vin kVTap− N k−( ) VTap−=

2Vin 2k N−( ) VTap=

Vin k N 2⁄−( ) VTap=


The last line of equation 4.3 indicates that the value of at which the input to the comparator

equals zero is linearly proportional to as desired. To take into account the effects of comparator

input currents, consider the case if the comparator input is a differential pair. Then bias current flows

only into the comparator terminal with the higher applied potential except when both terminals are

at nearly the same voltage in which case the input bias current divides equally between the two

terminals. This situation is depicted in figure 4.3 where the comparator’s inputs are assumed

to be balanced, and the base currents are labelled accordingly. The effective threshold voltage for

Figure 4.3. Differential reference ladder showing comparator input biascurrents.

Vin kth

k

kth

V0

V1

V2

Vk 1−

Vk

Vk 1+

VN 2−

VN 1−

VN

V0

V1

V2

Vk 1−

Vk

Vk 1+

VN 2−

VN 1−

VN

Vin Vin

Ib

Ib

Ib

Ib

Ib 2⁄

Ib

Ib

Ib

Ib

Ib 2⁄

Q1 Q2

ILadder ILadder

RTap RTap

RTapRTap


the comparator can be determined by again writing the equation which defines that threshold:

(4.4)

which can be expanded in terms of the ladder variables and the comparator input bias current to give

(4.5)

If is again assumed to equal , then equation 4.5 becomes

(4.6)

The last line of this equation implies that the input voltage which defines the threshold

increases linearly with . The only difference between this result and that found for the simplified

case with no comparator currents (Eq. 4.3) is that the proportionality constant changed from

to . This fact implies that in the differential ladder scheme presented,

comparator input currents do not affect threshold linearity but merely increase the uniform spacing

between thresholds by the quantity . The symmetry of the differential scheme can be

better appreciated as depicted in figure 4.4 where the comparators tap diametrically opposed points

along the two ladders drawn along the perimeter of a circle.

4.1.2 Interpolation

The conventional flash architecture was modified for use with the coarse quantizer by

kth

Vk VN k−=

Vin VBE1 kVTap− RTapIb k p− 1 2⁄+( )p 1=

k

∑−− =

V−= in VBE2 N k−( ) VTap− RTapIb N k− p− 1 2⁄+( )p 1=

N k−

∑−−

VBE1 VBE2

2Vin 2k N−( ) VTap RTapIbk2

2N k−( ) 2

2−

+=

Vin kN2

−( ) VTap

RTapIb

4k2 N2 2Nk k2−+−( )+=

kN2

−( )= VTap

NRTapIb

2k

N2

−( )+

kN2

−( )= VTap

NRTapIb

2+( )

kth

k

VTap

VTap NRTapIb 2⁄+

NRTapIb 2⁄


employing interpolation between adjacent comparator pre-amplifiers to reduce power dissipation

and capacitive loading. The interpolation utilized combines outputs from adjacent differential

comparator pre-amplifiers (Fig. 4.5) to create a “virtual” threshold for a comparator where no pre-

Figure 4.4. Three dimensional depiction of differential reference ladder withcomparator connections.

Figure 4.5. Interpolation between preamplifiers reduces loading ondifferential reference ladder and reduces power by halving the number ofcomparator pre-amplifiers.

"0"

"1"C0 C1 C2

VinVA

VA VB

VB

2Rtap ladIActual

ThresholdsInterpolatedThreshold

VB

C0

C1

C2

VA

VB

VA

Preamps Comparators

V0

Vn

V2

Vn-2


amplifier differential input voltage equals zero [3], [4], [5]. This operation relies on the fact that the

preamplifier output transition from one polarity to the other occurs over some reasonable range of

input voltage. Otherwise, the interpolation would be ineffective. By using this interpolation

technique, the number of pre-amplifiers used in the coarse quantizer was reduced from 15 to 8. This

reduction minimizes power dissipation and reduces capacitive loading on the differential reference

ladder significantly. The differential ladder with interpolation can be visualized abstractly with the

aid of figure 4.6 where pre-amplifier connections to the reference ladder are drawn in black, and

virtual connections which are generated with interpolation are drawn in grey.

Figure 4.6. Differential reference ladder drawn to emphasize circularsymmetry, and including reference to interpolated thresholds in grey.

+Vin -Vin

V0

V2 V2

V0

Vn Vn

Vn-2 Vn-2


4.1.3 Layout and DAC Interface

The eight differential-pair pre-amplifiers are laid out in a linear array with the differential

ladder to their left (as oriented in figure 4.7). This array is most easily connected to the comparator

array by abutment, so the 15 comparators must pitch-align with the 8 preamplifiers, implying that

a high aspect-ratio is necessary for the comparator layout (Fig. 4.8). Each comparator cell also

includes a differential pair serving as a current switch of the segmented reconstruction DAC.

Locating the DAC current switches within the comparator cells greatly reduces wiring capacitance,

and the direct connection between the flash comparators and the current segment switches provides

for maximum switching speed by eliminating all intervening logic [6]. The complete coarse

quantizer with differential ladder, interpolating pre-amplifiers, and comparators with internal DAC

switches is shown in figure 4.9.

References

[1] A. G. F. Dingwall, “Monolithic expandable 6 bit 20 MHz CMOS/SOS A/D converter,”IEEE Journal of Solid State Circuits, vol. SC-14, pp. 926–932, Dec. 1979.


[3] C. Lane, “A 10-Bit 60 MSPS flash ADC,” inBipolar Circuits and Technology Meeting, pp.44–47, IEEE, Sept. 1989.

[4] C. W. Mangelsdorf, “Parallel analog-to-digital converter.” U.S. Patent Number 4,924,227,May 1990.


[6] T. Kamoto, Y. Akazawa, and M. Shinagawa, “An 8-Bit 2-ns monolithic DAC,”IEEE Jour-


nal of Solid State Circuits, vol. SC-23, pp. 142–146, Feb. 1988.

Figure 4.7. Coarse quantizer preamplifier array driven by differentialreference ladder.

xcqprear Size: 1128 x 465 microns

###########################

#

##

##

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#

#

#

#

#

#

#

#

#

################################

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######

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#

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##

####

##

##

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##

##

##

##

##

##

# ######

##

##

##

##

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####

####

#

#

#

#

#

#

#

###

###

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##

##

####

####

#

#

#

#

#

#

#

#

#

#

####

########

########

#

##

###

###################

#

##

#

#####

###

########

########

#########

##########

#####

####

#

###

#####

###

########

##

#

#

#

#

## ###


Figure 4.8. Coarse quantizer comparator with internal DAC current switch.

cqltc

hvo

S

ize:

64

x 45

8 m

icro

ns

### ######## ####### ### ##

##### ####### #### # #

# ###

## ##### ########

#


Figure 4.9. Coarse quantizer latch array with current segment inputs anddifferential DAC output.

ltchar Size: 1184 x 601 microns

###

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#################################

#################################

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##

###########

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###

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Chapter 5

Digital –to–Analog Converter and

Residue Amplifier

The digital-to-analog converter within the 10-bit ADC produces an analog signal

proportional to the digital output from the coarse quantizer suitable for subtraction from the ADC

input signal. Because a coarse replica of the input signal is reconstructed at the DAC output, the

internal D/A converter is frequently termed areconstruction DAC. The subtraction of the

reconstructed signal from the input occurs within theresidue amplifier generating a result which

is then processed by the fine quantizer to complete the digitization. To ensure adequate linearity of

the ADC, both the D/A converter and the residue amplifier must perform their respective functions

with linearity errors below one 10-bit LSB. Since errors in these two components form only a

fraction of the total error affecting A/D operation, actual DAC and residue amplifier errors must be

well below this level. In addition to these accuracy requirements, both components must operate

very rapidly while dissipating low power. The architecture and circuit implementations of the D/A

converter and residue amplifier are discussed in detail next.

5.1 Segmented Approach

The most important requirement for the reconstruction DAC is that its linearity be

commensurate with 10-bit operation. Additionally, the DAC delay-time, as measured from a change

230 Chapter 5 Digital–to–Analog Converter and Residue Amplifier

in its digital input until its analog output has settled adequately, must be minimized; especially since

in the unconventional timing arrangement employed (Figs. 2.15 and 2.16) the DAC must track

dynamically changing digital inputs. Since the coarse quantizer comparator bank generates a

thermometer code output, a DAC architecture which directly interfaces with this format is desirable.

Several architectures were investigated for suitability as reconstruction DACs given the

aforementioned considerations. The R-2-R ladder DAC [1], [2], perhaps the most commonly

implemented D/A converter architecture, provides a very efficient solution since only one current

source is required per bit. However, the R-2-R topology exhibits high sensitivity to resistor

mismatch and is therefore unsuitable for the present application. D/A converters employing

dynamic element matching techniques offer excellent linearity and intolerance to device

mismatches [3], [4], [5], [6], [7] but generally require high power supply voltages and large off-chip

decoupling elements. Neither of these special requirements can be supported in the present design

so dynamic matching methods were abandoned. Current copier techniques offer high accuracy and

potentially low power dissipation [8], [9], but require CMOS devices which are unavailable in the

semiconductor process used here. A fully-segmented DAC architecture provides very low

sensitivity to device mismatches [10], [11] along with the simplest possible interface to the

thermometer code output from the coarse quantizer and was therefore selected as the architecture

for the reconstruction DAC.

The segmented implementation of the reconstruction D/A converter exhibits 4-bit

resolution and so consists of 15 equally weighted current segments which are switched under

control of the thermometer code output from the coarse quantizer (Fig. 5.1). Each

segment current is set by a reference voltage driving the base of a twice minimum-size transistor

stabilized by a 400 mV degeneration voltage. The ballast resistance necessary to establish this

degeneration is implemented by an NiCr thin-film resistor with

sheet resistance. These resistors were designed to be very large to minimize

mismatches along the segment array [12]. The anticipated mismatch of such a resistor, , in

Tektronix’ SHPi process is approximately 0.1%, typical of many modern semiconductor processes

[13], [11], [10].

250µA

1600Ω 800µm 25µm×

50Ω ⁄

σR µR⁄

5.2 Effects of Mismatches 231

5.2 Effects of Mismatches

Current segment mismatches arise from both random and deterministic phenomena.

Deterministic errors are caused largely by asymmetrical layout of the current segments. For

example, if thermal gradients exist across the segment array the equivalence between the segment

currents will be destroyed. Likewise, if the current segments see unequal wiring resistance to

ground, individual currents will be perturbed. These types of errors must be addressed during layout

but are not considered further here. Three sources ofrandom error degrade segment matching:

mismatches in transistor saturation current (which also manifest themselves as mismatches

when devices carry equal currents), mismatches in transistor current gain, , and mismatches in

current source degeneration resistance. Straightforward analysis [14] indicates that for degeneration

voltages a few times larger than the thermal voltage, , or more, the mismatch in degeneration

resistance dominates the other error sources. Since this condition holds in the DAC designed here,

where the degeneration voltage is 400 mV, the relative current source mismatch is approximated by

Figure 5.1. Fully-segmented current-output reconstruction DAC.

1

10 3 14 7 5 12 1 8 15 4 11 9 2 13 6

2 3 4 5 6 7 8 9 10 11 12 13 14 15

IOut IOut

+400mV-

Thin Film(NiCr)

Resistors

µm25

Wiring Matrix

VRefA=2

µm800 Aµ250

1600 Ω

= .1%RRσ

VBE

β

VT


the relative degeneration resistor mismatch. That is , where represents the

segment current and the degeneration resistance.

The effect of current source mismatch errors on reconstruction DAC and A/D performance

can be assessed via Monte Carlo simulation wherein current segment values are selected from an

assumed random distribution, and the resultant DAC output levels or A/D thresholds are calculated.

Simulation of DAC linearity using this technique led to figure 5.2 which plots DAC yield (assuming

peak INL must be below 1/2 of a 10-bit LSB) versus the DAC current segment mismatch, .

This figure indicates that yield is virtually 100% for , and significant degradation

occurs for . A more pertinent measure of the impact of current segment mismatch

is its effect on A/D converter SNR shown in figure 5.3 along with ADC yield (assuming minimally

acceptable SNR is 59 dB). This figure indicates that SNR degradation is minimal when

and approaches 1 dB when . Therefore, the above simulations

Figure 5.2. 10-bit yield for a fully-segmented DAC with 4 bit resolution versuscurrent segment mismatch assuming maximum INL is 1/2 LSB.

σI µI⁄ σR µR⁄≈ I

R

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Current Segment Mismatch (%)

0

10

20

30

40

50

60

70

80

90

100

Yie

ld (

%)

Resolution = 4 bitsPeak INL = 1/2 10-bit LSBNumber of Samples = 200

σI µI⁄

σI µI 0.2%<⁄

σI µI 0.3%≥⁄

σI µI 0.1%<⁄ σI µI 0.2= %⁄

5.2 Effects of Mismatches 233

indicate that DAC current source mismatches should not degrade A/D converter SNR significantly

since the resistor matching expected from the Tektronix process is quite good,

. However, the preceding simulations assume erroneously that segment

errors are uncorrelated with each other. In reality, a strong spatial correlation exists among resistors,

implying that if one resistor deviates from the norm, neighboring resistors tend to do so in the same

fashion [11]. Such spatial correlation degrades DAC INL from predicted levels. To counteract this

Figure 5.3. 10 bit A/D converter yield (upper) and mean SNR (lower) versussegmented DAC current source mismatch for both 4-7 and 5-6 partitioning.

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0DAC Current Source Matching (%)

54

55

56

57

58

59

60

61

62

Mea

n S

NR

(d

B)

0

10

20

30

40

50

60

70

80

90

100

AD

C Y

ield

at

59 d

B (

%)

n1=4n2=7

n1=5n2=6

n1=4n2=7

n1=5n2=6

σI µI⁄ σR µR⁄≈ 0.1%=


phenomenon, a wiring matrix added between the DAC current sources and the current switches

(Fig. 5.1) “randomizes” the apparent location of current segments by ensuring that physically

proximate segments are not connected to current switches which are located near to each other. An

optimum ordering for this scrambling procedure was developed by Conroy [11]. Others have

devised scrambling sequences to cancel the effects of current source errors where the mismatches

are assumed to follow a linear or quadratic function of distance from the array center [15], [16],

[17], [18], [19], [20], but the technique proposed by Conroy gives superior results and was used

here. When the current segments are thus scrambled, the Monte Carlo analysis described earlier

accurately predicts DAC and A/D converter performance degradation due to current segment errors.

Therefore, random errors afflicting current source values such that should not

significantly degrade the SNR of the 10-bit A/D converter.

5.3 Layout Considerations

To combat the potential deleterious effects of unforeseen deterministic errors such as

thermal gradients, three versions of the DAC array were implemented (and consequently three

versions of the A/D converter). The first layout of the DAC current segments (Fig. 5.4) corresponds

to the arrangement just described. The connections from the DAC switch array located in the coarse

quantizer enter the layout at the top left in sequential order, and as can be seen are connected to the

individual current segments in an apparent haphazard ordering. This ordering is actually the

optimum arrangement for removing spatial correlations alluded to earlier. The lines at the top left

of the layout connect seamlessly to those in the layout of the coarse quantizer (Fig. 4.9 at top right).

The second DAC current segment layout is intended to cancel linear thermal gradients

across the array. Therefore, two identical current source arrays (each with one half the required

current) are connected in parallel and physically arranged so that the centroid of each pair of sources

connected in parallel is located at the center of the array. Therefore, if the current segments are

numbered sequentially from 1 to 15, and the two sub-arrays are designated A and B such that

sources 1A and 1B are electrically connected in parallel, then moving from one end of the joint array

to the other, the sources encountered are . In the

layout of this current source array (Fig. 5.5), the wiring matrix also enters at the top left and

scrambles the effective locations of the sources to minimize the effects of spatial correlation.

The third DAC current source array is identical electrically to the first, but the degeneration

σI µI 0.1= %⁄

1A,15B,2A,14B,…,14A,2B,15A,1B

5.3 Layout Considerations 235

resistors are larger and include special tabs to facilitate laser trimming if necessary. The overall size

of the array (Fig. 5.6) is significantly larger than the nominal array and indicates the area penalty

paid to enable laser trimming of resistors [21], [22], [23].

Figure 5.4. Segmented DAC current source array with scrambled wiringmatrix at top.

dacarray Size: 668 x 1192 microns

#

#############

###########

##

#

#####

#

##

#

###

##

#

##

#

#####

#

###

###

##

#

###

##

#

##

#

##

#

##

#

##

###########################


5.4 Residue Amplifier

The purpose of the residue amplifier is to subtract the analog output of the reconstruction

Figure 5.5. Segmented DAC current source array with common centroidlayout.

dacar32 Size: 916 x 1152 microns

#

############

###################

#

####

#

####

#

#####

####

#

#########

#

####

#

#####

####

#

####

#

#########

#

#####

#####

####

#

#####

####

#

####

#

#####

####

#

#####

#####

####

#

#########

#

####

#

#####

####

#

####

#

#########

#

#####

####

#

####

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####

#

##################

#######################################

5.4 Residue Amplifier 237

DAC from the held signal out of the input T/H. To ensure very fast settling, this operation must be

performed with an open-loop circuit which achieves the requisite linearity. Since the reconstruction

DAC generates a current output, and since current-mode subtraction is inherently fast, it is desirable

to convert the T/H output signal from a voltage to a current before subtraction. A typical circuit for

performing the required transconductance and current-mode subtraction (Fig. 5.7a) relies upon a

linear transconductance operation followed by straightforward subtraction of the two current

signals. In this method, the transconductance operation must exhibit linearity commensurate with

Figure 5.6. Segmented DAC current source array with trimmable layout.

dactrim Size: 1236 x 1356 microns

#

###########

##############

#

######

###

#####

#

###

#####

#

########

#

######

##

#

##

#

##

#

###

##########################


10-bit operation. An improved technique (Fig. 5.7b) subtracts the signal currents at the emitters of

the transconductance amplifier taking advantage of the reduced dynamic range of the signal at this

location. Because the current subtraction takes place in the degeneration resistor of the

transconductance stage, the signal current modulating the of the input transistors is reduced

by a factor of 16 compared to the previous case. This reduction occurs because the DAC output

current is a close approximation to the transconductance current resulting in a current waveform

similar to that shown in figure 5.7c. The reduction in dynamic range reduces distortion significantly

since according to equations 3.52 and 3.53, is proportional to the signal amplitude, and

is proportional to the square of the signal amplitude. Therefore, the improved residue amplifier

reduces compared to the conventional case by , and the by a

dramatic . In addition to the improved linearity offered by the new approach,

Figure 5.7. Residue amplifier implementations. (a) Typical approach usingtransconductance cell and subtracting currents at output. (b) Improvedapproach subtracting currents at transconductor emitter.

DAC

+Vout-

+Vin -Vin+Vin -VinDAC

+Vout-

Vin

Vout

Coarse quantizer Thresholds

Residue Waveform(a) (b)

(c)

VBE

HD2 HD3

HD2 20 16log 24dB= HD3

20 162log 48dB=


the power dissipation is reduced compared to the conventional topology since the bias current of

the DAC is also used by the transconductance stage. By selecting the load resistors of the residue

amplifier to be twice the value of the degeneration resistor a gain of 4 is achieved along with the

subtraction operation. The physical implementation of the residue amplifier is shown in figure 5.8.

References

[1] D. J. Dooley, “A complete monolithic 10-b D/A converter,”IEEE Journal of Solid StateCircuits, vol. SC-8, pp. 404–408, Dec. 1973.

[2] B. E. Amazeen, P. R. Holloway, and D. A. Mercer, “A complete single-supply micropro-cessor-compatible 8-bit DAC,”IEEE Journal of Solid State Circuits, vol. SC-15, pp. 1059–

Figure 5.8. Residue amplifier and its replicas.

resa

mpa

r

Siz

e: 5

42 x

382

mic

rons

## ## ## ## ##### ##### ####### ## ##### ## ## ###### ###### ####### ########## ####### ####### ####### ######## #### ######## ############# ########### ############## ###### ###### ######## ############# ###### ######### ####### ######### ####### ###### ###### #### ## #### ## ## #### #### # ###### ## ##### ############# ############


1070, Dec. 1980.

[3] R. J. van de Plassche, “Dynamic element matching for high-accuracy monolithic D/A con-verters,”IEEE Journal of Solid State Circuits, vol. SC-11, pp. 795–800, Dec. 1976.

[4] R. J. van de Plassche and D. Goedhart, “A monolithic 14 bit D/A converter,”IEEE Journalof Solid State Circuits, vol. SC-14, pp. 552–556, June 1979.

[5] R. J. van de Plassche and H. J. Schouwennars, “A monolithic 14 bit A/D converter,”IEEEJournal of Solid State Circuits, vol. SC-17, pp. 1112–1117, Dec. 1982.

[6] E. C. Kwong, G. L. Baldwin, and T. Hornak, “A frequency-ratio-based 12-bit MOS preci-sion binary current source,”IEEE Journal of Solid State Circuits, vol. SC-19, pp. 1029–1037, Dec. 1984.

[7] H. J. Schouwenaars, E. C. Dijkmans, B. M. J. Kup, and E. J. M. van Tuijl, “A monolithicdual 16-bit D/A converter,”IEEE Journal of Solid State Circuits, vol. SC-21, pp. 424–429,June 1986.

[8] H. J. Schouwenaars, D. W. J. Groeneveld, and H. A. H. Termeer, “A low-power stereo 16-bit CMOS D/A converter for digital audio,”IEEE Journal of Solid State Circuits, vol. SC-23, pp. 1290–1297, Dec. 1988.

[9] D. W. J. Groeneveld, H. J. Schouwenaars, H. A. H. Termeer, and C. A. A. Bastiaansen, “Aself-calibration technique for monolithic high-resolution D/A converters,”IEEE Journal ofSolid State Circuits, vol. SC-24, pp. 1517–1522, Dec. 1989.

[10] J. A. Schoeff, “An inherently monotonic 12 bit DAC,”IEEE Journal of Solid State Circuits,vol. SC-14, pp. 904–911, Dec. 1979.

[11] C. S. G. Conroy, W. A. Lane, and M. A. Moran, “Statistical design techniques for D/A con-verters,”IEEE Journal of Solid State Circuits, vol. SC-24, pp. 1118–1128, Aug. 1989.

[12] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOStransistors,”IEEE Journal of Solid State Circuits, vol. SC-24, pp. 1453–1440, Oct. 1989.

[13] G. Kelson, H. H. Stellrecht, and D. S. Perloff, “A monolithic 10-b digital-to-analog con-verter using ion implantation,”IEEE Journal of Solid State Circuits, vol. SC-8, pp. 396–403, Dec. 1973.

[14] P. R. Gray and R. G. Meyer,Analysis and Design of Analog Integrated Circuits. JohnWiley and Sons, second ed., 1984.

[15] P. H. Saul and J. S. Urquhart, “Techniques and technology for high-speed D-A conver-sion,” IEEE Journal of Solid State Circuits, vol. SC-19, pp. 62–68, Feb. 1984.

[16] T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, “An 80MHz 8bCMOS D/A converter,” inInternational Solid State Circuits Conference, pp. 132–133,IEEE, Feb. 1986.

[17] T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, “An 80-MHz 8-bit CMOS D/A converter,”IEEE Journal of Solid State Circuits, vol. SC-21, pp. 983–988,Dec. 1986.

[18] Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, “A 10-b 70-MS/s CMOSD/A converter,” in1990 Symposium on VLSI Circuits Digest of Technical Papers, pp. 57–58, IEEE, 1990.


[19] Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, “A 10-b 70-MS/s CMOSD/A converter,”IEEE Journal of Solid State Circuits, vol. SC-26, pp. 637–642, Apr. 1991.

[20] F. G. Weiss, “A 1 Gs/s GaAS DAC with on-chip current sources,” inGaAs IC Symposium,pp. 217–220, IEEE, 1986.

[21] J. J. Price, “A passive laser-trimming technique to improve linearity of a 10-bit D/A con-verter,” IEEE Journal of Solid State Circuits, vol. SC-11, pp. 789–794, Dec. 1976.

[22] K. Kato, T. Ono, and Y. Amemiya, “A monolithic 14 bit D/A converter fabricated with anew trimming technique (DOT),”IEEE Journal of Solid State Circuits, vol. SC-19, pp.802–807, Oct. 1988.

[23] J. Shier, “A finite-mesh technique for laser trimming of thin-film resistors,”IEEE Journalof Solid State Circuits, vol. SC-23, pp. 1005–1009, Aug. 1988.

Chapter 6

Folding Fine Quantizer

6.1 Concept of Folding

As described in chapter 2, a feedforward multi-stage A/D converter gains efficiency by

partitioning an quantization into a number of lower-resolution quantizations. In such a

converter (Fig. 6.1a) an coarse quantizer digitizes the input signal with low resolution, and

applies the resultant codeword to a reconstruction DAC. The analog output of the DAC is then

subtracted from the original input to form a residue signal (Fig. 6.1b) which is quantized by an

fine quantizer. The advantage of this approach arises because the combined complexity of

the coarse quantizer and the fine quantizer can be far less than the complexity of a

single quantizer. The object of a folding quantizer is to form the residue signal with simple

analog circuits thereby obviating the need for the coarse quantizer, DAC, and subtracter

components of figure 6.1a. In such an implementation (Fig. 6.2), the low dynamic-range residue

signal generated by the analog folding circuit directly drives the fine quantizer. Because of the

periodic nature of the residue signal; however, the digitized output from the fine quantizer is

ambiguous, and a coarse quantizer is still necessary to ascertain in which period of the folding

circuit’s transfer characteristic the quantizer input signal lies. The input-output characteristic of the

analog folding circuit can be parameterized by the number of piece-wise linear segments, orfolds,

which it contains. This parameter, abbreviated , determines the resolution of both the coarse and

N-bit

n1-bit

n2-bit

n1-bit n2-bit

N-bit

F

244 Chapter 6 Folding Fine Quantizer

fine quantizers required in a folding A/D converter (Fig. 6.3). Since the coarse quantizer requires

Figure 6.1. Architecture of feedforward quantizer.

Figure 6.2. Folding A/D converter architecture. Analog folding with F folds

reduces fine quantizer resolution to .

DACADC

ADCVin Residue

N1Coarse

Bits

N2FineBits

Vin

Residue

2N1

Coarse Quantizer Thresholds 2N2

Fin

e T

hres

hold

s

(a)

(b)

Analog Folding Circuitwith F Folds

Vout

Vin

DigitalEncoder

Vout

Vin

Coarse Quantizer(F Thresholds)

Fin

e Q

uan

tize

r(2

/F T

hre

sho

lds)

N

MSB’s

LSB’s

N-bitOutput

2N F⁄

F

6.1 Concept of Folding 245

thresholds, its resolution is while the fine quantizer requires thresholds so its

resolution is .

6.1.1 Linear Folding Circuits

Folding A/D converters based on the architecture of figure 6.2 would be possible if simple

analog circuits could easily realize the piece-wise linear input-output characteristics indicated.

However, because of the discontinuities in the folding transfer function, these types of

characteristics are inherently difficult to realize. Several implementations have been developed

which approximate the triangle wave folding characteristic of figure 6.3, but each has significant

drawbacks. For example, the circuit of figure 6.4 [1], [2] based on the translinear principle, offers a

near ideal approximation to a triangle wave folding characteristic. However, the differential input

voltage varies by 2 diode drops for each fold within the transfer function. So if eight folds are

desired, the differential input voltage range is . This voltage swing

is unacceptably large for the low-power, high-frequency application considered here. A second

folding circuit which approximates the ideal triangle wave depicted in figure 6.3 is shown in figure

6.5 [3]. This topology also approximates the triangle waveform quite well, but also suffers from the

Figure 6.3. Reduction in dynamic range seen be comparator array for (a)sawtooth and (b) triangle folding characteristics.

FlashConverter

FoldingConverter

0

0A/D Input Signal

VFS/F

VFS

VFS

N2 /FThresholds

2Thresholds

N

Fold2

Fold F

Fold F-1

Fold 1

ComparatorArray Input

SignalFlash

Converter

FoldingConverter

0

0A/D Input Signal

VFS/F

VFS

VFS

N2 /FThresholds

2Thresholds

N

Fold2

Fold F

Fold F-1

Fold 1

(a) (b)

n1 log2= F 2N F⁄

n2 log2 2N F⁄( ) N n1−= =

16 VD× 16 0.7×≈ 11.2V=


large input swing requirement which plagued the first circuit. In addition, this implementation

exhibits a large common mode output current upon which the differential output current is

superimposed. In practical applications with limited power supply voltages, this common-mode

component could prove problematic. Generally, circuits with discontinuous input-output

characteristics are difficult to realize and are not amenable to high-speed applications. Therefore,

folding converters which do not rely upon piece-wise linear folding functions prevail.

Figure 6.4. Translinear-based current-mode folding circuit.

12

34

I

-I

α

Iout Iout-

I I I I I

Iout

Iout

(4-α)IαI

6.2 Sinusoidal Folding 247

6.2 Sinusoidal Folding

A folding A/D converter based upon a periodic, butnot piece-wise linear folding function

can be developed if the non-linear function is well behaved which in this context means that the

characteristic is periodic and does not saturate [4], [5]. A sinusoidal folding function (Fig. 6.6)

serves as an apt example. In this case, the folding characteristic resembles the triangle-wave

depicted in figure 6.3b; however, the output signal from the folding circuit is not a linear function

of the input. Therefore, the fine quantizer must contain thresholds which are not uniformly spaced,

but which are located according to an inverse-sine law. This threshold placement would be very

difficult to achieve in practice, but a simple alternative lies in generating many sinusoids, uniformly

shifted in phase with respect to each other (Fig 6.7). In this arrangement, the fine quantizer consists

of an array of comparators, each with its reference input grounded so that the quantizer thresholds

correspond to the zero-crossings of the sinusoids. Since the sinusoids are equally-spaced in phase,

their zero-crossings are equally-spaced along the analog input range, and the quantizer thresholds

are located correctly. Generating the phase-shifted waveforms with an array of sinusoidal folding

Figure 6.5. Current-mode folding circuit using cascodes.

I

I out I out

IIII

4I 4I

Iα (4- α)Ι

1

2

3

4

I

-I

α

Iout Iout-


circuits would be very inefficient, but a simplification of the scheme depicted in figure 6.7 obviates

the need for this type of redundancy. Instead, only two quadrature sinusoids are generated, and the

remaining signals are obtained by linear superposition between the first two. A simple technique for

Figure 6.6. A folding function which is not piece-wise linear. The transferfunction shown is sinusoidal for convenience but could be any non-saturating,periodic function.

Figure 6.7. An array of phase-shifted, non-linear folding blocks withcomparators detecting zero-crossings can circumvent the need for an inverse-sine quantizer.

Coarse Quantizer

DigitalEncoder

Inve

rse-

Sin

eF

ine

Qu

anti

zer

Vin

VoutSinusoidal Folding Circuit

Vout

Vin

Dig

ital

En

cod

er

Vin Θ = 90/Ν

Θ = 90Quadrature

Θ = 0In-Phase


achieving the superposition utilizes resistive interpolation (Fig. 6.8). By appropriately selecting the

interpolation resistors, any desirable phase angle, , can be generated. The folding quantizer

architecture presented in figure 6.8 is simple and potentially very efficient; however, practical

circuits must be available to generate the two quadrature sinusoids, and the interpolation scheme

must be easily implemented and robust. These two issues are discussed in the following sections.

6.2.2 Sinusoidal Folding Circuits

Several circuits with sinusoidal transfer functions were investigated for suitability in

folding quantizers. The first such circuit considered (Fig. 6.9) [1], is based on the translinear

principle and offers the advantages of simplicity and low common-mode output current for a given

differential output. However, as in the case with the previous translinear-based folding circuits, the

voltage drive required to obtain an input-output characteristics with 8 folds (or equivalently 4

periods) is on the order of 5 V. This voltage swing is not compatible with the quantizer being

designed here. Therefore, the circuit of figure 6.9 was rejected. A modification of this folding circuit

requires a differential current drive rather than a differential voltage drive (Fig. 6.10) [2], but still

demands a very large voltage swing at its input to generate several folds. A different approach which

does not require large voltage drive (because it is not a translinear circuit) is depicted in figure 6.11

Figure 6.8. Linear superposition implements non-uniform interpolation togenerate multiple sinusoids equally-spaced in phase from two quadraturesinusoids.

Vin

Θ = 90Quadrature

Θ = 0In-Phase

Dig

ital

En

cod

er

90/Ν

Θ = 0

Θ = 90

Inte

rpo

lati

on

I

Q

γ

γ


[6], [7]. This circuit relies on the hyperbolic tangent transfer function of a voltage driven bipolar

differential pair to approximate a sinusoid. By selecting the voltage separation between the

references , , , and appropriately, a good approximation to a sinusoid may be made

over a few periods. An appropriate voltage separation is a few times the thermal voltage, , so the

total input voltage swing is on the order of 1 V for an 8-fold circuit, an acceptable value. The circuit

of figure 6.11 suffers some important drawbacks. The input is single-ended so, as in the case of the

flash coarse quantizer from chapter 4, bias currents flowing into the folding circuit’s differential

pairs will perturb the apparent reference voltages thereby distorting the desired shape of the

sinusoid. Additionally, the output current from the folding circuit consists of a large common-mode

component with only a small differential component. Therefore, operation under limited power

supply voltage ranges poses biasing problems. Lastly, if many folds are desired, mandating many

differential pairs in the folding circuit, then the capacitive loading on the output node becomes large

adversely affecting settling time. Some of these drawbacks are overcome by the circuit of figure

6.12 [24], [9], [10], [12], [12], [13] which uses a wired-OR configuration at the differential pair

Figure 6.9. Translinear sinusoidal folding circuit with voltage drive.

I I I I I

I out

I out

Vin+ Vin-R RRR

I E

2 4 6 8

-2-4-6-8

I E

I E-

Vin+ Vin--IR

IncreasingIR

I out I out-

V1 V2 V3 V4

VT


outputs to reduce the common-mode output signal and to provide buffering. This circuit still suffers

from the threshold perturbing effects of a single-ended reference scheme. To eliminate this error

source, the sinusoidal folding circuit of figure 6.13 was developed. This circuit incorporates a

differential reference ladder identical to that described in chapter 4 [14], [23], [13], [16]. Therefore,

errors due to input bias current flowing through the resistive reference ladder and into the

differential pairs comprising the folding circuit are eliminated. Cascode devices are employed to

reduce the impedance at the common collector node loaded by significant device capacitance, and

de-bias resistors connected from the cascode emitters to the positive supply absorb most of the bias

current drawn by the differential pairs in the folding circuit. Owing to the low input impedance of

the cascode devices, only a small amount of signal current flows into the de-bias resistors.

Therefore, the output signal has a large differential-mode component and a small common-mode

component as desired. Two extra differential pairs are added to the folding circuit at the extremes

to ensure that each of the 9 remaining pairs in the circuit experience symmetric effects from nearest-

neighbor differential pairs. This technique maintains the fidelity of the sinusoid at the extremes of

Figure 6.10. Translinear sinusoidal folding circuit with current drive.

I out

I out

R 0.7RR0.7R

2R 2.4R 3.4R 2.4R 2R

IE

(1- α)IIα

IncreasingIR

1/4 1/2 3/4 1 α

I out I out-

IE

-IE


the input range. Notice that the phase of the resulting waveform can be controlled by shifting the

positions along the reference ladder to which the folding circuit connects. In this way, a second

folding circuit whose output is in quadrature with the first can easily be constructed. A significant

drawback of this folding circuit is its dependence on temperature. Since the gain of the differential

pairs within the circuit vary with temperature, and since the output waveform is not an exact

sinusoid but an approximation to one, the shape of the output waveform will change slightly with

temperature. This changing shape introduces errors into the resulting quantizer transfer function

which will be discussed in detail in the next sub-section.

Figure 6.11. Folding circuit based upon hyperbolic tangent transfer functionof voltage driven differential pairs.

Vout

Vin

IRL

-IR L

V1 V2 V3 V4

Vin

V V VV1 V2 V3 V4

I I I I

RLRL

-Vout

+

6.3 Non-uniform Interpolation 253

6.3 Non-uniform Interpolation

Figure 6.12. Folding circuit based on wired-OR interconnection.

Figure 6.13. Fully-differential sinusoidal folding circuit with differentialreference ladder, overflow compensation, and common-mode de-bias circuitry.

Vout

Vin

IRL

-IR L

V1 V2 V3 V4

Vin

V V VV1 V2 V3 V4

I II II I

RL RL RL RL RL

- Vout+

Rt Rt Rt Rt Rt Rt Rt Rt Rt

Vin+

Im

Rt Rt Rt Rt Rt Rt Rt Rt Rt

Vin-

Im

Rt

Rt

Rl

Ip Ip Ip Ip Ip IpIp Ip Ip Ip

Rl

+Vout-

Ip

Vout

1 2 3 4 5 6 7-1-2-3-4-5-6-7

IpRl

-IpRl

Vin+ - Vin-Im Rt


The interpolation scheme depicted in figure 6.8 is conceptually straightforward and can be

implemented with a simple resistive ladder as depicted in figure 6.14. Here differential emitter

followers buffer the quadrature signals output by the two folding circuits discussed above. The

quadrature waveforms are termed the In-phase signal and the Quadrature signal and are therefore

labelled I and Q in the schematic. The interpolation ladder is redrawn along with a phasor diagram

and plots of interpolated waveforms in figure 6.15 to emphasize the analogous representations. Note

the similarity, both physical and conceptual, between the electrical representation and the phasor

representation.

Comparator differential inputs connect to points diametrically opposed on the resistive

ring. Also, the symmetry of this configuration reduces the effects of distortion in the emitter

follower buffers. When , so that signal current flows from the node, through the

interpolation ring and into the node, but the voltages at and remain unperturbed so that no

Figure 6.14. Differential non-uniform interpolation ladder generatessinusoids equally spaced in phase from quadrature inputs. Distortion isminimized due to symmetry of circuit enabling use of simple, low-power emitterfollower buffers.

I

Q

I

Q

R1R2

R1R2R1

R2

R2

R1

R1

R2R2R1

R2

R2

R1

V6V5

V4

V3

V2

V1

I I= Q Q−= Q

Q I I

6.3 Non-uniform Interpolation 255

threshold variation results. Similarly, when , then so that signal current flowing from

the node equals that flowing from the node, and signal current flowing to the node equals that

flowing to the node. Therefore, resultant modulation in the emitter follower buffers cancels

and, again, no threshold perturbation results.

The resistor values required to obtain interpolated sinusoids equally-spaced in phase from

two quadrature waveforms can be found by simple trigonometric identities. The resistor spread

necessary is about 2:1, and sensitivity of ADC threshold placement to resistor errors is quite low.

When temperature is varied, the shape of the incoming quadrature signals changes leading to

threshold error. Simulations of this effect shown in figure 6.16 indicate that threshold errors are

nearly non-existent at room temperature as desired, but increase for both temperature extremes.

Maximum threshold error occurs when temperature is -55°C reaching a magnitude of

approximately 6% of an 8-bit LSB.

Figure 6.15. (a) Differential non-uniform interpolation ladder. (b) Phasorrepresentation of quadrature and interpolated signals. (c) Correspondingvoltage waveforms.

VFS-VFS

VIn

VOut

0

Q

V1

V2V3V4

V5

V6

Iθ

θθθθθ

θθ

I

I

Q

I

Q

R1R2

R1R2R1

R2

R2

R1

R1

R2R2R1

R2

R2

R1

V6V5

V4

V3

V2

V1

(a) (b)

(c)

I Q= I Q=

I Q I

Q VBE


6.4 Folding and Interpolating A/D Converter

The components required to implement the folding quantizer block diagram depicted in

figure 6.8 have been demonstrated; however, several additional functions must be added to form a

useful circuit. Figure 6.17 includes all necessary circuitry for a 7-bit folding quantizer. The input

signal (assumed differential) drives a differential reference ladder attached to two folding circuits

which generate quadrature differential sinusoidal outputs called I and Q. These signals are applied

via emitter follower buffers across a differential non-uniform interpolation ladder to generate an

array of equally phase-shifted sinusoids. The array of sinusoids must be digitized and encoded.

Additionally, a coarse quantizer must determine within which fold of the sinusoidal transfer

characteristic the input signal lies. The coarse quantizer is sometimes called a cycle-pointer because

it identifies which cycle of the folding characteristic the input signal occupies.

In the block diagram of figure 6.17, as in all folding A/D converters, the number of

Figure 6.16. Threshold error at interpolated thresholds.

0 16 32Interpolation Position

-8

-6

-4

-2

0

2

4

6

8D

NL

(%

of

8-B

it L

SB

) T=125T=100T=75T=50T=25T=0T=-25T=-55

6.4 Folding and Interpolating A/D Converter 257

thresholds, , is determined by

(6.1)

where is the number of folding circuits, is the number of folds in each folded waveform, and

is the interpolation factor. In the present design, since only the I and Q folding circuits

are used, which is a practical limit for low voltage-swing converters, and which is

required so that .

6.4.1 Encoding

The novel encoding technique used for this converter greatly reduces the complexity of the

necessary encoding circuitry (Fig. 6.18). Rather than drive comparators directly, the outputs from

the interpolation ladder are encoded in the analog domain before digitization. This encoding most

naturally maps to Gray code, wherein each decreasingly significant bit transitions at twice the rate

of its predecessor (Fig. 6.18, right side). In the present encoding scheme, this relationship is

produced by multiplying two quadrature signals which transition at the rate of the predecessor bit

(recall that the product of 2 quadrature sinusoids is a third sinusoid at twice the frequency). The

result is a simple encoding tree composed of multiplier elements: analog multiplier encoders and

digital Exclusive-OR gates. In fact, the analog encoders are very simple multiplier circuits identical

to Exclusive-OR gates. The latching comparators define the transition boundary across which

encoded analog signals become digital logic levels.

Figure 6.17. Folding, interpolating, and analog encoding fine quantizer usingquadrature folded waveforms.

SinewaveGenerators

DifferentialReference

Ladder(16 taps)

DigitalEncoding& Error

Correction

I

Q

Vin

DigitalOutput(7 Bits)

AnalogEncoding

andComparators

(5 Bits)

Cycle-Pointing CoarseQuantizer (3 Bits)

Folds perSinewave

TimesInterpolation

NonuniformDifferential

8XInterpolation

Ladder

X X2 8 8 = 128 7= 2

2N

2N AFI=

A F

I A 2=F 8= I 8=

AFI 128 27= =


6.4.2 Cycle Pointer (Coarse Quantizer)

The coarse quantizer output is in Gray code, for compatibility with the Gray-coded fine

quantizer, and also to minimize encoding errors caused by comparator metastability. Analog

encoders, simplified versions of folding amplifiers [17], [18], [19], [20], [21], [22], [23], produce

this Gray code (Fig. 6.19) by comparing the analog input with appropriate reference voltages.

Outputs from these analog processing blocks are digitized generating Gray code directly with no

other intervening logic.

6.4.3 Layout

The layout of the analog portion of the folding 7-bit quantizer (Fig. 6.20) includes the

differential reference ladder, the folding amplifiers, interpolation ladder, and analog multipliers

from the encoding block. This portion of the chip is approximately .

Figure 6.18. Improved encoding scheme significantly reduces hardwarecomplexity. All circuits are differential but are shown single-ended for simplicity.

NonuniformInterpolation

Ladder

R1

R2

R3

R4

R1

R2

R3

R4

R1

R2

R3

R4

R1

R2

R3

R4

Digital Encoding

BIT 5

BIT 4

BIT 3

BIT 2

ComparatorsAnalog

MultiplierEncoders

II QQBIT 1

Gray CodedOutput Waveforms

1100µm 1100µm×


References

[1] B. Gilbert, “Monolithic analog READ-ONLY memory for character generation,”IEEEJournal of Solid State Circuits, vol. SC-6, pp. 45–55, Feb. 1971.

[2] B. Gilbert, “A monolithic microsystem for analog synthesis of trigonometric functions andtheir inverses,”IEEE Journal of Solid State Circuits, vol. SC-17, pp. 1179–1191, Dec.1982.





[7] R. E. J. van de Grift and R. J. van de Plassche, “A monolithic 8-bit video A/D converter,”

Figure 6.19. Cycle pointer incorporating analog encoding. Actual circuit isdifferential but is shown single-ended for simplicity.

Vin

- Vout+1

+_

Vin

Vout

EVBV

2

_

Vin

Vout+

AV VVC VVD VVF

3

Input

Gray CodeDigitalOutput

MSB

MSB-1

MSB-2

MSB-3

VA BV CV

DV EV FV

out

In

1

VA BV CV

DV EV FV

out

In

2

VA BV CV

DV EV FV

out

In

3

VA BV CV

DV EV FV

out

In

4


IEEE Journal of Solid State Circuits, vol. SC-19, pp. 374–378, June 1984.




[11] R. J. van de Plassche and P. Baltus, “An 8-bit 100-MHz full Nyquist analog-to-digital con-

Figure 6.20. Layout of fine quantizer analog circuitry including differentialreference ladder, folding amplifiers, interpolation ladder, and analog multipliersfrom the encoding block.

xfqf

end

S

ize:

113

2 x

1113

mic

rons

############################ ############## ################### ############# ############## ##### ########################################## ##### ################################## ############## ############## #######

####### ########### #### ####### ############## ########### ################## ####### #######

##################### ##############

############################# ################################

################################ ################################ # #### ####

# # ##### # ######## # ####### ####

# ##### ######## ############

############

# ##########

###############################

############################

###############################

##### ########### ####################### ##

#########################

#####

### ######## ## ########## ########## ######### ############ # #############################

########################################## #####

##### ### ## ######

####

#

####### ######## ###### #

###### ## #

## #### ##### ##### ## #### # ##### ####

###### ######## ## ###### ### ##

# #### ##### ##

#

##### ##### ####

#### #### ######

#

###

###

#

# ### # #### ###### ##### ######### ##### ### #########

### ###


verter,” IEEE Journal of Solid State Circuits, vol. SC-23, pp. 1334–1344, Dec. 1988.



[14] L. M. Devito, “High-speed voltage-to-frequency converter.” U.S. Patent Number4,839,653, June 1989.



[17] J. J. Corcoran, K. L. Knudsen, D. R. Hiller, and P. W. Clark, “A 400MHz 6b ADC,” inIn-ternational Solid State Circuits Conference, pp. 294–295, IEEE, Feb. 1984.

[18] A. P. Brokaw, “Parallel analog-to-digital converter.” U.S. Patent Number 4,270,118, May1981.

[19] T. W. Henry and M. P. Morgenthaler, “Direct flash analog-to-digital converter and meth-od.” U.S. Patent Number 4,386,339, May 1983.


[21] C. W. Mangelsdorf and A. P. Brokaw, “Integrated circuit analog-to-digital converter.” U.S.Patent Number 4,596,976, June 1986.

[22] P. A. Reiling, “Translating circuits.” U.S. Patent Number 2,922,151, Jan. 1960.

[23] P. A. Reiling, “Analog-to-digital converter.” U.S. Patent Number 3,573,798, Apr. 1971.

Chapter 7

Gain Stabilization

7.1 Gain Matching Requirements

Gain mismatch among the 10-bit ADC components leads to threshold errors in the A/D

converter transfer function [1], [21], [3], [4], [5]. These errors are most easily quantified by their

effect on SNR according to equation 1.109. However, component gain errors also give rise to

distortion, since the threshold disturbances they cause are not random, but deterministic functions

of analog input voltage. As mentioned in section 10.2, a useful area of inquiry lies in determining

analytic expressions for ADC distortion in terms of pertinent gain mismatch factors.

Three component gain errors are considered: coarse quantizer gain error, DAC gain error,

and fine quantizer gain error. All other gain errors can be expressed as equivalent values of these

three. Variations in coarse quantizer gain from the ideal value cause equivalent variations in the

ADC gain, but do not degrade linearity. DAC gain errors cause the residue waveform to exceed the

input range of the fine quantizer for extreme values of input voltage (Fig. 7.1a). Such errors in the

residue waveform manifest themselves as SNR degradation. This effect, described in chapter 2 and

repeated here for convenience (Fig. 7.2), becomes excessive for DAC gain errors greater than about

1% in magnitude for the 4,7 partitioning used here. Fine quantizer gain errors cause periodic

disturbances of the A/D converter thresholds (Fig. 7.1b) which degrade linearity. Therefore, fine

quantizer gain error must also be limited to about 1% before SNR diminishes significantly (Fig.

264 Chapter 7 Gain Stabilization

7.3).

Figure 7.1. Effects of component gain errors on A/D transfer function. (a)Effect of fine quantizer gain error. (b) Effect of DAC gain error.

ReconstrucedA/D Output

Vin0

VfsVfs/2Vfs/4 3Vfs/4

Vfs/4

Vfs/2

3Vfs/4

Vfs

Ideal Waveform

A/D Output withIncorrect 2nd Quantizer

Full-Scale Range

VinVfsVfs/2Vfs/4

0

DAC gaintoo high

DAC gaintoo low

CorrectDAC Gain

Residue = VDAC

- Vin

3Vfs/4

V1 V2

Opamp ensuresV1=V2

Nominal Input Rangeto 2nd Quantizer

Segment10

Segment15

(a)

(b)

7.2 Gain Control 265

7.2 Gain Control

To avoid the errors described above, the full-scale range of the reconstruction DAC must

match the full-scale range of the input signal; and the residue, after amplification, must align with

the full-scale range of the fine quantizer. These gains are matched to one another using on-chip

replica circuits (Fig. 7.4) [20], [7], [23], [9]. An externally supplied reference voltage equal to the

Figure 7.2. 10 bit A/D converter SNR (upper) and gain error (lower) versusDAC gain error for both 4-7 and 5-6 partitioning.

-10 -8 -6 -4 -2 0 2 4 6 8 10DAC Gain Error (%)

-10

-5

0

5

10

AD

C G

ain

Err

or

(%)

44

46

48

50

52

54

56

58

60

62

SN

R (

dB

)

n1=4n2=7

n1=5n2=6

n1=5n2=6

n1=4n2=7


full-scale range of the input drives a scaled replica of the coarse quantizer differential reference

ladder, and an op-amp forces the DC voltage across both the replica and the main ladders to match

this reference. Similarly, the full-scale reference voltage and an attenuated version drive two scaled

replicas of the residue amplifier biased by two scaled DAC replicas set the specific thermometer

codes 111 and 011. (The scaling factor used here is 1:5 so the replica DAC settings correspond to

all 15 segments on and 10-of-15 segments on respectively.) A second op-amp controls the segment

currents in the replica and main DAC to align two peaks along the sawtooth residue characteristic

Figure 7.3. 10 bit A/D converter SNR (upper) and gain error (lower) versusfine quantizer gain error for both 4-7 and 5-6 partitioning.

-10 -8 -6 -4 -2 0 2 4 6 8 10Fine Quantizer Gain Error (%)

-0.05

-0.04

-0.03

-0.02

-0.01

0.00

0.01

0.02

0.03

0.04

0.05

AD

C G

ain

Err

or

(%)

44

46

48

50

52

54

56

58

60

62

SN

R (

dB

)

n1=4n2=7

n1=5n2=6

n1=5n2=6

n1=4n2=7

7.2 Gain Control 267

(voltages V1 and V2 in figure 7.1a). Thus, the DAC full-scale range aligns with the first quantizer

full-scale range. The output of one replica residue amplifier also supplies the reference level to a

replica of the second quantizer ladder. The second quantizer gain is controlled by a third op-amp

loop identical to that controlling the first quantizer gain. All three op-amps, which operate at DC in

the replica circuits, are off-chip.

References


[2] S. H. Lewis and P. R. Gray, “A pipelined 5-Msample/s 9-bit analog-to-digital converter,”

Figure 7.4. Gain-matching replica circuits and feedback loops which adjustcomponent gains.

+Vfs

-VfsScaledS/H 2

Replica

DACSegmentCurrents

HardwiredDAC Switch

"1 1 1"

4

Coarse QuantizerGain Loop

Reconstruction DACGain Loop

Fine QuantizerGain Loop

FirstQuantizer

Ladder

SecondQuantizer

Ladder

HardwiredDAC Switch

"0 1 1"


IEEE Journal of Solid State Circuits, vol. SC-22, pp. 954–961, Dec. 1987.








Chapter 8

Performance

Three versions of the 10-bit A/D converter differing exclusively in the layout of the

reconstruction DAC were fabricated in the Tektronix SHPi process. Each chip occupies the same

area and uses identical pad locations to facilitate testing. The performance of these chips is

discussed next. A separate 8-bit A/D converter based upon the 7-bit fine quantizer of chapter 6 was

also fabricated. Performance of the 8-bit device is discussed in chapter 9.

8.1 Circuit Layout

Because low complexity quantizers comprise the A/D converter, each chip incorporates

less than 2500 transistors and even fewer resistors so that the silicon area occupied is approximately

, or equivalently (Fig 8.1). The 4-bit coarse quantizer, DAC

current switches, and encoding logic (including the Coarse Ladder, Coarse Latches & DAC

Switches, Delay Stage, Correction MUX, and Coarse ROM as labelled in figure 8.1) occupy about

the same area as the 7-bit fine quantizer and its encoding logic (Folding Amps, Cycle Pointer, Fine

Encoding, and Error Correction in figure 8.1), thus confirming the original premise by which

conversion was partitioned between the two stages (see section 2.3.2 and figure 2.17). The input and

interstage T/H circuits are located at the top of the chip along with the residue amplifier. These are

the most sensitive analog components in the A/D converter and are therefore intentionally located

as far away as possible from digital components and from the output buffers. The coarse quantizer

4mm 4mm× 160mil 160mil×

270 Chapter 8 Performance

is on the left side of the chip with the fine quantizer on the right. The reconstruction DAC occupies

the center of the die in all 3 implementations, and the output buffers fill the bottom of the layout.

The 10-bit output word from the converter is Gray coded and includes one extra bit to indicate an

overflow or underflow condition. Each output latch switches a differential pair which drives

complementary open-emitter transistors. These output devices can be terminated off-chip by

differential ECL receivers. Thus, the on-chip output drivers are compatible with standard ECL logic

levels as are the sample-clock inputs. The analog input circuitry provides 50Ω termination resistors

from both complementary input nodes to ground and accepts ground-centered signals.

Figure 8.1. 10-bit A/D converter with constituent components highlighted.Die size is approximately 4 mm X 4 mm (160 mil X 160 mil). Analog input is attop, left of chip. Digital outputs are at bottom.

Error Correction

DAC

Coarse Latches& DAC Switches

Coarse ROM

Output Buffers

FoldingAmps

DelayStage

CoarseLadder

CyclePointer

4288mm

Res AmpT/H 1

T/H 2

Correction MUX

FineEncoding

4064µm

8.1 Circuit Layout 271

The version of the A/D converter utilizing the nominal DAC layout (Fig. 8.2) includes

significant unused silicon surrounding the DAC degeneration resistors (as shown in figure 8.1, the

DAC occupies the center portion of the circuit). This area is reserved to accommodate the larger

DAC layouts from other versions of the ADC chip. In the version of the converter using a common-

centroid reconstruction DAC (Fig. 8.3) this area is nearly filled, and in the version incorporating a

trimmable DAC (Fig. 8.4) the area is completely utilized. In fact, the excessively large size of

trimmable resistors is a significant impediment to their widespread use. Since the die-size and pad

Figure 8.2. Die photograph of 10-bit A/D converter with nominal DAC layout.Unused area surrounding DAC degeneration resistors is reserved for use inother ADC versions.


locations are identical for all versions of the converter chip, packaging and testing techniques were

also consistent among the different versions. Each chip has 100 pads, but many are used solely to

monitor internal bias voltages during testing with custom wafer probes. Therefore, the chips were

bonded in standard ceramic 68-pin leaded chip-carrier (LCC) packages. The three versions of the

10-bit converter shared a common reticle along with the 8-bit converter so that only one mask set

was required to fabricate all four circuits. No JFETs or PNP bipolar devices are included on any of

the four chips ensuring that the circuit design and layout are applicable to generally available silicon

bipolar processes.

Figure 8.3. Die photograph of 10-bit A/D converter with common centroidreconstruction DAC layout.

8.2 Test Methodology 273

8.2 Test Methodology

The A/D converter chips were tested by supplying sinusoidal input signals and ECL

compatible clocks to the device under test (DUT) and capturing the resultant digital output data in

high-speed memory for later evaluation by computer. The test set-up used for this purpose (Fig. 8.5)

supplies low-noise, sinusoidal analog input signals which are appropriately filtered to reduce

harmonics and which are phase-locked to low-noise, fast rise-time sample clocks. Passive phase-

splitters generate differential analog input signals in response to the single-ended versions

emanating from the frequency synthesizers. Digital data is captured in high-speed memory and later

downloaded to a laboratory computer for analysis. Additionally, a high-speed, 10-bit DAC

Figure 8.4. Die photograph of 10-bit A/D converter with trimmablereconstruction DAC layout.


reconstructs the digitized signal for analysis with an oscilloscope and spectrum analyzer. The test

set-up, a photograph of which appears in figure 8.6, also includes computer-controlled power

supplies and voltmeters to monitor bias voltages and power dissipation. Both probed wafers and

packaged parts were tested using this set-up. To facilitate testing of many devices, a fixture with a

low insertion-force socket was used when evaluating parts housed in the 68-pin ceramic packages

described above.

Several well-known analysis techniques enable characterization of A/D converter dynamic

performance from collections of digital output data taken from the DUT in response to known input

signals. In particular, performing the Fast Fourier Transform (FFT) on digitized waveforms

generates the ADC’s digital output spectrum from which SNR, SFDR, and THD can be ascertained

[1], [2], [3], [4]. Additionally, calculating histograms from large sets of output data generated in

response to input signals with known probability density functions enables determination of the

ADC’s dynamic integral and differential linearity error (INL and DNL) [1], [2]. Alternatively, INL

Figure 8.5. A/D converter test setup. All synthesizers are phase-locked toone master synthesizer. Pulse generator supplies ECL clock signal to DUTupon trigger from low phase-noise synthesized source. Four pulse generatorsare used to supply clocks to DUT, but only one is shown for simplicity. Off-chipreconstruction DAC is helpful for real-time debugging of system. Digitized datais captured in fast, deep memory and analyzed on workstation off-line.

Σ

Oscilloscope

SpectrumAnalyzer

HP 8662Freq. Synth.

HP 8662Freq. Synth.

HP 8662Freq. Synth.

ColbyPG5000

Pulse Gen.

BPF 10-BitDAC

Tek 9503Fast Data

Cache

PowerSupplies

Clock

AnalogInput

10 M

Hz

Ref

eren

ce

10

GPIB Control

Workstation

DUT

8.2 Test Methodology 275

and DNL can be calculated from measurements of the actual ADC threshold levels. Such

measurements are best performed with the aid of a hardware tracking loop which encloses the A/D

converter within a feedback loop to perform an integrated (and hence low-noise) measurement of

the particular threshold level in question [1], [5]. These analysis techniques allow calculation of

ADC dynamic performance without the intervention of a potentially error-prone reconstruction

DAC and were utilized to characterize the ADCs described here. The reconstruction DAC in the

test set-up above generates qualitative information for debugging and trouble-shooting, and does

not affect the accuracy of the performance data tabulated below.

Figure 8.6. A/D converter test setup. Synthesizers, pulse generators,spectrum analyzer, and filter bank are housed in rack on left. High-speedmemory and workstation are on right. Power supplies, oscilloscopes, and testfixtures are on bench in rear.


8.3 Test Results

Approximately 70 die sites were probed and 15 packaged parts tested for each of the three

ADC versions. The probed die sites were all located on one wafer, and the packaged parts were

taken from a second wafer. No significant difference in performance was noted between the three

versions so distinctions among the three circuits will no longer be made. About 70% of the circuits

tested exhibit the nominal performance described here. The ADC dissipates 800 mW from +5 V

and –5 V power supplies, excluding off-chip ECL supplies which bias the output devices. The +5 V

power supply is required only for the two T/H circuits. Although the converters performed

reasonably well at or beyond 100 Msps, reliable data could only be obtained at 75 Msps, and all of

the data reported below pertains to that sample-rate.

Spectral analysis of digitized sinewaves using 8192 point FFTs and Hamming window

filtering indicates dynamic performance consistent with 10-bit operation (Figs. 8.9 through 8.7). For

Figure 8.7. Digital output spectrum from A/D converter when sampling a5.87 MHz sinusoidal input at 75 Msps.

0 5 10 15 20 25 30 35 40Frequency (MHz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

Rel

ativ

e A

mpl

itude

(dB

c)

fin = 5.87 MHz

fs = 75 Msps

FFT block size = 8192

S/(N+D) = 59 dB

SFDR = -77 dBc

8.3 Test Results 277

a 5.87 MHz differential, full-scale input sinusoid converted at 75 Msps, the ratio of signal power to

all other power in the output spectrum, the so-called signal-to-noise-plus-distortion or S/(N+D), is

59 dB. Also, the spurious-free dynamic range (SFDR), specified by the highest spurious signal level

relative to the fundamental, is nearly . The spectra from figures 8.9 through 8.7 correspond

to three different ADCs operating at the frequencies specified above. All three devices give similar

S/(N+D), approximately 59 dB, which closely approaches the theoretical limit for a 10-bit ADC,

62 dB. The SFDR is about in all three cases. This figure falls short of the ideal for a 10-

bit converter, , but compares very favorably to the distortion performance reported

for other 10-bit converters extant.

When the analog input frequency is increased toward the target Nyquist rate of 50 MHz,

distortion increases as expected (Fig. 8.10). For a 49.6 MHz full-scale input and a 75 Msps

conversion rate, the S/(N+D) degrades only slightly to 56 dB while the SFDR, dominated by the

3rd harmonic, degrades to . The first several harmonics, although rearranged in position


0 5 10 15 20 25 30 35 40Frequency (MHz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

Rel

ativ

e A

mpl

itude

(dB

c)fin = 5.87 MHz

fs = 75 Msps


S/(N+D) = 59 dB

SFDR = -76 dBc

3fin

2fin

80dBc−

77dBc−

9N− 90dB−=

62dBc−


due to the effects of aliasing, are clearly visible above the noise floor in the spectrum plotted in

figure 8.10. The 3rd harmonic is dominant as mentioned, followed by the 2nd harmonic located at

. Other low-order harmonics are discernible but are near . The degraded

S/(N+D), 56 dB, is still greater than 9 effective bits and at 50 MHz surpasses the performance of

any known monolithic 10-bit ADC regardless of power dissipation. Likewise, the decreased SFDR

at 50 MHz nonetheless represents a significant improvement in achievable performance over any

10-bit A/D converter reported to date.

Integral linearity error (ILE) and differential linearity error (DLE), also known as integral

non-linearity (INL) and differential non-linearity (DNL) respectively can be calculated from

histograms of ADC output data in response to signals with know probability density functions [1],

[2]. By using this histogram method on data collected from the ADC when digitizing a 5.87 MHz

sinusoid at 75 Msps the DNL and INL plotted in figures 8.11 and 8.12 respectively result. Peak

DNL is less than 1/2 LSB and is for most thresholds below 0.2 LSB. The root-mean-square (rms)


0 5 10 15 20 25 30 35 40Frequency (MHz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0R

elat

ive

Am

plitu

de (

dBc)

fin = 5.87 MHz

fs = 75 Msps


S/(N+D) = 59 dB

SFDR = -75 dBc

3fin

2fin

69dBc− 80dBc−


DNL is approximately 0.1 LSB. Both of these figures are consistent with 10-bit linearity and

indicate that the nonuniform interpolation scheme used to eliminate threshold errors in the fine

quantizer works effectively as does the interstage gain-matching approach. Peak INL is below

3/4 LSB and for most thresholds is less than 1/2 LSB. Again, this uniformity of threshold placement

confirms the validity of the design techniques invoked to attain 10-bit operation with very low

complexity and power dissipation.

When the input frequency is increased from 5.87 MHz to 49.6 MHz, the threshold

uniformity degrades slightly. Plots of the DNL and INL calculated from the histogram technique at

this frequency are shown in figures 8.13 and 8.14 respectively. Peak DNL is still well below

1/2 LSB, and rms DNL is virtually unchanged from the 5.87 MHz case. INL no longer remains

below 3/4 LSB, extending to 0.8 LSB for a very few codes. This phenomenon is probably caused

by T/H distortion since the location of the ADC thresholds is independent of the analog input

frequency.


0 5 10 15 20 25 30 35 40Frequency (MHz)

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

Rel

ativ

e A

mpl

itude

(dB

c)fin = 49.6 MHz

fs = 75 Msps


S/(N+D) = 56 dB

SFDR = -62 dBc

5f 4f

2f

7f8f

3f

6f9f


A stringent test on A/D converter operation, called a beat-frequency test, entails driving the

T/H with an analog input frequency close to 1/2 the sample rate. Under these conditions, the input

signal traverses across the maximum number of thresholds between successive samples. Therefore,

signal slew-rates within the circuit are maximized resulting in greater distortion than in other modes

of operation. By applying the digital output from the A/D converter to a reconstruction DAC, the

resultant signal can be displayed on an oscilloscope exposing any signs of faulty operation such as

missing codes. A beat frequency test performed on this ADC operating at 75 Msps and with the

analog input set to 37.501 MHz results in the oscilloscope waveform depicted in figure 8.15. To

obtain this image, the output data stream from the ADC was decimated by 2 before being applied

to the reconstruction DAC. This operation is necessary because otherwise an envelope signal will

be displayed. Such an envelope results under near-Nyquist conditions because the A/D converter

will sample a sinusoid peak of one polarity, followed on the successive sample by a sinusoid peak

of the opposite polarity. For this reason, a test like that described here is sometimes called an

envelope test. When decimating by 2, every other sample is removed from the data stream so that

Figure 8.11. Differential linearity as measured by a histogram test withfin = 6MHz and fs = 75Msps.

0 .1 .2 .3 .4 .5 .6 .7 .8 .9 1 1.1Threshold Number (X1000)

-.5

-.4

-.3

-.2

-.1

0

.1

.2

.3

.4

.5T

hres

hold

Err

or (

LSB

's)


successive samples produce adjacent voltages. Note that the frequency difference from Nyquist,

that is , gives the frequency of the resultant waveform. The waveform shown in figure

8.15 shows no signs of distortion or missing codes even under the stressful conditions selected. The

fidelity of the beat frequency waveform implies that the T/H circuit can adequately track high-

frequency inputs without distortion due to slewing effects, and that the quantizer can adequately

track a voltage transition equal to its full-scale-range in one sample period.

Figure 8.12. Integral linearity as measured by a histogram test withfin = 5.87MHz and fs = 75Msps.


-1

-.8

-.6

-.4

-.2

0

.2

.4

.6

.8

1

Thr

esho

ld E

rror

(LS

B's

)

fin fS 2⁄−


Figure 8.13. Differential linearity as measured by a histogram test withfin = 49.6 MHz and fs = 75 Msps.


-.5

-.4

-.3

-.2

-.1

0

.1

.2

.3

.4

.5T

hres

hold

Err

or (

LSB

's)


Figure 8.14. Integral linearity as measured by a histogram test withfin = 5.87 MHz and fs = 75 Msps.


-1

-.8

-.6

-.4

-.2

0

.2

.4

.6

.8

1

Thr

esho

ld E

rror

(LS

B's

)


References

[1] Hewlett Packard,Dynamic Performance Testing of A–to–D Converters. Product Note5180A–2.

[2] J. Doernberg, H. Lee, and D. A. Hodges, “Full-speed testing of A/D converters,”IEEEJournal of Solid State Circuits, vol. SC-19, pp. 820–827, Dec. 1984.

[3] G. Pretzl, “Dynamic testing of high-speed A/D converters,”IEEE Journal of Solid StateCircuits, vol. SC-13, pp. 368–371, June 1978.

[4] T. E. Linnenbrink, “Effective bits: Is that all there is?,”IEEE Transactions on Instrumen-tation and Measurement, vol. IM-33, pp. 184–187, Mar. 1984.

[5] J. J. Corcoran, T. Hornak, and P. B. Skov, “A high-resolution error plotter for analog-to-digital converters,”IEEE Transactions on Instrumentation and Measurement, vol. IM-24,pp. 370–374, Dec. 1975.

Figure 8.15. Beat frequency test. fS = 75 Msps, fin = 37.501 MHz. ADCoutput is decimated by 2 then applied to reconstruction DAC and displayed onoscilloscope.

Chapter 9

8–Bit A/D Converter

The fine quantizer from the 10-bit ADC incorporates folding, interpolation, and analog

encoding to achieve efficient, high-speed operation. This building-block, suitably modified, forms

the quantizer of the 8-bit A/D converter described here. The input T/H from the 10-bit ADC

precedes this quantizer to ensure accurate digitization of dynamic signals. A brief description

detailing the architecture of this composite A/D appears next, followed by discussion of the

converter’s measured performance.

9.1 Architecture

Since the 8-bit ADC (Fig. 9.1) derives from its 7-bit predecessor (Fig. 6.17), the two

architectures share most features, differing in only two aspects. First, the 8-bit ADC features a T/H

to capture dynamic signals, and second, its interpolation factor is doubled (as is the complexity of

succeeding stages), thereby increasing the converter‘s resolution by one bit. The resolution, , of

the converter derives from

(9.1)

where is the number of folding amplifiers used, is the number of folds per sinewave, and is

the interpolation factor. For the 8-bit quantizer implemented, , , and ;

N

2N A F I××=

A F I

A 2= F 8= I 16=

286 Chapter 9 8–Bit A/D Converter

therefore,

(9.2)

as expected. The increased interpolation factor, , compared to the 7-bit case roughly doubles the

number of comparators necessary along with the complexity of the succeeding logic. Whereas the

differential reference ladder and folding amplifiers are identical among the two quantizers (owing

to the fact that and are equal), the die photograph (Fig. 9.2) indicates that the analog and digital

encoding banks are twice the size of those in the 7-bit quantizer (see figures 6.20 for comparison).

Even with this increase in complexity, the A/D chip still requires only 21 comparators: 17 to digitize

the interpolated sinusoids and 4 to form the cycle pointer. These components are visible when the

overlaid text is removed from the die photograph (Fig. 9.3). The entire converter utilizes only

approximately 1000 transistors and the fabricated die occupies about

( ).

Figure 9.1. 8-bit A/D converter architecture. T/H derives from input T/H in10-bit ADC. Quantizer is based upon 7-bit fine quantizer, also from 10-bitconverter.

SinewaveGenerators

DifferentialReference

Ladder(16 taps)

DigitalEncoding

& ErrorCorrection

I

Q

Vin

DigitalOutput(8 Bits)

Cycle-Pointing CoarseQuantizer (3 Bits)

Folds perSinewave

TimesInterpolation

X X2 8 16 = 256

AnalogEncoding

andComparators

(6 Bits)

NonuniformDifferential

16XInterpolation

Ladder

8= 2

T/H

A F I×× 2 8 16×× 256 28= = =

I

A F

3mm 3mm×120mils 120mils×

9.2 Performance 287

9.2 Performance

The 8-bit converter chips were tested using the same set-up and algorithms as the 10-bit

A/D. Different wafer probe cards and test fixtures were necessary to accommodate the smaller die

size and number of pads required for the 8-bit chip. Again, approximately 70 die sites were probed

and 15 packaged parts tested. The ADC dissipates 550 mW from +5 V and –5 V supplies, but only

the input T/H circuit requires the positive supply voltage. As in the 10-bit converter, digital inputs

and outputs are compatible with ECL logic levels, while the analog input provides 50Ω

terminations for a ground-centered differential signal.

Figure 9.2. 8-bit A/D converter with overlays to indicate location ofconstituent components.

Interpolation Ring

Output Buffers

Analog Encoding

Digital Encoding

Error Correction

T/H

CoarseQuantizer

DifferentialLadder &Folding

Amplifiers

3152mm

3056mm


FFT analysis of digital output data provides the corresponding spectrum generated by the

A/D converter. This output spectrum can be evaluated to ascertain SNR and harmonic distortion.

When performed over an array of input and sample frequencies, such analysis completely

characterizes ADC performance. FFT analysis on digitized data from the 8-bit converter generated

the plots of SNR and harmonic distortion shown in figures 9.4 through 9.11 below. This data covers

sample rates from 25 Msps to 200 Msps along with input frequencies from 1.5 MHz to the Nyquist

rate. Each plot includes measurements for nominal power supply voltages and for power supply

variations of +7% and –7%. The data contained in these curves should be compared to ideal

performance for an 8-bit quantizer which includes:

Figure 9.3. Die photograph of 8-bit A/D converter.

9.2 Performance 289

(9.3)

and

(9.4)

At 25 Msps (Fig. 9.4) SNR is near 48 dB for the nominal and high power supply voltages at input

frequencies below 20 MHz. Above this frequency, SNR degrades to 45 dB at 40 MHz. For the same

power supply values, harmonic distortion as specified by SFDR, varies between –58 dBc and –

Figure 9.4. Measured SNR and harmonic distortion versus input frequencyat 25 Msps.

SNR 6.02N 1.76dB+=6.02= 8× 1.76dB+50= dB

SFDR 9NdBc−=9 8dBc×−=72dBc−=

1 10 100Input Frequency (MHz)

20

25

30

35

40

45

50

SN

R (

dB

)


-65

-60

-55

-50

-45

-40

-35

Harm

on

ic Disto

rtion

(dB

c)

Nominal Power Supplies +7% Power Supplies-7% Power Supplies

FS=25Msps


62 dBc. This measured SNR and SFDR compares favorably with the ideal values specified in

equations 9.3 and 9.4 respectively. At power supply values 7% below nominal, both the measured

SNR and the measured SFDR are degraded significantly. This phenomenon is probably caused by

droop effects which are more pronounced at the 25 MHz sample rate than at the higher frequencies

for which the T/H was optimized. Improved performance at 50 Msps (Fig. 9.5) supports this

assertion. At this higher sample rate, performance is virtually independent of power supply showing

a gradual roll-off in SNR above 20 MHz input frequency to 40 dB at 80 MHz. Over this input

frequency range, SFDR increases from –60 dBc to –50dBc. These performance figures for low

input frequencies are excellent, indicating that the quantizer architecture operates with adequate

linearity. The degradation in SNR and SFDR at modest input frequencies implies, however, that the

T/H circuit cannot deliver adequate dynamic linearity to sustain the fidelity achievable by the

quantizer. Increasing the sample rate to 100 Msps reveals sensitivity to power supply voltage (Fig.

9.6). At this sample rate, SNR and SFDR are almost identical to those recorded at 50 Msps with the



20

25

30

35

40

45

50

SN

R (

dB

)


-65

-60

-55

-50

-45

-40

-35

Harm

on

ic Disto

rtion

(dB

c)


FS=50Msps

9.2 Performance 291

exception of data corresponding to –7% supply voltages which degrades very rapidly at 20 MHz

input frequency. Because this performance change is dependent upon input frequency, its cause

probably lies within the T/H circuit. SNR and SFDR continually degrade as sample rate is

increased. Figures 9.7 through 9.10 show SNR and SFDR for the sample rates 125 Msps, 150 Msps,

175 Msps, and 200 Msps respectively. This data indicates that dynamic linearity continues to

degrade with increasing sample rate at input frequencies above 10 MHz for all power supply values.

Linearity at low input frequencies remains unaffected until 175 Msps at which point SNR drops by

about 1 dB compared to lower sample-rate data. SNR is 46 dB (45 dB for –7% power supply

values) at 200 Msps, but dynamic linearity drops off severely.

The effect of substrate temperature on linearity can be seen in figures 9.11 and 9.12 which

plot SNR and SFDR versus input frequency for 200 Msps operation at –40°C and 125°C

respectively. SNR corresponding to 200 Msps and –40°C at low input frequency is about 45 dB,

but drops rapidly with increasing frequency. SNR taken at 200 Msps and 125°C is 38 dB at low

input frequency and also declines rapidly with input frequency. Clearly these extremes of

temperature and sample rate stress the converter beyond its limits for delivering linearity near that



20

25

30

35

40

45

50

SN

R (

dB

)


-65

-60

-55

-50

-45

-40

-35H

armo

nic D

istortio

n (d

Bc)


FS=100Msps


attainable with an ideal quantizer. Operation at low input frequencies and at sample rates below

175 Msps does, however, deliver adequate performance for most applications.

A summary of dynamic performance for sample rates from 100 Msps to 200 Msps is

depicted in figure 9.13 which plots SNR versus analog input frequency. All plots in this figure

correspond to room temperature operation with nominal power supply values. The data follows the

trend alluded to above: excellent SNR at low input frequencies rolling off quite steeply when input

frequency increases above about 10 MHz. This behavior is largely independent of sample rate with

200 Msps operation delivering performance only slightly worse than that at 100 Msps. These

symptoms are consistent with the hypothesis that the input T/H circuitry limits high-speed

performance.

Performance at low input frequencies was further quantified by measuring the threshold

voltages of the converter using a comparator feedback loop like that described in section 8.2. This

accurate, DC measurement led to the plots of peak and rms integral linearity error (or INL) included



20

25

30

35

40

45

50S

NR

(d

B)


-65

-60

-55

-50

-45

-40

-35

Harm

on

ic Disto

rtion

(dB

c)


FS=125Msps

9.2 Performance 293

in figure 9.14 which correspond to varying conditions of temperature and power supply voltage.

From room temperature to –40°C rms threshold errors remain below 25% of an LSB independent

of power supply voltages (within % of nominal) and peak threshold errors are below about 60%

LSB. Wen temperature increases to 125°C, rms INL increases to about 38% LSB, and peak INL

rises to 95% LSB. The DC values of INL for room temperature and below are adequate for many

applications and demonstrate the feasibility of achieving 8-bit A/D converter operation using the

folding architecture investigated here. Excessive threshold errors at high temperature represent a

deviation from simulated behavior worthy of further investigation.



20

25

30

35

40

45

50

SN

R (

dB

)


-65

-60

-55

-50

-45

-40

-35H

armo

nic D

istortio

n (d

Bc)


FS=150Msps

7±




20

25

30

35

40

45

50S

NR

(d

B)


-65

-60

-55

-50

-45

-40

-35

Harm

on

ic Disto

rtion

(dB

c)


FS=175Msps

9.2 Performance 295



20

25

30

35

40

45

50

SN

R (

dB

)


-65

-60

-55

-50

-45

-40

-35H

armo

nic D

istortio

n (d

Bc)


FS=200Msps


Figure 9.11. Measured SNR and harmonic distortion versus input frequencyat 200 Msps with T = -40 C.


20

25

30

35

40

45

50S

NR

(d

B)


-65

-60

-55

-50

-45

-40

-35

Harm

on

ic Disto

rtion

(dB

c)


FS=200Msps

T=-40C

9.2 Performance 297



25

30

35

40

45

SN

R (

dB

)


-55

-50

-45

-40

-35H

armo

nic D

istortio

n (d

Bc)


FS=200Msps T = 125C


Figure 9.13. Measured SNR versus input frequency at several sample rates.


20

25

30

35

40

45

50S

NR

(d

B)

FS=100Msps FS=125MspsFS=150MspsFS=175MspsFS=200Msps

9.2 Performance 299

Figure 9.14. Measured integral linearity error versus power supply variationat several temperatures with fS = 100 Msps. Upper curves plot peak INL. Lowercurves plot RMS INL.

-10 -8 -6 -4 -2 0 2 4 6 8 10Power Supply Variation (%)

0

20

40

60

80

100

Lin

eari

ty E

rro

r (%

of

LS

B)

T = 125 C T = 25 CT = -40 C

RMS Error

Peak Error

Chapter 10

Conclusions and Suggested

Further Research

10.1Conclusions

A 10-bit, untrimmed, silicon bipolar analog-to-digital converter was developed which is

capable of operation at over 75 Msps. When digitizing a 6 MHz sinusoid at this sample rate, the

resultant SNR is 59 dB and the SFDR is –77 dBc. For a 50 MHz input the SNR drops to 56 dB and

the SFDR decreases to –63 dBc. The measured peak INL is less than 3/4 LSB, and the peak DNL

is less than 1/2 LSB. The chip dissipates 800 mW from +5 V and –5 V supplies and incorporates

2500 transistors on a die which measures ( ).

The ADC utilizes a pipelined feedforward topology with a 4-bit flash coarse quantizer and

a 7-bit folding fine quantizer allowing 1 bit of redundancy for digital error correction. The coarse

quantizer output is converted back to the analog domain using a 4-bit fully-segmented DAC and

then subtracted from the held input signal. Dynamic signals are captured by an input T/H, and

pipelined operation is facilitated by an inter-stage T/H. Both of these circuits employ diode-bridge

switches. The fine quantizer utilizes an innovative folding architecture, shared by a companion 8-

bit A/D converter chip, to achieve high-speed, low-power operation. All circuits, including the ECL

compatible clock inputs and digital outputs, are differential in the ADC chip which utilizes only


302 Chapter 10 Conclusions and Suggested Further Research

NPN transistors and resistors.

An 8-bit, untrimmed A/D converter was developed using the same architecture as the 7-bit

fine quantizer from the 10-bit converter. The 8-bit ADC operates at 175 Msps delivering 47 dB SNR

and –58 dBc SFDR for input sinusoids up to 10 MHz. The measured peak INL is less than

60% LSB at or below room temperature rising to 90% LSB at 125°°C. The chip dissipates 550mW

from +5 V and –5 V supplies and employs 1200 transistors on a die which measures

( ).

Both the 7-bit and the 8-bit folding quantizers incorporate two analog folding amplifiers

whose input-output characteristics are quadrature sinusoids. ADC thresholds are generated using

non-uniform interpolation between the zero-crossings of these quadrature waveforms. The resultant

array of phase-shifted sinusoids is digitized and encoded using an efficient logic tree consisting of

analog multipliers followed by exclusive-OR gates. Because the sinusoidal waveforms are periodic,

this encoding generates an ambiguous estimate of the input signal amplitude. To resolve this

uncertainty, a flash quantizer called the cycle pointer identifies within which period of the sinusoidal

waveforms the input signal lies. A simple digital error correction algorithm then ensures proper

alignment of the coarse quantizer and fine quantizer thresholds.

Several architectural and circuit innovations enabled development of the A/D converters

described in this manuscript. The techniques utilized which were fundamental to the achieved

performance are tabulated below.

Architectural innovations which enhanced performance over more traditional approaches include:

• a pipelined feedforward A/D converter employing an efficient high-resolution fine

quantizer with a low-resolution coarse quantizer to minimize overall complexity.

• a pipelining arrangement which reduces the linearity required of the inter-stage T/H

to a level commensurate with the resolution of the fine quantizer, thereby reducing

the complexity and power dissipation of the T/H. This arrangement is only possible

when the coarse quantizer exhibits very low resolution as in the partitioning

mentioned above.

• a scheme which assures proper gain settings for the coarse quantizer, reconstruction

DAC, and fine quantizer. This technique utilizes scaled replicas of the pertinent


10.1 Conclusions 303

ADC components to recreate conditions within the actual circuits. The replicas are

enclosed within feedback loops which control replica bias (and hence gain) to ensure

that the replica gains are properly set. The bias of the actual ADC components equals

that of the corresponding replica components; therefore proper gain adjustment of

the actual ADC components obtains.

New circuits within the input T/H and the inter-stage T/H which enhanced performance include:

• a compensation technique which eliminates static distortion induced by finite

resistance loading diode-bridges. This method was generalized to mitigate the

dynamic distortion caused by the load presented by the hold capacitor itself.

• a very low power, highly linear, unity-gain postamplifier with no signal-dependent

thermal effects and utilizing only NPN transistors and resistors.

The coarse quantizer utilizes two unconventional techniques:

• a 4-bit flash quantizer incorporating a differential reference ladder to eliminate

threshold errors induced by comparator bias current. The emitter followers

comprising the differential ladder also provide buffering to minimize the capacitive

load presented by the quantizer.

• an interpolation method which halves the required number of comparator pre-

amplifiers. This implementation reduces power dissipation and also reduces settling

time in the resistive reference ladder by halving the capacitive load.

Design approaches central to the performance of the reconstruction DAC and residue amplifier

include:

• a fully-segmented D/A converter topology which provides the simplest possible

interface to the flash coarse quantizer with the lowest sensitivity of DAC linearity to

current source mismatches. The individual segments are connected in a specific

order which minimizes the effects of spatial correlations among current source

errors on the INL of the DAC transfer function.

• a current-mode subtraction technique which reduces signal-dependent modulation


of bias levels in active devices to an amount proportional to the amplitude of the

residue signal rather than the input signal. This arrangement reduces by a factor of

16 compared to a more traditional approach the signal-induced bias modulation in

active devices, thus affording a commensurate improvement in linearity.

Many innovations contributed to the efficiency and performance of the unorthodox fine quantizer

including:

• a pair of folding circuits constructed with a number of simply inter-connected

differential pairs which exhibit quadrature sinusoidal input-output characteristics

when driven by a differential reference ladder (identical in form to that used in the

coarse quantizer). As in the coarse quantizer, this symmetric arrangement eliminates

errors caused by bias currents flowing into the folding circuits.

• a non-uniform interpolation method based on trigonometric identities which

generates from the two quadrature signals at the folding circuits’ outputs an array of

sinusoids uniformly-spaced in phase. The zero-crossings of these sinusoids

correspond to the threshold locations of the quantizer and are uniformly-spaced

along the quantizer input voltage range as desired. The interpolation is achieved with

a simple resistive ladder whose symmetry minimizes signal current flow, thereby

minimizing distortion in the buffers driving the ladder.

• an analog encoding technique based on simple multiplier cells (equivalent to digital

XOR gates) which halves the number of comparators required and significantly

reduces the complexity of the further digital encoding necessary.

• a simple digital encoding algorithm consistent with the analog encoding procedure

described above which employs a logic tree of XOR gates and generates Gray coded

output data from the digitized sinusoids.

• a coarse quantizer, sometimes called a cycle pointer, which ascertains in which

period of the quadrature sinusoids’ input-output characteristic the input signal is

located. This 3-bit (plus overflow) quantizer utilizes a differential reference scheme

to eliminate errors induced by comparator bias currents, and exploits analog

encoding to reduce the required number of comparators from 9 to 4.

10.2 Further Research Opportunities 305

The research leading to this thesis, and the results obtained therefrom enable some

conclusions to be drawn regarding performance limits imposed upon the types of A/D converters

studied. In multistage ADCs employing digital error correction, converter resolution is primarily

limited by the accuracy of the internal D/A converters and by the relative accuracy of the gain

matching between the composite stages. D/A converter design is a mature field, and many ingenious

techniques exist to produce high-accuracy, high-resolution DACs. The problem in multi-stage

ADCs is slightly different however, since, in most cases, a high-accuracy, low-resolution DAC is

necessary. Nonetheless, techniques exist to produce accurate DACs for use in pipelined A/D

converters. Therefore, accurate gain matching among multistage A/D components remains as the

factor limiting resolution. Where high-gain op-amps are available, the problem is mitigated, but

since pipelined A/D converters are relied upon for their speed potential, op-amp based (and hence

frequency limited) implementations are often inappropriate. Open-loop, untrimmed matching of

pipelined A/D converter components is therefore limited by the intrinsic matching of integrated

circuit components to about 0.1%. Depending upon the particular partitioning involved, such ADC

component gain mismatch places a limit on achievable resolution in multistage A/D converters

which is approximately 10 to 12 bits. New conversion algorithms which alleviate this constraint

imposed by component gain matching should be developed.

Resolution in folding A/D converters of the type developed here is limited by mismatches

in transistor . Since the full-scale range of a high-speed folding ADC is practically limited (by

several considerations including speed) to about 2 Volts, typical transistor mismatches

( ) limit converter resolution to about 9 bits.

10.2Further Research Opportunities

Several opportunities exist to extend the analysis presented here or to enhance the

performance of the circuits developed. Some of the more promising areas for investigation are

delineated below.

As mentioned above, one limit to achievable resolution in untrimmed multi-stage ADCs is

imposed by the linearity of the reconstruction DAC. The segmented D/A converter topology

provides excellent performance in this regard but is still limited to approximately 10 bit

performance. Other approaches amenable to implementation in bipolar technology which exceed

this linearity invoke dynamic averaging techniques to improve matching [1], [2], [3], [4], [5].

VBE

σVBE1 2mV⁄≈


Because of their increased complexity over the conventional segmented approach, these dynamic

element matching topologies were not considered for this project. However, the prospect of

improved linearity promised by such D/A converters make their adoption worthy of further

consideration.

Threshold errors in flash ADCs and in folding ADCs arise from offset voltages inherent in

the comparators which comprise the converter. The effect of these offsets can be mitigated by

spatially averaging the offsets from a number of neighboring comparators. An ingenious method

for performing this operation resistively couples outputs from adjacent comparator pre-amplifiers

to obtain the necessary averaging of offset voltages [6]. A similar method could be applied to the

analog encoders interposed between the non-uniform interpolation ladder and the comparator bank

of the folding quantizer. This technique should improve linearity of the folding converter. A similar

technique applied to the outputs of the folding amplifiers themselves would greatly improve

achievable linearity since transistor mismatches in the folding circuits currently limit folding A/D

resolution. The details and effectiveness of such an implementation are not clear.

Gain matching in multi-stage A/D converters places a fundamental limit on achievable

performance. New algorithms which do not rely upon accurate gain matching would greatly

improve capabilities of high-speed converters. However, no simple solution to this fundamental

problem currently presents itself. As such, this area remains an important and interesting field of

inquiry.

The effect of deterministic threshold perturbations on the spectra of quantized signals

remains an important area where better understanding is needed. Certain A/D converter

architectures give rise to predictable threshold errors which ultimately limit linearity; however,

determining distortion spectra based upon these errors is still impractical. For example, “reference

bowing” in bipolar flash converters, gain mismatches among components in multi-stage ADCs, and

temperature changes in folding converters all give rise to deterministic threshold errors which are

easily characterized as functions of the relevant parameters. Development of techniques for

predicting A/D converter output spectra including such threshold perturbations would prove

invaluable for high-performance data converter design.

10.2 Further Research Opportunities 307

References






[6] K. Kattmann and J. Barrow, “A technique for reducing differential non-linearity errors inflash A/D converters,” inInternational Solid State Circuits Conference, pp. 170–171,IEEE, Feb. 1991.

Bibliography

A list of references which pertain to high-speed analog-to-digital and digital-to-analog

conversion follows. The list is sorted alphabetically by principal author and includes papers,

patents, books, and application notes. Most entries involve bipolar implementations of data

conversion integrated circuits, but some MOS and some GaAs MESFET papers are included where

the architectures or concepts relate to those described in this manuscript. Several entries describe

testing and/or characterization of data converters, an increasingly important topic as A/D

performance increases near the limit of testability with conventional techniques. The list is fairly

comprehensive regarding high-speed data conversion but does not include references describing

oversampling or sigma-delta converters which have heretofore been relegated to high-resolution,

low-speed applications; but which represent a promising trend for future developments in the high-

speed data converter arena.

[1] J. L. Addis, “Precision differential amplifier having fast overdrive recovery.” U.S. PatentNumber 4,714,896, Dec. 1987.

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adc - a 10bit 100msps adc with folding interpolation and analog encoding -thesis

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