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ACM SIGDA Publications on CDROM
DAC 9835th Design Automation Conference
June 15 – 19, 1998San Francisco, CA
Copyright © 1998 by the Association for Computing Machinery, Inc (ACM). Permission to make digital or hard copies of portions of this work for personalor classroom use is granted without fee provided that the copies are not made or distributed for profit or commercial advantage and that copies bear thisnotice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit ispermitted. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permission torepublish from: Publications Dept. ACM, Inc., FAX +1-212-869-0481 or E-mail <[email protected]>. For other copying of articles that carry a code atthe bottom of the first or last page, copying is permitted provided that the per-copy fee indicated in the code is paid through the Copyright Clearance Center,222 Rosewood Drive, Danvers, MA 01923.
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Cover Page Front Matter Table of ContentsSession Index Author Index
DESIGN AUTOMATION CONFERENCE®
Sponsored by
special interest group on
des ign au tomat ion®CONSORTIUM
Moscone Center, San Francisco, CA June 15 - 19, 1998
PROCEEDINGS 1998
PROCEEDING OF THE 35th DESIGN AUTOMATION CONFERENCE
The Association for Computing Machinery, Inc.
1515 Broadway
New York, NY 10036
Copyright © 1998 by the Association for Computing Machinery, Inc (ACM). Permission to make digital or
hard copies of portions of this work for personal or classroom use is granted without fee provided that the
copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the
full citation on the first page. Copyrights for components of this work owned by others than ACM must be hon-
ored. Abstracting with credit is permitted.
To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission
and/or a fee. Request permission to republish from: Publications Dept. ACM, Inc., FAX +1-212-869-0481 or
E-mail <[email protected]>.
For other copying of articles that carry a code at the bottom of the first or last page, copying is permitted pro-
vided that the per-copy fee indicated in the code is paid through the Copyright Clearance Center, 222 Rosewood
Drive, Danvers, MA 01923.
IEEE Catalog Number 98CH36175
ACM Order Number 477980 ISBN 0-7803-4409-X (Casebound Edition)
ISBN 0-89791-964-5 ISBN 0-7803-4410-3 (Microfiche Edition)
Library of Congress Number 85-644924 ISSN 0738-100X
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ii
TECHNICAL PROGRAMCO-CHAIR, DESIGN TOOLSRandal E. BryantCarnegie Mellon Univ.School of CSPittsburgh, PA 15213(412) [email protected]
FINANCE CHAIRGiovanni De MicheliStanford Univ.Gates Computer Science Bldg.Rm. 333Stanford, CA 94305-9030(650) [email protected]
ELECTRONIC SYSTEMSINDUSTRY CHAIRBryan D. AcklandLucent Technologies, Bell Labs.101 Crawfords Corner Rd.Rm. 4E-508Holmdel, NJ 07733-1900(732) [email protected]
ELECTRONIC MEDIA CHAIRMichael LorenzettiMentor Graphics Corp.8005 SW Boeckman Rd.Wilsonville, OR 97070-7777(503) [email protected]
TECHNICAL PROGRAMCO-CHAIR, DESIGN METHODSJan M. RabaeyUniv. of CaliforniaDept. of EECS, 511 Cory HallBerkeley, CA 94720(510) [email protected]
TUTORIAL CHAIRAntun DomicSynopsys, Inc.700 E. Middlefield Rd.Mountain View, CA 94043-4033(650) [email protected]
EDA INDUSTRY CHAIRThomas P. PenninoLucent Technologies, Bell Labs.101 Crawfords Corner Rd.Rm. 1M-415Holmdel, NJ 07733(732) [email protected]
PUBLICITY CHAIRAbbie KendallOrCAD9300 SW Nimbus Ave.Beaverton, OR 97008(503) [email protected]
EXECUTIVE COMMITTEEGENERAL CHAIR
Basant R. ChawlaLucent Technologies
283 King George Rd., E4D43Warren, NJ 07059
(908) [email protected]
VICE CHAIRMary Jane IrwinPenn State Univ.
Dept. of CS and Engr.220 Pond Lab.
University Park, PA 16802-6106(814) 865-1802
EUROPE/MIDDLE EASTREPRESENTATIVEGerry MusgraveBrunel Univ.Dept. of EEEUxbridge, UB8 3PH, UK(44) [email protected]
ACM REPRESENTATIVEJames CohoonUniv. of VirginiaDept. of Computer ScienceOlsson HallCharlottesville, VA 22903(804) [email protected]
IEEE-CAS REPRESENTATIVEMichael LightnerUniv. of ColoradoDept. of ECE, Campus Box 425Boulder, CO 80309-0425(303) [email protected]
EXHIBIT MANAGERMarie R. PistilliMP Associates, Inc.5305 Spine Rd., Ste. ABoulder, CO 80301(303) [email protected]
PAST CHAIREllen J. YoffaIBM Corp.T.J. Watson Research Ctr.P.O. Box 218, Rm. 33-109Yorktown Heights, NY 10598(914) [email protected]
ASIA/INDIA/S. PACIFICREPRESENTATIVEFumiyasu HiroseFujitsu Labs. Ltd.CAD Lab.4-1-1 Kamikodanaka, Nakahara-kuKawasaki 211, Japan(81) [email protected]
EDAC REPRESENTATIVELorie Bowlby111 W. St. John St., Ste. 200San Jose, CA 95123-1104(408) [email protected]
CONFERENCE MANAGERP.O. PistilliMP Associates, Inc.5305 Spine Rd., Ste. ABoulder, CO 80301(303) [email protected]
EXECUTIVE COMMITTEE (cont.)
Technical Program Committee
Randal E. BryantDesign Tools Co-ChairCarnegie Mellon Univ.School of CSPittsburgh, PA 15213(412) [email protected]
Jan M. Rabaey Design Methods Co-ChairUniv. of California Dept. of EECS, 511 Cory HallBerkeley, CA 94720 (510) [email protected]
Bryan D. Ackland Lucent Technologies, Bell Labs. Rm. 4E-508 101 Crawfords Corner Rd. Holmdel, NJ 07733-1900 (732) 949-7248 [email protected]
David T. Blaauw Motorola, Inc. Advanced Design Tech.Bridgepoint, Plaza 15918 W. Courtyard Dr., Ste. 330 Austin, TX 78730 (512) 794-4356 [email protected]
Ivo Bolsens IMEC VSDM, Kapeldreef 75 Leuven, BE B-3001 Belgium (32) 16-281-211 [email protected]
Anantha Chandrakasan Massachusetts Inst. of Tech. Dept. of EE, Rm. 38-107 50 Vassar St. Cambridge, MA 02139 (617) 258-7619 [email protected]
Mojy C. ChianHarris SemiconductorP.O. Box 883MS 62BO22Melbourne, FL 32902 (407) 724-7782 [email protected]
Nanette CollinsConsultant37 Symphony Rd., Unit ABoston, MA 02115(617) [email protected]
Jason Cong Univ. of California 4711 Boelter Hall Dept. of CS Los Angeles, CA 90095 (310) 206-2775 [email protected]
Anders Forsen Ericsson Radio Systems AB RCUR-T/N, Kista Stockholm, S-16480 Sweden (46) 8-7572-541 [email protected]
Patrick Groeneveld Magma Design Automation 1025A Terra Bella Ave. Mountain View, CA 94043(415) 938-6970 [email protected]
Rajesh K. Gupta Univ. of California 444 Computer Science, 208B IREF Irvine, CA 92697 (714) 824-8052 [email protected]
Randolph E. Harr Synopsys, Inc. 700 E. Middlefield Rd. Mountain View, CA 94043-4033 (415) 694-1927 [email protected]
TingTing Hwang Tsing Hua Univ.Dept. of Computer Science Hsin-Chu, 30043 Taiwan ROC(886) [email protected]
Technical Program Committee (cont.)Takahide Inoue Sony Corp. 530 Cottonwood Dr. Milpitas, CA 95035 (408) 955-4279 [email protected]
Andrew B. Kahng Univ. of California Dept. of CS, 3713 Boelter Hall Los Angeles, CA 90024-1596 (310) 206-7073 [email protected]
Timothy Y. Kam Intel Corp. Strategic CAD Labs., JFT-102 5200 NE Elam Young Pkwy. Hillsboro, OR 97124-6497 (503) 264-7536 [email protected]
David Ku Escalade Corp. 2575 Augustine Dr. Santa Clara, CA 95054 (408) 654-1617 [email protected]
Andreas Kuehlmann IBM Corp. T.J. Watson Research Ctr. P.O. Box 218 Yorktown Heights, NY 10598 (914) 945-3458 [email protected]
Luciano Lavagno Cadence Design Systems, Inc.2001 Addison St., 3rd Fl.Berkeley, CA 94704-1103(510) [email protected]
Sharad Malik Princeton Univ.Dept. of EE Princeton, NJ 08544 (609) 258-4625 [email protected]
Alan Mantooth Analogy, Inc. 9205 SW Gemini Dr. Beaverton, OR 97075-1669 (503) 626-9700 [email protected]
Teresa Meng Stanford Univ. Gates Computer ScienceBldg. 301 Stanford, CA 94028 (415) 725-3636 [email protected]
Mike Murray Acuson 1220 Charleston Rd.MS L-1, Box 7393 Mountain View, CA 94039 (415) 694-5876 [email protected]
Kunle Olukotun Stanford Univ. Gates Computer Science Gates 3A, Rm. 302 Stanford, CA 94305-9030 (415) 725 3713 [email protected]
Hidetoshi Onodera Kyoto Univ. Dept. of Electronics & Comm. Sakyo-ku Kyoto, 606-01 Japan(81) 75-753-5314 [email protected]
Janusz RajskiMentor Graphics Corp.8005 SW Boeckman Rd.Wilsonville, OR 97070-7777(503) 685-4797 [email protected]
James A. Rowson Alta Group of Cadence Design Systems, Inc.555 N. Matilda Ave.Sunnyvale, CA 94086 (408) 523-4157 [email protected]
Louis SchefferCadence Design Systems, Inc.555 River Oaks Pkwy.Bldg. 2, MS 2B1San Jose, CA 95134(408) [email protected]
Technical Program Committee (cont.)
Sunil D. Sherlekar Silicon Automation Systems 3008, 12th B Main, 8th Cross HAL 2nd Stage, Indiranagar Bangalore, 560008 India (91) [email protected]
Richard Smith Cadence Design Systems, Inc. 5215 N. O'Connor Rd., Ste. 1000 Irving, TX 75039(972) 889-0033 [email protected]
Vivek Tiwari Intel Corp.2200 Mission College Blvd.MS-RN 5-09 Santa Clara, CA 95052-8119 (408) 765-0589 [email protected]
Kazutoshi Wakabayashi NEC Corp. C&C Research Labs. 4-1-1 Miyazaki Kawasaki, 216 Japan (81) 44-856-2134 [email protected]
Neil Weste Macquarie Univ. Electronics Dept. Sydney, 2109 Australia(61) 2-850-9149 [email protected]
Andrew T. Yang Univ. of WashingtonDept. of EE, FT-10Seattle, WA 98195(206) 543-2932 [email protected]
Kenji Yoshida Toshiba Corp. 580-1 Horikawa-Cho Saiwai-ku Kawasaki, 210 Japan(81) 44 548 2400 [email protected]
Yervant Zorian LogicVision, Inc. 101 Metro Dr., Third Fl. San Jose, CA 95110 (408) 453-0146 [email protected]
Panel Sub-Committee
Nanette CollinsConsultant37 Symphony Rd., Unit ABoston, MA 02115(617) [email protected]
Takahide Inoue Sony Corp. 530 Cottonwood Dr. Milpitas, CA 95035 (408) 955-4279 [email protected]
Andrew B. Kahng Univ. of California Dept. of CS, 3713 Boelter Hall Los Angeles, CA 90024-1596 (310) 206-7073 [email protected]
Mike Murray Acuson 1220 Charleston Rd.MS L-1, Box 7393 Mountain View, CA 94039 (415) 694-5876 [email protected]
General Chair’s Welcome
Welcome to the 35th Design Automation Conference!
This marks a significant milestone in the history of DAC. It started as a small special interest group at theIBM SHARE meeting back in 1963, blossomed as the Design Automation Workshop in 1964, and finallyripened as the Design Automation Conference in 1975. The vendor exhibits, as we know them today,originated in 1983.
Ever since its beginning, DAC has maintained excellence in its technical program and has become thepremier conference for the presentation of research and development work in design automation ofintegrated circuits and electronic systems. DAC has also become the premier forum for the EDA industryto exhibit the leading edge products and make new product announcements.
For the past several years, the DAC Executive Committee has been focusing on expanding the technicalprogram to meet the needs of the design engineers. This year, we received a record number of technicalpapers on design methodology. It gives me great pleasure to say that about 40% of the technical programnow concentrates on design methodology. To complement the expansion of the technical program, wehave also expanded the exhibit area by introducing a special area on the floor, called Silicon Village, whichis dedicated to Silicon vendors to address the growing interdependence between Silicon and EDA vendors.This will provide an opportunity for the attendees to interact with both EDA vendors and Silicon vendorsat the same venue.
Another new attraction at DAC this year is the University Design Contest, a competition where universityresearchers submitted system designs to be judged on the basis of innovation in their design flows and theiruse of EDA tools. The top contestants will present their designs in a special session - a great place for thepracticing design engineers to interact with the university researchers.
These Proceedings, representing an outstanding expanded technical program were assembled under theleadership of this year’s Co-Technical Program Chairs Randy Bryant and Jan Rabaey. Three hundredninety papers from around the world were submitted to the design tools and design methods tracks, andwere reviewed by over 700 professionals along with detailed examination by the Technical ProgramCommittee, yielding 142 papers presented at the conference. The papers are complemented by nine panelsessions and 8 embedded tutorials. Special this year is a session to commemorate the 35th DesignAutomation Conference which provides both a retrospective of our past accomplishments and a view tothe future.
I want to thank all the people who contributed to DAC maintaining the premier conference status that itenjoys: the Executive Committee, the Technical Program Committee, the EDA Industry Committee,DAC’s sponsors, MP Associates, and especially the exhibitors, authors, speakers, session organizers andsession chairs. DAC is sponsored by ACM/SIGDA, IEEE Circuits and Systems Society, and EDAConsortium. Their members represent the breadth of DAC’s participants and we are thankful for theircontinued and active support.
Welcome to San Francisco and the 35th Design Automation Conference. We wish you a very productiveand fun-filled week, and trust you will find these proceedings to be a valuable information reference formany years to come.
Basant R. ChawlaGeneral Chair, 35th Design Automation Conference
OPENING KEYNOTE ADDRESS
William J. SpencerChairman of the BoardSEMATECH, Inc.Austin, TX
DESIGN AUTOMATION CAN HELP THE SEMICONDUCTORINDUSTRY ADDRESS ITS MANY CHALLENGES
Silicon technology has been the economic driver for much of the Information Age, by providing a 25-30%year-over-year improvement in cost per unit of performance. This amazing performance has been fueledby constantly improving semiconductor technology, including major gains in design automation. For theindustry to remain on the historic productivity curve, break-throughs will be required in several aspects ofsemiconductor manufacturing technology often linked strongly to design.
Bill Spencer is currently Chairman of SEMATECH, a research and development consortium consisting ofsixteen international corporations involved in semiconductor manufacturing. From 1990-1997, he servedas President and Chief Executive Officer of SEMATECH. Prior to 1990, he was Group Vice President andSenior Technical Officer at Xerox Corporation in Stanford, Connecticut, as well as Vice President andManager of the Xerox Palo Alto Research Center (PARC). He was Director of Systems Development andalso Director of Microelectronics at Sandia National Laboratories from 1973 to 1981, prior to joiningXerox. He began his career at Bell Telephone Laboratories in 1959. He received his Ph.D. and M.S. fromKansas State University, and an A.B. from William Jewell College in Missouri.
Spencer is also a Research Professor of Medicine at the University of New Mexico, where the firstimplantable electronic drug delivery systems were developed jointly with Sandia National Labs. For thiswork, he received the Regents Meritorious Service Medal and later a doctor of science degree fromWilliam Jewell College. He is currently a Director of Adobe Systems, Investment Corporation of America,SRI International and the Austin Symphony. He is also a member of the Board of Trustees of the ComputerMuseum and William Jewell College.
He has served on several National Research Council studies in the areas of technology, trade, corporationand competition. In 1998, he will co-chair, with Dick Thornburgh, an NRC workshop on “HarnessingTechnology for America’s Future Economic Growth”. He will also serve as a Regents Professor at theUniversity of California at Berkeley.
THURSDAY KEYNOTE ADDRESS
George H. HeilmeierChairman EmeritusBellcoreMorristown, NJ
FROM POTS TO PANS: TRANSITION IN THE WORLD OFTELECOMMUNICATIONS FOR THE LATE 90s AND BEYOND
The telecommunications industry is undergoing transitions at an unprecented rate from a provider of plainold telephone service (POTS) to a provider of “pretty awesome new services” (PANS). This presentationwill discuss the forcing factors and the technical/business transitions that are occuring at the industry,network, service and operations systems level. Key technical issues facing the industry as well as someagenda setting themes will also be discussed along with some of the implications for the microelectronicsindustry.
Dr. Heilmeier, world renowned for his pioneering work in the development of liquid crystal displays(LCDs) and the recipient of numerous awards including the National Medal of Science and the IEEEMedal of Honor, was drafted out of Texas Instruments in 1991 to fill the top job at Bellcore. Over the pastsix years, Heilmeier has piloted the company’s successful transition from the nation’s largest resourceconsortium to a competitive, profitable, growing, commercial enterprise with an expanded client base ofmore than 800 customers in the U.S. and abroad.Prior to joining Bellcore in March 1991, as the company’s President and Chief Executive Officer,Heilmeier was Senior Vice President and Chief Technical Officer of Texas Instruments, Inc. Dr. Heilmeier,a native of Philadelphia, holds a B.S. in electrical engineering from the University of Pennsylvania andM.A., M.S.E., and Ph.D. degrees in solid-state electronics from Princeton University. He has also beenawarded honorary doctorates from Stevens Institute and Technion, the Israel Institute of Technology.
1998 Best Paper Award
This year, awards are made for the best papers in four categories. Winners are determined from detailedreviews of the accepted papers in the technical sessions. Each award is accompanied by a plaque and acash award of $400. The awards are given by ACM/SIGDA (Special Interest Group on DesignAutomation), IEEE/CAS (Institute of Electrical and Electronics Engineers/Circuits and Systems Society)and EDA Consortium (Electronic Design Automation Companies).
PHYSICAL DESIGN AND LOGIC SYNTHESIS
Paper 17.1: “Generic Global Placement and Floorplanning”Authors: Hans Eisenmann, Frank M. JohannesAffiliation: Technical Univ. of Munich, Munich, Germany
HIGH-LEVEL SYNTHESIS, VERIFICATION AND CODESIGN
Paper 32.1: “A Decision Procedure for Bit-Vector Arithmetic”Authors: Clark W. Barrett, David L. Dill, Jeremy R. LevittAffiliation: Stanford Univ., Stanford, CA
MODELING, SIMULATION AND ESTIMATION
Paper 13.1: “A Fast Hierarchical Algorithm For 3-D Capacitance Extraction”Authors: Weiping Shi, Jianguo Liu, Naveen Kakani Tiejun YuAffiliation: Univ. of North Texas, Denton, TX Univ. of North Carolina, Charlotte, NC
DESIGN METHODOLOGY
Paper 9.1: “OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification”
Authors: Farzan Fallah, Srinivas Devadas Kurt KeutzerAffiliation: Massachusetts Inst. of Tech., Cambridge, MA Synopsys, Inc., Mountain View, CA
Paper 39.1: “Functional Verification of a Multiple-Issue, Out-of-Order, Superscaler Alpha Processor—The Alpha 21264 CPU Chip”
Authors: Michael Quinn, Scott TaylorAffiliation: Digital Equipment Corp., Hudson, MA
Advancement in Computer Science andElectrical Engineering Undergraduate Scholarships
The objective of the ACSEE Scholarship program is to increase the pool of professionals in ElectricalEngineering and Computer Science from under-represented groups (Women, African American, Hispanic,Native American, and Physically Challenged). In 1989, ACM Special Interest Group on DesignAutomation (SIGDA) began providing the program. Beginning in 1993, the Design AutomationConference provides the funds for the scholarship and SIGDA continues to administer the program forDAC. DAC normally funds two $4000 scholarships renewable up to 5 years to graduating high schoolseniors. In 1997 three awards were made.
The 1998 winners will be announced at the Conference.
1997 DAC ACSEE Undergraduate ScholarshipsDAC $4K: Bryan Neil Ramirez, Crook, CO - attending Colorado School of Mines
DAC $4K: Christine Joyce Mina, Minot, MA - attending Worcester Polytechnic InstituteDAC $4K: Diala William Abboud, Charlotte, NC - attending Univ. of North Carolina at Charlotte
For more information about the ACSEE Scholarship, please contact Dr. Cherrice Traver, EE/CSDepartment, Union College, Schenectady, NY 12308 email: [email protected].
Design Automation Conference Graduate Scholarships
Each year the Design Automation Conference sponsors several $24,000 scholarships to support graduateresearch and study in Design Automation (DA), with emphasis in "design and test automation of electronicand computer systems". Each scholarship is awarded directly to a university for the Faculty Investigatorto expend in direct support of one or more DA graduate students.
The criteria for granting such a scholarship expanded in 1996 to include financial need. The criteria are:the academic credentials of the student(s); the quality and applicability of the proposed research; theimpact of the award on the DA program at the institution; and financial need. Preference is given toinstitutions that are trying to establish new DA research programs.
Information on next year's DAC scholarship award program will be available on the DAC World WideWeb page at: http://www.dac.com/scholarship.html.
Design Automation Conference Graduate Scholarship Awards• Prof. Rajesh K. Gupta of the University of California, Irvine, CA, for Ali Dasdan. Their project is entitled,
"Framework for Timing Constraint Analysis and Debugging for Embedded Systems".
• Prof. John Lillis of the University of Illinois, Chicago, IL, for Sung-Woo Hur and Prashanthi Malireddy. Their project is entitled, "New Techniques for Timing-Driven Placement".
• Prof. Frank Vahid of the University of California, Riverside, CA, for Tony Givargis. Their project is entitled, "Interface Exploration for Core-Based Systems".
The IEEE CAS supported DAC Graduate Scholarship is awarded to:
• Prof. Soha Hassoun of the Tufts University, Medford, MA, for Alexndros Margomenos, Terry Orfanos and Edmund Sullivan. Their project is entitled, "Microarchitectural Optimizations and Synthesis".
Design Automation Conference Graduate Scholarship Committee
The 1998 DAC Scholarship Committee was comprised of the following people:
James P. Cohoon, University of Virginia (Chair)Michael Lightner, University of Colorado
Jeffrey S. Salowe, Cadence Design Systems, Inc.
1998 SIGDA Meritorious Service AwardsFor contributions in producing SIGDA CD ROM’s-
Archiving the knowledge of the Design Automation Community
Jason Cong, University of California, Los Angeles, CABryan Preas, Xerox PARC, Palo Alto, CA
Kathy Preas, KP Publications on CD-ROM, Palo Alto, CAChong-Chian Koh, University of California, Los Angeles, CACheng-Kok Koh, University of California, Los Angeles, CA
1998 IEEE FellowsWilliam Joyner - IBM Corp., T.J. Watson Research Ctr., Yorktown Heights, NY
Michael Lightner - Univ. of Colorado, Boulder, COMichael Nakhala - Carleton Univ., Ottawa, ON, Canada
Rob A. Rutenbar - Carnegie Mellon Univ., Pittsburgh, PAKarem Sakallah - Univ. of Michigan, Ann Arbor, MI
REVIEWERSA total of 390 manuscripts were submitted to the 1998 DAC. The Conference Executive and TechnicalProgram Committees wish to acknowledge the time and effort spent by the following people who reviewedthese manuscripts and returned the review forms completed. Our thanks to all of those who participatedand contributed to the success of the Conference.
Magdy S. AbadirMiron AbramoviciKhosrow AdibsamiiGaurav AggarwalDavid G. AgnewVishwani D. AgrawalTakashi AikyoRobert AitkenKahlid M. Al-RuwaihiAkhtar AliSalahuddin AlmajdoubCharles J. AlpertJoachim AltmeyerTod AmonKurt AntreichRafael AquinoGuido AraujoPranav AsharWilliam W. AuMichael S. AustwickRosa Maria BadiaFranklin M. BaezBrian BaileySmita BakshiFelice BalarinErich BarkeJohn K. BartholomewJohn G. BateRobert K. BeachlerDerek L. BeattyJames A. BeausangJames E. BeckBernd BeckerPeter BeerelDirk BehrensBill BellNikolaos BelliasTarek Ben IsmailCarina E. Ben-ZviLuca BeniniReinaldo BergamaschiMichel BerkelaarE. BerrebiNarasimha Bhat
Sandeep BhatiaSubhrajit BhattacharyaSudipta BhawmikSiddharth BhingardePeter BingleyStephen BlytheAlessandro BoglioloPascal BolcatoCristiana BolchiniMassimo BombanaCarsten BorchersGaetano BorrielloBhaskar BoseEric BrackenAnsgar BredenfeldForrest D. BrewerJay B. BrockmanThomas BuechnerGiacomo BuonannoJerry R. BurchTimothy M. BurksGianpiero CabodiPaolo E. CamuratiAriel CaoWanlin CaoRobert CarragherDon CarterFrancky CatthoorPatrizia CavalloroMustafa CelikKrishnendu ChakrabartyAbhijeet ChakrabortyTapan J. ChakrabortyTharini ChakrabortySrimat T. ChakradharSreejit ChakravartyRabih N. ChamounV. ChandramouliK.C. ChangShih-Chieh ChangYao-Wen ChangKaram S. ChathaChien-In Henry ChenChih-Tung Chen
Dahe ChenGuohua ChenHoward H. ChenSao-Jie ChenWenfeng ChenXinghao ChenYirng-An ChenDavid I. ChengShu-Mei ChengWu-Tung ChengBrian V. ChessChun-Ping George ChiMassino ChiapponeAnton V. ChichkovVenkat ChiluvuriMassimiliano ChiodoEli ChiproutSilvia ChiusanoHoon ChoiKiyoung ChoiPai ChouTan-Li ChouAmit ChowdharySalim ChowdhuryMalgorzata Chrzanowska-JeskeJohan CockxPaul CoeneJohn M. CohnTimothy W. ColleranAlan J. CoppolaFulvio CornoJose Luis Correia NevesJordi CortadellaDonald CottrellOlivier R. CoudertBernard CourtoisVinay P. DabholkarAjay J. DagaJoseph P. DamoreHiroshi DateBharat P. DaveRichard A. DaviesKaushik DeGjalt De Jong
Linda DebrunnerAnirudh DevganAllen M. DeweySujit DeyOlivier DeygasNagu R. DhanwadaAbhijit DharchoudhuryAjit T. DingankarRainer DoemerAntun DomicJack E. DonovanBernard J. DorayRolf DrechslerAnthony D. DrummMario DufresneJohn DuhNikil D. DuttKlaus EcklStephen A. EdwardsHans EisenmannCindy EisnerIbrahim M. ElfadelNorman J. EliasGary EllisFrank ElofBernhard EschermannNong FanRong FanAmir H. FarrahiErin P. FassioGary K. FedderPeter FeldmannJoel FergusonFabrizio FerrandiJosef FleischmannPaulo FloresMarie-Lise FlottesPaul FranzonMark S. FredricksonNorbert FroehlichRobert C. FryeHiroshige FujiiTakashi FujiiMasahiro FujitaFranco FummiGeorge GadelkarimAnthony J. GadientDaniel D. GajskiNeeta GangulyShantanu Ganguly
Joseph GanleyAndreas GanzDavid S.-W. GaoChristophe GauthronCatherine H. GebotysDaniel GeistVassilios GerousisAndreas GerstlauerIndradeep GhoshEkaterini E. GikasDimitris GizopoulosJames A. GodaNicole GoeckelManish GoelRich GoldmanNanda GopalNobuyuki GotoSriram GovindarajanRavender GoyalF. Gail GrayGary S. GreensteinPaul GrojeanJ.P. GrossmanJohn S. GroutLon GroverXinli GuCarlo GuardianiWolfgang GuentherMichaela GuineyKiran GullapalliPei-Ning GuoRohini GuptaSubodh GuptaMohan GuruswamyMitch R. GusatPaul GutwinIan A. GuylerDong S. HaIbrahim N. HajjReinhard V. HanxledenIkuo HaradaKlaus HarbichJustin HarlowSoha HassounGagan HasteerDavid J. HathawayLei HeJim HeatonLars HedrichCarl Hein
Sybille HellebrandShankar HemmadyStefan HendricxManfred HenftlingHarry HengsterJoerg HenkelKeerthi HeraguHiroyuki HiguchiDwight D. HillKen HinesLynwood HinesKanji HirabayashiMokhtar HirechKei HirosePei-Hsin HoShervin HojatUlrich HoltmannInki HongSeongsoo HongWei HongYou-Pyo HongHarry HsiehHong-Yean HsiehPao-Ann HsiungFrank F. HsuYaun-Chung HsuAlan J. HuXiaobo HuChing-Chao HuangPujiang HuangYing-Min I. HuangJose L. Huertas DiazChristophe P. Hui-Bon-HoaJos A. HuiskenBrad HutchingsMichael HuttonYeanyow HwangTakaki IchimoriPaolo IenneAkihiko InoueAtsuki InoueC. Norris IpMary Jane IrwinShinya IshiharaTohru IshiharaBalakrishnan IyerMahesh A. IyerNeil G. JacobsonMargarida JacomeGeert Jahssen
Jae-Young JangAlvin JeeNiraj K. JhaPradip JhaYi-Min JiangFrank M. JohannesEric N. JohnsonEric W. JohnsonVess L. JohnsonK.D. JonesLuli JosephsonRaju JoshiJing-Yang JouAttila JurecskaKnut JustHilary J. KahnAsawaree KalavadeSudhakar KalePriyank KallaRobert L. KanzelmanWilliam H. KaoAshish KapoorSharad KapurJean-Michel KaramArvind K. KarandikarOsamu KaratsuMaddumage KarunaratneMark A. KassabSrinivas KatkooriMeenakshi KaulMasamichi KawarabayashiRobert J. KayeWuudiann KeHolger KedingMartin KeimPratibha KelapureChristoph KernKevin J. KernsJohn E. KerroManpreet KhairaSanjay A. KhanSunil KhatriKei-Yong KhooBruce KimChoon KimJaewon KimShinji KimuraDarko KirovskiPolen KissionRobert H. Klenke
Alfred KoelblCheng-Kok KohHisao KolzumiVenk KommuAlex KondratyevSusanto M. Kong WoeiAndrzej KrasniewskiByron KrauterHarish KriplaniShankar KrishnamoorthyStanley J. KrolikoskiKayhan KucukcakarPrabhakar KudvaYuji KukimotoBalakrishna KumthekarDavid S. KungWolfgang KunzGanesh LakshminarayanaRudy LauwereinsJens LeenstraChristian LeglDaksh LehtherGuang-Tsai LeiWilliam C. Lester Jr.Rainer LeupersRegis LeveugleSteven LevitanSamuel LevitinJeremy R. LevittYanbing LiStan LiaoLuigi LicciardiJohn LillisDavid D. LingAntonio LioyPaul E. LippensFang-Jou LiuYu LiuArun N. LokanathanMichael LorenzettiAiguo LuGabriele LuculliYufeng LuoFadi MaamariAlberto MaciiEnrico MaciiJ. Christophe MadreSerge MaginotNaresh MaheshwariEnrico Malavasi
Yossi MalkaNazanin MansouriHenri J. MaramisP.J. MarchandGilberto MarchioroDiana MarculescuRadu MarculescuIgor L. MarkovGrant E. MartinMichael MartinTom MartinPeter MarwedelAlida MascitellAnmol MathurMasataka MatsuiYusuke MatsunagaPeter C. MaxwellRobert L. MaziaszKevin W. McCauleyPatrick McGuinnessGrace McNallyUwe B. MedingMahesh MehendaleRenu MehraAmit MehrotraSharad MehrotraGaurav MehtaStephen MeierChristoph MeinelKevin L. MeloccoNoel MenezesPrem R. MenonScott F. MidkiffPaolo MiliozziFumihiro MinamiShin-ichi MinatoSalvador MirManmohan MittalHiroshi MiyashitaToshiaki MiyazakiPeter MoceyunasPaul MolitorRobert MolyneauxDelfin Y. MontunoDaniel G. MoritzVasily G. MoshnyagaDinos MoundanosKlaus D. Mueller-GlaserAshutosh S. MujumdarPradipto Mukherjee
Rajarshi MukherjeeTamal MukherjeeFidel MuradaliMasami MurakataHiroshi MurataTakahiro MurookaGerry MusgraveLode NachtersaeleBenoit Nadeau-DostieSudip K. NagSurendra NaharVinod T. NairYuichi NakamuraJ. NarasimhanNaren NarasimhanUnni NarayananDanial NeebelMahadevamurty NemaniHoracio NetoTuyen V. NguyenLisa M. NoackAdrian Nunez-AldanaEmil S. OchottaPeter OdrynaKyung S. OhSeong Yong OhmMitsuyasu OhtaMakiko OkumuraArlindo OliveiraYukihito OowakiNeven OrhanovicRoss B. OrtegaIyad E. OuaissAndras PahiParimal Pal ChaudhuriSarala PaliwalWenwei PanRajendran V. PandaShipra PandaManish PandeyMaurizio PaoliniChristos A. PapachristouAbelardo PardoRubin A. ParekhjiKeshab K. ParhiNish P. ParikhIn-Cheol ParkEnric PastorJanak H. PatelRakesh J. Patel
Lalit M. PatnaikMichael PayerStefan PeesMarco A. PenaMarek A. PerkowskiWim PhilipsenJoel R. PhillipsMarc PicquendarKaren L. PieperLawrence T. PileggiAlain PirsonCarl P. PixleyLuis A. PlanaPaul PloegerFrancois PogodallaIrith PomeranzMassimo PoncinoAndras PoppeGuido PostMiodrag M. PotkonjakDhiraj K. PradhanMukul R. PrasadPierre PribetichPaolo PrinettoIksoo PyoIsa S. QamberGiu QinruStefano QuerIvan P. RadivojevicVijay RaghavendraAnand RaghunathanRichard RaimiRajesh RainaSalil RajeSuresh RajgopalShankar RamanSrilata RamanJerome RamponeRajeev K. RanjanShishpal S. RawatAlain RaynaudPhilippe P. RaynaudBill ReadMaurizio RebaudengoMark A. RempelMarta RenczKarla ReynoldsMichael RiepeBernhard M. RiessAnn M. Rincon
Ramine RoaneOriol RoigAndreas RopersWolfgang RosenstielCharles RosenthalMark RossmanKaushik RoyRabindra K. RoyElizabeth RudnickAdoracion RuedaCharlie RuppHarald H. SackP. SadasivanOmer G. SahhanHans SahmAlexander SaldanhaBill SalefskiJeffrey S. SaloweRaul San MartinFermin Sanchez CarraledoJagesh SanghaviAmbar SarkarKoichi SatoJanardhan H. SatyanarayanaGabriele SaucierEric SaxVikram SaxenaRiccardo ScarsiPatrick R. SchaumontUlf SchlichtmannStefan SchmerlerChristoph SchollEndric SchubertBernd SchuermannDonatella SciutoAndrew SeawrightCarl SechenReza Sedaghat-NamanJoel SeidmanMasatoshi SekineEllen M. SentovichJonjen SernDorothy E. SetliffPradip ShahWilliam D. SharonWen-Zen ShenNarendra V ShenoyDer-Y SheuHyongkyoon ShinThomas R. Shiple
Allan SilburtJulio SilvaL. Miguel SilveiraKanwar J. SinghVigyan SinghalMukund SivaramanJoseph P. SkudlarekEric SkuldtAnna SlobodovaRoss SmithMani SomaLeiLei SongMohamed SoufiLarry P. SouleLambert SpaanenburgJim SprochGiovanni A. SquilleroRajagopala SrinivasanVinoo N. SrinivasanMysore SriramMani SrivastavaBrian StaceyJason W. StaiertGeorge StamoulisChristian StangierBalsha R. StanisicDon StarkGuenter StenzJack A. StinsonJoern StohmannLeon StokNeal StollonNoel StraderLixin SuPeter R. SuarisRavi SubramanianAshok SudarsanamStephen SugiyamaWei-Kai SunPeter SuttonGitanjali M. SwamyJoseph M. SwentonV. SzekelyFrank SzorcThomas G. SzymanskiMasayoshi TachibanaPaul TafertshoferHaruyuki TagoYutaka TamiyaHiroshi Tanimoto
Alexander TaubinRamesh C. TekumallaChin-Chi TengShashidhar ThakurMichael TheobaldThorsten TheobaldMichael W. TianAdwin H. TimmerYosef Gavriel Tirat-GefenSteve TjiangHoria TomaHiroyuki TomiyamaMasahiko ToyonagaQuan TranTuan Anh TranStephen TrimbergerYatin TrivediAnne-Marie Trullemans-AnckaertHuan-Chih TsaiChi-Ying TsuiRaymond Y. TsuiEmre TuncerBogdan TutuianuJon G. UdellSanjay UpretiShmuel UrFrank VahidRadha VaidyanathanCarlos ValderramaDavid Van CampenhoutN.P. Van Der MeijsArjan Van GenderenJagadeesh VasudevamurthyRanga VemuriRaja VenkatachalamIngrid VerbauwhedeWim VerhaeghDiederik VerkestSerge VernaldeIdalina J. VideiraRoberto ViettiAshok VittalJeroen P. VoetenSarma VrudhulaDuncan M. WalkerRobert A. WalkerDavid WallaceJeffrey WalrathPiet WambacqChuan-Yu Wang
Duen-Jeng WangJimmy S. WangSeongmoon WangYosinori WatanabeJoseph C. WatkinsIvan L. WempleYen-Cheng WenManfred WieselJoerg WilbergBruce WileMarkus WillemsJohn WillisSteven J.E. WiltonBruce WinterAlain D. WittmannAnthony S. WojcikWayne WolfYaron WolfsthalAllen C.-H. WuChang WuQing WuMin XuSongjie XuAlexandre YakovlevMasaaki YamadaRyuichi YamaguchiKoichi YamashitaLawrence R YangHiroto YasuuraYibin YeJenny YeeTi-Yen YenDah-Cherng YuanFrank Y. YuanJun YuanLi-Pen YuanJoel T. YuenRoberto ZafalonAmir M. ZarkeshPeter W. ZepterMin ZhaoHai ZhouLixin ZhouJiabi J. ZhuAvi ZivVojin ZivojnovicKristian M. ZoerhoffXiao Zuonan
DAC is the premier conference devoted solely to the field of DesignAutomation. All aspects of the use of computers as aids to the design processare welcome, from conceptual design to manufacturing. Five types ofsubmissions are invited: regular papers, special topic sessions, panels,tutorials, and design contest entries. All types of submissions should be sentto the Program Chair, postmarked NO later than October 9, 1998.
Authors are invited to submit original technical papers describing recent andnovel research or engineering developments in all areas of design automation.The DESIGN TOOLS TRACK (T) is devoted to contributions to the researchand development of design tools and the supporting algorithms. The DESIGNMETHODS TRACK (M) deals with contributions to the research anddevelopment of design methodologies and applications of design automationtools to designs. Topics of interest include, but are not limited to:
DESIGN TOOLS TRACK:
T0.1 Fundamental CAD Algorithms, e.g., BDDs, graph coloring, partitioningT1.1 Electrical-level circuit and timing simulationT1.2 Discrete simulationT1.3 Critical path analysis and timing verificationT1.4 Power estimation T2.1 Testing, fault modeling and simulation, TPG, test validation and DFTT2.2 Design and implementation verification (excluding layout verification)T3.1 Floorplanning and placementT3.2 Global and detailed routing T3.3 Module generation and compaction, transistor sizing and cell library
optimization, layout verification T4.1 Technology independent, combinational logic synthesisT4.2 Technology dependent logic synthesis, library mapping, interactions between
logic design and layoutT4.3 Sequential and asynchronous logic synthesis and optimizationT4.4 High-level synthesisT5.1 Hardware Description Languages T5.2 Hardware/Software co-design, partitioning, system-level specification and
design aidsT5.3 Software synthesis and retargetable compilationT5.4 Hardware/Software co-simulationT6.1 Interconnect and packaging modeling and extractionT6.2 Signal integrity and reliability analysisT6.3 Analog and mixed-signal design tools and RFT6.4 Microsensor and microactuator design toolsT6.5 Statistical design and yield maximizationT7.1 Frameworks, intertool communication, WWW-based tools and
databases
DESIGN METHODS TRACK:
The Design Methods track (M) deals with innovative methodologies for thedesign of electronic circuits and systems, as well as creative experiences withdesign automation in state-of-the-art designs. Submissions for this track will bejudged on how effectively they teach new art in the development and applicationof new tools and techniques to real-world design problems.M1 Design methodologies and case studies for specific design tasksM1.1 Design entry and specificationM1.2 Simulation, analysis, modeling and estimationM1.3 Verification, test and debuggingM1.4 Physical design, module generation, design for manufacturingM1.5 Logic and high-level synthesis and optimizationM1.6 System-level design, embedded-system design and co-designM1.7 OtherM2 Design methodologies and case studies for specific application
domains and platformsM2.1 Configurable computing, FPGA and rapid prototypingM2.2 Systems on a chipM2.3 Microprocessor and multiprocessorM2.4 DSP, data-paths, multimedia and communicationM2.5 Wireless and data networkingM2.6 Other (MCM, optical, consumer)
Watch the WWW for updates! (http://www.dac.com)
M3 Performance and technology driven design techniques
M3.1 Deep sub-micron: signal integrity, interconnect and modelingM3.2 High-performance design: timing, clocking and power
distributionM3.3 Low power designM3.4 Mixed-signal, analog, and RFM3.5 Process technology development, extraction, modelingM3.6 Other (MEMS, sensors, new devices)M4 Integration and management of DA systemsM4.1 Management of DA systems, design interfaces, standardsM4.2 Distributed, networked, and collaborative designM4.3 Intellectual property, design re-use and design libraries
Previously published papers, including workshop proceedings, will not beconsidered. Each submission should include one cover page and eleven (11)stapled copies of the complete manuscript.The one cover page should include: • Name, affiliation, and complete address for each author• A designated contact person including his/her telephone number, fax number, and email address • A designated presenter, should the paper be accepted• A list of topic numbers preceded by the letter T (Tools Track) or M
(Methods Track), ordered by relevancy, most clearly matching the content of the paper• The following signed statement: “All appropriate organizational approvals
for the publication of this paper have been obtained. If accepted, the author(s) will prepare the final manuscript in time for inclusion in the Conference Proceedings and will present the paper at the Conference”.
To permit a blind review, do not include name(s) or affiliation(s) of theauthor(s) on the manuscript. Include:• Title of paper• 60-word abstract indicating significance of contribution • The complete text of the paper in English, including all illustrations and
references, not exceeding 4000 words. The papers will be reviewed as finished papers. Preliminary submissions will be at a disadvantage.
Notice of acceptance will be mailed to the contact person by February 19,1999. Authors of accepted papers must sign a copyright release form.
Proposals should not exceed two pages in length and should describe the topicand intended audience. They must include a list of all participants, including themoderator for panels. For proposal instructions, send a one-line emailmessage to [email protected] with “proposal” in the subject field, orwww.dac.com.
Special Topic Sessions may be either independent papers with a common themeor a set of closely related papers describing an overall system. In both cases,independent reviews of each paper and evaluation of the session as a whole willbe used to select sessions. Proposals for Special Topic Sessions should besubmitted along with the list of papers to be included in the session and shoulddescribe the session’s theme. These proposals and paper submissions mustbe postmarked no later than October 9, 1998.
Submissions of original electronic designs (circuit or system), developed atuniversities and research organizations after June 1997 and resulting inoperational implementations are invited. Submissions should contain the titleof the project, a 60-word abstract and a complete description of the design, notexceeding 4000 words in text. The submission should clarify the originality,distinguishing features, and the measured performance metrics of the design.Proof-of-implementation in the form of die or board photographs and measurementdata is a must.Submitted designs should not have received awards in othercontests. Submissions will be reviewed by a special committee of experts.Selected designs will be presented and exhibited at the conference.
MP Associates, Inc.ATTN: Technical Program Co-ChairsRandal E. Bryant/Bryan Ackland5305 Spine Rd., Suite ABoulder, CO 80301For information call: (303) 530-4333
CALL FOR PAPERS36th DESIGN AUTOMATION CONFERENCE ®
ERNEST N. MORIAL CONVENTION CENTER • NEW ORLEANS, LA • JUNE 21 - 25, 1999
TOPICS OF INTEREST
REQUIREMENTS FOR SUBMISSION OF
PANELS, TUTORIALS, SPECIAL TOPIC
UNIVERSITY DESIGN CONTEST
PROGRAM CHAIR
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Sponsored by:
Table of Contents
General Chair’s Welcome .........................................................................................................................................iii
Executive Committee................................................................................................................................................iv
Technical Program Committee..................................................................................................................................vi
1998 Best Paper Award .............................................................................................................................................ix
ACSEE Undergraduate Scholarships........................................................................................................................ix
Design Automation Conference Graduate Scholarship Awards ................................................................................x
1998 IEEE Fellows ....................................................................................................................................................x
SIGDA Meritorious Service Award ...........................................................................................................................x
36th Call for Papers ..................................................................................................................................................xi
Reviewers .................................................................................................................................................................xii
Opening Keynote Address—William J. Spencer ..................................................................................................xviii
Thursday Keynote Address—George H. Heilmeier ...............................................................................................xix
Executive Plenary Panel: Customers, Vendors, and Universities:Determining the Future of EDA Together
Chair: Thomas P. PenninoOrganizer: Mike MurrayPanel Members: Aart de Geus, Jack Harding, Walden Rhines, Robert Brodersen,Johan Danneels, Gadi Singer..........................................................................................................1
Session 1Interfaces for Design Reuse
Chair: Gaetano BorrielloOrganizers: Timothy Kam, Luciano Lavagno
1.1 Embedded Tutorial: Asynchronous Interface Specification, Analysis and SynthesisMichael Kishinevsky, Jordi Cortadella, Alex Kondratyev ........................................................2
1.2 Automatic Synthesis of Interfaces between Incompatible ProtocolsRoberto Passerone, James A. Rowson, Alberto Sangiovanni-Vincentelli.................................8
1.3 Automated Composition of Hardware ComponentsJames Smith, Giovanni De Micheli........................................................................................14
Session 2Analog and Mixed-Signal Design Tools
Chair: Joseph P. SkudlarekOrganizers: Alan Mantooth, Hidetoshi Onodera
2.1 Multilevel Integral Equation Methods for the Extraction of Substrate CouplingParameters in Mixed-Signal IC's
Mike Chou, Jacob White.........................................................................................................202.2 Phase Noise in Oscillators: A Unifying Theory and Numerical Methods for
CharacterisationAlper Demir, Amit Mehrotra, Jaijeet Roychowdhury .............................................................26
2.3 Efficient Analog Test Methodology Based on Adaptive AlgorithmsLuigi Carro, Marcelo Negreiros.............................................................................................32
2.4 General AC Constraint Transformation for Analog ICsB. G. Arsintescu, E. Charbon, E. Malavasi, U. Choudhury, W. H. Kao................................38
xx
Session 3University Design Contest
Chair: Mary Jane IrwinOrganizer: Jan M. Rabaey
3.1 Design Methodology Used in a Single-Chip CMOS 900 MHz Spread-Spectrum WirelessTransceiver
Jacob Rael, Ahmadreza Rofougaran, Asad Abidi ..................................................................443.2 A Video Signal Processor for MIMD Multiprocessing
Jörg Hilgenstock, Klaus Herrmann, Jan Otterstedt, Dirk Niggemeyer, Peter Pirsch............503.3 Realization of a Programmable Parallel DSP for High Performance Image Processing
ApplicationsJens Peter Wittenburg, Willm Hinrichs, Johannes Kneip, Martin Ohmacht,Mladen Berekovic, Hanno Lieske, Helge Kloos, Peter Pirsch ...............................................56
3.4 A Multiprocessor DSP System Using PADDI-2Roy A. Sutton, Vason P. Srini, Jan M. Rabaey........................................................................62
3.5 Design and Implementation of the NUMAchine MultiprocessorA. Grbic, S. Brown, S. Caranci, R. Grindley, M.Gusat, G. Lemieux, K. Loveless,N. Manjikian, S. Srbljic, M. Stumm, Z. Vranesic, Z. Zilic......................................................66
Session 4Embedded System Design and Exploration
Chair: Ivo BolsensOrganizers: James A. Rowson, Anders Forsen
4.1 Design and Specification of Embedded Systems in Java Using Successive, FormalRefinement
James Shin Young, Josh MacDonald, Michael Shilman, Abdallah Tabbara,Paul Hilfinger, A. Richard Newton.........................................................................................70
4.2 Efficient System Exploration and Synthesis of Applications with Dynamic Data Storageand Intensive Data Transfer
Julio Leao da Silva Jr., Chantal Ykman-Couvreur, Miguel Miranda, Kris Croes,Sven Wuytack, Gjalt de Jong, Francky Catthoor, Diederik Verkest, Paul Six,Hugo De Man.........................................................................................................................76
4.3 Design Space Exploration Algorithm for Heterogeneous Multi-processor EmbeddedSystem Design
Ireneusz Karkowski, Henk Corporaal....................................................................................824.4 Modal Processes: Towards Enhanced Retargetability through Control Composition of
Distributed Embedded SystemsPai Chou, Gaetano Borriello..................................................................................................88
Session 5Taming Noise in Deep-Submicron Digital Designs
Chair: Nagaraj NSOrganizers: Kenneth L. Shepard, Nagaraj NS
5.1 Embedded Tutorial: Design Methodologies for Noise in Digital Integrated CircuitsKenneth L. Shepard.................................................................................................................94
Panel: Taming Noise in Deep Submicron Digital Integrated CircuitsChair: Nagaraj NSOrganizers: Kenneth Shepard, Takahide InouePanel Members: Chris Houghton, Barbara Chappell, Xiaonan Zhang,John MacDonald, John McBride, Bob Masleid ..........................................................................100
xxi
Session 6Control and Data Driven High Level Synthesis
Chair: Kayhan KucukcakarOrganizers: David Ku, Timothy Kam
6.1 FACT: A Framework for the Application of Throughput and Power OptimizingTransformations to Control-flow Intensive Behavioral Descriptions
Ganesh Lakshminarayana, Niraj K. Jha..............................................................................1026.2 Incorporating Speculative Execution into Scheduling of Control-flow Intensive
Behavioral DescriptionsGanesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha...........................................108
6.3 The DT-Model: High-Level Synthesis Using Data TransfersShantanu Tarafdar, Miriam Leeser.......................................................................................114
6.4 Rate Optimal VLSI Design from Data Flow GraphMoonwook Oh, Soonhoi Ha.................................................................................................118
Session 7Synthesis Flow in Deep Submicron Technologies
Chair: Ralph H. J. M. OttenOrganizers: Sharad Malik, Randal E. Bryant
7.1 Embedded Tutorial: Planning for PerformanceRalph H. J. M. Otten, Robert K. Brayton.............................................................................122
7.2 A DSM Design Flow: Putting Floorplanning, Technology-Mapping, and Gate-PlacementTogether
Amir H. Salek, Jinan Lou, Massoud Pedram.......................................................................128
Session 8Environment for Collaborative Design
Chair: Takahide InoueOrganizers: Richard Smith, Takahide Inoue
8.1 Framework Encapsulations: A New Approach to CAD Tool InteroperabilityPeter R. Sutton, Stephen W. Director....................................................................................134
8.2 A Geographically Distributed Framework for Embedded System Design and Validation
Ken Hines, Gaetano Borriello..............................................................................................1408.3 WELD — An Environment for Web-Based Electronic Design
Francis L. Chan, Mark D. Spiller, A. Richard Newton ........................................................146
Session 9New Methods in Functional Verification
Chair: Rajesh K. GuptaOrganizers: Vivek Tiwari, Kenji Yoshida
9.1 OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics forFunctional Verification
Farzan Fallah, Srinivas Devadas, Kurt Keutzer...................................................................1529.2 User Defined Coverage — A Tool Supported Methodology for Design Verification
Raanan Grinwald, Eran Harel, Michael Orgad, Shmuel Ur, Avi Ziv ..................................1589.3 Enhanced Visibility and Performance in Functional Verification by Reconstruction
Joshua Marantz ....................................................................................................................1649.4 Virtual Chip: Making Functional Models Work on Real Target Systems
Namseung Kim, Hoon Choi, Seungjong Lee, Seungwang Lee, In-Cheol Park,Chong-Min Kyung ................................................................................................................170
xxii
Session 10Panel: Hardware/Software Co-Design:
The Next Embedded System Design ChallengeChair: Pete Heller Organizers: Diane Orr, Kristin HehirPanel Members: James A. Rowson, Guido Arnout, Fred Rose, Vess L. Johnson........................174
Session 11System-Level Power Optimization
Chair: Vivek TiwariOrganizers: Rajesh K. Gupta, Sunil D. Sherlekar
11.1 Power Optimization of Variable Voltage Core-Based SystemsInki Hong, Darko Kirovski, Gang Qu, Miodrag M. Potkonjak, Mani B. Srivastava ...........176
11.2 Policy Optimization for Dynamic Power ManagementG. A. Paleologo, L. Benini, A. Bogliolo, G. De Micheli.......................................................182
11.3 A Framework for Estimating and Minimizing Energy Dissipation of EmbeddedHW/SW Systems
Yanbing Li, Jörg Henkel.......................................................................................................188
Session 12Boolean Methods
Chair: Fabio SomenziOrganizers: Sharad Malik, Randal E. Bryant
12.1 Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability
Peixin Zhong, Pranav Ashar, Sharad Malik, Margaret Martonosi......................................19412.2 Fast Exact Minimization of BDDs
Rolf Drechsler, Nicole Drechsler, Wolfgang Günther...........................................................20012.3 Boolean Matching for Large Libraries
Uwe Hinsberger, Reiner Kolla..............................................................................................206
Session 13Extraction and Modeling for Interconnect
Chair: Hidetoshi OnoderaOrganizers: Hidetoshi Onodera, Alan Mantooth
13.1 A Fast Hierarchical Algorithm for 3-D Capacitance ExtractionWeiping Shi, Jianguo Liu, Naveen Kakani, Tiejun Yu ..........................................................212
13.2 Boundary Element Method Macromodels for 2-D Hierarchical Capacitance Extraction
E. Aykut Dengi, Ronald A. Rohrer........................................................................................21813.3 Efficient Three-Dimensional Extraction Based on Static and Full-Wave Layered
Green's FunctionsJinsong Zhao, Wayne W. M. Dai, Sharad Kapur, David E. Long ........................................224
Session 14Processor Design and Simulation
Chair: Randolph E. HarrOrganizers: Anantha Chandrakasan, Randolph E. Harr
14.1 Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHzCMOS Microprocessor
Nevine Nassif, Madhav P. Desai, Dale H. Hall ...................................................................230
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14.2 A Top-down Design Environment for Developing Pipelined DatapathsRobert McGraw, James H. Aylor, Robert H. Klenke ............................................................236
14.3 Validation of an Architectural Level Power Analysis TechniqueRita Yu Chen, Robert M. Owens, Mary Jane Irwin, Raminder S. Bajwa.............................242
14.4 Design Methodology of a 200MHz Superscalar Microprocessor: SH-4Toshihiro Hattori, Yusuke Nitta, Mitsuho Seki, Susumu Narita, Kunio Uchiyama,Tsuyoshi Takahashi, Ryuichi Satomura................................................................................246
Session 15Panel: How Much Analog Does a Designer Need
To Know for Successful Mixed-Signal Design?Chair: Stephan OhrOrganizer: Georgia MarszalekPanel Members: Felicia James, Ken Kundert, Lavi Lev, Maq Mannan, Rob Rutenbar,Bob Dobkin..................................................................................................................................250
Session 16Performance Modeling and Characterization for Embedded Systems
Chair: Sunil D. SherlekarOrganizers: Sunil D. Sherlekar, Rajesh K. Gupta
16.1 Hierarchical Algorithms for Assessing Probabilistic Constraints on System Performance
G. de Veciana, M. Jacome, J.-H. Guo ..................................................................................25116.2 A Tool for Performance Estimation of Networked Embedded End-Systems
Asawaree Kalavade, Pratyush Moghé..................................................................................25716.3 Rate Derivation and Its Applications to Reactive, Real-time Embedded Systems
Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta............................................................263
Session 17Advances in Placement and Partitioning
Chair: Antun DomicOrganizers: Patrick Groeneveld, Andrew B. Kahng
17.1 Generic Global Placement and FloorplanningHans Eisenmann, Frank M. Johannes..................................................................................269
17.2 Congestion Driven Quadratic PlacementPhiroze N. Parakh, Richard B. Brown, Karem A. Sakallah .................................................275
17.3 Potential_NRG: Placement with Incomplete DataMaogang Wang, Prithviraj Banerjee, Majid Sarrafzadeh....................................................279
17.4 Performance-Driven Multi-FPGA Partitioning Using Functional Clustering and Replication
Wen-Jong Fang, Allen C.-H. Wu...........................................................................................28317.5 Multi-pad Power/Ground Network Design for Uniform Distribution of
Ground BounceJaewon Oh, Massoud Pedram ..............................................................................................287
Session 18Parasitic Device Extraction and Interconnect Modeling
Chair: David D. LingOrganizers:Alan Mantooth, Hidetoshi Onodera
18.1 Layout Extraction and Verification Methodology for CMOS I/O CircuitsTong Li, Sung-Mo (Steve) Kang ...........................................................................................291
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18.2 A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-OrderModeling of 3D Interconnects
Nuno Marques, Mattan Kamon, Jacob White, L. Miguel Silveira .......................................29718.3 Layout Based Frequency Dependent Inductance and Resistance Extraction for
On-Chip Interconnect Timing AnalysisByron Krauter, Sharad Mehrotra..........................................................................................303
Session 19Design Optimization for DSP
Chair: James A. RowsonOrganizers:Anders Forsen, Ivo Bolsens
19.1 A Methodology for Guided Behavioral-Level OptimizationLisa Guerra, Miodrag Potkonjak, Jan Rabaey.....................................................................309
19.2 A Programming Environment for the Design of Complex High Speed ASICsPatrick Schaumont, Serge Vernalde, Luc Rijnders, Marc Engels, Ivo Bolsens....................315
19.3 Media Architecture: General Purpose vs. Multiple Application-Specific Programmable Processor
Chunho Lee, Johnson Kin, Miodrag Potkonjak, William H. Mangione-Smith ....................321
Session 20Panel: User Experience with High Level Formal Verification
Chair: Gerry MusgraveOrganizers: Randal E. Bryant, Gerry MusgravePanel Members: Fumiyasu Hirose, Michael Payer, Pierre Aulagnier, Allan Silbert,John Van Tassel............................................................................................................................327
Session 21Bridging the Gap Between Simulation and Formal VerificationChair: Andreas KuehlmannOrganizers: Randal E. Bryant, Sharad Malik
21.1 Embedded Tutorial: What's Between Simulation and Formal Verification?David L. Dill.........................................................................................................................328
Session 22Logic Optimization
Chair: Albert WangOrganizers: Jason Cong, TingTing Hwang
22.1 Optimal FPGA Mapping and Retiming with Efficient Initial State ComputationJason Cong, Chang Wu.........................................................................................................330
22.2 M32:A Constructive Multilevel Logic Synthesis SystemVictor N. Kravets, Karem A. Sakallah..................................................................................336
22.3 Efficient Boolean Division and SubstitutionShih-Chieh Chang, David Ihsin Cheng................................................................................342
22.4 Delay-Optimal Technology Mapping by DAG CoveringYuji Kukimoto, Robert K. Brayton, Prashant Sawkar..........................................................348
22.5 A Fast Fanout Optimization Algorithm for Near-Continuous Buffer LibrariesDavid S. Kung.......................................................................................................................352
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Session 23Routing for Performance and Crosstalk
Chair: Sachin S. SapatnekarOrganizers: Patrick Groenveld, Andrew B. Kahng
23.1 Performance Driven Multi-Layer General Area Routing for PCB/MCM DesignsJason Cong, Patrick H. Madden...........................................................................................356
23.2 Buffer Insertion for Noise and Delay OptimizationCharles J. Alpert, Anirudh Devgan, Stephen T. Quay..........................................................362
23.3 Table-Lookup Methods for Improved Performance-Driven RoutingJohn Lillis, Premal Buch ......................................................................................................368
23.4 Global Routing with Crosstalk ConstraintsHai Zhou, D.F. Wong............................................................................................................374
23.5 Timing and Crosstalk Driven Area RoutingHsiao-Ping Tseng, Louis Scheffer, Carl Sechen...................................................................378
Session 24Practical Optimization Methodologies for High Performance Design
Chair: Vivek TiwariOrganizers: Vivek Tiwari, Kenji Yoshida
24.1 Process Multi-Circuit OptimizationArun Lokanathan, Jay Brockman.........................................................................................382
24.2 Migration:A New Technique to Improve Synthesized Designs through Incremental Customization
Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton,David Blaauw.......................................................................................................................388
24.3 A Practical Repeater Insertion Method in High Speed VLSI CircuitsJulian Culetu, Chaim Amir, John MacDonald.....................................................................392
24.4 Practical Experiences with Standard-Cell Based Datapath Design Tools — Do We Really Need Regular Layouts?
Paolo Ienne, Alexander Grieβing.........................................................................................39624.5 A Statistical Performance Simulation Methodology for VLSI Circuits
Michael Orshansky, James C. Chen, Chenming Hu.............................................................402
Session 25RF IC Design Methodology
Chair: Mojy C. ChianOrganizers: Bryan D. Ackland, Mojy C. Chian
25.1 Embedded Tutorial: RF IC Design ChallengesBehzad Razavi.......................................................................................................................408
25.2 Tools and Methodology for RF IC DesignAl Dunlop, Alper Demir, Peter Feldmann, Sharad Kapur, David Long, Robert Melville,Jaijeet Roychowdhury...........................................................................................................414
25.3 Electromagnetic Modeling and Signal Integrity Simulation of Power/Ground Networks in High Speed Digital Packages and Printing Circuit Boards
Frank Y. Yuan ........................................................................................................................421
Session 26Theory and Practice in High Level Synthesis
Chair: Steve TjiangOrganizers: David Ku, Timothy Kam
26.1 Efficient Coloring of a Large Spectrum of GraphsDarko Kirovski, Miodrag Potkonjak.....................................................................................427
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26.2 Arithmetic Optimization Using Carry-Save-AddersTaewhan Kim, William Jao, Steve Tjiang.............................................................................433
26.3 Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions
Ganesh Lakshminarayana, Niraj K. Jha..............................................................................439
Session 27BDD Approximation Techniques
Chair: Andreas KuehlmannOrganizers:Andreas Kuehlmann, Kunle Olukotun
27.1 Approximation and Decomposition of Binary Decision DiagramsKavita Ravi, Kenneth L. McMillan, Thomas R. Shiple, Fabio Somenzi...............................445
27.2 Approximate Reachability with BDDs Using Overlapping ProjectionsShankar G. Govindaraju, David L. Dill, Alan J. Hu, Mark A. Horowitz.............................451
27.3 Incremental CTL Model Checking Using BDD SubsettingAbelardo Pardo, Gary D. Hachtel........................................................................................457
Session 28Interconnect Modeling and Timing Simulation
Chair: Andrew T. YangOrganizers:Andrew T. Yang, Hidetoshi Onodera
28.1 PRIMO: Probability Interpretation of Moments for Delay CalculationRony Kay, Lawrence Pileggi.................................................................................................463
28.2 ftd: An Exact Frequency to Time Domain Conversion for Reduced Order RLCInterconnect Models
Ying Liu, Lawrence T. Pileggi, Andrzej J. Strojwas..............................................................46928.3 Extending Moment Computation to 2-Port Circuit Representations
Fang-Jou Liu, Chung-Kuan Cheng.......................................................................................47328.4 Adjoint Transient Sensitivity Computation in Piecewise Linear Simulation
Tuyen V. Nguyen, Anirudh Devgan, Ognen J. Nastov ..........................................................477
Session 29Low Power Design Using Multiple Thresholds and Supplies
Chair: Bryan D. AcklandOrganizers:Anantha Chandrakasan, Bryan D. Ackland
29.1 Design Methodology of Ultra Low-power MPEG4 Codec Core Exploiting Voltage Scaling Techniques
Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa,Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa,Tadahiro Kuroda...................................................................................................................483
29.2 Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits
Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De................................48929.3 MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns
James Kao, Siva Narendra, Anantha Chandrakasan...........................................................495
Session 30Panel: Technical Challenges of IP and System-on-Chip:
The ASIC Vendor PerspectiveChair: A. Richard NewtonOrganizers:Andrew Graham, Andrew B. KahngPanel Members: Bruce Beers, Jeffery Hilbert, Anand Naidu, Bob Payne, L.J. Reed,Mark Stibitz, Hitoshi Yoshizawa ..................................................................................................501
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Session 31Software Synthesis and Retargetable Compilation
Chair: Kurt KeutzerOrganizers: Luciano Lavagno, Sharad Malik
31.1 Software Synthesis of Process-Based Concurrent ProgramsBill Lin..................................................................................................................................502
31.2 Don't Care-Based BDD Minimization for Embedded SoftwareYoupyo Hong, Peter A. Beerel, Luciano Lavagno, Ellen M. Sentovich................................506
31.3 Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator
Silvina Hanono, Srinivas Devadas.......................................................................................51031.4 Code Compression for Embedded Systems
Haris Lekatsas, Wayne Wolf..................................................................................................516
Session 32Formal Methods in Functional Verification
Chair: Kunle OlukotunOrganizers: Kunle Olukotun, Andreas Kuehlmann
32.1 A Decision Procedure for Bit-Vector ArithmeticClark W. Barrett, David L. Dill, Jeremy R. Levitt................................................................522
32.2 Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability
Farzan Fallah, Srinivas Devadas, Kurt Keutzer...................................................................52832.3 Automatic Generation of Assertions for Formal Verification of PowerPC™
Microprocessor Arrays Using Symbolic Trajectory EvaluationLi-C. Wang, Magdy S. Abadir, Nari Krishnamurthy ............................................................534
32.4 Combining Theorem Proving and Trajectory Evaluation in an Industrial EnvironmentMark D. Aagaard, Robert B. Jones, Carl-Johan H. Seger...................................................538
Session 33Core Test and BIST
Chair: Janusz RajskiOrganizers: Yervant Zorian, Janusz Rajski
33.1 A Fast and Low Cost Testing Technique for Core-based System-on-ChipIndradeep Ghosh, Sujit Dey, Niraj K. Jha............................................................................542
33.2 Introducing Redundant Computations in a Behavior for Reducing BIST ResourcesIshwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer.......................................................548
33.3 A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability AnalysisIndradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik..............................................................554
Session 34Interconnect Analysis and Reliability in Deep Sub-Micron
Chair: Kenji YoshidaOrganizers: Kenji Yoshida, David T. Blaauw
34.1 Figures of Merit to Characterize the Importance of On-Chip InductanceYehea I. Ismail, Eby G. Friedman, Jose L. Neves ................................................................560
34.2 Layout Techniques for Minimizing On-Chip Interconnect Self InductanceYehia Massoud, Steve Majors, Tareq Bustami, Jacob White................................................566
34.3 A Practical Approach to Static Signal Electromigration AnalysisNagaraj NS, Frank Cano, Haldun Haznedar, Duane Young................................................572
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Session 35Panel: Design Productivity: How to Measure It, How to Improve It
Chair: Carlos DangeloOrganizers: Ronald E. Collett,Andrew B. Kahng,Panel Members: Andy Bechtolsheim, Ronald E. Collett, Jeff Hilbert, Chris Malachowsky,Leif Rosqvist, Jim Thomas...........................................................................................................578
Session 36Timing Analysis
Chair: Tom SzymanskiOrganizers: Sharad Malik, Farid N. Najm
36.1 Hierarchical Functional Timing AnalysisYuji Kukimoto, Robert K. Brayton........................................................................................580
36.2 Making Complex Timing Relationships Readable: Presburger Formula Simplification Using Don't Cares
Tod Amon, Gaetano Borriello, Jiwen Liu.............................................................................58636.3 Delay Estimation of VLSI Circuits from a High-Level View
Mahadevamurty Nemani, Farid N. Najm.............................................................................59136.4 TETA: Transistor-Level Engine for Timing Analysis
Florentin Dartu, Lawrence T. Pileggi...................................................................................595
Session 37New Techniques in State Space Explorations
Chair: Carl-Johan H. SegerOrganizers:Andreas Kuehlmann, Kunle Olukotun
37.1 Validation with Guided Search of the State SpaceC. Han Yang, David L. Dill...................................................................................................599
37.2 Efficient State Classification of Finite State Markov ChainsAiguo Xie, Peter A. Beerel....................................................................................................605
37.3 An Implicit Algorithm for Finding Steady States and its Application to FSMVerification
Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee............................................................61137.4 Hybrid Verification Using Saturated Simulation
Adnan Aziz, Jim Kukula, Tom Shiple....................................................................................615
Session 38Advanced ATPG Techniques
Chair: Yervant ZorianOrganizers: Yervant Zorian, Janusz Rajski
38.1 Fast State VerificationDechang Sun, Bapiraju Vinnakota, Wanli Jiang ..................................................................619
38.2 A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance
Aiman El-Maleh, Mark Kassab, Janusz Rajski....................................................................62538.3 Fault-Simulation Based Design Error Diagnosis for Sequential Circuits
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu....................632
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Session 39Practical Experience of Functional Verification for Complex ICsChair: Rajesh RainaOrganizers: David T. Blaauw, Kenji Yoshida
39.1 Functional Verification of a Multiple-issue, Out-of-Order, Superscalar Alpha Processor—The DEC Alpha 21264 Microprocessor
Scott Taylor, Michael Quinn, Darren Brown, Nathan Dohm, Scot Hildebrandt,James Huggins, Carl Ramey.................................................................................................638
39.2 Design Reliability—Estimation Through Statistical Analysis of Bug Discovery DataYossi Malka, Avi Ziv..............................................................................................................644
39.3 Functional Verification of Large ASICsAdrian Evans, Allan Silburt, Gary Vrckovnik, Thane Brown, Mario Dufresne,Geoffrey Hall, Tung Ho, Ying Liu.........................................................................................650
Session 40Panel: The EDA Start-up Experience: The First Product
Chair: Erach DesaiOrganizer: Mike MurrayPanel Members: Rick Carlson, Lorne Cooper, Dean Drako, Rajeev Madhavan,John Sanguinetti, Curtis Widdoes................................................................................................656
Session 41Fast Functional Simulation
Chair: Patrick C. McGeerOrganizers: Rajesh K. Gupta, David Ku
41.1 Embedded Tutorial: Digital System Simulation: Methodologies and ExamplesKunle Olukotun, Mark Heinrich, David Ofelt......................................................................658
41.2 Hybrid Techniques for Fast Functional SimulationYufeng Luo, Tjahjadi Wongsonegoro, Adnan Aziz................................................................664
41.3 A Reconfigurable Logic Machine for Fast Event-Driven SimulationJerry Bauer, Michael Bershteyn, Ian Kaplan, Paul Vyedin..................................................668
Session 42Power Estimation and Modeling
Chair: Farid N. NajmOrganizers: Farid N. Najm, Andrew T. Yang
42.1 Parallel Algorithms for Power EstimationVictor Kim, Prithviraj Banerjee ...........................................................................................672
42.2 A Power Macromodeling Technique Based on Power SensitivityZhanping Chen, Kaushik Roy ...............................................................................................678
42.3 Maximum Power Estimation Using the Limiting Distributions of ExtremeOrder Statistics
Qinru Qiu, Qing Wu, Massoud Pedram................................................................................68442.4 An Optimization-Based Error Calculation for Statistical Power Estimation
of CMOS Logic CircuitsByunggyu Kwak, Eun Sei Park .............................................................................................690
42.5 Using Complementation and Resequencing to Minimize TransitionsRajeev Murgai, Masahiro Fujita, Arlindo Oliveira..............................................................694
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Session 43Technology Mapping for Programmable Logic
Chair: Jonathan RoseOrganizers: Jason Cong, TingTing Hwang
43.1 Technology Mapping for Large Complex PLDsJason Helge Anderson, Stephen Dean Brown......................................................................698
43.2 Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTsJason Cong, Songjie Xu........................................................................................................704
43.3 Exact Tree-based FPGA Te ch n o l ogy Mapping for Logic Blocks with Independent LUTsMadhukar R. Korupolu, K. K. Lee, D. F. Wong....................................................................708
43.4 Compatible Class Encoding in Hyper-Function Decomposition for FPGA SynthesisJie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang.........................................................712
43.5 In-Place Power Optimization for LUT-Based FPGAsBalakrishna Kumthekar, Luca Benini, Enrico Macii, Fabio Somenzi..................................718
43.6 A Re-engineering Approach to Low Power FPGA Design Using SPFDJan-Min Hwang, Feng-Yi Chiang, TingTing Hwang............................................................722
Session 44Power Dissipation and Distribution in High Performance Processors
Chair: David T. BlaauwOrganizers: Anatha Chandrakasan, Jan M. Rabaey
44.1 Power Considerations in the Design of the Alpha 21264 MicroprocessorMichael K. Gowan, Larry L. Biro, Daniel B. Jackson.........................................................726
44.2 Reducing Power in High-Performance MicroprocessorsVivek Tiwari, Deo Singh, Suresh Rajgopal, Gaurav Mehta, Rakesh Patel,Franklin Baez........................................................................................................................732
44.3 Design and Analysis of Power Distribution Networks in PowerPC™ MicroprocessorsAbhijit Dharchoudhury, Rajendran Panda, David Blaauw, Ravi Vaidyanathan,Bogdan Tutuianu, David Bearden........................................................................................738
44.4 Full-Chip Verification Methods for DSM Power Distribution SystemsGregory Steele, David Overhauser, Steffen Rochel, Syed Zakir Hussain ............................744
Session 45Challenge in the Test on System-On-A-Chip Era
Chair: Prab VarmaOrganizers: Prab Varma, Takahide InouePanel: System Chip Test Challenges, Are There Solutions Today?
Panel Members: Erik Jan Marinissen, Bruce Mathewson, Rudy Garcia,Yervant Zorian, Sujit Dey, Rob Roy......................................................................................750
45.1 Embedded Tutorial: System-Chip Test StrategiesYervant Zorian......................................................................................................................752
Session 46Controller Decomposition for Power and Area Minimization
Chair: Fabio SomenziOrganizers: Timothy Kam, Luciano Lavagno
46.1 Finite State Machine Decomposition for Low PowerJosé C. Monteiro, Arlindo L. Oliveira..................................................................................758
46.2 Computational Kernals and Their Application to Sequential Power OptimizationL. Benini, G. De Micheli, A. Lioy, E. Macii, G. Odasso, M Poncino ..................................764
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46.3 Partitioning and Optimizing Controllers Synthesized from Hierarchical High-LevelDescriptions
Andrew Seawright, Wolfgang Meyer ....................................................................................770
Session 47IP Protection Technologies
Chair: Tom VandenBergeOrganizers: Richard Smith, Takahide Inoue
47.1 Watermarking Techniques for Intellectual Property ProtectionA. B. Kahng, J. Lach, W. H. Mangione-Smith, S. Mantik, I. L. Markov,M. Potkonjak, P. Tucker, H. Wang, G. Wolfe .........................................................................776
47.2 Robust IP Watermarking Methodologies for Physical DesignAndrew B. Kahng, Stefanus Mantik, Igor L. Markov, Miodrag Potkonjak,Paul Tucker, Huijuan Wang, Gregory Wolfe .........................................................................782
47.3 Data Security for Web-based CADScott Hauck, Stephen Knol...................................................................................................788
Session 48Case Studies of New Design Methods
Chair: Anders ForsenOrganizers: Ivo Bolsens, James A. Rowson
48.1 Design of a SPDIF Receiver using Protocol CompilerUlrich Holtmann, Peter Blinzer............................................................................................794
48.2 MetaCore: An Application Specific DSP Development SystemJin-Hyuk Yang, Byoung-Woon Kim, Sang-Jun Nam, Jang-Ho Cho, Sung-Won Seo,Chang-Ho Ryu, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Jong-Sun Kim,Hyun-Dhong Yoon, Jae-Yeol Kim, Kun-Moo Lee, Chan-Soo Hwang, In-Hyung Kim,Jun-Sung Kim, Kwang-Il Park, Kyu-Ho Park, Yong-Hoon Lee, Seung-Ho Hwang,In-Cheol Park, Chong-Min Kyung........................................................................................800
48.3 A Case Study in Embedded System Design: An Engine Control UnitTullio Cuatto, Claudio Passerone, Luciano Lavagno, Attila Jurecska, Antonino Damiano,Claudio Sansoè, Alberto Sangiovanni-Vincentelli................................................................804
48.4 HW/SW CoVerification Performance Estimation & Benchmark for a 24 Embedded RISCCore Design
Thomas W. Albrecht, Johann Notbauer, Stefan Rohringer...................................................80848.5 System-Level Exploration with SpecSyn
Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong.................................................812
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Session Index
Session 1 - Interfaces for Design ReuseSession 2 - Analog and Mixed-Signal Design ToolsSession 3 - University Design ContestSession 4 - Embedded System Design and ExplorationSession 5 - Taming Noise in Deep-Submicron Digital DesignsSession 6 - Control and Data Driven High Level SynthesisSession 7 - Synthesis Flow in Deep Submicron TechnologiesSession 8 - Environment for Collaborative DesignSession 9 - New Methods in Functional VerificationSession 10 - Panel: Hardware/Software Co-Design: The Next Embedded System Design ChallengeSession 11 - System-Level Power OptimizationSession 12 - Boolean MethodsSession 13 - Extraction and Modeling for InterconnectSession 14 - Processor Design and SimulationSession 15 - Panel: How Much Analog Does a Designer Need To Know for Successful Mixed-Signal
Design?Session 16 - Performance Modeling and Characterization for Embedded SystemsSession 17 - Advances in Placement and PartitioningSession 18 - Parasitic Device Extraction and Interconnect ModelingSession 19 - Design Optimization for DSPSession 20 - Panel: User Experience with High Level Formal VerificationSession 21 - Embedded Tutorial: Bridging the Gap between Simulation and Formal VerificationSession 22 - Logic OptimizationSession 23 - Routing for Performance and CrosstalkSession 24 - Practical Optimization Methodologies for High Performance DesignSession 25 - RF IC Design MethodologySession 26 - Theory and Practice in High Level SynthesisSession 27 - BDD Approximation TechniquesSession 28 - Interconnect Modeling and Timing SimulationSession 29 - Low Power Design Using Multiple Thresholds and SuppliesSession 30 - Panel: Technical Challenges of IP and System-on-Chip: The ASIC Vendor PerspectiveSession 31 - Software Synthesis and Retargetable CompilationSession 32 - Formal Methods in Functional VerificationSession 33 - Core Test and BISTSession 34 - Interconnect Analysis and Readability in Deep Sub-MicronSession 35 - Panel: Design Productivity: How to Measure It, How to Improve ItSession 36 - Timing AnalysisSession 37 - New Techniques in State Space ExplorationsSession 38 - Advanced ATPG TechniquesSession 39 - Practical Experience of Functional Verification for Complex ICsSession 40 - Panel: The EDA Start-up Experience: The First ProductSession 41 - Fast Functional SimulationSession 42 - Power Estimation and ModelingSession 43 - Technology Mapping for Programmable LogicSession 44 - Power Dissipation and Distribution in High Performance ProcessorsSession 45 - Challenge in the Test on System-On-A-Chip EraSession 46 - Controller Decomposition for Power and Area MinimizationSession 47 - IP Protection TechnologiesSession 48 - Case Studies of New Design Methods
AAagaard, M. D. 538Abadir, M. S. 534Abidi,A. 44Albrecht, T. W. 808Alpert, C. J. 362Amir, C. 392Amon, T. 586Anderson, J. H. 698Arakida, H. 483Arnout, G. 174Arsintescu, B. G. 38Ashar, P. 194Aulagnier, P. 327Aylor, J. H. 236Aziz,A. 615,664
BBaez, F. 732Bajwa, R. S. 242Banerjee, P. 279, 611,672Barrett, C. W. 522Bauer, J. 668Bearden, D. 738Bechtolsheim,A. 578Beerel, P. A. 506,605Beers, B. 501Benini, L. 182,718, 764Berekovi c, M. 56Bershteyn, M. 668Bhawmik, S. 554Biro, L. L. 726Blaauw, D. 388,738Blinzer, P. 794Bogliolo,A. 182Bolsens, I. 315Borriello, G. 88, 140, 586Brayton, R. K. 122, 348, 580Breuer, M. A. 548Brockman, J. 382Brodersen, R. 1Brown, D. 638Brown, R. B. 275Brown, S. 66Brown, S. D. 698Brown, T. 650Buch, P. 368Bustami, T. 566
CCano, F. 572Caranci, S. 66Carlson,R. 656Carro, L. 32Catthoor, F. 76Chan, F. L. 146Chandrakasan,A. 495Chang, S.-C. 342
Chappell, B. 100Charbon, E. 38Chen, J. C. 402Chen, K.-C. 632Chen, R. Y. 242Chen, Z. 489, 678Cheng, C.-K. 473Cheng, D. I. 342Cheng, K.-T. 632Chiang, F.-Y. 722Cho, J.-H. 800Choi, H. 170Chou, M. 20Chou, P. 88Choudhury, U. 38Collett, R. E. 578Cong, J. 330,356, 704Cooper, L. 656Corporaal, H. 82Cortadella, J. 2Croes, K. 76Cuatto, T. 804Culetu, J. 392
Dda Silva Jr., J. L. 76Dai, W. W. M. 224Damiano,A. 804Danneels, J. 1Dartu, F. 595Dasdan,A. 263de Geus,A. 1de Jong, G. 76De, V. 489De Man, H. 76De Micheli, G. 14,182, 764de Veciana, G. 251Demir, A. 26,414Dengi, E. A. 218Desai, M. P. 230Devadas, S. 152, 510,528Devgan,A. 362,477Dey, S. 542, 750Dharchoudhury, A. 388, 738Dill, D. L. 328, 451, 522, 599Director, S. W. 134Dobkin, B. 250Dohm, N. 638Drako, D. 656Drechsler, N. 200Drechsler, R. 200Dufresne, M. 650Dunlop,A. 414
EEdwards, T. 388Eisenmann, H. 269El-Maleh,A. 625
Engels,M. 315Evans,A. 650
FFallah, F. 152,528Fang, W.-J. 283Feldmann, P. 414Friedman, E. G. 560Fujita, M. 694
GGajski, D. D. 812Garcia, R. 750Ghosh, I. 542, 554Gong, J. 812Govindaraju, S. G. 451Gowan,M. K. 726Grbic, A. 66Grießing, A. 396Grindley, R. 66Grinwald, R. 158Guerra, L. 309Günther, W. 200Guo, J.-H. 251Gupta, R. K. 263Gupta, S. K. 548Gusat,M. 66
HHa, S. 118Hachtel, G. D. 457Hall, D. H. 230Hall, G. 650Hamada,M. 483Hanono, S. 510Harding, J. 1Harel, E. 158Hasteer, G. 611Hattori, T. 246Hauck, S. 788Haznedar, H. 572Heinrich, M. 658Henkel, J. 188Herrmann,K. 50Hilbert, J. 501, 578Hildebrandt, S. 638Hilfinger, P. 70Hilgenstock, J. 50Hines, K. 140Hinrichs, W. 56Hinsberger, U. 206Hirose, F. 327Ho, T. 650Holtmann, U. 794Hong, I. 176Hong, Y. 506
818
Conference Author/Panelist Index
Horowitz, M. A. 451Houghton, C. 100Hu,A. J. 451Hu, C. 402Huang, J.-D. 712Huang, S.-Y. 632Huggins, J. 638Hussain, S. Z. 744Hwang, C.-S. 800Hwang, J.-M. 722Hwang, S.-H. 800Hwang, T. 722
IIenne, P. 396Igarashi, M. 483Irwin, M. J. 242Ishikawa, T. 483Ismail, Y. I. 560
JJackson, D. B. 726Jacome, M. 251James, F. 250Jao, W. 433Jha, N. K. 102, 108, 439, 542, 554Jiang, J.-H. R. 712Jiang, W. 619Johannes, F. M. 269Johnson, M. 489Johnson, V. L. 174Jones, R. B. 538Jou, J.-Y. 712Jurecska,A. 804
KKahng, A. B. 776,782Kakani, N. 212Kalavade, A. 257Kamon, M. 297Kanazawa,M. 483Kang, S.-M. 291Kao, J. 495Kao, W. H. 38Kaplan, I. 668Kapur, S. 224, 414Karkowski, I. 82Kassab, M. 625Kay, R. 463Keutzer, K. 152, 528Kim, B.-W. 800Kim, I.-H. 800Kim, J.-S. 800Kim, J.-S. 800Kim, J.-Y. 800Kim, N. 170Kim, T. 433Kim, V. 672Kin, J. 321Kirovski, D. 176, 427Kishinevsky, M. 2Klenke, R. H. 236Kloos, H. 56
Kneip, J. 56Knol, S. 788Kolla, R. 206Kondratyev, A. 2Korupolu, M. R. 708Krauter, B. 303Kravets, V. N. 336Krishnamurthy, N. 534Kukimoto, Y. 348, 580Kukula, J. 615Kumthekar, B. 718Kundert, K. 250Kung, D. S. 352Kuroda, T. 483Kwak, B. 690Kwon, Y.-S. 800Kyung, C.-M. 170,800
LLach, J. 776L a k s h m i n a raya n a , G. 1 0 2 , 1 0 8 ,4 3 9Lavagno,L. 506, 804Lee, C. 321Lee, D.-H. 800Lee, J.-Y. 800Lee, K. K. 708Lee, K.-M. 800Lee, S. 170Lee, S. 170Lee, Y.-H. 800Leeser, M. 114Leif Rosqvist, L. 578Lekatsas, H. 516Lemieux, G. 66Lev, L. 250Levitt, J. R. 522Li, T. 291Li, Y. 188Lieske, H. 56Lillis, J. 368Lin, B. 502Lioy, A. 764Liu, F.-J. 473Liu, J. 212,586Liu, Y. 469, 650Lokanathan,A. 382Long, D. E. 224, 414Lou, J. 128Loveless, K. 66Lu, J.-Y. J. 632Luo, Y. 664
MMacDonald, J. 70, 100, 392Macii, E. 718, 764Madden, P. H. 356Madhavan, R. 656Majors, S. 566Malachowsky, C. 578Malavasi, E. 38Malik, S. 194Malka, Y. 644Mangione-Smith, W. H. 321, 776Manjikian, N. 66Mannan, M. 250
Mantik, S. 776, 782Marantz, J. 164Marinissen, E. J. 750Markov, I. L. 776, 782Marques, N. 297Martonosi, M. 194Masleid, B. 100Massoud, Y. 566Mathewson, B. 750Mathur, A. 611McBride, J. 100McGraw, R. 236McMillan, K. L. 445Mehrotra,A. 26Mehrotra, S. 303Mehta, G. 732Melville, R. 414Meyer, W. 770Miranda,M. 76Moghé, P. 257Monteiro, J. C. 758Murgai, R. 694
NNaidu,A. 501Najm, F. N. 591Nam, S.-J. 800Narayan, S. 812Narendra, S. 495Narita, S. 246Nassif, N. 230Nastov, O. J. 477Negreiros, M. 32Nemani, M. 591Neves, J. L. 560Newton,A. R. 70, 146Nguyen, T. V. 477Niggemeyer, D. 50Nitta, Y. 246Norton, J. 388Notbauer, J. 808NS, N. 572
OOdasso, G. 764Ofelt, D. 658Oh, J. 287Oh, M. 118Ohmacht, M. 56Oliveira,A. 694Oliveira,A. L. 758Olukotun,K. 658Orgad, M. 158Orshansky, M. 402Otten, R. H. J. M. 122Otterstedt, J. 50Overhauser, D. 744Owens, R. M. 242
PPaleologo, G. A. 182Panda, R. 388, 738Parakh, P. N. 275
819
Pardo,A. 457Park, E. S. 690Park, I.-C. 170,800Park, K.-H. 800Park, K.-I. 800Parulkar, I. 548Passerone, C. 804Passerone, R. 8Patel,R. 732Payer, M. 327Payne, B. 501Pedram, M. 128, 287, 684Pileggi, L. T. 463, 469, 595Pirsch, P. 50, 56Poncino, M. 764Potkonjak, M. 176, 309, 321, 427,
776, 782
QQiu, Q. 684Qu, G. 176Quay, S. T. 362Quinn, M. 638
RRabaey, J. M. 62, 309Rael, J. 44Raghunathan,A. 108Rajgopal, S. 732Rajski, J. 625Ramanathan, D. 263Ramey, C. 638Ravi, K. 445Razavi, B. 408Reed, L. J. 501Rhines, W. 1Rijnders, L. 315Rochel, S. 744Rofougaran,A. 44Rohrer, R. A. 218Rohringer, S. 808Rose, F. 174Rowson, J. A. 8, 174Roy, K. 489, 678Roy, R. 750Roychowdhury, J. 26, 414Rutenbar, R. 250Ryu,C.-H. 800
SSakallah, K. A. 275, 336Salek,A. H. 128Sangiovanni-Vincentelli,A. 8, 804Sanguinetti, J. 656Sansoè,C. 804Sarrafzadeh, M. 279Satomura, R. 246Sawkar, P. 348
Schaumont, P. 315Scheffer, L. 378Seawright,A. 770Sechen, C. 378Seger, C.-J. H. 538Seki, M. 246Sentovich,E. M. 506Seo, S.-W. 800Shepard, K. L. 94Shi, W. 212Shilman, M. 70Shiple, T. 615Shiple, T. R. 445Silbert,A. 327Silburt,A. 650Silveira,L. M. 297Singer, G. 1Singh, D. 732Six, P. 76Smith, J. 14Somenzi, F. 445, 718Spiller, M. D. 146Srbljic, S. 66Srini, V. P. 62Srivastava, M. B. 176Steele, G. 744Stibitz, M. 501Strojwas,A. J. 469Stumm, M. 66Sun, D. 619Sutton, P. R. 134Sutton, R. A. 62
TTabbara,A. 70Takahashi, M. 483Takahashi, T. 246Tarafdar, S. 114Taylor, S. 638Terazawa, T. 483Thomas, J. 578Tiwari, V. 732Tjiang, S. 433Tseng, H.-P. 378Tucker, P. 776,782Tutuianu, B. 738
UUchiyama, K. 246Ur, S. 158Usami,K. 483
VVahid, F. 812Vaidyanathan, R. 738Van Tassel, J. 327Verkest, D. 76
Vernalde, S. 315Vinnakota, B. 619Vranesic, Z. 66Vrckovnik, G. 650Vyedin, P. 668
WWang, H. 776, 782Wang, L.-C. 534Wang, M. 279Wei, L. 489White, J. 20, 297, 566Widdoes, C. 656Wittenburg, J. P. 56Wolf, W. 516Wolfe, G. 776, 782Wong, D. F. 374,708Wongsonegoro, T. 664Wu,A. C.-H. 283Wu,C. 330Wu, Q. 684Wuytack, S. 76
XXie, A. 605Xu, S. 704
YYang, C. H. 599Yang, J.-H. 800Ykman-Couvreur, C. 76Yoon,H.-D. 800Yoshizawa, H. 501Young, D. 572Young, J. S. 70Yu, T. 212Yuan, F. Y. 421
ZZhang, X. 100Zhao, J. 224Zhong, P. 194Zhou, H. 374Zilic, V. 66Ziv, A. 158, 644Zorian, Y. 750, 752
820