a.1. aes cryptography_pdf

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    RV-VLSIDesignCenter

    BEProjects2012

    DigitalsignatureimplementationusingAESalgorithmforsecurecommunicationProjectDescription:Adigitalsignatureordigitalsignatureschemeisamathematicalschemefordemonstratingtheauthenticityofadigitalmessageordocument.Avaliddigitalsignaturegivesarecipientreasontobelievethatthemessagewascreatedbyaknownsender,andthatitwasnotalteredintransit.Digitalsignaturesarecommonlyusedforsoftwaredistribution,financialtransactions,andinothercaseswhereitisimportanttodetectforgeryortampering.

    AdvancedEncryptionStandard(AES)isaspecificationfortheencryptionofelectronicdata.Itisavailableinmanydifferentencryptionpackages.AESisbasedonadesignprinciple

    knownasaSubstitutionpermutationnetwork.Itisfastinbothsoftwareandhardware.OriginallycalledRijndael,thecipherwasdevelopedbytwoBelgiancryptographers,JoanDaemenandVincentRijmen,andsubmittedbythemtotheAESselectionprocess.

    AEShasafixedblocksizeof128bitsandakeysizeof128,192,or256bits,whereasRijndaelcanbespecifiedwithblockandkeysizesinanymultipleof32bits,withaminimumof128bits.Theblocksizehasamaximumof256bits,butthekeysizehasnotheoreticalmaximum.

    AESoperatesona44column-majorordermatrixofbytes,termedthestate(versionsofRijndaelwithalargerblocksizehaveadditionalcolumnsinthestate).MostAEScalculationsaredoneinaspecialfinitefield.TheAEScipherisspecifiedasanumberofrepetitionsoftransformationroundsthatconverttheinputplaintextintothefinaloutputofciphertext.Eachroundconsistsofseveralprocessingsteps,includingonethatdependsontheencryptionkey.Asetofreverseroundsareappliedtotransformciphertextbackintotheoriginalplaintextusingthes

    ameencryptionkey.

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    Blockdiagram:

    Name

    Type

    Description

    CLK

    Input

    Coreclocksignal

    EN

    Input

    Synchronousenablesignal.WhenLOWthecoreignoresallitsinputsandallitsoutputsmustbeignored.

    Start

    Input

    WhengoesHIGH,acryptographicoperationisstarted

    Load

    Output

    Inputdatarequestsignal

    Ready

    Output

    Outputdatareadyandvalid

    8-bitDataInterface

    KEY[7:0]

    Input

    EncryptionKey

    PT[7:0]

    Input

    InputPlainTextData

    CT[7:0]

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    Output

    OutputCipherTextData

    ToolEnvironment:QuartusII,QuestaSim,ALTERAFPGAboards,Cables,PCScopeofProjectinIndustry/Applications:

    1.Communicationsystems2.Internetsecurity

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    ProjectStages:

    1.Training2.Algorithmstudyanddevelopment3.RTLimplementationofalgorithmandverification4.RealizationonFPGAafterRTLisproven.5.Applicationfordemonstration(dependingontimeavailability)

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