a wideband digital tv receiver front-end with noise and distortion cancellation

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A Wideband Digital TV Receiver Front-End WithNoise and Distortion Cancellation

Donggu Im, Member, IEEE, and Ilku Nam, Senior Member, IEEE

Abstract—A low noise and highly linear wideband CMOS re-ceiver front-end for digital TV receivers is proposed. The proposedRF front-end comprises a wideband noise canceling common gatelow noise amplifier (LNA) with a capacitively cross-coupled cur-rent source, a highly linear up-conversion micromixer with third-order intermodulation distortion cancellation, and a highly linearsurface acoustic wave (SAW) driver with enhanced loop gain. TheRF front-end was fabricated using a 0.13 m CMOS process andit draws 27 mA from a 1.5 V supply voltage. It achieves a voltagegain of 23 dB, a noise figure of less than 4 dB, an IIP3 of greaterthan 6.5 dBm, and an IIP2 of greater than 28 dBm across the en-tire input band from 54 MHz to 882 MHz.

Index Terms—CMOS, distortion cancellation, front-end, micromixer, noise cancellation, TV receiver, wideband.

I. INTRODUCTION

I N MANY countries, analog TV broadcasting services arebeing replaced by digital TV (DTV) broadcasting services,

because DTV signals have advantages of high quality and band-width efficiency. Accordingly, DTV tuners are expected to be-come leaders in the TV tuner market. Most terrestrial and cableDTV standards such as Digital Video Broadcasting (DVB) andAdvanced Television Systems Committee (ATSC) use broad-band frequencies from 54 MHz to 882 MHz. This wideband na-ture of broadcast signals causes two technical bottlenecks thatdo not exist in the conventional narrowband receivers: second-order intermodulation distortion problems and local oscillator(LO) harmonic mixing problems [1]–[3]. The second-order in-termodulation distortion problem can be solved using differen-tial circuits or by adopting a second-order intermodulation dis-tortion canceling technique [4]. In order to solve the LO har-monic mixing problem, various receiver architectures have beendeveloped. The single conversion receiver with a harmonic re-jection mixer (HRM) has been a good candidate due to its highintegration [3]. Unfortunately, because the HRM alone cannot

Manuscript received December 01, 2012; revised May 10, 2013; acceptedJune 14, 2013. This work was supported by Basic Science Research Programthrough the National Research Foundation of Korea (NRF) funded by the Min-istry of Education (NRF-2013R1A1A2011732). This paper was recommendedby Associate Editor A. Mazzanti.D. Im was with the Department of Electrical Engineering, Korea Advanced

Institute of Science and Technology, Daejeon 305-701, Korea. He is now withthe Texas Analog Center of Excellence, Department of Electrical Engineering,University of Texas, Dallas, TX 75080 USA (e-mail: [email protected]).I. Nam is with the Department of Electrical Engineering, and also with

PNU-LG Electronics Smart Control Center, Pusan National University, Busan609-735, Korea (e-mail: [email protected]).Digital Object Identifier 10.1109/TCSI.2013.2278386

achieve a harmonic rejection ratio (HRR) of over 60 dB due tosome gain and phase mismatches [5], a low noise and highlylinear tunable filter is required in front of the HRM to suppressthe residue LO harmonics. However, it is very difficult to de-sign a wide dynamic range tunable filter with a wide frequencytuning range. For integrated active tunable filters such as the

filter [6] or a harmonic-rejecting LNA [7], its linearityperformance is not sufficient to meet the stringent requirementsfor the DTV receiver despite its heavy power consumption. Onthe other hand, passive tunable filters that adopt digitally con-trollable switched capacitor arrays have excellent linearity andlow noise performances [8], but they employ several off-chipinductors. In addition, these tunable filters require calibrationalgorithms and circuits for the center frequency tuning in orderto compensate the process, voltage, and temperature (PVT) vari-ations.The dual conversion (up and down conversions) receiver

of Fig. 1 is another candidate for a wideband DTV tuner[9]–[11]. With the use of an external SAW bandpass filter(BPF), it provides robust harmonic rejection and interferencesuppression due to the sharp skirt characteristic of the SAWfilter. In particular, if the up-conversion receiver front-end infront of the SAW BPF is highly linear, the dual conversionreceiver is more resilient to noisy interference environmentswith large undesired-to-desired signal (U/D) ratios such as theGSM850 and GSM900 interoperability in the DVH-T/H mode.In a single conversion receiver, because the allowed outputvoltage swing of the down-conversion mixer according to alarge blocker limits the maximum gain of the RF front-end,the sensitivity becomes degraded due to the high noise of thefollowing analog baseband (ABB) chain. However, in the dualconversion receiver, the SAW BPF suppresses a large blockersignal and as a result the down-conversion mixer can havesufficiently high gain to suppress the noise contribution of theABB chain.A low noise and highly linear up-conversion receiver

front-end is an essential building block for a wideband dualconversion TV receiver. In order to obtain high sensitivity, theup-conversion receiver front-end should have a sufficientlyhigh gain and low noise figure (NF). In addition to the in-herent noise of the receiver, the digital switching noise fromthe crystal, data converter, and digital signal processing unitdirectly degrades the sensitivity. The digital TV receiver isvulnerable to the switching noise because the desired channelin the VHF band is very close to the clocking frequency.Therefore, an inductor-less LNA is desirable in order to reducethe digital switching noise coupled to the LNA due to the lowimpedance level of the RF inductors in the low frequency band( 54 MHz) [12].

1549-8328 © 2013 IEEE


2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

Fig. 1. Up-conversion receiver front-end architecture for dual (up and down) conversion TV receiver.

In order to meet the ATSC A/74 specification [13], the re-ceiver must manage strong blockers without suffering from de-sensitization; hence, linearity is a key performance factor. Forcable TV applications, because hundreds of unfiltered channelsenter the receiver, the second-order intercept point (IIP2) as wellas the third-order intercept point (IIP3) should be as high as pos-sible in order to satisfy the linearity requirements [14].In this paper, a low noise and highly linear wideband CMOS

up-conversion receiver front-end is presented as part of amulti-standard dual conversion DTV receiver. The buildingblocks presented in this paper can be adopted in other appli-cations such as ultra wideband (UWB) receiver front-ends,software defined radios (SDRs), and traditional transmitterfront-ends. Section II describes the architecture and RF specifi-cations of the up-conversion receiver front-end. In Section III,the conventional wideband common gate (CG) LNAs arereviewed and then a new wideband noise canceling CG LNAthat does not have RF choke inductors is proposed. Next,a highly linear up-conversion micromixer using third-orderintermodulation (IM3) distortion cancellation and a highlylinear SAW driver with an enhanced loop gain are describedin Sections IV and V, respectively. Section VI presents theexperimental results for the proposed up-conversion receiverfront-end, followed by conclusions in Section VII.

II. ARCHITECTURE AND RF SPECIFICATIONS OFUP-CONVERSION RECEIVER FRONT-END

The up-conversion receiver front-end is composed of a wide-band LNA, an up-conversion mixer, and a SAW driver. Thisfront-end converts input signals in the frequency range from 54MHz to 882MHz to a common frequency of 1160MHz. In orderto provide an RF SAW BPF with stable termination impedanceand to compensate for its insertion loss, a highly linear SAWdriver is situated immediately after the up-conversion mixer.Table I presents the RF specifications of the up-conversion re-

ceiver front-end for digital TV applications. In the dual conver-sion receiver architecture, since the SAW driver and SAW filterusually cause the voltage loss of approximately 10 dB, the LNAand up-conversionmixer should provide high gain in order to re-duce the noise contribution of the following blocks. However, avery high gain of the RF front-end degrades the gain bandwidthand linearity of the receiver. Therefore, in this specification, the

Fig. 2. Calculated signal-to-noise ratio (SNR), composite triple beat (CTB) andcomposite second-order (CSO) distortions of the digital TV receiver with RFspecifications presented in Table I.

TABLE IRF SPECIFICATIONS OF UP-CONVERSION RECEIVER FRONT-END FOR DIGITAL

TV APPLICATIONS

signal-to-noise ratio (SNR) degradation by 0.5 dB due to thedown converter (down-conversion mixer ABB chain) with theNF of 15 dB is allowed, and the minimum voltage gain of the RFfront-end (LNA up-conversion mixer SAW driver SAWfilter) is calculated as 22 dB. As shown in Fig. 2, the dual con-version receiver with RF specifications presented in Table I hasa SNR of 18.3 dB and satisfies a minimum SNR of 16 dB inorder to receive weak signal less than 84 dBm in the terres-trial mode.


IM AND NAM: A WIDEBAND DIGITAL TV RECEIVER FRONT-END WITH NOISE AND DISTORTION CANCELLATION 3

Fig. 3. (a) Differential common gate (CG) LNA, (b) generic -boosted CG LNA, and (c) capacitively cross-coupled CG LNA.

For the cable mode, the linearity specifications such as thecomposite triple beat (CTB) and composite second-order (CSO)distortions are more stringent [14]. The theoretical relationshipbetween CTB (CSO) and IIP3 (IIP2) is derived in [14]. Undera fully loaded spectrum condition of 137 multi-tones, each ofwhich has a power of 33 dBm, the receiver should satisfy si-multaneously the CTB and CSO of less than 55 dBc and theSNR of 50 dB. As the gain of the RF front-end is reduced, boththe IIP3 and IIP2 increase, while the NF degrades. This indicatesthat the CTB and CSO are improved, whereas the SNR is de-graded. Therefore, the linearity specification of the RF front-endfor the cable mode should be represented by the output-referredIP3 (OIP3) and output-referred IP2 (OIP2). As shown in Table I,the LNA with the OIP3 of 19 dBm and up-conversion mixerwith the OIP3 of 29 dBm are required in order to achieve theCTB of less than 55 dBc. In this circumstance, the gain andNFshould be considered to satisfy the required SNR of 50 dB. TheOIP3 of the SAW driver is relatively relaxed due to out-of-bandfiltering by the LC load of the up-conversion mixer. Throughthe system simulation, the OIP3 of 25 dBm is required for theSAW driver in order to maintain the CTB performance at theoutput of the up-conversion mixer. On the other hand, in orderto achieve the CSO of less than 55 dBc, the OIP2 of more than55 dBm is required for all building blocks of the up-conversionreceiver front-end.All building blocks adopt a fully differential topology in order

to meet the stringent OIP2 specification and to render the circuitless susceptible to digital switching noise. For the up-conver-sion mixer, the active mixer topology is chosen due to its higherconversion gain and lower NF compared with the passive alter-natives. In a wideband LNA, the need for a high gain to com-pensate for the signal loss from the passive mixer severely de-grades the linearity and gain bandwidth of the receiver. There-fore, the highly linear micromixer topology is adopted becauseit has a wideband nature and high linearity compared with theGilbert-type mixer [15]–[17]. In addition, because the linearityburden lies in the up-conversion mixer and SAW driver, the lin-earization technique is adopted to these building blocks.

III. WIDEBAND NOISE CANCELING CG LNA

A. Review of Conventional Wideband LNAs

Among the various known wideband LNA topologies suchas the distributed amplifier (DA) [18], CG amplifier [19], andfeedback amplifier [20], CG LNAs are the most widely used due

to their good wideband input impedance matching and high lin-earity [21], [22]. Fig. 3 presents the schematics of a conventionaldifferential CG LNA, generic transconductance -boostedCG LNA, and capacitively cross-coupled CG LNA. The com-parison of the RF performances among these CG LNA topolo-gies has been reported in [23].For the differential CG LNA shown Fig. 3(a), even if the

noise generated by the load is ignored, the NF goes be-yond 4 dB due to the power matching constraint. In order toreduce the noise contribution of the input transistor , the-boosted CG LNA shown in Fig. 3(b) was introduced [19],

[21]. The feedforward path of gain enhances the effectivetransconductance of and improves the noise performance.The NF of the -boosted CG LNA is reduced by a factor of

compared with the CG LNA shown in Fig. 3(a) [19],[21]. However, the additional noise introduced by the auxiliaryvoltage gain amplifier degrades the overall NF of the LNA [24].This additional noise could be addressed through the use of aninductive transformer [22]; however, a large extra silicon areawould be required. Practically, this -boosting technique isonly useful for the capacitively cross-coupled differential CGLNA shown in Fig. 3(c), where the unit voltage gainis achieved easily using the naturally differential signaling.The differential voltage gain , input impedance

, and noise factor of the capacitively cross-cou-pled CG LNA are as follows [21], [23]:

(1)

(2)

(3)

where denotes the ratio of thermal noise at any given drainbias to the value of the thermal noise at V, is equalto , where is the channel conductance atV [25]. Compared with the differential CG LNA, the dominantnoise contribution by is halved; this can be explained from anoise-canceling point of view [26]. Nevertheless, the overall NFof the capacitively cross-coupled CG LNA remains greater than3 dB for a typical of 4/3 as a result of the noise contributionfrom the load . In order to suppress the noise contributionfrom the load , the CG LNA should have a high value for ;however, a high value reduces the voltage headroom, linearity,and bandwidth of the LNA. Moreover, it is difficult to target ahigh value because the loading stage (e.g., passive mixerand micromixer) usually limits the output impedance to a lower



Fig. 4. Proposed wideband noise canceling CG LNA.

value. In order to avoid the loading effect of the up-conversionmixer, a wideband CG LNA merging with an inter-stage bufferis proposed.

B. Wideband Noise Canceling CG LNA Without RF ChokeInductors

Fig. 4 presents the proposed wideband noise canceling CGLNA; a version without was developed in our previousstudies [27], [28]. In Fig. 4, the noise voltage waveforms at eachnode according to the channel thermal noise current ( ; leftside in a differential pair) are presented in order to demonstratehow the noise is canceled while maintaining the signal strong.The generates noise voltages and withthe same polarity at nodes IP and IN, respectively. Becausethe polarity of the noise voltage at the diode-connected load

opposes that of the noise voltage at the LNA input, perfectnoise cancellation for the noise current is achieved at theoutput by adding two paths, i.e., the CG path with currentamplification and the common source (CS) path, with equalgain. When the input impedance is well matched to the sourceimpedance , the condition for aperfect noise cancellation is given by:

(4)

where is the current mirror ratio.Many LNA topologies involving a CS path (negative gain)

and a CG path (positive gain) for noise cancellation have beenreported [29]–[31]. Compared with these LNAs, the proposednoise canceling LNA with current amplification has somemerits. Firstly, the noise cancellation is relatively robust toPVT variations because equation (4) is wholly determinedby the transconductance ratio of the same kind of MOSFETs.Secondly, the proposed LNA reuses the dc current flowingthrough the CS and CG paths for the current mirror amplifierof the combining network, while other LNAs consume extra dccurrent for the combining network. Considering that the currentmirror amplifier without the voltage-to-current con-version process is quite linear [32], the proposed LNA achieveshigh gain and OIP3 with low power consumption. Thirdly,the proposed LNA is very suitable for driving low impedance

Fig. 5. Overall NF of the proposed LNA according to the variation of thefor and 4. The CCCG LNA denotes capacitively cross-cou-

pled CG LNA of Fig. 3(c).

loads, such as a switching passive mixer and micromixer,without requiring additional inter-stage buffers.Under the condition expressed in equation (4), the andof the proposed noise canceling LNA are derived as follows:

(5)

(6)

where is the load impedance, and the excess noise factorsand denote the noise contributions

of , and . From (6), the noise contribution of loadfor the proposed noise canceling CG LNA is reduced by a

factor of compared with that of the capacitively cross-cou-pled CG LNA shown in Fig. 3(c). Fig. 5 presents the overall NFof the proposed LNA according to the variation of thewhen is 1, 2, 3, and 4. Because the input impedance of themicromixer is in the range of 50 to 200 in order to achievereasonable gain bandwidth, linearity, and noise performances,the load in equation (6) is set equal to 100 . Under theallowed gain bandwidth and voltage headroom, it is desirableto reduce the in order to suppress the noise contributionfrom the diode-connected load . In this design, theis approximately 0.1 at an of 37.5 . As shown in Fig. 6, anincrease in leads to a decrease in NF and an improvement inthe voltage gain, but it results in the increment of the power con-sumption due to the dc current amplification. In order to achievean overall NF of less than 3 dB, a current mirror ratio ofgreater than 2 is required.As mentioned above, the proposed LNA has a relatively high

OIP3 due to the current amplification. For the current mirror,long channelMOSFETs are desirable in order to reduce the non-linearity as well as noise because the main nonlinearity sourcesof the current mirror that affect the linearity of the LNA are thetransistor mismatch and channel length modulation. As with thenoise, the nonlinearity generated from the CG amplifier iscanceled out [31]. This indicates that the distortion performanceof the total LNA is determined by that of the CS amplifier .



Fig. 6. Calculated NF and voltage gain of the LNA versus the current mirrorratio . It is assumed that the and are 0.1 and 100 , respectively.

As a result, in order to improve the linearity of the LNA, theoverdrive voltage of the should be higher while satisfying(4).For DTV receiver applications, it is desirable to eliminate the

external RF choke inductors because they make the LNA sus-ceptible to digital switching noise due to their low impedancecharacteristics in the lower VHF bands ( 54 MHz) and theyalso increase the bill of materials (BOM) cost. Fig. 7 showsthe complete noise canceling CG LNA adopting a capacitivelycross-coupled current source (CCCS) instead of RF choke in-ductors. The CCCS was first introduced in [23] and [33]. Here,a CCCS is adopted instead of a simple current source withoutin order to reduce the required for the perfect thermal

noise cancellation of the input transistor . The of thecomplete LNA in Fig. 7 is expressed as follows:

(7)

and its is identical to that in (5). Assuming perfect inputimpedance matching , the condition for a per-fect noise cancellation is given by:

(8)

Compared with (4), the required is reduced fromto . This improves the linearity and gain band-width of the LNA due to the smaller width and higher overdrivevoltage of the transistor under the same current consump-tion.One interesting fact is that the channel thermal noise currentgenerated from the CCCS is partially canceled out at the

LNA output. The from (left side) generates input noisevoltages ( and ) and output noise currents (and ). Their magnitudes and polarities are given by:

(9)

Fig. 7. Complete noise canceling CG LNA adopting a CCCS to remove RFchoke inductors.

TABLE IIDESIGN PARAMETERS FOR NOISE CANCELING CG LNAS WITH RF CHOKEINDUCTORS AND A CAPACITIVELY CROSS-COUPLED CURRENT SOURCE

From (9), the output referred noise current according to iscalculated as follows:

(10)

We know that the partial noise cancellation occurs at the LNAoutput because the input noise voltage and output noisecurrent have the same polarity in opposite differentialbranch. Under the condition described in (8), the of the com-plete LNA is as follows:

(11)

Compared with the of the noise canceling CG LNA withRF choke inductors, the increment is approximately

. If the simple current source without is adoptedto the noise canceling LNA instead of the CCCS, the incre-ment becomes . Thus, the NF degradation by the currentsource is halved in the complete noise canceling CG LNA withof 2. The higher reduces the required for perfect

noise cancellation and as a result improves the bandwidth andlinearity of the LNA, but increases the noise contribution fromthe . Therefore, a design trade-off is required. In this design,the ratio of the to the is set to approximately 0.25.Table II summarizes the design parameters for the noise can-

celing CGLNAswith RF choke inductors and a CCCS. Becausethe characteristic impedance of a TV receiver is 75 is



Fig. 8. Simulated NF and IIP3 of the LNA with a CCCS. The noise summaryis simulated at 400MHz. The two-tone spacing for the simulated IIP3 is 6 MHz.

Fig. 9. Simulated voltage gain (from differential input to differential output)of two LNAs with RF choke inductors and a CCCS.

set as 75 for the input impedance matching. Based on theseparameters, the calculated NF and the simulated NF at the of37.5 are compared. Assuming that ranges from 1 to 4/3[34], the calculated NF is well matched to the simulated NF.The CCCS degrades the NF by approximately 0.2 dB in boththe calculation and the simulation. Fig. 8 presents the simulatedNF and IIP3 of the LNA with a CCCS over the TV frequencybands. From 50 MHz to 1 GHz, the simulated NF is less than3 dB. As predicted, in the simulated noise summary showingthe noise contributions of each component to the total outputnoise of the LNA, there is no contribution from the CG amplifier

due to the perfect noise cancellation. The linearity exhibitsa typical IIP3 of 0 dBm over the TV frequency bands. Fig. 9shows the simulated voltage gain (from the differential input tothe differential output) of two LNAs with RF choke inductorsand a CCCS. The LNA with a CCCS has a wider bandwidththan the LNA with RF choke inductors while achieving perfectnoise cancellation for the .

IV. HIGHLY LINEAR UP-CONVERSION MICROMIXER

Fig. 10 shows the up-conversion differential micromixeradopting the IM3 distortion cancellation. This micromixer issuitable for wideband input matching and has a flat gain overa wide operating frequency range, which is attributed to theCG input stage. The differential topology leads to a high IIP2performance.

Fig. 10. Proposed up-conversion micromixer with IM3 distortion cancellation.

If ideal switching is assumed in the LO switches of theup-conversion mixer, the gain of the up-conversion mixercan be expressed as follows:

(12)

The output noise voltage of the up-conversion mixer canbe calculated as ,where is the noise generated in the transconductors( , and ), is that in the switching transistors( , and ), and is that in the load resistor

. Here, can be expressed as follows:

(13)

where is the bandwidth in hertz. The output noise voltagespectral density attributed to the switching pair and load resistor( and , respectively) can be approximated asfollows:

(14)

(15)

where is the drain conductance of the switching tran-sistor at V, and factor 4 in (14) originates from the fourswitching transistors ( , and ). Fig. 11 shows thesimulated NF of the proposed micromixer with the IM3 distor-tion cancellation.If the transconductor’s nonlinearity is assumed to dominate

the linearity of the up-conversion mixer, the IM3 distortion cur-rent of the transconductor should be minimized in order to im-prove the linearity of the up-conversion mixer. The IM3 dis-tortion current of the up-conversion mixer’s transcon-ductor in Fig. 10 can be expressed as follows:

(16)



Fig. 11. Simulated NF of the proposed up-conversion micromixer.

Fig. 12. Simulated OIP3 of the proposed up-conversion micromixer with IM3distortion cancellation.

Fig. 13. Simulated OIP3 of the proposed micromixer over process and temper-ature variation. TT, FF, and SS stand for typical, fast, and slow model, respec-tively.

where is the small signal input voltage of the mixer andis the second derivative of the transconductance [35].

A high IIP3 value can be obtained if the magnitude ofis minimized by selecting an appropriate aspect ratio

and bias for , and . Fig. 12 shows the simulated OIP3of the proposed micromixer with the IM3 distortion cancella-tion and the conventional micromixer without the IM3 distor-tion cancellation under the same current consumption. For a faircomparison, the two micromixers are designed to have a gainof approximately 13 dB under the same current consumption.

Fig. 14. Two voltage followers with negative feedbacks such as a flippedvoltage follower (Loop A) and a super source follower (Loop B) for the SAWdriver.

The conventional micromixer uses an identical aspect ratio for, and , and then the magnitude of is

not minimized. As shown in Fig. 12, the proposed micromixerachieves a 7.5 dB of OIP3 improvement. Fig. 13 shows thesimulated OIP3 of the proposed micromixer versus the processand temperature variation. The proposed micromixer provides astable OIP3 performance over the process and temperature vari-ation. The driving impedance of the SAW filter must be welldefined during operation in order to maintain the SAW filteringperformances. Therefore, a SAW driver is required to isolate theSAW BPF from the up-conversion micromixer and to providethe SAW BPF with 50 termination impedance.

V. HIGHLY LINEAR SAW DRIVER

For impedance matching with the RF SAW BPF, a SAWdriver with an output impedance of 50 is conventionallyadopted as the impedance transformer. Because the linearityburden lies in the last stage of the up-conversion receiverfront-end, high IIP2 and IIP3 values are required for the SAWdriver.A simple topology for a SAW driver is the differential

source follower (DSF). When a voltage follower drives theload impedance , its loop gain is expressed as ,where is the closed loop output impedance of the voltagefollower. This means that a smaller of the voltage fol-lower leads to better linearity thanks to the negative feedback.When the voltage follower drives a large , it maintainsrelatively high linearity due to the large loop gain. In contrast,when the voltage follower drives a small such as that of anRF SAW filter, its linearity is severely degraded due to the loopgain roll off. Therefore, it is important to reduce the ofthe voltage follower in order to maintain a large loop gain andhigh linearity when driving a low .Fig. 14 shows two voltage followers with negative feedbacks:

a flipped voltage follower (loop A) [36] and a super source fol-lower (loop B) [37]. The negative feedback decreasesand enhances the linearity of the voltage follower. The nega-tive feedback loops A and B can be simultaneously applied toa conventional DSF in order to achieve significant linearity en-hancement. While the of the DSF is , theof the voltage follower with loops A and B is reduced to ap-proximately at lowfrequencies, where and respectively de-note the transconductance and output resistance of transistors

, and .



Fig. 15. Proposed voltage follower with enhanced loop gain.

Fig. 16. Simulated linearity performances of the DSF, voltage follower withloops A and B in Fig. 14, and proposed voltage follower in Fig. 15 when the

is 50 . Two tones at 1100 MHz and 1200 MHz with 10 dBm of powerare used.

Fig. 17. Chip photograph of the proposed up-conversion receiver front-end.

Unfortunately, the linearity improvement is limited by theloop gain roll off at high frequencies. The frequency responseof the loop gain is given by

(17)

where and denote the total resistance and capaci-tance at node X, respectively, and is approximated by

. For a of 70 mS, a of 15 mS, anda of 500 fF, the loop gain is approximately 23 at 1.16

Fig. 18. Measured input and output reflection coefficients ( and ) of theup-conversion receiver front-end.

Fig. 19. Measured power gain and NF of the up-conversion receiver front-end.

GHz. Under the power consumption and stability constraints, aremarkable improvement in the loop gain cannot be achievedthrough transistor sizing due to the severe tradeoff between thetransconductance and capacitance.The voltage follower presented in Fig. 15 is proposed to in-

crease the loop gain without sacrificing the current consumptionand stability. By injecting the signal at node X into the oppo-site current source , the effective in feedback loop Ais doubled without additional current consumption. Clearly, thetotal is slightly increased by , but this increase is negli-gible due to the small width of transistor . The andhave identical sizes. Because the is much greater than the

in typical designs, the loop gain of the proposed voltagefollower is approximately twice that of the previous one shownin Fig. 14 at the desired RF frequency. A chip resistorof approximately 25 is added in series at each differentialoutput for impedance matching with the RF SAW BPF becausethe output impedance of the proposed voltage follower is closeto 0 .Fig. 16 presents the simulated linearity of the DSF, the voltage

follower with loops A and B in Fig. 14, and the proposed voltagefollower in Fig. 15 when the load impedance is 50 . Fora fair comparison under 50 output impedance matching, thevalue of is set to 40 mS for all topologies and the chip re-sistor of 25 is added to the voltage followers in Figs. 14



TABLE IIIMEASUREMENT SUMMARY AND COMPARISON WITH PREVIOUS WORKS

Fig. 20. Measured IIP3 (OIP3) and IIP2 (OIP2) of the up-conversion receiverfront-end.

and 15. As predicted, the voltage followers with a negative feed-back have excellent linearity compared with the DSF. In addi-tion, the proposed voltage follower improves the IIP3 by 4 dB,without additional power consumption compared with that ofthe voltage follower shown in Fig. 14.

VI. EXPERIMENTAL RESULTS

The proposed up-conversion receiver front-end was imple-mented using a 0.13 m CMOS process as part of a DTVreceiver. Fig. 17 shows the chip photograph of the proposedup-conversion receiver front-end and its chip core size is 0.73mm 0.95 mm. The LNA, up-conversion micromixer, andSAW driver consumes 7 mA, 7 mA, and 13 mA, respectively,at a supply voltage of 1.5 V. The total current consumptionis approximately 27 mA. The proposed receiver front-endwas measured using chip-on-board packages on a 1.13 mmthick FR4 substrate. A wideband 1:1 balun of M/A-COM’sMABA-007871 is used at the input port for the differentialoperation during the test. Its typical insertion loss is approx-imately 0.5 dB over the TV bands. The insertion loss of theinput balun is de-embedded for the gain and NF of the receiverfront-end.

Fig. 18 shows the measured input and output reflection coeffi-cients ( and , respectively) of the up-conversion receiverfront-end. The measured is less than 10 dB over all TVbands, and near-perfect output impedance matching is achievedat an IF of 1160 MHz. This ensures predictable RF performancefor the external RF SAW BPF such as insertion loss, pass-bandripple, and out-of-band rejection characteristics. Fig. 19 showsthe measured power gain and NF of the up-conversion receiverfront-end. The input frequency was swept from 54 MHz to 882MHz while converting a constant IF of 1160 MHz. The averagegain is approximately 23 dB, and the 3 dB bandwidth in gainis greater than 1 GHz. The measured NF is less than 4 dB overthe TV bands, and a minimum NF of 3.3 dB is achieved at 400MHz.Two-tone measurements for the intermodulation distortion

were performed over the TV bands. The tone spacing used in thelinearity measurement was 6 MHz and 40 dBm of power wasapplied. For the second-order intermodulation (IM2) distortion,the component at the sum frequency of the two-tone interfererswas measured. As shown in Fig. 20, the IIP3 of 4.5– 6.5dBm (OIP3 of 16.5–18.5 dBm) and IIP2 of 28–36 dBm (OIP2of 52–60 dBm) are obtained. This linearity performance meetsthe stringent selectivity test patterns for DTV receivers, such asthe ATSC A/74, CTB, and CSO specifications.Table III summarizes and compares the performance of the

proposed RF front-end against those in other previous works.Due to the noise cancellation for the LNA, the distortion can-cellation for the up-conversion micromixer, and the loop gainenhancement for the SAW driver, the proposed RF front-endhas lower NF and higher linearity than previous designs, whileconsuming less power.

VII. CONCLUSION

This paper presents the implementation of a highly linear andlow noise broadband RF front-end for the DTV receivers using a0.13 m CMOS process. The proposed RF front-end consists ofa noise canceling CG LNA, an up-conversion micromixer withIM3 distortion cancellation, and a highly linear SAWdriver withan enhanced loop gain. Therefore, it obtains excellent sensitivity(low NF) and selectivity (high linearity) for DTV applications.



Thus, it is suitable as an up-conversion receiver front-end fora broadband digital terrestrial and cable TV receiver. In addi-tion, the proposed RF front-end adopting noise and distortioncancellation is applicable in conventional wideband receiversor transmitter front-end building blocks.

ACKNOWLEDGMENT

The authors would like to thank the reviewers for their valu-able comments and advice.

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Donggu Im (S’09-M’13) received the B.S., M.S.,and Ph.D. degrees in electrical engineering andcomputer science from the Korea Advanced Instituteof Science and Technology (KAIST), Daejeon, in2004, 2006, and 2012, respectively.His doctoral research focused on integrated RF

front-ends with antenna switch, power amplifier,directional coupler with transmitter leakage sup-pression, and tunable impedance matching circuitsin silicon-on-insulator (SOI) CMOS. From 2006 to2009, he was an Associate Research Engineer with

LG Electronics, Seoul, Korea, where he was involved in the developmentof universal analog and digital TV receiver ICs. From 2012 to 2013, he wasa Postdoctoral Researcher with KAIST, where he was responsible for thedevelopment of switch MOSFETs, power MOSFETs, and ESD devices of thefirst RF SOI CMOS technology in Korea. In 2013, he joined the Texas AnalogCenter of Excellence, Department of Electrical Engineering, University ofTexas at Dallas, as a Research Associate, where he is currently engaged in thedevelopment of ultra-low-power radios.

Ilku Nam (S’02–M’06–SM’13) received the B.S.degree in electronics engineering from YonseiUniversity, Seoul, Korea, in 1999, and the M.S.and Ph.D. degrees in electrical engineering andcomputer science from the Korea Advanced Instituteof Science and Technology (KAIST), Daejeon, in2001 and 2005, respectively.From 2005 to 2007, he was a Senior Engineer

with Samsung Electronics, Gyeonggi, Korea, wherehe was involved in the development of mobiledigital TV tuner IC. In 2007, he joined the School of

Electrical Engineering, Pusan National University, Busan, Korea, and is nowan Associate Professor. His research interests are CMOS RF/mixed-mode ICand RF system design for wireless communications.Prof. Nam was the recipient of the Bronze Medal in Korea Semiconductor

Design Contest in 2006 and the Junior Faculty Research Award of Pusan Na-tional University in 2009. Prof. Nam was a member of the technical programcommittees of the IEEE ASSCC in 2011 and the IEEE Wireless Symposium in2013.

a wideband digital tv receiver front-end with noise and distortion cancellation

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