wideband, low distortion driver amplifierthe kh561 is a wideband dc coupled, amplifier that combines...

Featuresn 150MHz bandwidth at +24dBm output n Low distortion

(2nd/3rd: -59/-62dBc @ 20MHz and 10dBm) n Output short circuit protection n User-definable output impedance, gain,

and compensation n Internal current limitingn Direct replacement for CLC561

Applicationsn Output amplificationn Arbitrary waveform generationn ATE systemsn Cable/line drivingn Function generatorsn SAW driversn Flash A/D driving and testing

General DescriptionThe KH561 is a wideband DC coupled, amplifier thatcombines high output drive and low distortion. Atan output of +24dBm (10Vpp into 50Ω), the -3dBbandwidth is 150MHz. As illustrated in the tablebelow, distortion performance remains excellenteven when amplifying high-frequency signals to highoutput power levels.

With the output current internally limited to 250mA,the KH561 is fully protected against shorts to groundand can, with the addition of a series limiting resistorat the output, withstand shorts to the ±15V supplies.

The KH561 has been designed for maximum flexibilityin a wide variety of demanding applications. Thetwo resistors comprising the feedback network setboth the gain and the output impedance, withoutrequiring the series backmatch resistor needed by mostop amps. This allows driving into a matched loadwithout dropping half the voltage swing through aseries matching resistor. External compensation allowsuser adjustment of the frequency response. TheKH561 is specified for both maximally flat frequencyresponse and 0% pulse overshoot compensations.

The combination of wide bandwidth, high outputpower, and low distortion, coupled with gain, outputimpedance and frequency response flexibility, makesthe KH561 ideal for waveform generator applications.Excellent stability driving capacitive loads yields superior performance driving ADC’s, long transmissionlines, and SAW devices. A companion part, theKH560, offers superior pulse fidelity for high accuracyDC coupled applications.

The KH561 is constructed using thin film resistor/bipolartransistor technology, and is available in the followingversions:

KH561AI -25°C to +85°C 24-pin Ceramic DIPKH561AK -55°C to +125°C 24-pin Ceramic DIP,

features burn-in and hermetic testing

KH561AM -55°C to +125°C 24-pin Ceramic DIP, environmentally screenedand electronically testedto MIL-STD-883

KH561Wideband, Low Distortion Driver Amplifier

REV. 1A January 2004

4

19

23

21

20

15

10

5

18

8 +

-

Compensation

Vo

-VCC

All undesignatedpins are internally unconnected. Maybe grounded ifdesired.

+VCC

V+

V-

K

Frequency Response vs. Output Power

Gai

n(d

B)

Frequency (MHz)

5

16

12

60 40 80 120 160 200

10

8

14Po = 10dBm

Vo = 2Vpp

Po = 24dBmVo = 10Vpp

Po = 27.5dBmVo = 15Vpp

Po = 18dBmVo = 5Vpp

Typical Distortion Performance

Output 20MHz 50MHz 100MHzPower 2nd 3rd 2nd 3rd 2nd 3rd

10dBm -59 -62 -52 -60 -35 -4918dBm -52 -48 -45 -46 -30 -3624dBm -50 -41 -36 -32 -40 -30

2 REV. 1A January 2004

DATA SHEET KH561

PARAMETERS CONDITIONS TYP MIN & MAX RATINGS UNITS SYM

Case Temperature KH561AI +25°C -25°C +25°C +85°C

Case Temperature KH561AK/AM +25°C -55°C +25°C +125°C

FREQUENCY DOMAIN RESPONSE (Max. Flat Compensation)= -3dB bandwidth= maximally flat compensation Vo <2Vpp (+10dBm) 215 >175 >185 >175 MHz SSBW

0% overshoot compensation Vo <2Vpp (+10dBm) 210 >170 >180 >170 MHzlarge signal bandwidth Vo <10Vpp (+24dBm) 150 >145 >135 >120 MHz FPBW

(see Frequency Response vs. Output Power plot)gain flatness Vo <2Vpp (+10dBm)

= peaking 0.1 -50MHz 0 <0.50 <0.40 <0.50 dB GFPL= peaking >50MHz 0 <1.75 <0.75 <1.00 dB GFPH= rolloff at 100MHz 0.1 <1.00 <0.75 <1.00 dB GFR

group delay to 100MHz 2.9 – – – ns GDlinear phase deviation to 100MHz 0.6 <1.7 <1.2 <1.7 ° LPDreturn loss (see discussion of Rx) to 100MHz -15 <-11 <-11 <-11 dB RL

DISTORTION (Max. Flat Compensation)2nd harmonic distortion

= 24dBm (10Vpp): 20MHz -50 <-38 <-40 <-38 dBc HD2HL= 50MHz -36 <-29 <-29 <-22 dBc HD2HM

100MHz -40 <-25 <-25 <-25 dBc HD2HH= 18dBm (5Vpp): 20MHz -52 <-42 <-44 <-42 dBc HD2ML= 50MHz -45 <-30 <-35 <-30 dBc HD2MM= 100MHz -30 <-22 <-25 <-25 dBc HD2MH= 10dBm (2Vpp): 20MHz -59 <-48 <-52 <-48 dBc HD2LL= 50MHz -52 <-36 <-40 <-40 dBc HD2LM

100MHz -35 <-27 <-28 <-28 dBc HD2LH3rd harmonic distortion

= 24dBm (10Vpp): 20MHz -41 <-34 <-34 <-30 dBc HD3HL= 50MHz -32 <-26 <-26 <-21 dBc HD3HM= 100MHz -30 <-24 <-24 <-24 dBc HD3HH= 18dBm (5Vpp): 20MHz -48 <-40 <-44 <-44 dBc HD3ML= 50MHz -46 <-37 <-37 <-35 dBc HD3MM

100MHz -36 <-30 <-30 <-30 dBc HD3MH= 10dBm (2Vpp): 20MHz -62 <-54 <-57 <-57 dBc HD3LL= 50MHz -60 <-49 <-52 <-49 dBc HD3LM

100MHz -49 <-45 <-45 <-45 dBc HD3LH2-tone 3rd orderintermod intercept2 20MHz 38 >36 >36 >36 dBm IM3L

50MHz 35 >32 >32 >32 dBm IM3M100MHZ 29 >27 >27 >23 dBm IM3H

Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters.

KH561 Electrical Characteristics (Av = +10V, VCC = ±15V, RL = 50Ω, Rf = 410Ω, Rg = 40Ω, Ro = 50Ω; unless specified)

NOTES TO THE ELECTRICAL SPECIFICATIONSThe electrical characteristics shown here apply to the specific test conditions shown above (see also Figure 1 indescription of the operation). The KH561 provides an equivalent, non-zero, output impedance determined by theexternal resistors. The signal gain to the load is therefore load dependent. The signal gain shown above (Av =+10) is the no load gain. The actual gain to the matching 50Ω load used in these specifications is half of this (+5).

The KH561 requires an external compensation capacitor. Unless otherwise noted, this has been set to 10.5pF forthe frequency domain specifications (yielding a maximally flat frequency response) and 12.5pF for the time domainspecifications (yielding a 0% small signal pulse overshoot response).

KH561 DATA SHEET

REV. 1A January 2004 3

PARAMETERS CONDITIONS TYP MIN & MAX RATINGS UNITS SYM

Case Temperature KH561AI +25°C -25°C +25°C +85°C

Case Temperature KH561AK/AM +25°C -55°C +25°C +125°C

TIME DOMAIN RESPONSE (0% Overshoot Compensation)rise and fall time2V step 1.5 <2.0 <1.9 <2.0 ns TRS10V step 2.4 <2.8 <2.8 <3.4 ns TRLsettling time to 0.5% (time <1µs) 5V step 7 <12 <12 <15 ns TSlong term thermal tail (time >1µs) 5V step 1.5 <2.0 <2.0 <2.0 % SEslew rate 10Vpp, 175MHz 3300 >3000 >2900 >2500 V/µs SRovershoot 2V step

maximally flat compensation 5 <13 <10 <13 % OSMF0% overshoot compensation 0 <5 <3 <5 % OSZO

EQUIVALENT INPUT NOISEvoltage >100KHz 2.1 <2.5 <2.5 <2.5 nV/√Hz VNinverting current >100KHz 34 <40 <40 <45 pA/√Hz ICNnon-inverting current >100KHz 2.8 <4.5 <4.5 <5.0 pA/√Hz NCNnoise floor >100KHz -159 <-157 <-157 <-157 dBm/(1Hz) SNFintegrated noise 1kHz to 200MHz 35 <45 <45 <45 µV INVnoise figure >100KHz 15 <17 <17 <17 dB NF

STATIC, DC PERFORMANCE* input offset voltage 2.0 <14.0 <5.0 <15.0 mV VIO

average temperature coefficient 35 <100 – <100 µV/°C DVIO* non-inverting bias current 5.0 <35 <20 <20 µA IBN

average temperature coefficient 20 <175 – <100 nA/°C DIBN* inverting bias current 10.0 <50 <30 <50 µA IBI

average temperature coefficient 100 <200 – <200 nA/°C DIBI* power supply rejection ratio (DC) 57 >54 >54 >52 dB PSRR* supply current no load 50 <60 <60 <65 mA ICC

MISCELLANEOUS PERFORMANCEopen loop current gain (±2% tolerance) 10.0 – – – mA/mA G

average temperature coefficient +0.02 <+.03 – <+.02 %/°C DGinverting input resistance (±5% tolerance) 14.0 – – – Ω RIN

average temperature coefficient +.02 <+.025 – <+.025 Ω/°C DRINnon-inverting input resistance 700 >200 >400 >400 KΩ RNInon-inverting input capacitance to 100MHz 2.7 <3.5 <3.5 <3.5 pF CNIoutput voltage range 150mA load current ±10.5 – >±10.0 – V VOoutput current limit 210 <250 <250 <250 mA OCL

Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters.

Absolute Maximum Ratings Recommended Operating ConditionsVCC (reversed supplies will destroy part) ±20V VCC ±10V to ±15Vdifferential input voltage ±3V Io ≤ ±200mAcommon mode input voltage ±VCC common mode input voltage < ±(|VCC| -6)Vjunction temperature (see thermal model) +175°C output impedance 25Ω to 200Ωstorage temperature -65°C to +150°C gain range (no-load voltage gain) +5 to +80lead temperature (soldering 10s) +300°C case temperature: AI -25°C to +85°C output current (internally limited) ±250mA AK/AM -55°C to +125°C

Notes1) * AI, AK, AM 100% tested at +25°C

= AK, AM 100% tested at at +25°C and sample tested at -55°C and +125°C

= AI sample tested at +25°C2) Test Tones are set ±100kHz of indicated frequency.

KH561 Electrical Characteristics (Av = +10V, VCC = ±15V, RL = 50Ω, Rf = 410Ω, Rg = 40Ω, Ro = 50Ω; unless specified)

DATA SHEET KH561


KH561 Typical Performance Characteristics (TA = +25°C, Circuit in Figure 1; unless specified)

Small Signal Gain and Phase

Gai

n(d

B)

Frequency (MHz)

5

6

8

10

12

14

16

0 50 100 150 200 250

Maximally Flat Phase

(degrees)

0

-90

-360

-180

-270

0% Overshoot

GainPhase

Po = 10dBm

Frequency Response vs. Gain

Nor

mal

ized

Mag

nitu

de(1

dB/d

iv)

Frequency (MHz)

5

0 50 100 150 200 250

Po = 10dBmAv = 10

Av = 5

Av = 15

Av = 20Re-compensated at each gain (see text)

Frequency Response vs. Output Power

Gai

n(d

B)

Frequency (MHz)

5

16

12

60 40 80 120 160 200

10

8

14Po = 10dBm

Vo = 2Vpp

Po = 24dBmVo = 10Vpp

Po = 27.5dBmVo = 15Vpp

Po = 18dBmVo = 5Vpp

Frequency Response vs. RL

Nor

mal

ized

Mag

nitu

de(1

dB/d

iv)

Frequency (MHz)

5

0 50 100 150 200 250

Pi = -4dBm

RL = 50Ω

RL = 25Ω

RL = 75Ω

RL = 100Ω

Fixed gain andcompensated vs. load

Frequency Response vs. Power Supply

Frequency (MHz)

5

0 50 100 150 200 250

Po = 10dBm

±VCC = 18

±VCC = 12

±VCC = 15

±VCC = 10

Gai

n(d

B)

16

12

6

10

8

14

Re-compensated at each supply voltage

Frequency Response vs. Ro

Frequency (MHz)

5

0 50 100 150 200 250

Pi = -4dBm

Nor

mal

ized

Mag

nitu

de(1

dB/d

iv)

Ro = 50ΩRo = 25Ω

Ro = 75Ω

Ro = 100Ω

Response measured with matched loadRe-compensated at each Ro

Frequency Response vs. Gain (Ro, RL= 75Ω)

Frequency (MHz)

5

0 50 100 150 200 250

Vo = 2Vpp

Nor

mal

ized

Mag

nitu

de(1

dB/d

iv)

Av = 5

Av = 10

Av = 15

Av = 20

Re-compensated at each gain

Gain Flatness/Deviation from Linear Phase

Gai

n(0

.1dB

/div

)

Frequency (MHz)

5

0 20 40 60 80 100

Phase

(0.5°/div)

Gain

Phase

Po = 10dBm

Internal Current Gain and Phase

Gai

n(1

0dB

/div

)

Frequency (MHz)

5

-30

-20

0

20

30

10

0 100 200 300 400 500

Phase

(90°/div)

180

90

-180

0

-90

Gain

Phase

-10

Cx = 0RL = 0

Phase consistant with currentpolarity connection of Figure 3

Two Tone, 3rd-Order Intermodulation

Inte

rcep

t(2.

5dB

/div

)

Frequency (MHz)

5

45

35

200 20 40 60 80 100

30

25

40

Av = 15

Av = 5

Av = 10

Av = 20

Re-compensated at each gain

2nd Harmonic Distortion vs. Frequency

Dis

tort

ion

(dB

c)

Output Power (dB)

5

-25

-45

-754 8 12 16 20 24

-55

-65

-35

50MHz

10MHz

20MHz

100MHz

3rd Harmonic Distortion vs. Frequency

Dis

tort

ion

(dB

c)

Output Power (dB)

5

-25

-45

-754 8 12 16 20 24

-55

-65

-35

50MHz

10MHz

20MHz

100MHz

Frequency Response Driving CL

Frequency (MHz)

5

0 50 100 150 200 250

Gai

n(1

dB/d

iv)

Av = +5Ro = 25Vo = 2Vpp

CL = 100pF

CL = 20pF

CL = 50pF

Re-compensated at each CL

2nd Harmonic Distortion Driving CL

Frequency (MHz)

5

10 20 30 40 50 100

Dis

tort

ion

(5dB

c/di

v)

Av = +5Ro = 25Vo = 2Vpp

CL = 100pF

CL = 20pF

CL = 50pF

70-80

-70

-60

-50

-40

-30Compensation as shown inFrequency Response plot

3rd Harmonic Distortion Driving CL

Frequency (MHz)

5

10 20 30 40 50 100

Dis

tort

ion

(5dB

c/di

v)

Av = +5Ro = 25Vo = 2Vpp

CL = 100pF

CL = 20pF

CL = 50pF

70-80

-70

-60

-50

-40

-30

KH561 DATA SHEET


KH561 Typical Performance Characteristics (TA = +25°C, Circuit in Figure 1; unless specified)

Small Signal Pulse Response

Time (2ns/div)

5

Out

putV

olta

ge(V

)

Maximally Flat Compensation

0

-1.2

-0.8

-0.4

0.4

1.2

0% OvershootCompensation

0.8

Large Signal Pulse Response

Time (5ns/div)

5O

utpu

tVol

tage

(V)


0

-6

-4

-2

2

6

0% OvershootCompensation

4

Uni-Polar Pulse Response

Time (5ns/div)

5

Out

putV

olta

ge(V

)


0

-6

-4

-2

2

6

4

Settling Time into 50Ω Load

Time (sec)

5

Set

tling

Err

or(%

)

0

-1.5

-1.0

-0.5

0.5

1.5

1.0

2.0

-2.010-9 10-7 10-5 10-3 10-1 101

5V Output Step

Settling Time into 500Ω Load

Time (sec)

5

Set

tling

Err

or(%

)5V Output Step

0

-1.5

-1.0

-0.5

0.5

1.5

1.0

2.0

-2.010-9 10-7 10-5 10-3 10-1 101

Reverse Transmission Gain & Phase (S12)

Rev

erse

Gai

n(d

B)

Frequency (MHz)

5

-100

-80

-60

-40

-20

0

0 50 100 150 200 250

Reverse

Phase

(degrees)

0

-45

-180

-90

-135

Gain

Phase

Settling Time into 50pF Load

Time (sec)

5

Set

tling

Err

or(%

)

5V Output Step

0

-1.5

-1.0

-0.5

0.5

1.5

1.0

2.0

-2.010-9 10-7 10-5 10-3 10-1 101

Output Return Loss (S22)

Mag

nitu

de(d

B)

Frequency (MHz)

5

-25

-20

-15

-10

-5

0

0 50 100 150 200 250

Ro = 50ΩRx = 0Ω

-50

-45

-40

-35

-30

Ro = 40ΩRx = 10Ω

Re-compensated at each Rx

Input Return Loss (S11)

Mag

nitu

de(d

B)

Frequency (MHz)

5

-50

-40

-30

-20

-10

0

0 50 100 150 200 250

Phase

(degrees)

0

-45

-180

-90

-135

Magnitude

Phase

Re-compensated at each Rx

-1dB Compensation Point

-1dB

Com

pens

atio

n(d

Bm

)

Frequency (MHz)

5

29

30

31

32

33

34

0 20 40 60 80 100

Ro = 50Ω

24

25

26

27

28

Ro = 75Ω

Match LoadRe-compensated at each load

Noise Figure

Noi

seF

igur

e(d

Bm

)

No Load Gain

5

17

18

19

20

21

22

5 10 15 20 25 30

Ro = 50Ω

12

13

14

15

16

Ro = 25Ω

Ro = 75Ω

Ro = 100Ω

Non-inverting input impedancematched to source impedance

Equivalent Input Noise

Noi

seV

olta

ge(n

V/√

Hz)

Frequency (Hz)

5

1

6

20

40

60

100

100 1k 10k 100k 10M 100M

Inverting Current 34pA/√Hz

Noise

Current(pA

/√Hz)

10

4

2

1

6

20

40

60

100

10

4

2Non-Inverting Voltage 2.1nV/√Hz

Non-Inverting Current 2.8pA/√Hz

1M

Group Delay

Gro

upD

elay

(ns)

Frequency (MHz)

5

3.0

3.2

3.4

3.6

3.8

4.0

0 50 100 150 200 2502.0

2.2

2.4

2.6

2.8

Aperture set to 5%of span (12.8MHz)

Gain Error Band (Worst Case, DC)

Gai

nE

rror

atLo

ad(%

)

No Load Gain

5

0

1

2

3

4

5

5 9 13 17 21 25-5

-4

-3

-2

-1

Ro (nominal) = 50ΩRL = 50Ω ± 0%

Rf and Rgtolerance = ±0.1%

Rf and Rgtolerance = ±1%

PSRR

PS

RR

(dB

)

Frequency (Hz)

5

50

60

70

80

90

100

100 1k 10k 100k 1M 100M0

10

20

30

40

10M

DATA SHEET KH561


SUMMARY DESIGN EQUATIONS AND DEFINITIONS

KH561 Description of OperationLooking at the circuit of Figure 1 (the topology and resistor values used in setting the data sheet specifica-tions), the KH561 appears to bear a strong externalresemblance to a classical op amp. As shown in the simplified block diagram of Figure 2, however, it differs inseveral key areas. Principally, the error signal is a current into the inverting input (current feedback) and theforward gain from this current to the output is relativelylow, but very well controlled, current gain. The KH561has been intentionally designed to have a low internalgain and a current mode output in order that an equivalentoutput impedance can be achieved without the seriesmatching resistor more commonly required of low outputimpedance op amps. Many of the benefits of a high loopgain have, however, been retained through a very carefulcontrol of the KH561’s internal characteristics.

The feedback and gain setting resistors determine boththe output impedance and the gain. Rf predominatelysets the output impedance (Ro), while Rg predominatelydetermines the no load gain (Av). solving for the requiredRf and Rg, given a desired Ro and Av, yields the designequations shown below. Conversely, given an Rf and Rg,the performance equations show that both Rf and Rg playa part in setting Ro and Av. Independent Ro and Avadjustment would be possible if the inverting input imped-ance (Ri) were 0 but, with Ri = 14Ω as shown in the specification listing, independent gain and output imped-ance setting is not directly possible.

Figure 1: Test Circuit

Design Equations

Performance EquationsSimplified Circuit DescriptionLooking at the KH561’s simplified schematic in Figure 2,the amplifier’s operation may be described. Going fromthe non-inverting input at pin 8 to the inverting input at pin18, transistors Q1 – Q4 act as an open loop unity gainbuffer forcing the inverting node voltage to follow the non-inverting voltage input.

Transistors Q3 and Q4 also act as a low impedance (14Ωlooking into pin 18) path for the feedback error current.This current, (ierr), flows through those transistors into avery well defined current mirror having a gain of 10 fromthis error current to the output. The current mirror outputsact as the amplifier output.

The input stage bias currents are supply voltage inde-pendent. Since these set the bias level for the whole

Rf – Feedback resistorfrom output to invertinginputRg – Gain settingresistor from invertinginput to ground

Cx – External compensation capacitorfrom output to pin 19 (in pF)

Where:Ro – Desired equivalent output impedance

Av – Non-inverting input to output voltagegain with no load

G – Internal current gain from inverting inputto output = 10 ±1%

Ri – Internal inverting input impedance = 14Ω ±%5

Rs – Non-inverting input termination resistor

RL – Load resistor

AL – Voltage gain from non-inverting input to load resistor

R G 1 R A R

RR RA 1

C1

R

300 12

R

0.08

f o v i

gf o

v

xo

g

= +( ) −

=−

−

=

−

−

6.8µF.1µF

-VCC (-15)

410ΩRg

40Ω

5,10,15,20

Rf

21

KH561+

-18Rs

50Ω

8Vi(Pi)

RL50Ω

Vo(Po)

Ro

4 19

+VCC (+15)

.1µF6.8µF

+

+Cx

23

10.5pF

Resistor Values shown result in:

Ro = 50Ω

Av = +10(no-load gain)

AL = +5 [14dB](gain to 50Ω load)

K

R G 1 R A R

RR RA 1

f o v i

gf o

v

= +( ) −

=−

−

R

R R 1RR

G 1RR

A 1RR

GRR

G 1RR

o

f if

g

i

g

vf

g

i

f

i

g

=

+ +

+ +

= +−

+ +

Where:

G ≡ forward current gain(=10)

Ri ≡ inverting node inputresistance (=14Ω)

Ro ≡ desired output impedance

Av ≡ desired non-inverting voltage gain with no load

KH561 DATA SHEET


part, relatively constant performance over supply voltageis achieved. A current sense in the error current leg ofthe 10X current mirror feeds back to the bias currentsetup providing a current shutdown feature when the output current approaches 250mA.

Figure 2: Simplified Circuit Diagram

Developing the Performance EquationsThe KH561 is intended to provide both a controllable voltage gain from input to output as well as a controllableoutput impedance. It is best to treat these two operationsseparately with no load in place. Then, with the no-loadgain and output impedance determined, the gain to theload will simply be the no-load gain attenuated by thevoltage divider formed by the load and the equivalent output impedance.

Figure 3 steps through the output impedance develop-ment using an equivalent model of Figure 2. Offering anequivalent, non-zero, output impedance into a matchedload allows the KH561 to operate at lower internal volt-age swings for a given desired swing at the load. Thisallows higher voltage swings to be delivered at the loadfor a given power supply voltage at lower distortion levelsthan an equivalent op amp needing to generate twice thevoltage swing actually desired at the matched load. Thisimproved distortion is specified and tested over a widerange as shown in the specification listing.

Get both Vo and Io into terms of just the error current, ierr,using:

Figure 3: Output Impedance Derivation

Note that the Ro expression simplifies considerably if Ri = 0. Also note that if the forward current gain were togo to infinity, the output impedance would go to 0. Thiswould be the normal op amp topology with a very highinternal gain. The KH561 achieves a non-zero Ro by setting the internal forward gain to be a low, well controlled, value.

Developing the No-Load Gain ExpressionTaking the output impedance expression as one con-straint setting the external resistor values, we now needto develop the no-load voltage gain expression from thenon-inverting input to the output as the other constraint.Figure 4 shows the derivation of the no load gain.

Rg

RoierrVo

Rf

Cx19

Io

Io

Ibias 10X Current MirrorCurrent Limit

5pFQ3

Q1-VCC

+VCC

4

Ibias 10X Current MirrorCurrent Limit

5pFQ4

Q2+VCC

-VCC

21

238Vi

ierr

RgRf

if

Gierr

RoVo

X1

Ri lo

V-

+

-

V i R and

i iVR

i 1RR

V V i R i R R 1RR

V i R R 1RR

and

I Gi i i G 1

err i

f errg

erri

g

o f f err i fi

g

o err f if

g

o err f err

−

−

−

=

= + = +

= + = + +

= + +

= + = + ++

≡ =

+ +

+ +

=+

=

RR

then

RVI

R R 1RR

G 1RR

note that RR

G 1

R 0

i

g

oo

o

f if

g

i

g

of

i

ierr

RgRf

Gierr

VoX1

Ri

V-

+

-

Vi

DATA SHEET KH561


Figure 4: Voltage Gain Derivation

Note again that if Ri = 0 this expression would simplifyconsiderably. Also, if G were very large the voltage gainexpression would reduce to the familiar non-inverting opamp gain equation. These two performance equations,shown below, provide a means to derive the designequations for Rf and Rg given a desired no load gain andoutput impedance.

Performance Equations Design Equations

Equivalent ModelGiven that the physical feedback and gain setting resistors have been determined in accordance with thedesign equations shown above, an equivalent modelmay be created for the gain to the load where the amplifier block is taken as a standard op amp. Figure 5shows this analysis model and the resulting gain equation to the load.

Figure 5: Equivalent Model

This model is used to generate the DC error and noiseperformance equations. As with any equivalent model,the primary intent is to match the external terminal characteristics recognizing that the model distorts theinternal currents and voltages. In this case, the modelwould incorrectly predict the output pin voltage swing fora given swing at the load. But it does provide a simplifiedmeans of getting to the external terminal characteristics.

External Compensation Capacitor (Cx)As shown in the test circuit of Figure 1, the KH561 requiresan external compensation capacitor from the output topin 19. The recommended values described here assumethat a maximally flat frequency response into a matchedload is desired. The required Cx varies widely with the desired value of output impedance and to a lesserdegree on the desired gain. Note from Figure 2, the simplified internal schematic, that the actual total compensation (Ct) is the series combination of Cx andthe internal 10pF from pin 19 to the compensation nodes.The total compensation (Ct) is developed in two steps asshown below.

recognize that [taking V positive]

V V Gi R

solving for V from two directions

V V i R G 1 i R

solving for i from this

iV

G 1 R R

then

V VV R

G 1 R R

and, substituting for V and i in the original V expression

V V 1GR R

i

o err f

i err i err g

err

erri

g i

ii i

g i

err o

o if

= +

= − = +( )

=+( ) +

= −+( ) +

= + −

−

−

−

−

−

ii

g i

f

g

vo

i

f

g

i

f

i

g

vf

g

i

G 1 R R

pulling anRR

out of the fraction

AVV

1RR

GRR

G 1RR

note that A 1RR

GG 1

R 0

+( ) +

≡ = +−

+ +

= ++

=

R

R RRR

GRR

ARR

GRR

GRR

o

f if

g

i

g

vf

g

i

f

i

g

=

+ +

+ +

= +−

+ +

1

1

11

R G R A R

RR RA

f o v i

gf o

v

= +( ) −

=−

−

1

1

Rg

Vi

RL

VoRo

Rf - Ro

Classical op-amp

+

-

VV

1R R

RR

R R

substituting in for R and R with their designequation yields

VV

AR

R RA (gain to load)

o

i

f o

g

L

L o

f g

o

iv

L

L oL

= +−

+

=+

=

C300R

12.0R

pF intermediate equation

CC

1 0.02 CpF total compensation

1o g

t1

1

= −

=+ ( )

KH561 DATA SHEET


With this total value derived, the required external Cx isdeveloped by backing out the effect of the internal 10pF.This, and an expression for the external Cx without theintermediate steps are shown below.

The plot in Figure 6 shows the required Cx vs. gain forseveral desired output impedances using the equationsshown above. Note that for lower Ro’s, Cx can get verylarge. But, since the total compensation is actually theseries combination of Cx and 10pF, going to very highCx’s is increasingly ineffective as the total compensationis only slightly changed. This, in part, sets the lower limits on allowable Ro.

Figure 6: External Compensation Capacitance (Cx)

A 0% small signal overshoot response can be achievedby increasing Cx slightly from the maximally flat value.Note that this applies only for small signals due to slewrate effects coming into play for large, fast edge rates.

Beyond the nominal compensation values developedthus far, this external Cx provides a very flexible meansfor tailoring the frequency response under a wide varietyof gain and loading conditions. It is oftentimes useful touse a small adjustable cap in development to determinea Cx suitable to the application, then fixing that value forproduction. An excellent 5pF to 20pF trimmer cap for thisis a Sprague-Goodman part #GKX20000.

When the KH561 is used to drive a capacitive load, suchas an ADC or SAW device, the load will act to compen-sate the response along with Cx. Generally, considerablylower Cx values are required than the earlier develop-ment would indicate. This is advantageous in that a lowRo would be desired to drive a capacitive load which,without the compensating effect of load itself, would otherwise require very large Cx values.

Gain and Output Impedance RangeFigure 7 shows a plot of the recommended gain and output impedances for the KH561. Operation outside ofthis region is certainly possible with some degradation inperformance. Several factors contribute to set this range.At very low output impedances, the required value offeedback resistor becomes so low as to excessively loadthe output causing a rapid degradation in distortion. The maximum Ro was set somewhat arbitrarily at 200Ω.This allows the KH561 to drive into a 2:1 step down transformer matching to a 50Ω load. (This offers some advantages from a distortion standpoint. See KotaApplication Note KAN-01 for details.)

Figure 7: Recommended Gain and Output Impedance Range

For a given Ro, the minimum gain shown in Figure 7 hasbeen set to keep the equivalent input noise voltage lessthan 4nV/√Hz. Generally, the equivalent input noise volt-age decreases with higher signal gains. The high gainlimit has been set by targeting a minimum Rg of 10Ω or aminimum Rf of 100Ω.

Amplifier ConfigurationsThe KH561 is intended for a fixed, non-inverting, gainconfiguration as shown in Figure 1. The KH560 offersthe better pulse fidelity with its improved thermal tail inthe pulse response (vs. the KH561). Due to its low internal forward gain, the inverting node does not presenta low impedance, or virtual ground, node. Hence, in aninverting configuration, the signal’s source impedancewill see a finite load whose value depends on the outputloading. Inverting mode operation can be best achievedusing a wideband, unity gain buffer with low outputimpedance, to isolate the source from this varying load.A DC level can, however, be summed into the invertingnode to offset the output either for offset correction or signal conditioning.

Accuracy CalculationsSeveral factors contribute to limit the achievable KH561accuracy. These include the DC errors, noise effects,and the impact internal amplifier characteristics have onthe signal gain. Both the output DC error and noisemodel may be developed using the equivalent model ofFigure 5. Generally, non-inverting input errors show up

C10 C

10 C

or

C1

R

300 12

R

0.08pF

xt

t

xo

g

=−

=

−

−

Cx

(pF

)

No Load Voltage Gain

K

0

2

4

6

8

10

12

14

16

18

20

5 10 15 20 25 30 35 40 45 50 55

Maximally Flat Responseinto a Matched Load

Ro = 50Ω

Ro = 75Ω

Ro = 100Ω

No

Load

Gai

nOutput Impedance (Ω)

0

10

20

30

40

50

60

70

80

90

100

0 20 40 60 80 100 120 140 160 180 200

Low Rf or Rg Region

RecommendedRegion

High Noise Region

DATA SHEET KH561


at the output with the same gain as the input signal, whilethe inverting current errors have a gain of simply (Rf - Ro)to the output voltage (neglecting the Ro to RL attenuation).

Output DC Offset:The DC error terms shown in the specification listingalong with the model of Figure 5 may be used to estimatethe output DC offset voltage and drift. Each term shownin the specification listing can be of either polarity. Whilethe equations shown below are for output offset voltage,the same equation may be used for the drift with eachterm replaced by its temperature drift value shown in thespecification listing.

Recall that the source impedance, Rs, includes both theterminating and signal source impedance and that theactual DC level to the load includes the voltage dividerbetween Ro and RL. Also note that for the KH561, as wellas for all current feedback amplifiers, the non-invertingand inverting bias currents do not track each other ineither magnitude or polarity. Hence, there is no meaningin an offset current specification, and source impedancematching to cancel bias currents is ineffective.

Noise Analysis:Although the DC error terms are in fact random, the cal-culation shown above assumes they are all additive in aworst case sense. The effect of all the various noisesources are combined as a root sum of squared terms toget an overall expression for the spot noise voltage. Thecircuit of Figure 8 shows the equivalent circuit with all thevarious noise voltages and currents included along withtheir gains to the output.

where: Gain to eo

eni – non-inverting input voltage noise Avini – non-inverting input current noise AvRsii – inverting input current noise Rf - Ro

Av

Rf - Ro

1

1

Figure 8: Equivalent Noise Model

To get an expression for the equivalent output noise volt-age, each of these noise voltage and current terms mustbe taken to the output through their appropriate gainsand combined as the root sum of squares.

Where the 4kT(Rf - Ro) Av term is the combined noisepower of Rg and Rf - Ro.

It is often more useful to show the noise as an equivalentinput spot noise voltage where every term shown aboveis reflected to the input. This allows a direct measure ofthe input signal to noise ratio. This is done by dividingevery term inside the radical by the signal voltage gainsquared. This, and an example calculation for the circuitof Figure 1, are shown below. Note that RL may beneglected in this calculation.

V I R V 1R R

RI R R

where: I non inverting bias currentI inverting bias currentV input offset voltage

V 5 A 25 2.0mV 10 10 A 36012.4mV

attentuation betweenR and R

os bn s iof o

gbi f o

bn

bi

io

o

o L

1/ 2

= ⋅ ±( ) ⋅ +−

± −( )

≡ −≡≡

= ⋅ ±( ) ± ( )[ ]= ±

↑

µ µΩ Ω L

An example calculation for the circuit in Figure 1 usingtypical 25°C DC error terms and Rs = 25Ω, RL = 50Ωyields:

Rgii

eo

Ro

Rf - Ro

Classical op-amp

+

-

√4kTRVo

√4kT(Rf - Ro)

**

√4kTRs

√4kT Rg

*

*

Rs

ini**

*eni

4

4

4

4

kTR source resis ce voltagenoise

kT R gain settling resistornoise current

kT R R feedback resistorvoltage noise

kTR output resistor voltage noise

s

g

f o

o

−

−

−( ) −

−

tan

/

e e i R kTR A i R R

kT R R A kTR

o ni ni s s v i f o

f o v o

= + ( ) +( ) + −( )

+ −( ) +

2 2 2 2 24

4 4

L

e e i R kTRi R R

A

kT R R

AkTR

A

n ni ni s si f o

v

f o

v

o

v

= + ( ) + +−( )

+

−( )+

2 22 2

2

2

4

4 4

L

DC

KH561 DATA SHEET


For the circuit of Figure 1, the equivalent input noise voltage may be calculated using the data sheet spot noises and Rs = 25Ω, RL = ∞. Recall that 4kT = 16E-21J.All terms cast as (nV/√Hz)2

Gain Accuracy (DC):A classical op amp’s gain accuracy is principally set bythe accuracy of the external resistors. The KH561 also depends on the internal characteristics of the forward current gain and inverting input impedance. Theperformance equations for Av and Ro along with theThevinin model of Figure 5 are the most direct way ofassessing the absolute gain accuracy. Note that internaltemperature drifts will decrease the absolute gain slightly as the part warms up. Also note that the para-meter tolerances affect both the signal gain and outputimpedance. The gain tolerance to the load must includeboth of these effects as well as any variation in the load.The impact of each parameter shown in the performanceequations on the gain to the load (AL) is shown below.

Increasing current gain G Increases ALIncreasing inverting input Ri Decreases ALIncreasing Rf lncreases ALIncreasing Rg Decreases AL

Applications SuggestionsDriving a Capacitive Load:The KH561 is particularly suitable for driving a capacitiveload. Unlike a classical op amp (with an inductive outputimpedance), the KH561’s output impedance, while starting out real at the programmed value, goes some-what capacitive at higher frequencies. This yields a verystable performance driving a capacitive load. The over-all response is limited by the (1/RC) bandwidth set by theKH561’s output impedance and the load capacitance. Itis therefore advantageous to set a low Ro with the constraint that extremely low Rf values will degrade thedistortion performance. Ro = 25Ω was selected for thedata sheet plots. Note from distortion plots into a capacitive load that the KH561 achieves better than60dBc THD (10-bits) driving 2Vpp into a 50pF loadthrough 30MHz.

Improving the Output Impedance Match vs. Frequency - Using Rx:Using the loop gain to provide a non-zero output impedance provides a very good impedance match atlow frequencies. As shown on the Output Return Lossplot, however, this match degrades at higher frequencies.Adding a small external resistor in series with the output,Rx, as part of the output impedance (and adjusting theprogrammed Ro accordingly) provides a much bettermatch over frequency. Figure 9 shows this approach.

Figure 9: Improving Output Impedance Match vs. Frequency

Increasing Rx will decrease the achievable voltage swingat the load. A minimum Rx should be used consistentwith the desired output match. As discussed in the thermal analysis discussion, Rx is also very useful in limiting the internal power under an output shorted condition.

Interpreting the Slew Rate:The slew rate shown in the data sheet applies to the volt-age swing at the load for the circuit of Figure 1. Twice thisvalue would be required of a low output impedanceamplifier using an external matching resistor to achievethe same slew rate at the load.

Layout Suggestions:The fastest fine scale pulse response settling requirescareful attention to the power supply decoupling.Generally, the larger electrolytic capacitor ground connections should be as near the load ground (or cableshield connection) as is reasonable, while the higher frequency ceramic de-coupling caps should be as nearthe KH561’s supply pins as possible to a low inductanceground plane.

Evaluation Boards:An evaluation board (showing a good high frequency lay-out) for the KH561 is available. This board may beordered as part #730019.

Thermal Analysis and ProtectionA thermal analysis of a chip and wire hybrid is directed at determining the maximum junction temperature of all the internal transistors. From the totalinternal power dissipation, a case temperature may bedeveloped using the ambient temperature and the caseto ambient thermal impedance. Then, each of the dominant power dissipating paths are considered todetermine which has the maximum rise above case temperature.

The thermal model and analysis steps are shown below.As is typical, the model is cast as an electrical modelwhere the temperatures are voltages, the power dissipa-tors are current sources, and the thermal impedancesare resistances. Refer to the summary design equationsand Figure 1 for a description of terms.

e 2.1 .07 .632 1.22 .759 .089

2.62nV/ Hz

n2 2 2 2 2 2= ( ) + ( ) + ( ) + ( ) + ( ) + ( )

= Rg

Vi

RL

VoRx

Rf

KH561

+

-

Rs

R'o = Rx + RoCx

Ro = R'o - Rx

With:

Ro = KH561 output impedanceand Ro + Rx = RL generally

A

DATA SHEET KH561


Figure 10: Thermal Model

Note that the Pt and Pq equations are written for positiveVo. Absolute values of -VCC, Vo, and Io, should be usedfor a negative going Vo. since we are only interested indelta V’s. For bipolar swings, the two powers for eachoutput polarity are developed as shown above thenratioed by the duty cycle. Having the total internal power,as well as its component parts, the maximum junctiontemperature may be computed as follows.

Tc = TA + (Pq + PT + Pcircult) • θca Case Temperature

θca = 35°C/W for the KH561 with no heatsink in still air

Tj(t) = Tc + Pt • 20°C/Woutput transistor junction temperature

Tj(q) = Tc + Pq • 200°C/Whottest internal junction temperature

The Limiting Factor for Output Power is MaximumJunction TemperatureReducing θca through either heatsinking and/orairflow can greatly reduce the junction temperatures.One effective means of heatsinking the KH561 is to usea thermally conductive pad under the part from the pack-age bottom to a top surface ground plane on the compo-nent side. Tests have shown a θca of 24°C in still airusing a “Sil Pad” available from Bergquist (800-347-

4572).As an example of calculating the maximum internal junc-tion temperatures, consider the circuit of Figure 1 driving±2.5V, 50% duty cycle, square wave into a 50Ω load.

Note that 1/2 of the total PT and Pa powers were usedhere since the 50% duty cycle output splits the powerevenly between the two halves of the circuit whereas thetotal powers were used to get case temperature.

Even with the output current internally limited to 250mA,the KH561’s short circuiting capability is principally athermal issue. Generally, the KH561 can survive shortduration shorts to ground without any special effort. Forprotection against shorts to the ±15 volt supply voltages,it is very useful to reduce some of the voltage across theoutput stage transistors by using some external outputresistance, Rx, as shown in Figure 9.

Evaluation BoardAn evaluation board (part number 730019) for the KH561is available.

R 50410 5

5 145.6

I 2.5V / 45.6 54.9mA

I 54.9mA 54.9mA .06 68.1mA

P 68.1mA 15 2.5 0.7 15.3 68.1mA 733mWtotal power in both sides of the output stage

P 2 68.1mA 15 1.4 17.3 68.1mA 169mWtotal power in both sides of hottest

eq

o

T12

2 2

T

q

= ⋅−

=

= ( ) =

= + ( ) + ( )

=

= − − − ⋅[ ] =

= ⋅ − − ⋅[ ] =

Ω Ω Ω

Ω

Ω

Ω0.junctionsjunctions

prior to output stage

P 1.3 15 2 68.1mA 54.9mA 19.2mA733mW 169mW 1.058W

power in the remainder of circuit

With these powers and T 25 C and 35 C / W

T 25 C .733 .169 1.058 35 94 Ccase temperature

From this, the hottest internal junctions may be found as

T t 94 C .733 20 101

circuit

A ca

c

j12

= ⋅ ( ) ⋅ ⋅ − +[ ]− − =

= ° = °

= ° + + +( ) ⋅ = °

( ) = ° + ( ) ⋅ = °

θ

CC output stage

T q 94 C .169 200 111 Chottest internal junction

j12( ) = ° + ( ) ⋅ = °

AmbientTemperature

θca200°C/W20°C/W

Tj(t) TA

Pt

Tj(q)

Pq Pcircuit

Case TemperatureTc

Case to AmbientTermal Impedance

I V / R total output current

withR RR AA 1

total load

I I I .06

total internal output stage current

P I V 1.4 17.3 I output stage power

P .2 I V V 0.7 15.3 Ipower in hottest internal junctionprior

o o eq

eq Lf L

L

t12 o o

2 2

t t CC t

q t CC o t

=

=−

= + + ( )

= ⋅ − − ⋅( )

= ⋅ ⋅ − − − ⋅( )

Ω

Ω0

toto output stage

P 1.3 V 2 I I 19.2mA P Ppower in remainder of circuit [note V | V |]

circuit CC t o t q

CC CC

= ⋅ ⋅ ⋅ − +( ) − −= −

KH561 Package Dimensions

DATA SHEET KH561

b1

A

L

D1

Pin #1 Index

Q

b

e

D

E E1

C

A1

2

Symbol Inches Milimeters

Minimun Maximum Minimum Maximum

A 0.225 5.72

A1 0.139 0.192 3.53 4.88

b 0.014 0.026 0.36 0.66

b1 0.050 BSC 1.27 BSC

c 0.008 0.018 0.20 0.46

D 1.190 1.290 30.23 32.77

D1 1.095 1.105 27.81 28.07

E 0.500 0.610 12.70 15.49

E1 0.600 BSC 15.24 BSC

e 0.100 BSC 2.54 BSC

L 0.165 BSC 4.19 BSC

Q 0.015 0.075 0.38 1.91

NOTES: Seal: seam weld (AM, AK), epoxy (AI) Lead finish: gold finish Package composition: Package: ceramic Lid: kovar/nickel (AM, AK), ceramic (AI) Leadframe: alloy 42 Die attach: epoxy

©

wideband, low distortion driver amplifierthe kh561 is a wideband dc coupled, amplifier that combines...

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