IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 4, APRIL 1998 669

A Transistorless-Current-Mode Static RAM ArchitectureH. J. Levy, E. S. Daniel, and T. C. McGill

Abstract—We propose a static memory architecture in whicheach bit consists of a single two-terminal device that is bistable incurrent. Current-mode operation of the memory array removesthe need for cell-isolation transistors, thus, allowing huge in-creases in density over inverter-based SRAM and capacitor-basedDRAM. Low power consumption and fast read/write speeds areensured by taking advantage of the exponential nature of thememory’s current-voltage characteristic.

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I. INTRODUCTION

W HILE recent improvements in microprocessor tech-nology have pushed clock rates higher and higher,

DRAM access times have not improved at the same rate.This is because DRAM capacitor-discharge currents are toosmall—much less than SRAM transistor currents for compa-rable memory cell density—and it is these currents which areintegrated over the sense time to provide the necessarysense charge to a digital amplifier [1]. As a result,faster SRAM cache memory has become critically importantin minimizing wasted processor cycles. While SRAM accessspeeds comparable to processor speeds can be achieved, asevere density penalty must be paid as a typical SRAM cellconsists of at least five devices and, hence, DRAM remainsthe solution of choice for mass storage [2], [3]. The needfor both types of memory could be obviated by a memoryarchitecture consisting of a very compact bit circuit capable ofdelivering large amounts of current for a “one” state read cycle,supporting fast write cycles, and maintaining many of theadvantages common to both SRAM and DRAM designs, suchas an exponentially lower “zero” state current, low quiescentpower, and ease of large-scale fabrication and integration.

Consider the tunnel switch diode (TSD) device discoveredby Yamamotoet al. [4] [Fig. 1(a)]. This device is characterizedby a thyristor-like I–V characteristic, consisting of a high-impedance region, a negative differential resistance (NDR)region, and a low-impedance region. A typical I–V curvefor a large area (2.5 10 cm ) discrete device is found inFig. 1(c). If this device is placed in a circuit with a seriesresistance as shown in Fig. 1(b), a load line analysis [Fig. 1(c)]demonstrates that, for a range of voltages, two stable states areallowed, differing in current by orders of magnitude. Outsideof this voltage range, there is a single stable state in either

Manuscript received January 2, 1997; revised July 3, 1997.The authors are with the T. J. Watson Sr. Laboratory of Applied Physics,

California Institute of Technology, Pasadena, CA 91125 USA.Publisher Item Identifier S 0018-9200(98)02342-7.

(a)

(b)

(c)

Fig. 1. (a) The TSD device consists of ap+ silicon substrate with annsilicon epilayer, typically a few microns thick, followed by a tunnel oxide(20–40A), with a metal (e.g. Al) gate on top. (b) Load-line analysis circuit.(c) A measured I–V curve for a 2.5�10�5 cm2 device plotted along witha 2.5-V, 10- load line, illustrating the two stable current states. For thisparticular device,Ihigh = 100 mA, Ivalley = 100 �A, Ipeak = 9 �A,Vvalley = 1 V, andVpeak = 4 V.

the high- or the low-current region. Note also that within therange of voltages for which there are two stable states, thelevel of the high-current state increases over several orders ofmagnitude.

0018–9200/98$10.00 1998 IEEE

670 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 4, APRIL 1998

(a)

(b)

Fig. 2. Read Scheme. (a) A sample 2�2 bit array in which the top rowis selected to be read out. (b) Typical TSD I–V curve with load linescorresponding to static bias and read bias.

II. CIRCUIT OPERATION

We propose a memory architecture [5] in which each bit iscomprised of a single TSD device, with the bit informationstored in the current state of the device. Because the infor-mation is stored as a current rather than a voltage, there isno need for isolation transistors between devices, allowingperhaps maximal density as each bit consists of a single, simpledevice. A typical layout [Fig. 2(a)] is used in which the bitsare placed in an array, the “” terminal of each device in ahorizontal row connected to a bit line, and the “” terminal ofeach device in a vertical row connected to a word line. Notethat the resistors displayed in the figure are meant to representthe parasitic resistance of the circuit, not supplemental circuitelements, and in fact we shall see that any such resistance isundesirable, as it tends to reduce the read current and, hence,lengthen the sense time. We will show that by adjusting thevoltages on the bit and word lines, we will be able to readfrom and write to individual bits.

First, consider a static situation in which no read or write isbeing performed. In this situation, we wish to keep a low bias

across each bit such that power consumption is minimized,while the bit information is preserved [see Fig. 2(b)]. This is

(a)

(b)

Fig. 3. Write Scheme. (a) A sample 2�2 bit array in which the bit in theupper left corner is to be written. (b) Typical TSD I–V curve depicting loadlines employed for writing both the “one” and “zero” states.

easily done by applying a voltage to the bit lines andto the word lines such that .

When a bit is to be read, we would like to maximize the“one” state current in order to minimize while stillpreserving the bit state, so we wish to increase the bias acrossthat bit to [see Fig. 2(b)]. One method for performingthis is illustrated in Fig. 2(a) in which the voltage on agiven word line is raised by an amount ,thereby increasing the currents of all bits along that row to theappropriate read currents. If the selected bit along a particularbit line is in the “one” state, the read current generated bythat bit will dominate the total bit line current, as it is ordersof magnitude larger than any of the quiescent currents. If thisbit is in the “zero” state, the current along the bit line willbe exponentially smaller. Thus, in either case, the entire rowof bits can be read out simultaneously by sense amplifiersconnected to the bit lines. Other read schemes are possiblewhich select a single bit rather than a row of bits [6]. Note thatwe wish to minimize the parasitic series resistance in order tomaximize the possible read current, as mentioned previously.

A simple write scheme can be similarly executed (Fig. 3).To write a “one” state, for example, the word line correspond-ing to that bit is raised by an amount while the bit line

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 4, APRIL 1998 671

TABLE IIDC ELECTRICAL CHARACTERISTICS OFCOMMERCIALLY AVAILABLE SRAM AND DRAM CHIPS. THE

QUIESCENTPOWER IS ESTIMATED AS Irefresh � Vsupply/# BITS FOR DRAM, AND AS

(Isnooze;Istandby)� Vsupply /# BITS FOR SRAM. COMPARE THE ESTIMATED QUIESCENT

POWER VALUES TO THE�40 nW FOR THE TSD MEMORY DESCRIBED IN THE TEXT

corresponding to that bit is lowered by, where is chosensuch that and . This forcesthe selected bit into the high-current state while preserving allof the other bit states. As the additional biases are removed,the newly written bit relaxes along the high-current portion ofthe I–V curve, preserving its state. The method for writing a“zero” state is identical, where now is negative, satisfying

and .

III. FABRICATION AND PERFORMANCE

Notice that the device consists of a simple stack of semi-conductor and oxide layers, and nothing further is needed toconstruct a bit. Therefore, in principle, a dense memory arraycould consist of closely spaced rows of conducting word lines,separated vertically from perpendicular columns of bit lines bya TSD stack (Fig. 4). Assuming these features can all be madeas small as the minimum feature size, this yields a cell size of4 with an active device area of —the minimum possiblecell size for an isolated array structure. Of course, such ascheme would require somewhat nonstandard fabrication stepsbeyond those of conventional CMOS, but they should be nomore costly than the additional steps required to make DRAMcapacitors. In order to stay somewhat within the boundaries ofCMOS process capabilities, a larger cell size would probablybe necessary. In addition, it may not be possible to create aburied conductive (Si) layer with a high enough conductanceto support a negligible voltage drop along the line, so laterallydisplaced metal contacts may be required.

The characteristics of the memory array will depend crit-ically on the attainable parameters of the discrete devices.It is, therefore, worthwhile to establish a causal relationshipbetween device I–V characteristic and the required designspecifications such as cell density, power consumption, andaccess speed. For the purpose of this discussion, we willassume the density-maximizing fabrication scheme presentedabove with a cell area of 4 and a device area of .

We begin by assuming that we are constrained to a minimumvalue (we assume 100 fC, a typical CMOS value [2]),

and that we are willing to dissipate no more that 1 A/cmofcurrent in the quiescent state, corresponding to1 W/cm fora typical V. Then, given the maximum read current,

, we calculate the necessary ratio in order

(a) (b)

Fig. 4. Density maximizing fabrication scheme. (a) Self-aligned scheme forfabricating a dense addressable TSD array. (b) The area of the cell, 4�2 isthe maximum possible for a planar array of isolated devices.

to meet the power-dissipation requirement for an array of cells,and we compute the possible cell size for the quiescent currentdensity and a set of possible sense times. The results arepresented in Table I.

Note that there is a tradeoff between cell density and sensetime, as the device can simply be made larger in order tosource more current in a given time. Also, notice that inorder to achieve low power dissipation and a short sense timesimultaneously, we wish to make as large as possible. Atpresent, we have fabricated large area discrete TSD deviceswith in excess of 1000 with as high as 4000 A/cm[see Fig. 1(c)], and constructed a working 22 prototype withthese discrete devices. Based on Table I, this suggests that itwould be possible to fabricate a 25-Mb/cmSRAM with a2.5-ns sense time, dissipating 1 W/cmin the quiescent statewith the density-maximizing fabrication scheme.

For a rough comparison, consider the characteristics ofa few typical commercially available SRAM and DRAMchips presented in Table II. While the estimated standbypower consumption of the 25-Mb transistorless SRAM schemedescribed above (40 nW/b) is comparable at best to presentSRAM and DRAM, the simultaneous improvement in speedand density may warrant higher power consumption. We hopeto be able to better optimize the TSD device characteristicsfor lower power and higher speeds by experimentally andtheoretically exploring device parameters.

Other device characteristics will be important as well, suchas switching speed and device lifetime. Bidirectional switchingtimes in the 1–2 ns range have been reported for large area

672 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 4, APRIL 1998

TABLE IPERFORMANCE ESTIMATES. FOR A GIVEN MAXIMUM -READ CURRENT DENSITY

Jread, WE CALCULATE THE NECESSARYCURRENT RATIO � = Jread=Js FOR A

1- A/cm2 POWER DISSIPATION, AND THEPOSSIBLE DEVICE SIZE AND DENSITY

FOR SEVERAL POSSIBLE READ TIMES, ASSUMING A 100-fC SENSECHARGE. OUR

CURRENT EXPERIMENTAL RESULTS ARE REPRESENTED BY THEBOTTOM LINE

discrete devices [4], [7], and such devices have been operatedin excess of 10 h without failure [4].

IV. CONCLUSION

In summary, we have described the layout and operationof a novel memory architecture in which each bit consists ofa single nonlinear device, the TSD. This design is capableof high speed and high density simultaneously as a result ofthe unique properties of the TSD device. We have fabricateddevices with characteristics which suggest that this technologycould compete with traditional SRAM and DRAM designs.

REFERENCES

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[2] , “Trends in low-power RAM circuit technologies,”Proc. IEEE,vol. 83, pp. 524–543, Apr. 1995.

[3] H. Nambu, K. Kanetani, Y. Idei, N. Homma, K. Yamaguchi, T.Hiramoto, N. Tamba, M. Odaka, K. Watanabe, T. Ikeda, K. Ohhata,and Y. Sakurai, “High-speed sensing techniques for ultrahigh-speedSRAM’s,” IEEE J. Solid-State Circuits, vol. 27, pp. 632–640, Apr. 1992.

[4] T. Yamamoto, K. Kawamura, and H. Shimizu, “Siliconp-n insulator-metal(p-n-I-M) devices,”Solid-State Electron., vol. 19, pp. 701–706,1976.

[5] H. J. Levy, “Application and integration of quantum-effect devicesfor cellular VLSI,” Ph.D. Thesis, California Institute of Technology(Caltech), Pasadena, Dec. 1994.

[6] H. J. Levy and T. C. McGill, “Patent #5 535 156,” 1996.[7] H. Kroger and H. A. R. Wegener, “Steady-state characteristics of two

terminal inversion-controlled switches,”Solid-State Electron., vol. 21,pp. 655–661, 1978.

[8] Micron Technology, Inc., “Data sheet—MT58LC128K32/36D8 128 K� 32/36 Syncburst SRAM,” 1997.

[9] IBM Corporation, “Data sheet—IBM04184ARLAA 256 K� 18SRAM,” 1997.

[10] Micron Technology, Inc., “Data sheet—16 Meg� 4 EDO DRAM,”1997.

[11] IBM Corporation, “Data sheet—IBM0364804C 64 Mb SynchronousDRAM,” 1997.