a six-input channel analog front end ad73360l · 2019. 12. 23. · –2– rev. 0...

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aAD73360L

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700 World Wide Web Site: http://www.analog.comFax: 781/326-8703 © Analog Devices, Inc., 2000

FEATURESSix 16-Bit A/D ConvertersProgrammable Input Sample RateSimultaneous Sampling76 dB SNR64 kS/s Maximum Sample Rate–95 dB CrosstalkLow Group Delay (25 �s Typ per ADC Channel)Programmable Input GainFlexible Serial Port Which Allows Multiple Devices to

Be Connected in CascadeSingle (2.7 V to 3.6 V) Supply Operation80 mW Max Power Consumption at 2.7 VOn-Chip Reference28-Lead SOIC Package

APPLICATIONSGeneral-Purpose Analog InputIndustrial Power MeteringMotor ControlSimultaneous Sampling Applications

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTIONThe AD73360L is a six-input channel analog front-end proces-sor for general-purpose applications, including industrial power

metering or multichannel analog inputs. It features six 16-bitA/D conversion channels, each of which provides 76 dB signal-to-noise ratio over a dc-to-4 kHz signal bandwidth. Eachchannel also features a programmable input gain amplifier (PGA)with gain settings in eight stages from 0 dB to 38 dB.

The AD73360L is particularly suitable for industrial powermetering as each channel samples synchronously, ensuring thatthere is no (phase) delay between the conversions. The AD73360Lalso features low group delay conversions on all channels.

An on-chip reference voltage is included with a nominal valueof 1.2 V.

The sampling rate of the device is programmable, with fourseparate settings offering 64 kHz, 32 kHz, 16 kHz, and 8 kHzsampling rates (from a master clock of 16.384 MHz).

A serial port (SPORT) allows easy interfacing of single or cas-caded devices to industry-standard DSP engines. The SPORTtransfer rate is programmable to allow interfacing to both fastand slow DSP engines.

The AD73360L is available in 28-lead SOIC package.

Six-Input ChannelAnalog Front End

VINN1

VINP1 ANALOG�-�

MODULATORSDI

SDIFS

SCLK

REFCAP

REFOUT

SE

RESET

SDOFS

SDO

MCLK

VINN2

VINP2

VINN3

VINP3

VINN4

VINP4

VINN5

VINP5

VINN6

VINP6

AD73360L

SIGNALCONDITIONING

0/38dBPGA

DECIMATOR

SERIALI/O

PORT

ANALOG�-�

MODULATOR

SIGNALCONDITIONING

0/38dBPGA

DECIMATOR

ANALOG�-�

MODULATOR

SIGNALCONDITIONING

0/38dBPGA

DECIMATOR

ANALOG�-�

MODULATOR

SIGNALCONDITIONING

0/38dBPGA

DECIMATOR

ANALOG�-�

MODULATOR

SIGNALCONDITIONING

0/38dBPGA

DECIMATOR

ANALOG�-�

MODULATOR

SIGNALCONDITIONING

0/38dBPGA

DECIMATOR

REFERENCE

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AD73360L–SPECIFICATIONS1 (AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 3.6 V; DGND = AGND = 0 V, fMCLK = 16.384 MHz,fSCLK = 8.192 MHz, fS = 8 kHz; TA = TMIN to TMAX, unless otherwise noted.) AD73360LA

Parameter Min Typ Max Unit Test Conditions/Comments

REFERENCEREFCAP

Absolute Voltage, VREFCAP 1.08 1.2 1.32 VREFCAP TC 50 ppm/°C 0.1 µF Capacitor Required from REFCAP

to AGND2REFOUT

Typical Output Impedance 130 ΩAbsolute Voltage, VREFOUT 1.08 1.2 1.32 V UnloadedMinimum Load Resistance 1 kΩMaximum Load Capacitance 100 pF

ADC SPECIFICATIONSMaximum Input Range at VIN2, 3 1.578 V p-p Measured Differentially

–2.85 dBmNominal Reference Level at VIN 1.0954 V p-p Measured Differentially

(0 dBm0) –6.02 dBmAbsolute Gain

PGA = 0 dB –1.3 +0.6 dB 1.0 kHzPGA = 38 dB 0.6 dB 1.0 kHz

Signal to (Noise + Distortion)PGA = 0 dB 76 dB 0 Hz to 4 kHz; fS = 8 kHzPGA = 0 dB 71 76 dB 0 Hz to 2 kHz; fS = 8 kHz; fIN = 60 HzPGA = 38 dB 58 dB 0 Hz to 4 kHz; fS = 64 kHz

Total Harmonic DistortionPGA = 0 dB –80 –71 dB 0 Hz to 2 kHz; fS = 8 kHz; fIN = 60 HzPGA = 38 dB –64 dB 0 Hz to 2 kHz; fS = 64 kHz; fIN = 60 Hz

Intermodulation Distortion –78 dB PGA = 0 dBIdle Channel Noise –68 dB PGA = 0 dB, fS = 64 kHz; SCLK = 16 MHzCrosstalk ADC-to-ADC –95 dB ADC1 at Idle

ADC2 to ADC6 Input Signal: 60 HzDC Offset –30 +30 mV PGA = 0 dBPower Supply Rejection –55 dB Input Signal Level at AVDD and DVDD

Pins 1.0 kHz, 100 mV p-p Sine WaveGroup Delay4, 5 25 µs 64 kHz Output Sample Rate

50 µs 32 kHz Output Sample Rate95 µs 16 kHz Output Sample Rate190 µs 8 kHz Output Sample Rate

Input Resistance at VIN2, 4 25 kΩ6 DMCLK = 16.384 MHzPhase Mismatch 0.15 Degrees fIN = 1 kHz

0.01 Degrees fIN = 60 Hz

FREQUENCY RESPONSE(ADC)7 Typical Output

Frequency (Normalized to fS)0 0 dB0.03125 –0.1 dB0.0625 –0.25 dB0.125 –0.6 dB0.1875 –1.4 dB0.25 –2.8 dB0.3125 –4.5 dB0.375 –7.0 dB

0.4375 –9.5 dB> 0.5 < –12.5 dB

LOGIC INPUTSVINH, Input High Voltage VDD – 0.8 VDD VVINL, Input Low Voltage 0 0.8 VIIH, Input Current 10 µACIN, Input Capacitance 10 pF

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Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC OUTPUTVOH, Output High Voltage VDD – 0.4 VDD V |IOUT| ≤ 100 µAVOL, Output Low Voltage 0 0.4 V |IOUT| ≤ 100 µAThree-State Leakage Current –10 +10 µA

POWER SUPPLIESAVDD1, AVDD2 2.7 3.6 VDVDD 2.7 3.6 VIDD8 See Table I

NOTES1Operating temperature range is as follows: –40°C to +85°C. Therefore, TMIN = –40°C and TMAX = +85°C.2Test conditions: Input PGA set for 0 dB gain (unless otherwise noted).3At input to sigma-delta modulator of ADC.4Guaranteed by design.5Overall group delay will be affected by the sample rate and the external digital filtering.6The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK.7Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifierbypassed and input gain of 0 dB.

8Test Conditions: no load on digital inputs, analog inputs ac-coupled to ground.

Specifications subject to change without notice.

Table I. Current Summary (AVDD = DVDD = 3.3 V)

TotalCurrent MCLK

Conditions (Max) SE ON Comments

ADCs Only On 25 1 Yes REFOUT DisabledREFCAP Only On 1.0 0 No REFOUT DisabledREFCAP and REFOUT Only On 3.5 0 NoAll Sections On 26.5 1 Yes REFOUT EnabledAll Sections Off 1.0 0 Yes MCLK Active Levels Equal to 0 V and DVDDAll Sections Off 0.05 0 No Digital Inputs Static and Equal to 0 V or DVDD

The above values are in mA and are typical values unless otherwise noted. MCLK = 16.384 MHz; SCLK = 16.384 MHz.

TIMING CHARACTERISTICSLimit at

Parameter TA = –40�C to +85�C Unit Description

Clock Signals See Figure 1.t1 61 ns min MCLK Periodt2 24.4 ns min MCLK Width Hight3 24.4 ns min MCLK Width Low

Serial Port See Figures 3 and 4.t4 t1 ns min SCLK Periodt5 0.4 × t1 ns min SCLK Width Hight6 0.4 × t1 ns min SCLK Width Lowt7 20 ns min SDI/SDIFS Setup before SCLK Lowt8 0 ns min SDI/SDIFS Hold after SCLK Lowt9 10 ns max SDOFS Delay from SCLK Hight10 10 ns max SDOFS Hold after SCLK Hight11 10 ns max SDO Hold after SCLK Hight12 10 ns max SDO Delay from SCLK Hight13 30 ns max SCLK Delay from MCLK

(AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 3.6 V; AGND = DGND = 0 V; TA = TMlN to TMAX, unless other-wise noted.)

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t3

t2

t1

Figure 1. MCLK Timing

TO OUTPUTPIN

2.1V

100�A

100�A IOL

IOH

CL15pF

Figure 2. Load Circuit for Timing Specifications

t3 t1 t2

t13

* SCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE).

t4

t5 t6

MCLK

SCLK*

Figure 3. SCLK Timing

t11

t7

t9 t10

t12

t7

t8

SE (I)

SCLK (O)

SDIFS (I)

SDI (I)

SDOFS (O)

SDO (O)

THREE-STATE

THREE-STATE

THREE-STATE

D15 D2 D1 D0 D14

D15D1D14D15

D15

t8

D0

Figure 4. Serial Port (SPORT)

VIN – dBm0–85 5–75 –65 –55 –45 –35 –25 –15 –5

80

70

–10

S/(

N+D

) –

dB

30

20

10

0

50

40

60

3.17

Figure 5. S/(N+D) vs. VIN (ADC @ 3 V) Over VoicebandBandwidth (300 Hz–3.4 kHz)

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ABSOLUTE MAXIMUM RATINGS*(TA = 25°C unless otherwise noted)

AVDD, DVDD to GND . . . . . . . . . . . . . . . . –0.3 V to +4.6 VAGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 VDigital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 VAnalog I/O Voltage to AGND . . . . . . . . . . . . –0.3 V to AVDDOperating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°CStorage Temperature Range . . . . . . . . . . . . –65°C to +150°CMaximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C

ORDERING GUIDE

Temperature Package PackageModel Range Description Option

AD73360LAR –40°C to +85°C Small Outline IC (SOIC) R-28

PIN CONFIGURATION

R-28

CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection. Althoughthe AD73360L features proprietary ESD protection circuitry, permanent damage may occur ondevices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions arerecommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

SOIC, θJA Thermal Impedance . . . . . . . . . . . . . . . . . . 75°C/WLead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°CInfrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only; functional operation of thedevice at these or any other conditions above those listed in the operationalsections of this specification is not implied. Exposure to absolute maximum ratingconditions for extended periods may affect device reliability.

TOP VIEW(Not to Scale)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

AD73360L

SDO

MCLK

SCLK

RESET

DVDD

DGND

AGND2

VINP2

VINN2

VINP1

VINN1

AVDD2

REFCAP

REOUT

SDOFS

SDIFS

SDI

SE

AGND1

AVDD1

VINP6

VINN3

VINP3

VINN4

VINP4

VINN6

VINP5

VINN5

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PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 VINP2 Analog Input to the Positive Terminal of Input Channel 2.2 VINN2 Analog Input to the Negative Terminal of Input Channel 2.3 VINP1 Analog Input to the Positive Terminal of Input Channel 1.4 VINN1 Analog Input to the Negative Terminal of Input Channel 1.5 REFOUT Buffered Output of the Internal Reference, which has a nominal value of 1.2 V.6 REFCAP Reference Voltage for ADCs. A Bypass Capacitor to AGND2 of 0.1 µF is required for the on-chip

reference. The capacitor should be fixed to this pin. The internal reference can be overdriven by anexternal reference connected to this pin if required.

7 AVDD2 Analog Power Supply Connection.8 AGND2 Analog Ground/Substrate Connection.9 DGND Digital Ground/Substrate Connection.10 DVDD Digital Power Supply Connection.11 RESET Active Low-Reset Signal. This input resets the entire chip, resetting the control registers and clearing

the digital circuitry.12 SCLK Output Serial Clock, whose rate determines the serial transfer rate to/from the AD73360L. It is used

to clock data or control information to and from the serial port (SPORT). The frequency of SCLK isequal to the frequency of the master clock (MCLK) divided by an integer number—this integer num-ber being the product of the external master clock rate divider and the serial clock rate divider.

13 MCLK Master Clock Input. MCLK is driven from an external clock signal.14 SDO Serial Data Output of the AD73360L. Both data and control information may be output on this

pin and are clocked on the positive edge of SCLK. SDO is in three-state when no information is beingtransmitted and when SE is low.

15 SDOFS Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and it is active oneSCLK period before the first bit (MSB) of each output word. SDOFS is referenced to the positiveedge of SCLK. SDOFS is in three-state when SE is low.

16 SDIFS Framing Signal Input for SDI Serial Transfers. The frame sync is one-bit wide and it is valid oneSCLK period before the first bit (MSB) of each input word. SDIFS is sampled on the negative edge ofSCLK and is ignored when SE is low.

17 SDI Serial Data Input of the AD73360L. Both data and control information may be input on this pin andare clocked on the negative edge of SCLK. SDI is ignored when SE is low.

18 SE SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, theoutput pins of the SPORT are three-stated and the input pins are ignored. SCLK is also disabled inter-nally in order to decrease power dissipation. When SE is brought high, the control and data registers ofthe SPORT are at their original values (before SE was brought low); however, the timing counters andother internal registers are at their reset values.

19 AGND1 Analog Ground Connection.20 AVDD1 Analog Power Supply Connection.21 VINP6 Analog Input to the Positive Terminal of Input Channel 6.22 VINN6 Analog Input to the Negative Terminal of Input Channel 6.23 VINP5 Analog Input to the Positive Terminal of Input Channel 5.24 VINN5 Analog Input to the Negative Terminal of Input Channel 5.25 VINP4 Analog Input to the Positive Terminal of Input Channel 4.26 VINN4 Analog Input to the Negative Terminal of Input Channel 4.27 VINP3 Analog Input to the Positive Terminal of Input Channel 3.28 VINN3 Analog Input to the Negative Terminal of Input Channel 3.

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TERMINOLOGYAbsolute GainAbsolute gain is a measure of converter gain for a known signal.Absolute gain is measured (differentially) with a 1 kHz sinewave at 0 dBm0 for each ADC. The absolute gain specificationis used for gain tracking error specification.

CrosstalkCrosstalk is due to coupling of signals from a given channel toan adjacent channel. It is defined as the ratio of the amplitude ofthe coupled signal to the amplitude of the input signal. Crosstalkis expressed in dB.

Gain Tracking ErrorGain tracking error measures changes in converter output fordifferent signal levels relative to an absolute signal level. Theabsolute signal level is 0 dBm0 (equal to absolute gain) at 1 kHzfor each ADC. Gain tracking error at 0 dBm0 (ADC) is 0 dB bydefinition.

Group DelayGroup delay is defined as the derivative of radian phase withrespect to radian frequency, dø(f)/df. Group delay is a measureof average delay of a system as a function of frequency. A linearsystem with a constant group delay has a linear phase response.The deviation of group delay from a constant indicates thedegree of nonlinear phase response of the system.

Idle Channel NoiseIdle channel noise is defined as the total signal energy measuredat the output of the device when the input is grounded (mea-sured in the frequency range 0 Hz–4 kHz).

Intermodulation DistortionWith inputs consisting of sine waves at two frequencies, fa andfb, any active device with nonlinearities will create distortionproducts at sum and difference frequencies of mfa ± nfb wherem, n = 0, 1, 2, 3, etc. Intermodulation terms are those for whichneither m nor n are equal to zero. For final testing, the secondorder terms include (fa + fb) and (fa – fb), while the third orderterms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

Power Supply RejectionPower supply rejection measures the susceptibility of a device tonoise on the power supply. Power supply rejection is measuredby modulating the power supply with a sine wave and measuringthe noise at the output (relative to 0 dB).

Sample RateThe sample rate is the rate at which each ADC updates its outputregister. It is set relative to the DMCLK and the programmablesample rate setting.

SNR + THDSignal-to-noise ratio plus harmonic distortion is defined to bethe ratio of the rms value of the measured input signal to therms sum of all other spectral components in a given frequencyrange, including harmonics but excluding dc.

ABBREVIATIONSADC Analog-to-Digital Converter.

BW Bandwidth.

CRx A Control Register where x is a placeholder foran alphabetic character (A–E). There are eightread/write control registers on the AD73360L—designated CRA through CRE.

CRx:n A bit position, where n is a placeholder for anumeric character (0–7), within a control regis-ter; where x is a placeholder for an alphabeticcharacter (A–E). Position 7 represents the MSBand Position 0 represents the LSB.

DMCLK Device (Internal) Master Clock. This is theinternal master clock resulting from the externalmaster clock (MCLK) being divided by the on-chip master clock divider.

FSLB Frame Sync Loop-Back—where the SDOFS ofthe final device in a cascade is connected to theRFS and TFS of the DSP and the SDIFS of firstdevice in the cascade. Data input and outputoccur simultaneously. In the case of non-FSLB,SDOFS and SDO are connected to the Rx Portof the DSP while SDIFS and SDI are connectedto the Tx Port.

PGA Programmable Gain Amplifier.

SC Switched Capacitor.

SNR Signal-to-Noise Ratio.

SPORT Serial Port.

THD Total Harmonic Distortion.

VBW Voice Bandwidth.

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FUNCTIONAL DESCRIPTIONGeneral DescriptionThe AD73360L is a six-input channel, 16-bit, analog front end.It comprises six independent encoder channels each featuringsignal conditioning, programmable gain amplifier, sigma-deltaA/D converter and decimator sections. Each of these sections isdescribed in further detail below.

Encoder ChannelEach encoder channel consists of a signal conditioner, a switchedcapacitor PGA, and a sigma-delta analog-to-digital converter(ADC). An on-board digital filter, which forms part of thesigma-delta ADC, also performs critical system-level filtering.Due to the high-level of oversampling, the input antialias require-ments are reduced such that a simple single pole RC stage issufficient to give adequate attenuation in the band of interest.

Signal ConditionerEach analog channel has an independent signal conditioningblock. This allows the analog input to be configured by the userdepending on whether differential or single-ended mode is used.

Programmable Gain AmplifierEach encoder section’s analog front end comprises a switchedcapacitor PGA that also forms part of the sigma-delta modula-tor. The SC sampling frequency is DMCLK/8. The PGA,whose programmable gain settings are shown in Table II, maybe used to increase the signal level applied to the ADC fromlow-output sources such as microphones, and can be used toavoid placing external amplifiers in the circuit. The input signallevel to the sigma-delta modulator should not exceed the maxi-mum input voltage permitted.

The PGA gain is set by bits IGS0, IGS1, and IGS2 in controlRegisters D, E, and F.

Table II. PGA Settings for the Encoder Channel

IxGS2 IxGS1 IxGS0 Gain (dB)

0 0 0 00 0 1 60 1 0 120 1 1 181 0 0 201 0 1 261 1 0 321 1 1 38

ADCEach channel has its own ADC consisting of an analog sigma-delta modulator and a digital antialiasing decimation filter. Thesigma-delta modulator noise-shapes the signal and produces1-bit samples at a DMCLK/8 rate. This bitstream, representingthe analog input signal, is input to the antialiasing decimationfilter. The decimation filter reduces the sample rate and increasesthe resolution.

Analog Sigma-Delta ModulatorThe AD73360L input channels employ a sigma-delta conver-sion technique, which provides a high resolution 16-bit outputwith system filtering being implemented on-chip.

Sigma-delta converters employ a technique known as over-sampling, where the sampling rate is many times the highestfrequency of interest. In the case of the AD73360L, the initialsampling rate of the sigma-delta modulator is DMCLK/8. Themain effect of oversampling is that the quantization noise isspread over a very wide bandwidth, up to fS/2 = DMCLK/16(Figure 6a). This means that the noise in the band of interest ismuch reduced. Another complementary feature of sigma-deltaconverters is the use of a technique called noise-shaping. Thistechnique has the effect of pushing the noise from the band ofinterest to an out-of-band position (Figure 6b). The combina-tion of these techniques, followed by the application of a digitalfilter, reduces the noise in band sufficiently to ensure gooddynamic performance from the part (Figure 6c).

BANDOF

INTEREST

fS/2DMCLK/16

fS/2DMCLK/16

fS/2DMCLK/16

DIGITAL FILTER

NOISE-SHAPING

BANDOF

INTEREST

BANDOF

INTEREST

a.

b.

c.

Figure 6. Sigma-Delta Noise Reduction

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Figure 7 shows the various stages of filtering that are employedin a typical AD73360L application. In Figure 7a we see the trans-fer function of the external analog antialias filter. Even though itis a single RC pole, its cutoff frequency is sufficiently far awayfrom the initial sampling frequency (DMCLK/8) that it takes careof any signals that could be aliased by the sampling frequency.This also shows the major difference between the initial oversam-pling rate and the bandwidth of interest. In Figure 7b, the signaland noise-shaping responses of the sigma-delta modulator areshown. The signal response provides further rejection of anyhigh-frequency signals while the noise-shaping will push theinherent quantization noise to an out-of-band position. The detailof Figure 7c shows the response of the digital decimation filter(sinc-cubed response) with nulls every multiple of DMCLK/256, which is the decimation filter update rate. The final detailin Figure 7d shows the application of a final antialias filter in theDSP engine. This has the advantage of being implemented accord-ing to the user’s requirements and available MIPS. The filtering inFigures 7a through 7c is implemented in the AD73360L.

FB = 4kHz FSINIT = DMCLK/8

a. Analog Antialias Filter Transfer Function

FB = 4kHz FSINIT = DMCLK/8

NOISE TRANSFER FUNCTION

SIGNAL TRANSFER FUNCTION

b. Analog Sigma-Delta Modulator Transfer Function

FB = 4kHz FSINTER = DMCLK/256

c. Digital Decimator Transfer Function

FB = 4kHz FSINTER = DMCLK/256FSFINAL = 8kHz

d. Final Filter LPF (HPF) Transfer Function

Figure 7. DC Frequency Responses

Decimation FilterThe digital filter used in the AD73360L carries out two impor-tant functions. Firstly, it removes the out-of-band quantizationnoise, which is shaped by the analog modulator and secondly, itdecimates the high-frequency bitstream to a lower rate 15-bit word.

The antialiasing decimation filter is a sinc-cubed digital filterthat reduces the sampling rate from DMCLK/8 to DMCLK/256, and increases the resolution from a single bit to 15 bits. ItsZ transform is given as: [(1–Z–32)/(1–Z–1)]3. This ensures a mini-mal group delay of 25 µs.Word growth in the decimator is determined by the samplingrate. At 64 kHz sampling, where the oversampling ratio betweenthe sigma-delta modulator and decimator output equals 32,there are five bits per stage of the three-stage Sinc3 filter. Due tosymmetry within the sigma-delta modulator, the LSB will alwaysbe a zero; therefore, the 16-bit ADC output word will have2 LSBs equal to zero, one due to the sigma-delta symmetry andthe other being a padded zero to make up a 16-bit word. Atlower sampling rates, decimator word growth will be greaterthan the 16-bit sample word, therefore truncation occurs in trans-ferring the decimator output as the ADC word. For exampleat 8 kHz sampling, word growth reaches 24 bits due to the OSRof 256 between sigma-delta modulator and decimator. This yieldseight bits per stage of the three stage Sinc3 filter.

ADC CodingThe ADC coding scheme is in two’s complement format (seeFigure 8). The output words are formed by the decimationfilter, which grows the word length from the single-bit output ofthe sigma-delta modulator to a 15-bit word, which is the finaloutput of the ADC block. In 16-bit Data Mode this value is leftshifted with the LSB being set to 0. For input values equal to orgreater than positive full scale, however, the output word is setat 0x7FFF, which has the LSB set to 1. In mixed Control/DataMode, the resolution is fixed at 15 bits, with the MSB of the16-bit transfer being used as a flag bit to indicate either controlor data in the frame.

VREF + (VREF � 0.32875)

VREF

VREF – (VREF � 0.32875)

10...00 00...00 01...11

ADC CODE DIFFERENTIAL

ANALOGINPUT

VINN

VINP

VREF + (VREF � 0.6575)

VREF – (VREF � 0.6575)

10...00 00...00 01...11ADC CODE SINGLE-ENDED

ANALOGINPUT

VINP

VINN

Figure 8. ADC Transfer Function

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Voltage ReferenceThe AD73360L reference, REFCAP, is a bandgap referencethat provides a low noise, temperature-compensated referenceto the ADC. A buffered version of the reference is also madeavailable on the REFOUT pin and can be used to bias otherexternal analog circuitry. The reference has a default nominalvalue of 1.2 V.

The reference output (REFOUT) can be enabled for biasingexternal circuitry by setting the RU bit (CRC:6) of CRC.

Serial Port (SPORT)The AD73360Ls communicate with a host processor via thebidirectional synchronous serial port (SPORT) which is compat-ible with most modern DSPs. The SPORT is used to transmitand receive digital data and control information. Two AD73360Lscan be cascaded together to provide additional input channels.

In both transmit and receive modes, data is transferred at theserial clock (SCLK) rate with the MSB being transferred first.

Due to the fact that the SPORT of each AD73360L block usesa common serial register for serial input and output, communi-cations between an AD73360L and a host processor (DSPengine) must always be initiated by the AD73360Ls themselves.In this configuration the AD73360Ls are described as being inMaster mode. This ensures that there is no collision betweeninput data and output samples.

SPORT OverviewThe AD73360L SPORT is a flexible, full-duplex, synchronousserial port whose protocol has been designed to allow up toeight AD73360L devices to be connected in cascade, to a singleDSP via a six-wire interface. It has a very flexible architecturethat can be configured by programming two of the internalcontrol registers in each device. The AD73360L SPORT hasthree distinct modes of operation: Control Mode, Data Modeand Mixed Control/Data Mode.

MCLK

MCLKDIVIDER

DMCLK(INTERNAL)

SERIAL PORT(SPORT)

SERIAL REGISTER

SCLKDIVIDER

CONTROLREGISTER

C

CONTROLREGISTER

D

CONTROLREGISTER

E

CONTROLREGISTER

F

CONTROLREGISTER

G

CONTROLREGISTER

H

CONTROLREGISTER

A

CONTROLREGISTER

B

SE

RESET

SDIFS

SDI3

8 8 8 8 8

8

2

SCLK

SDOFS

SDO

Figure 9. SPORT Block Diagram

Note: As each AD73360L has its own SPORT section, theregister settings in all SPORTs must be programmed. The regis-ters that control SPORT and sample rate operation (CRA andCRB) must be programmed with the same values, otherwiseincorrect operation may occur.

In Program Mode (CRA:0 = 0), the device’s internal configura-tion can be programmed by writing to the eight internal controlregisters. In this mode, control information can be written to orread from the AD73360L. In Data Mode (CRA:0 = 1), any infor-mation that is sent to the device is ignored, while the encodersection (ADC) data is read from the device. In this mode, onlyADC data is read from the device. Mixed mode (CRA:0 = 1 andCRA:1 = 1) allows the user to send control information andreceive either control information or ADC data. This is achievedby using the MSB of the 16-bit frame as a flag bit. Mixed modereduces the resolution to 15 bits with the MSB being used toindicate whether the information in the 16-bit frame is controlinformation or ADC data.

The SPORT features a single 16-bit serial register that is used forboth input and output data transfers. As the input and outputdata must share the same register, some precautions must beobserved. The primary precaution is that no information must bewritten to the SPORT without reference to an output sampleevent, which is when the serial register will be overwritten withthe latest ADC sample word. Once the SPORT starts to outputthe latest ADC word, it is safe for the DSP to write new controlwords to the AD73360L. In certain configurations, data can bewritten to the device to coincide with the output sample beingshifted out of the serial register—see section on interfacingdevices. The serial clock rate (CRB:2–3) defines how many 16-bitwords can be written to a device before the next output sampleevent will happen.

The SPORT block diagram, shown in Figure 9, details the blocksassociated with AD73360L including the eight control registers(A–H), external MCLK to internal DMCLK divider and serialclock divider. The divider rates are controlled by the setting ofControl Register B. The AD73360L features a master clockdivider that allows users the flexibility of dividing externallyavailable high-frequency DSP or CPU clocks to generate a lowerfrequency master clock internally in the AD73360L which may bemore suitable for either serial transfer or sampling rate require-ments. The master clock divider has five divider options (÷ 1default condition, ÷ 2, ÷ 3, ÷ 4, ÷ 5) that are set by loading themaster clock divider field in Register B with the appropriatecode (see Table XIII). Once the internal device master clock(DMCLK) has been set using the master clock divider, the samplerate and serial clock settings are derived from DMCLK.

The SPORT can work at four different serial clock (SCLK) rates:chosen from DMCLK, DMCLK/2, DMCLK/4 or DMCLK/8,where DMCLK is the internal or device master clock resultingfrom the external or pin master clock being divided by the masterclock divider. Care should be taken when selecting Master Clock,Serial Clock, and Sample Rate divider settings to ensure thatthere is sufficient time to read all the data from the AD73360Lbefore the next sample interval.

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Table IV. Control Word Description

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

C/D R/W DEVICE ADDRESSS REGISTER ADDRESS REGISTER DATA

Control Frame Description

Bit 15 Control/Data When set high, it signifies a control word in Program or Mixed Program/Data Modes. When setlow, it signifies an invalid control word in Program Mode.

Bit 14 Read/Write When set low, it tells the device that the data field is to be written to the register selected by theregister field setting provided the address field is zero. When set high, it tells the device that theselected register is to be written to the data field in the serial register and that the new controlword is to be output from the device via the serial output.

Bits 13–11 Device Address This 3-bit field holds the address information. Only when this field is zero is a device selected. Ifthe address is not zero, it is decremented and the control word is passed out of the device via theserial output.

Bits 10–8 Register Address This 3-bit field is used to select one of the eight control registers on the AD73360L.Bits 7–0 Register Data This 8-bit field holds the data that is to be written to the selected register provided the device

address field is zero.

Table III. Control Register Map

Address (Binary) Name Description Type Width Reset Setting (Hex)

000 CRA Control Register A R/W 8 0x00001 CRB Control Register B R/W 8 0x00010 CRC Control Register C R/W 8 0x00011 CRD Control Register D R/W 8 0x00100 CRE Control Register E R/W 8 0x00101 CRF Control Register F R/W 8 0x00110 CRG Control Register G R/W 8 0x00111 CRH Control Register H R/W 8 0x00

Table V. Control Register A Description

7 6 5 4 3 2 1 0

RESET DC2 DC1 DC0 SLB RES MM DATA/PGM

Bit Name Description

0 DATA/PGM Operating Mode (0 = Program; 1 = Data Mode)1 MM Mixed Mode (0 = OFF; 1 = Enabled)2 Reserved Must Be Programmed to Zero (0)3 SLB SPORT Loop-Back Mode (0 = OFF; 1 = Enabled)4 DC0 Device Count (Bit 0)5 DC1 Device Count (Bit 1)6 DC2 Device Count (Bit 2)7 RESET Software Reset (0 = OFF; 1 = Initiates Reset)

CONTROL REGISTER A

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Table VI. Control Register B Description

7 6 5 4 3 2 1 0

CEE MCD2 MCD1 MCD0 SCD1 SCD0 DR1 DR0


0 DR0 Decimation Rate (Bit 0)1 DR1 Decimation Rate (Bit 1)2 SCD0 Serial Clock Divider (Bit 0)3 SCD1 Serial Clock Divider (Bit 1)4 MCD0 Master Clock Divider (Bit 0)5 MCD1 Master Clock Divider (Bit 1)6 MCD2 Master Clock Divider (Bit 2)7 CEE Control Echo Enable (0 = OFF; 1 = Enabled)

Table VII. Control Register C Description

7 6 5 4 3 2 1 0

RES RU PUREF RES RES RES RES GPU


0 GPU Global Power-Up Device (0 = Power Down; 1 = Power Up)1 Reserved Must Be Programmed to Zero (0)2 Reserved Must Be Programmed to Zero (0)3 Reserved Must Be Programmed to Zero (0)4 Reserved Must Be Programmed to Zero (0)5 PUREF REF Power (0 = Power Down; 1 = Power Up)6 RU REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT)7 Reserved Must Be Programmed to Zero (0)

Table VIII. Control Register D Description

7 6 5 4 3 2 1 0

PUI2 I2GS2 I2GS1 I2GS0 PUI1 I1GS2 I1GS1 I1GS0


0 I1GS0 ADC1:Input Gain Select (Bit 0)1 I1GS1 ADC1:Input Gain Select (Bit 1)2 I1GS2 ADC1:Input Gain Select (Bit 2)3 PUI1 Power Control (ADC1); 1 = ON, 0 = OFF4 I2GS0 ADC2:Input Gain Select (Bit 0)5 I2GS1 ADC2:Input Gain Select (Bit 1)6 I2GS2 ADC2:Input Gain Select (Bit 2)7 PUI2 Power Control (ADC2); 1 = ON, 0 = OFF

CONTROL REGISTER B

CONTROL REGISTER D

CONTROL REGISTER C

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Table IX. Control Register E Description

7 6 5 4 3 2 1 0




Table X. Control Register F Description

7 6 5 4 3 2 1 0




Table XI. Control Register G Description

7 6 5 4 3 2 1 0

SEEN RMOD CH6 CH5 CH4 CH3 CH2 CH1


0 CH1 Channel 1 Select1 CH2 Channel 2 Select2 CH3 Channel 3 Select3 CH4 Channel 4 Select4 CH5 Channel 5 Select5 CH6 Channel 6 Select6 RMOD Reset Analog Modulator7 SEEN Enable Single-Ended Input Mode

CONTROL REGISTER E

CONTROL REGISTER G

CONTROL REGISTER F

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Table XII. Control Register H Description

7 6 5 4 3 2 1 0

INV TME CH6 CH5 CH4 CH3 CH2 CH1


0 CH1 Channel 1 Select1 CH2 Channel 2 Select2 CH3 Channel 3 Select3 CH4 Channel 4 Select4 CH5 Channel 5 Select5 CH6 Channel 6 Select6 TME Test Mode Enable7 INV Enable Invert Channel Mode

REGISTER BIT DESCRIPTIONSControl Register ACRA:0 Data/Program Mode. This bit controls the operating mode of the AD73360L. If CRA:1 is 0, a 0 in this bit places the

part in Program Mode. If CRA:1 is 0, a 1 in this bit places the part in Data Mode.

CRA:1 Mixed Mode. If this bit is a 0, the operating mode is determined by CRA:0. If this bit is a 1, the part operates inMixed Mode.

CRA:2 Reserved. This bit is reserved and should be programmed to 0 to ensure correct operation.

CRA:3 SPORT Loop Back. This is a diagnostic mode. This bit should be set to 0 to ensure correct operation.

CRA:4–6 Device Count Bits. These bits tell the AD73360L how many devices are used in a cascade. Both devices in thecascade should be programmed to the same value ensure correct operation. See Table XVI.

CRA:7 Reset. Writing a 1 to this bit will initiate a software reset of the AD73360L.

Control Register BCRB:0–1 Decimation Rate. These bits are used to set the decimation of the AD73360L. See Table XV.

CRB:2–3 Serial Clock Divider. These bits are used to set the serial clock frequency. See Table XIV.

CRB:4–6 Master Clock Divider. These bits are used to set the Master Clock Divider ratio. See Table XIII.

CRB:7 Control Echo Enable. Setting this bit to a 1 will cause the AD73360L to write out any control words it receives.This is used as a diagnostic mode. This bit should be set to 0 for correct operation in Mixed Mode or Data Mode.

Control Register CCRC:0 Global Power-Up. Writing a 1 to this bit will cause all six channels of the AD73360L to power up, regardless of

the status of the Power Control Bits in CRD-CRF. If fewer than six channels are required, this bit should be set to0 and the Power Control Bits of the relevant channels should be set to 1.

CRC:1–4 Reserved. These bits are reserved and should be programmed to 0 to ensure correct operation.

CRC:5 Power-Up Reference. This bit controls the state of the on-chip reference. A 1 in this bit will power up the refer-ence. A 0 in this bit will power down the reference. Note that the reference is automatically powered up if anychannel is enabled.

CRC:6 Reference Output. When this bit is set to 1, the REFOUT pin is enabled.

CRC:7 Reserved. This bit is reserved and should be programmed to 0 to ensure correct operation.

Control Register DCRD:0–2 Input Gain Selection. These bits select the input gain for ADC1. See Table II.

CRD:3 Power Control for ADC1. A 1 in this bit powers up ADC1.

CRD:4–6 Input Gain Selection. These bits select the input gain for ADC2. See Table II.

CRD:7 Power Control for ADC2. A 1 in this bit powers up ADC2.

Control Register ECRE:0–2 Input Gain Selection. These bits select the input gain for ADC3. See Table II.

CRE:3 Power Control for ADC3. A 1 in this bit powers up ADC3.

CRE:4–6 Input Gain Selection. These bits select the input gain for ADC4. See Table II.

CRE:7 Power Control for ADC4. A 1 in this bit powers up ADC4.

CONTROL REGISTER H

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Control Register FCRF:0–2 Input Gain Selection. These bits select the input gain for ADC5. See Table II.

CRF:3 Power Control for ADC5. A 1 in this bit powers up ADC5.

CRF:4–6 Input Gain Selection. These bits select the input gain for ADC6. See Table II.

CRF:7 Power Control for ADC6. A 1 in this bit powers up ADC6.

Control Register GCRG:0–5 Channel Select. These bits are used in association with CRG:6 and CRG:7. If the Reset Analog Modulator bit

(CRG:6) is 1, a 1 in a Channel Select bit location will reset the Analog Modulator for that channel. If the Single-Ended Enable Mode bit (CRG:7) is 1, a 1 in a Channel Select bit location will put that channel into Single-EndedMode. If any channel has its Channel Select bit set to 0, the channel will be set for Differentially-Ended Mode andwill not have its analog modulator reset regardless of the state of CRG:6 and CRG:7.

CRG:6 Reset Analog Modulator. Setting this bit to a 1 will reset the Analog Modulators for any channel whose ChannelSelect bit (CRG:0–5) is set to 1. This bit should be set to 0 for normal operation.

CRG:7 Single-Ended Enable Mode. Setting this bit to a 1 will enable Single-Ended Mode on any channel whose ChannelSelect bit (CRG:0–5) is set to 1. Setting this bit to 0 will select Differentially-Ended Input Mode for all channels.

Control Register HCRH:0–5 Invert Select. These bits are used in association with CRH:7. If the Enable Invert Channel Mode bit (CRH:7) is 1,

a 1 in a Channel Select bit location will put that channel into Inverted Mode. If any channel has its Channel Selectbit set to 0, the channel will not be inverted regardless of the state CRH:7.

CRH:6 Test Mode Enable. This bit should be set to 0 to ensure normal operation.

CRH:7 Enable Invert Channel Mode. Setting this bit to a 1 will enable invert any channel whose Channel Select bit(CRH:0–5) is set to 1. Setting this bit to 0 will select Noninverted (Normal) Mode for all channels.

SPORT Register MapsThere are eight control registers for the AD73360L, each eightbits wide. Table III shows the control register map for theAD73360L. The first two control registers, CRA and CRB, arereserved for controlling the SPORT. They hold settings forparameters such as bit rate, internal master clock rate, and devicecount. If two AD73360Ls are cascaded, Registers CRA andCRB on each device must be programmed with the same settingto ensure correct operation (this is shown in the programmingexamples). The other six registers; CRC through CRH areused to hold control settings for the Reference, Power Control,ADC channel, and PGA sections of the device. It is not necessarythat the contents of CRC through CRH on each AD73360Lare similar. Control registers are written to on the negativeedge of SCLK.

Master Clock DividerThe AD73360L features a programmable master clock dividerthat allows the user to reduce an externally available masterclock, at pin MCLK, by one of the ratios 1, 2, 3, 4, or 5 toproduce an internal master clock signal (DMCLK) that is usedto calculate the sampling and serial clock rates. The masterclock divider is programmable by setting CRB:4-6. Table XIIIshows the division ratio corresponding to the various bit set-tings. The default divider ratio is divide-by-one.

Table XIII. DMCLK (Internal) Rate Divider Settings

MCD2 MCD1 MCD0 DMCLK Rate

0 0 0 MCLK0 0 1 MCLK/20 1 0 MCLK/30 1 1 MCLK/41 0 0 MCLK/51 0 1 MCLK1 1 0 MCLK1 1 1 MCLK

Serial Clock Rate DividerThe AD73360L features a programmable serial clock dividerthat allows users to match the serial clock (SCLK) rate of thedata to that of the DSP engine or host processor. The maximumSCLK rate available is DMCLK and the other available ratesare: DMCLK/2, DMCLK/4, and DMCLK/8. The slowest rate(DMCLK/8) is the default SCLK rate. The serial clock divideris programmable by setting bits CRB:2–3. Table XIV shows theserial clock rate corresponding to the various bit settings.

Table XIV. SCLK Rate Divider Settings

SCD1 SCD0 SCLK Rate

0 0 DMCLK/80 1 DMCLK/41 0 DMCLK/21 1 DMCLK

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Decimation Rate DividerThe AD73360L features a programmable decimation rate dividerthat allows users flexibility in matching the AD73360L’s ADCsample rates to the needs of the DSP software. The maximumsample rate available is DMCLK/256 and the other availablerates are: DMCLK/512, DMCLK/1024, and DMCLK/2048. Theslowest rate (DMCLK/2048) is the default sample rate. Thesample rate divider is programmable by setting bits CRB:0-1.Table XV shows the sample rate corresponding to the variousbit settings.

Table XV. Decimation Rate Divider Settings

DR1 DR0 Sample Rate

0 0 DMCLK/20480 1 DMCLK/10241 0 DMCLK/5121 1 DMCLK/256

OPERATIONGeneral DescriptionThe AD73360L inputs and outputs data in a Time DivisionMultiplexing (TDM) format. When data is being read from theAD73360L each channel has a fixed time slot in which its datais transmitted. If a channel is not powered up, no data is trans-mitted during the allocated time slot and the SDO line will bethree-stated. When the AD73360L is first powered up or reset itwill be set to Program Mode and will output an SDOFS. After areset the SDOFS will be asserted once every sample period(125 µs assuming 16.384 MHz master clock). If the AD73360Lis configured in Frame Sync Loop-Back Mode, one controlword can be transmitted after each SDOFS pulse. Figure 10ashows the SDO and SDOFS lines after a reset. The serial datasent by SDO will not contain valid ADC data until the AD73360Lis put into Data Mode or Mixed Mode. Control Registers D

through F allow channels to be powered up individually. Thisgives greater flexibility and control over power consumption.Figure 10b shows the SDOFS and SDO of the AD73360L whenall channels are powered up and Figure 10c shows SDOFS andSDO with Channels 1, 3, and 5 powered up.

Resetting the AD73360LThe RESET pin resets all the control registers. All registers arereset to zero, indicating that the default SCLK rate (DMCLK/8)and sample rate (DMCLK/2048) are at a minimum to ensurethat slow speed DSP engines can communicate effectively. Aswell as resetting the control registers using the RESET pin, thedevice can be reset using the RESET bit (CRA:7) in ControlRegister A. Both hardware and software resets require fourDMCLK cycles. On reset, DATA/PGM (CRA:0) is set to 0(default condition) thus enabling Program Mode. The resetconditions ensure that the device must be programmed to thecorrect settings after power-up or reset. Following a reset, theSDOFS will be asserted approximately 2070 master (MCLK)cycles after RESET goes high. The data that is output followingthe reset and during Program Mode is random and contains novalid information until either data or mixed mode is set.

Power ManagementThe individual functional blocks of the AD73360L can be enabledseparately by programming the power control register CRC. Itallows certain sections to be powered down if not required, whichadds to the device’s flexibility in that the user need not incur thepenalty of having to provide power for a certain section if it isnot necessary to their design. The power control registers provideindividual control settings for the major functional blocks oneach analog front-end unit and also a global override that allowsall sections to be powered up/down by setting/clearing the bit.Using this method the user could, for example, individuallyenable a certain section, such as the reference (CRC:5), anddisable all others. The global power-up (CRC:0) can be used toenable all sections but if power-down is required using the global

SDOFS

SDO

SE

1/FSAMPLE

Figure 10a. Output Timing After Reset (Program Mode)

SDOFS

SDO

SE

CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6

Figure 10b. Output Timing: All Channels Powered Up (Data/Mixed Mode)

SDOFS

SDO

SE

CHANNEL 5CHANNEL 1 CHANNEL 3

Figure 10c. Output Timing: Channels 1, 3, and 5 Powered Up (Data/Mixed Mode)

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control, the reference will still be enabled; in this case, becauseits individual bit is set. Refer to Table VII for details of the settingsof CRC. CRD–CRF can be used to control the power status ofindividual channels allowing multiple channels to be powereddown if required.

Operating ModesThree operating modes are available on the AD73360L. They areProgram, Data, and Mixed Program/Data. The device configu-ration—register settings—can be changed only in Program andMixed Program/Data Modes. In all modes, transfers of infor-mation to or from the device occur in 16-bit packets, thereforethe DSP engine’s SPORT will be programmed for 16-bit transfers.

Program (Control) ModeIn Program Mode, CRA:0 = 0, the user writes to the controlregisters to set up the device for desired operation—SPORToperation, cascade length, power management, input gain, etc. Inthis mode, the 16-bit information packet sent to the device bythe DSP engine is interpreted as a control word whose format isshown in Table IV. In this mode, the user must address the deviceto be programmed using the address field of the control word. Thisfield is read by the device and if it is zero (000 bin), the devicerecognizes the word as being addressed to it. If the address fieldis not zero, it is then decremented and the control word is passedout of the device—either to the next device in a cascade or backto the DSP engine. This 3-bit address format allows the user touniquely address any one of up to eight devices in a cascade. Ifthe AD73360L is used in a stand-alone configuration connectedto a DSP, the device address corresponds to 0. If, on the otherhand, the AD73360L is configured in a cascade of two devices,its device address corresponds with its hardwired position inthe cascade.

Following reset, when the SE pin is enabled, the AD73360Lresponds by raising the SDOFS pin to indicate that an outputsample event has occurred. Control words can be written to thedevice to coincide with the data being sent out of the SPORT,as shown in Figure 12 (Directly Coupled), or they can lag theoutput words by a time interval that should not exceed the sampleinterval (Indirectly Coupled). Refer to the Digital Interface sectionfor more information. After reset, output frame sync pulseswill occur at a slower default sample rate, which is DMCLK/2048, until Control Register B is programmed, after which theSDOFS will be pulsed at the selected rate. This is to allowslow controller devices to establish communication with theAD73360L. During Program Mode, the data output by thedevice is random and should not be interpreted as ADC data.

Data ModeOnce the device has been configured by programming the cor-rect settings to the various control registers, the device may exitProgram Mode and enter Data Mode. This is done by program-ming the DATA/PGM (CRA:0) bit to a 1 and MM (CRA:1) to0. Once the device is in Data Mode, the input data is ignored.When the device is in normal Data Mode (i.e., Mixed Modedisabled), it must receive a hardware reset to reprogram any ofthe control register settings.

Appendix C details the initialization and operation of an analogfront-end cascade in normal Data Mode.

Mixed Program/Data ModeThis mode allows the user to send control words to the devicewhile receiving ADC words. This permits adaptive control ofthe device whereby control of the input gains can be affected byreprogramming the control registers. The standard data frameremains 16 bits, but now the MSB is used as a flag bit to indicatethat the remaining 15 bits of the frame represent control infor-mation. Mixed Mode is enabled by setting the MM bit (CRA:1)to 1 and the DATA/PGM bit (CRA:0) to 1. In the case wherecontrol setting changes will be required during normal opera-tion, this mode allows the ability to load control informationwith the slight inconvenience of formatting the data. Note thatthe output samples from the ADC will also have the MSB set tozero to indicate it is a data word.

A description of a single device operating in mixed mode isdetailed in Appendix B, while Appendix D details the initializa-tion and operation of an analog front-end cascade operating inmixed mode. Note that it is not essential to load the controlregisters in Program Mode before setting mixed mode active.Mixed Mode may be selected with the first write by programmingCRA and then transmitting other control words.

Channel SelectionThe ADC channels of the AD73360L can be powered up ordown individually by programming the PUIx bit of registers CRDto CRF. If the AD73360L is being used in Mixed Data/ControlMode individual channels may be powered up or down as theprogram requires. In Data Mode, the number of channels selectedwhile the AD73360L was in Program Mode is fixed and cannotbe altered without resetting and reprogramming the AD73360L.In all cases, ADC Channel 1 must be powered up as the framesync pulse generated by this channel defines the start of a newsample interval.

INTERFACINGThe AD73360L can be interfaced to most modern DSP enginesusing conventional serial port connections and an extra enablecontrol line. Both serial input and output data use an accompa-nying frame synchronization signal that is active high one clockcycle before the start of the 16-bit word or during the last bit ofthe previous word if transmission is continuous. The serial clock(SCLK) is an output from the AD73360L and is used to definethe serial transfer rate to the DSP’s Tx and Rx ports. Two primaryconfigurations can be used: the first is shown in Figure 11 wherethe DSP’s Tx data, Tx frame sync, Rx data, and Rx frame sync areconnected to the AD73360L’s SDI, SDIFS, SDO, and SDOFSrespectively. This configuration, referred to as indirectly coupledor nonframe sync loop-back, has the effect of decoupling thetransmission of input data from the receipt of output data. Whenprogramming the DSP serial port for this configuration, it isnecessary to set the Rx frame sync as an input to the DSP andthe Tx frame sync as an output generated by the DSP. Thisconfiguration is most useful when operating in mixed mode, asthe DSP has the ability to decide how many words can be sentto the AD73360L(s). This means that full control can be imple-mented over the device configuration in a given sample interval.

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The second configuration (shown in Figure 12) has the DSP’sTx data and Rx data connected to the AD73360L’s SDI andSDO, respectively, while the DSP’s Tx and Rx frame syncs areconnected to the AD73360L’s SDIFS and SDOFS. In this con-figuration, referred to as directly coupled or frame sync loop-back,the frame sync signals are connected together and the input datato the AD73360L is forced to be synchronous with the output datafrom the AD73360L. The DSP must be programmed so thatboth the Tx and Rx frame syncs are inputs as the AD73360L’sSDOFS will be input to both. This configuration guaranteesthat input and output events occur simultaneously and is thesimplest configuration for operation in normal Data Mode. Notethat when programming the DSP in this configuration it isadvisable to preload the Tx register with the first control word tobe sent before the AD73360L is taken out of reset. This ensuresthat this word will be transmitted to coincide with the first out-put word from the device(s).

TFS

DT

SCLK

DR

RFS

ADSP-21xxDSP

AD73360LANALOG

FRONT-END

SDIFS

SDI

SCLK

SDO

SDOFS

FL0

FL1

RESET

SE

Figure 13. AD73360L Connected to ADSP-21xx

FSX

DX

CLKX

CLKR

DR

TMS320C5xDSP

AD73360LANALOG

FRONT-END

SDIFS

SDI

SCLK

SDO

SDOFSFSR

XF RESET

SE

Figure 14. AD73360L Connected to TMS320C5x

TFS

DT

SCLK

DR

RFS

ADSP-21xxDSP AD73360L

SDIFS

SDI

SCLK

SDO

SDOFS

Figure 11. Indirectly Coupled or Nonframe Sync Loop-Back Configuration

TFS

DT

SCLK

DR

RFS

ADSP-21xxDSP AD73360L

SDIFS

SDI

SCLK

SDO

SDOFS

Figure 12. Directly Coupled or Frame Sync Loop-Back Configuration

Digital InterfacingThe AD73360L is designed to easily interface to most commonDSPs. The SCLK, SDO, SDOFS, SDI, and SDIFS must beconnected to the SCLK, DR, RFS, DT, and TFS pins of theDSP respectively. The SE pin may be controlled from a paralleloutput pin or flag pin such as FL0–2 on the ADSP-21xx (or XFon the TMS320C5x) or, where SPORT power-down is notrequired, it can be permanently strapped high using a suitablepull-up resistor. For consistent performance the SE should besynchronized to the rising edge of MCLK using a circuit similar tothat of Figure 19. The RESET pin may be connected to the systemhardware reset structure or it may also be controlled using adedicated control line. In the event of tying it to the global systemreset, it is necessary to operate the device in mixed mode, whichallows a software reset, otherwise there is no convenient way ofresetting the device. Figures 11 and 12 show typical connectionsto an ADSP-2181 while Figures 13 and 14 show typical connec-tions to an ADSP-21xx and a TMS320C5x, respectively.

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SE

SDI CONTROL WORD CONTROL WORD

SDIFS

UNDEFINED DATASDO UNDEFINED DATA

SDOFS

SCLK

Figure 15a. Interface Signal Timing for Program Mode Operation (Writing to a Register)

SE

SCLK

SDIFS

SDI REGISTER READ INSTRUCTION 0x7FFF OR CONTROL WORD

UNDEFINED DATASDO READ RESULT

SDOFS

Figure 15b. Interface Signal Timing for Program Mode Operation (Reading a Register)

SE

SDOFS

SCLK

SDIFS

SDI CONTROL WORD CONTROL WORD

CHANNEL 1 ADC SAMPLE WORDSDO CHANNEL 6 ADC SAMPLE WORD

Figure 16a. Interface Signal Timing for Mixed Mode Operation

SE

SDOFS

SCLK

SDIFS

SDI DON'T CARE DON'T CARE

CHANNEL 1 ADC SAMPLE WORDSDO CHANNEL 6 ADC SAMPLE WORD

Figure 16b. Interface Signal Timing for Data Mode Operation

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In Cascade Mode, both devices must know the number of devicesin the cascade to be able to output data at the correct time.Control Register A contains a 3-bit field (DC0–2) that is pro-grammed by the DSP during the programming phase. The defaultcondition is that the field contains 000b, which is equivalent to asingle device in cascade (see Table XVI). However, for cascadeoperation this field must contain a binary value that is one lessthan the number of devices in the cascade. With a cascade, eachdevice takes a turn to send an ADC result to the DSP. Forexample, the data will be output as Device 2-Channel 1, Device1-Channel 1, Device 2-Channel 2, Device 1-Channel 2 etc. Whenthe first device in the cascade has transmitted its channel datathere is an additional SCLK period during which the last deviceasserts its SDOFS as it begins its transmission of the next chan-nel. This will not cause a problem for most DSPs as they countclock edges after a frame sync and hence the extra bit will beignored.

When two devices are connected in cascade there are also restric-tions concerning which ADC channels can be powered up. In allcases the cascaded devices must all have the same channelspowered up (i.e., for a cascade requiring Channels 1 and 2 onDevice 1 and Channel 5 on Device 2, Channels 1, 2, and 5must be powered up on both devices to ensure correct opera-tion). Figure 18 shows the timing sequence for two devices incascade. In all cases Channel 1 of all devices must be powered up.

Table XVI. Device Count Settings

DC2 DC1 DC0 Cascade Length

0 0 0 10 0 1 2

Connection of a cascade of devices to a DSP, as shown in Figure17, is no more complicated than connecting a single device.Instead of connecting the SDO and SDOFS to the DSP’s Rxport, these are now daisy-chained to the SDI and SDIFS of thenext device in the cascade. The SDO and SDOFS of the seconddevice in the cascade are connected to the DSP’s Rx port tocomplete the cascade. SE and RESET on both devices are fedfrom the signals that were synchronized with the MCLK usingthe circuit of Figure 19. The SCLK from only one device needbe connected to the DSP’s SCLK input(s) as both deviceswill be running at the same SCLK frequency and phase.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

DEVICE 2 – CHANNEL 1 DEVICE 1 – CHANNEL 1

1 2 3 4 5 6 7 8

DEVICE 2 – CHANNEL 2

Figure 18. Cascade Timing for a Two-Device Cascade

Cascade OperationThe AD73360L has been designed to support two devices in acascade connected to a single serial port (see Figure 17). TheSPORT interface protocol has been designed so that deviceaddressing is built into the packet of information sent to thedevice. This allows the cascade to be formed with no extra hard-ware overhead for control signals or addressing. A cascade canbe formed in either of the two modes previously discussed.

TFS

DT

DR

RFS

AD73360L

SDIFS

SDI

SCLK

SDO

SDOFS

SCLK

DEVICE 1

MCLK

SE

RESET

AD73360L

74HC74

Q0

Q1D1

D0

FL0 FL1

ADSP-21xxDSP

CLK

SDIFS

SDI

SCLKSDO

SDOFS

DEVICE 2

MCLK

SE

RESET

Figure 17. Connection of Two AD73360Ls Cascaded toADSP-21xx

There may be some restrictions in cascade operation due to thesample clock and the serial clock rate chosen. The formula belowgives an indication of whether the combination of sample rate andserial clock can be successfully cascaded. This assumes a directlycoupled frame sync arrangement as shown in Figure 12 and doesnot take any interrupt latency into account.

1 6 1 16 17

f

Device Count

SCLKS≥

× − × +[(( ) ) ]

When using the indirectly coupled frame sync configuration incascaded operation it is necessary to be aware of the restrictionsin sending control word data to all devices in the cascade. Theuser should ensure that there is sufficient time for all the controlwords to be sent between reading the last ADC sample and thestart of the next sample period.

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The sampling rate can be varied by programming the DecimationRate Divider settings in CRB. For a DMCLK of 16.384 MHzsample rates of 64 kHz, 32 kHz, 16 kHz and 8 kHz are available.Figure 21 shows the final spectral response of a signal sampledat 8 kHz using the maximum oversampling rate.

FREQUENCY – kHz0

0

dB

–20

2 4

–100

–140

–120

–40

–60

–80

SNR = 78dB (DC TO 4kHz)

Figure 21. FFT (ADC 8 kHz Internally Decimated from64 kHz)

It is possible to generate lower sample rates through reducingthe oversampling ratio by programming the DMCLK RateDivider Settings in CRB (MCD2-MCD1). This will have theeffect of spreading the quantization noise over a lesser band-width resulting in a degradation of dynamic performance.Figure 22 shows a FFT plot of a signal sampled at 8 kHz rateproduced by reducing the DMCLK Rate.

FREQUENCY – kHz0

0

dB

–20

2 4

–100

–140

–120

–40

–60

–80

SNR = 72.2dB (DC TO fS/2)

Figure 22. FFT (ADC 8 kHz Sampling with ReducedDMCLK Rate)

1/274HC74

CLK

D QDSP CONTROLTO SE

MCLK

SE SIGNAL SYNCHRONIZEDTO MCLK

1/274HC74

CLK

D QDSP CONTROLTO RESET

MCLK

RESET SIGNAL SYNCHRONIZEDTO MCLK

Figure 19. SE and RESET Sync Circuit for CascadedOperation

PERFORMANCEAs the AD73360L is designed to provide high-performance,low-cost conversion, it is important to understand the means bywhich this high performance can be achieved in a typical appli-cation. This section will, by means of spectral graphs, outlinethe typical performance of the device and highlight some of theoptions available to users in achieving their desired sample rate,either directly in the device or by doing some post-processing inthe DSP, while also showing the advantages and disadvantagesof the different approaches.

Encoder SectionThe encoder section samples at DMCLK/256, which gives a64 kHz output rate for DMCLK equal to 16.384 MHz. Thenoise-shaping of the sigma-delta modulator also depends on thefrequency at which it is clocked, which means that the bestdynamic performance in a particular bandwidth is achieved byoversampling at the highest possible rate. If we assume that thesignals of interest are in the bandwidth of dc–4 kHz, then sam-pling at 64 kHz gives a spectral response which ensures goodSNR performance in that bandwidth, as shown in Figure 20.

FREQUENCY – kHz0

0

dB

–20

8 16 24 32

–100

–140

–120

–40

–60

–80

SNR = 59.0dB (DC TO fS/2)SNR = 78.2dB (DC TO 4kHz)

Figure 20. FFT (ADC 64 kHz Sampling)

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VIN

TO INPUT BIASCIRCUITRY

VINPx

VINNx

REFOUT

REFCAPVOLTAGE

REFERENCE

0.047�F 0.047�F

100�

100�

0.1�F

Figure 24. Example Circuit for Differential Input(DC Coupling)

The AD73360L’s on-chip 38 dB preamplifier can be enabledwhen there is not enough gain in the input circuit; the preampli-fier is configured by bits IGS0–2 of CRD. The total gain must beconfigured to ensure that a full-scale input signal produces asignal level at the input to the sigma-delta modulator of theADC that does not exceed the maximum input range.

The dc biasing of the analog input signal is accomplished withan on-chip voltage reference. If the input signal is not biased atthe internal reference level (via REFOUT), then it must beac-coupled with external coupling capacitors. CIN should be0.1 µF or larger. The dc biasing of the input can then be accom-plished using resistors to REFOUT as in Figure 25.

VIN

TO INPUT BIASCIRCUITRY

VINPx

VINNx

REFOUT

REFCAP

VOLTAGEREFERENCE

0.047�F

100�

100�

CIN

CIN

10k�

10k�

0.047�F

0.1�F

Figure 25. Example Circuit for Differential Input(AC Coupling)

Figures 26 and 27 detail ac- and dc-coupled input circuits forsingle-ended operation respectively.

VINVINPx

VINNx

REFOUT

REFCAPVOLTAGE

REFERENCE

100�CIN

10k�0.047�F

0.1�F

Figure 26. Example Circuit for Single-Ended Input(AC Coupling)

VINVINPx

VINNx

REFOUT

REFCAPVOLTAGE

REFERENCE

100�

0.047�F

0.1�F

Figure 27. Example Circuit for Differential Input(DC Coupling)

Figure 23 shows a comparison of SNR results achieved by vary-ing either the Decimation Rate Setting or the DMCLK RateSettings.

SAMPLING FREQUENCY – kHz8

SN

R –

dB

71

REDUCEDDMCLK

DMCLK = MCLK

72

73

74

75

76

77

78

79

80

81

16 24 32 40 48 56 64

Figure 23. Comparison of DMCLK and Decimation RateSettings

Encoder Group DelayThe AD73360L implementation offers a very low level of groupdelay, which is given by the following relationship:

Group Delay (Decimator) = Order × ((M – 1)/2) × Tdecwhere:

Order is the order of the decimator (= 3),

M is the decimation factor (= 32), and

Tdec is the decimation sample interval (= 1/2.048e6).

=> Group Delay (Decimator) = 3 × (32 – 1)/2 × (1/2.048e6)= 22.7 µs

If final filtering is implemented in the DSP, the final filter’sgroup delay must be taken into account when calculating overallgroup delay.

DESIGN CONSIDERATIONSAnalog InputsThe AD73360L features six signal conditioning inputs. Eachsignal conditioning block allows the AD73360L to be used witheither a single-ended or differential signal. The applied signalcan also be inverted internally by the AD73360L if required.The analog input signal to the AD73360L can be dc-coupled,provided that the dc bias level of the input signal is the same asthe internal reference level (REFOUT). Figure 24 shows therecommended differential input circuit for the AD73360L. Thecircuit of Figure 24 implements first-order low-pass filterswith a 3 dB point at 34 kHz; these are the only filters that mustbe implemented external to the AD73360L to prevent aliasingof the sampled signal. Since the ADC uses a highly oversampledapproach that transfers the bulk of the antialiasing filtering intothe digital domain, the off-chip antialiasing filter need only be ofa low order. It is recommended that for optimum performance thecapacitors used for the antialiasing filter be of high-qualitydielectric (NPO).

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DIGITAL GROUND

ANALOG GROUND

Figure 29. Ground Plane Layout

Avoid running digital lines under the device for they will couplenoise onto the die. The analog ground plane should be allowedto run under the AD73360L to avoid noise coupling. The powersupply lines to the AD73360L should use as large a trace aspossible to provide low impedance paths and reduce the effectsof glitches on the power supply lines. Fast switching signals suchas clocks should be shielded with digital ground to avoid radiatingnoise to other sections of the board, and clock signals shouldnever be run near the analog inputs. Traces on opposite sidesof the board should run at right angles to each other. This willreduce the effects of feedthrough through the board. A micro-strip technique is by far the best but is not always possible witha double-sided board. In this technique, the component sideof the board is dedicated to ground planes while signals areplaced on the other side.

Good decoupling is important when using high-speed devices. Allanalog and digital supplies should be decoupled to AGND andDGND respectively, with 0.1 µF ceramic capacitors in parallelwith 10 µF tantalum capacitors. To achieve the best from thesedecoupling capacitors, they should be placed as close as possibleto the device, ideally right up against it. In systems where acommon supply voltage is used to drive both the AVDD andDVDD of the AD73360L, it is recommended that the system’sAVDD supply be used. This supply should have the recom-mended analog supply decoupling between the AVDD pins ofthe AD73360L and AGND and the recommended digital supplydecoupling capacitors between the DVDD pin and DGND.

DSP Programming ConsiderationsThis section discusses some aspects of how the serial port of theDSP should be configured and the implications of whether Rxand Tx interrupts should be enabled.

DSP SPORT ConfigurationFollowing are the key settings of the DSP SPORT required forthe successful operation with the AD73360L:

• Configure for external SCLK.• Serial Word Length = 16 bits.• Transmit and Receive Frame Syncs required with every word.• Receive Frame Sync is an input to the DSP.• Transmit Frame Sync is an:

Input—in Frame Sync Loop-Back Mode,Output—in Nonframe Sync Loop-Back Mode.

• Frame Syncs occur one SCLK cycle before the MSB of theserial word.

• Frame Syncs are active high.

Digital InterfaceAs there are a number of variations of sample rate and clockspeeds that can be used with the AD73360L in a particular appli-cation, it is important to select the best combination to achieve thedesired performance. High-speed serial clocks will read the datafrom the AD73360L in a shorter time, giving more time forprocessing at the expense of injecting some digital noise intothe circuit. Digital noise can also be reduced by connectingresistors (typ

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DSP SPORT InterruptsIf SPORT interrupts are enabled, it is important to note that theactive signals on the frame sync pins do not necessarily corre-spond with the positions in time of where SPORT interrupts aregenerated.

On ADSP-21xx processors, it is necessary to enable SPORTinterrupts and use Interrupt Service Routines (ISRs) to handleTx/Rx activity, while on the TMS320CSx processors it is pos-sible to poll the status of the Rx and Tx registers, which meansthat Rx/Tx activity can be monitored using a single ISR thatwould ideally be the Tx ISR as the Tx interrupt will typicallyoccur before the Rx ISR.

APPLICATIONS EXAMPLESVector Motor ControlThe current drawn by a motor can be split into two compo-nents: one produces torque and the other produces magneticflux. For optimal performance of the motor, these two compo-nents should be controlled independently. In conventionalmethods of controlling a three-phase motor, the current (orvoltage) supplied to the motor and the frequency of the drive arethe basic control variables. However, both the torque and fluxare functions of current (or voltage) and frequency. This cou-pling effect can reduce the performance of the motor because,for example, if the torque is increased by increasing the fre-quency, the flux tends to decrease.

Vector control of an ac motor involves controlling phase inaddition to drive and current frequency. Controlling the phaseof the motor requires feedback information on the position ofthe rotor relative to the rotating magnetic field in the motor.Using this information, a vector controller mathematically trans-forms the three-phase drive currents into separate torque andflux components. The AD73360L, with its six-channel simulta-neous sampling capability, is ideally suited for use in vectormotor control applications.

A block diagram of a vector motor control application using theAD73360L is shown in Figure 30. The position of the field isderived by determining the current in each phase of the motor.VIN1, VIN2, and VIN3 of the AD73360L are used to digitize thisinformation.

Simultaneous sampling is critical to maintain the relative phaseinformation between the channels. A current-sensing isolationamplifier, transformer or Hall-effect sensor is used between themotor and the AD73360L. Rotor information is obtained bymeasuring the voltage from the three inputs to the motor. VIN4,VIN5, and VIN6 of the AD73360L are used to obtain this informa-tion. A DSP microprocessor is used to perform the mathematicaltransformations and control loop calculations on the informa-tion fed back by the AD73360L.

DAC

DRIVECIRCUITRY

TORQUESETPOINT

FLUXSETPOINT

THREE-PHASEMOTOR

IC

IB

IA

ISOLATIONAMPLIFIERS

VC

VB

VA

VOLTAGEATTENUATORS

DSPMICROPROCESSOR

TORQUE & FLUXCONTROL LOOPCALCULATIONS

DAC

DAC

AD73360L

VIN1

VIN2

VIN3

VIN4

VIN6

VIN5

TRANSFORMATIONTO TORQUE &

FLUXCURRENT

COMPONENTS

Figure 30. Vector Motor Control Using the AD73360L

Industrial Power MeteringThe AD73360L can be used to measure the voltage and currentin all three phases of a three-phase supply. The simultaneoussampling architecture of the AD73360L is ideal for this applica-tion where simultaneous sampling is critical to maintaining therelative phase information between the three voltage and threecurrent phases. Figure 31 shows a block diagram of a three-phase metering system. The VIN1, VIN2, and VIN3 channels areused to measure the voltages in each phase (via voltage attenua-tors). The current flowing in each phase can be detected by theuse of current-sensing isolation amplifiers, transformers orHall-effect sensors. VIN4, VIN5, and VIN6 are used to digitizethis information. A DSP microprocessor is used to performthe mathematical calculations on the information providedby the AD73360L.

DSPMICROPROCESSOR

ISOLATIONAMPLIFIERS

VOLTAGEATTENUATORS

�3

�2

�1

THREE-PHASE

SUPPLY

IC

IB

IA

VC

VB

VA

AD73360L

VIN1

VIN2

VIN3

VIN4

VIN6

VIN5

Figure 31. Three-Phase Power Metering

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Programming a Single AD73360L for Data Mode OperationThis section describes a typical sequence in programming asingle AD73360L to operate in normal Data Mode. It detailsthe control (program) words that are sent to the device to con-figure its internal registers and shows the typical output datareceived during both Program and Data Modes. The device isconnected in Frame Sync Loop-Back Mode (see Figure 12),which forces an input word from the DSP’s Tx register each timethe AD73360L outputs a word via the SDO/SDOFS lines (whilethe AD73360L is in Program Mode the data transmitted will beinvalid ADC data and will, in fact, be a modified version of thelast control word written in by the DSP). In each case the DSP’sTx register is preloaded with the data before the frame pulse isreceived. In Step 1, the part has just been reset and on the firstoutput event the AD73360L presents an invalid output word*.The DSP’s Tx register contains a control word that programsCRB with the data byte 0x03. This sets the sample rate at

8 kHz (with a master clock of 16.384 MHz). In Step 2, the con-trol word in the DSP’s Tx register will cause all the AD73360Lschannels to power up. This data is received by the AD73360Lwith the next frame sync pulse. An invalid ADC word is alsoreceived at the DSP’s Rx register. Step 3 selects the settings foreach channel of the AD73360L. This set can be repeated asnecessary to program all the channels to the desired settings.Steps 4 and 5 program the modes of each channel (i.e., single-ended or differential mode and normal or inverted). Step 6 putsthe AD73360L into Data Mode and in Step 7 the first validADC word is received.

*This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are enabled.It is important to ensure there is no latency (separation) between control words ina cascade configuration. This is especially the case when programming ControlRegister B, as it contains settings for SCLK and DMCLK rates.

DSP Tx REG

CONTROL WORD1000 0001 0000 0011

DEVICE 1

ADC WORD 1*0000 0000 0000 0000

DSP Rx REG

0000 0000 0000 0000

STEP 1

DON'T CARE

DSP Tx REG

CONTROL WORD1000 0010 0000 0001

DEVICE 1

ADC WORD 1*1011 1111 0000 0011

DSP Rx REG

1011 1111 0000 0011

STEP 2

DON'T CARE

DSP Tx REG

CONTROL WORD1000 0011 1000 1111

DEVICE 1

ADC WORD 1*1011 1010 0000 0001

DSP Rx REG

1011 1010 0000 0001

STEP 3

DON'T CARE

DSP Tx REG

CONTROL WORD1000 0110 0011 1111

DEVICE 1

ADC WORD 1*1011 1011 1000 1111

DSP Rx REG

1011 1011 1000 1111

STEP 4

DON'T CARE

DSP Tx REG

CONTROL WORD1000 0111 0011 1111

DEVICE 1

ADC WORD 1*1011 1111 0011 1111

DSP Rx REG

1011 1110 0011 1111

STEP 5

DON'T CARE

DSP Tx REG

CONTROL WORD1000 0000 0000 0001

DEVICE 1

ADC WORD 1*1011 1111 0011 1111

DSP Rx REG

1011 1111 0011 1111

STEP 6

DON'T CARE

DSP Tx REG

CONTROL WORD0111 1111 1111 1111

DEVICE 1

ADC WORD 11000 0000 0000 0000

DSP Rx REG

1000 0000 0000 0000

STEP 7

ADC WORD 1

SET 8kHz SAMPLING

GLOBAL POWER-UP

SET CHANNEL GAINS

SET CHANNEL MODE

SET CHANNEL INVERSION

SET DATA MODE

RECEIVE VALID ADC DATA

*ADC DATA RECEIVED BY THE DSP DURING THE PROGRAMMING PHASE SHOULD NOT BE CONSIDERED VALID RESULTS.

Figure 32. Programming a Single AD73360L for Operation in Data Mode

APPENDIX A

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–26–

APPENDIX B

DSP Tx REG

CONTROL WORD1000 0001 0000 0011

DEVICE 1

ADC WORD 1*0000 0000 0000 0000

DSP Rx REG

0000 0000 0000 0000

STEP 1

DON'T CARE

DSP Tx REG

CONTROL WORD1000 0011 1111 1010

DEVICE 1

ADC WORD 1*1011 1001 0000 0011

DSP Rx REG

0000 0000 0000 0000

STEP 2

DON'T CARE

DSP Tx REG

CONTROL WORD1000 0010 1110 0000

DEVICE 1

ADC WORD 1*1011 1011 1111 1010

DSP Rx REG

0000 0000 0000 0000

STEP 3

DON'T CARE

DSP Tx REG

CONTROL WORD1000 0000 0000 0010

DEVICE 1

ADC WORD 1*1011 1010 1110 0000

DSP Rx REG

0000 0000 0000 0000

STEP 4

DON'T CARE

DSP Tx REG

CONTROL WORD0111 1111 1111 1111

DEVICE 1

ADC WORD 11000 0000 0000 0000

DSP Rx REG

1000 0000 0000 0000

STEP 5

ADC WORD 1

DSP Tx REG

CONTROL WORD0111 1111 1111 1111

DEVICE 1

ADC WORD 21111 0000 0000 0000

DSP Rx REG

1111 0000 0000 0000

STEP 6

ADC WORD 2

DSP Tx REG

CONTROL WORD1000 0011 1000 0010

DEVICE 1

INVALID DATAxxxx xxxx xxxx xxxx

DSP Rx REG

1111 0000 0000 0000

STEP 7

ADC WORD 2

SET 8kHz SAMPLING

POWER-UP CHANNEL 1 AND 2 AND SET GAINS

POWER-UP REFERENCE

SET MIXED MODE

CHANGE GAIN ON CHANNEL 1



*ADC DATA RECEIVED BY THE DSP DURING THE PROGRAMMING PHASE SHOULD NOT BE CONSIDERED VALID RESULTS.

Figure 33. Programming a Single AD73360L for Operation in Mixed Mode

Programming a Single AD73360L for Mixed Mode OperationThis section describes a typical sequence in programming asingle AD73360L to operate in Mixed Mode. The device isconfigured in Nonframe Sync Loop-Back (see Figure 11), whichallows the DSP’s Tx Register to determine how many words aresent to the device during one sample interval. In NonframeSync Loop-Back mode, care must be taken when writing tothe AD73360L that an ADC result or register read result con-tained in the device’s serial register is not corrupted by a write.The best way to avoid this is to only write control words whenthe AD73360L has no more data to send. This can limit thenumber of times a DSP can write to the AD73360L and isdependant on the SCLK speed and the number of channelspowered up. In this example it is assumed that there are onlytwo channels powered up and that there is adequate time totransmit data after the ADC results have been read.

In Step 1, the device has just been reset and the on first outputevent the AD73360L presents an invalid ADC sample word*.Once this word has been received the DSP can begin transmit-ting programming information to the AD73360L. The firstcontrol word sets the sampling rate at 8 kHz. In Step 2, theDSP instructs the AD73360L to power up channels 1 and 2and sets the gain of each. No data is read from the AD73360Lat this point. Steps 3 and 4 set the reference and places the partinto Mixed Mode. In Steps 5 and 6 valid ADC results are readfrom the AD73360L and in Step 7 the DSP sends an instruc-tion to the AD73360L to change the gain of Channel 1.

*This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are enabled.It is important to ensure there is no latency (separation) between control words ina cascade configuration. This is especially the case when programming ControlRegister B, as it contains settings for SCLK and DMCLK rates.

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APPENDIX C

Configuring a Cascade of Two AD73360Ls to Operate inData ModeThis section describes a typical sequence of control words thatwould be sent to a cascade of two AD73360Ls to set them upfor operation. It is not intended to be a definitive initializationsequence, but will show users the typical input/output eventsthat occur in the programming and operation phases*. Thisdescription panel refers to Figure 34.

In Step 1, we have the first output sample event following devicereset. The SDOFS signal is raised on both devices simulta-neously, which prepares the DSP Rx register to accept the ADCword from Device 2, while SDOFS from Device 1 becomes anSDIFS to Device 2. As the SDOFS of Device 2 is coupled tothe DSP’s TFS and RFS, and to the SDIFS of Device 1, thisevent also forces a new control word to be output from the DSPTx register to Device 1. The control word loaded to Device 1 isaddressed to Device 2 (i.e., the address field is 001). Device 1will decrement the address field and pass it to Device 2 whenthe next frame sync arrives. As the DSP is transmitting a controlword, Device 2 is outputting an invalid ADC word. (Note thatthe AD73360L will not output valid ADC words until the deviceis placed in either mixed mode or data mode. Any ADC valuesreceived during the programming phase should be discarded.)At the same time, Device 1 will output its ADC result to Device2. Once all the data has been transferred, Device 1 will containan instruction for Device 2 (which instructs the part to set itsSCLK frequency), Device 2 will have received an ADC resultfrom Device 1 and the DSP will have received an ADC resultfrom Device 2.

In Step 2, Device 2 will begin transmitting the ADC word itreceived from Device 1. This will cause the DSP to transmit asecond command word, which tells Device 1 to change its serialclock. Simultaneously, Device 1 passes the first control word onto Device 2. In this manner both devices receive control wordinstructions and act upon them at the same time.

Step 3 is similar to Step 1 in that the DSP transmits a controlword for Device 2. Device 1 passes an invalid ADC result toDevice 2 and Device 2 transmits its own invalid ADC resultto the DSP.

In Step 4, Device 2 will transmit the invalid ADC sample itreceived from Device 1 while receiving a control word fromDevice 1 at the same time. Device 2 transmitting will cause theDSP to transmit a control word for Device 1. This should besimilar to the control word transmitted in Step 3 except that thisword is intended for Device 1. When transmission is completeboth devices have received instructions to power up all channelsand set the reference etc. Steps 3 and 4 can be repeated, as neces-sary, to program other registers concerned with the analog section.

Step N is the first stage of changing the operating modes of thedevices to Data Mode. As Device 2 outputs an ADC word theDSP will transmit a control word intended for CRA of Device 2to Device 1. As in Step 1, Device 1 will decrement the addressfield and pass on the control word on the next frame sync.

In Step N + 1, Device 2 transmits an ADC word it receivedfrom Device 1. This causes the DSP to transmit a control wordto Device 1 (intended for its CRA register). At the same timeDevice 2 is receiving its control word from Device 1. Both devicessimultaneously receive commands to change from ProgramMode to Data Mode and the number of devices in the cascade isalso programmed here.

In Step N + 2, we begin to receive valid ADC data. Note thatthe data comes from the last device in the chain (Device 2) first.As Device 2 transmits its ADC data, it is receiving ADC datafrom Device 1. Any data transmitted from the DSP will beignored from now on.

In Step N + 3, Device 2 has received an ADC sample fromDevice 1 and transmits it to the DSP. Steps N + 2 and N + 3are repeated as long as samples are required.

*This sequence assumes that the DSP SPORT’s Rx and Tx interrupts are enabled.It is important to ensure that there is no latency (separation) between controlwords in a cascade configuration. This is especially the case when programmingControl Register B as it contains settings for SCLK and DMCLK rates.

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DSP Tx REG

CONTROL WORD 11000 1001 0000 0011

DEVICE 1

ADC WORD 1*0000 0000 0000 0000

DEVICE 2

0000 0000 0000 0000

DSP Rx REG

ADC WORD 2*

STEP 1

ADC WORD 2*0000 0000 0000 0000

DSP Tx REG

CONTROL WORD 11000 0001 0000 0011

DEVICE 1

ADC WORD 1*xxxx xxxx xxxx xxxx

DEVICE 2

xxxx xxxx xxxx xxxx

DSP Rx REG

ADC WORD 1*

STEP 2


DSP Tx REG

CONTROL WORD 21000 1010 1110 0001

DEVICE 1


DEVICE 2

xxxx xxxx xxxx xxxx

DSP Rx REG

A

a six-input channel analog front end ad73360l · 2019. 12. 23. · –2– rev. 0...

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