a reconfigurable system featuring dynamically extensible embedded microprocessor, fpga, and...

A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA, and customizable I/O

Borgatti, M. Lertora, F. Foret, B. Cali, L.

STMicroelectronics, Agrate Brianza,Italy

IEEE Journal of Solid-State Circuits, March 2003, Volume: 38, Issue: 3, pp.521-529

Presenter: Ching-Chi Hu

112/04/18 A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA, and customizable I/O 2/20

Abstract A system chip targeting image and voice

processing and recognition application domains is implemented as a representative of the potential of using programmable logic in system design. It features an embedded reconfigurable processor built by joining a configurable and extensible processor core and an SRAM-based embedded field-programmable gate array (FPGA). Application-specific bus-mapped coprocessors and flexible input/output peripherals and interfaces can also be added and dynamically modified by reconfiguring the embedded FPGA.


Abstract (Cont.)

The architecture of the system is discussed as well as the design flows for pre- and post-silicon design and customization. The silicon area required by the system is 20 mm2 in a 0.18 μm CMOS technology. The embedded FPGA accounts for about 40% of the system area .


Motive

The economics of system integration pushes logic suppliers toward ever more complex system-chip devices

Increasing design complexity and its associated risks, increase of non-recurrent engineering expenses, and shorter time-to-market and product life are causing manufacturers to look for faster turnaround and lower risk solutions for design and technology


Embedded programmable logic in ASICs

On the logic design side, the ASIC introduces many design challenges because performance in terms of density, speed, and power consumption is significantly less aggressive than in cell-based design the use of configurable logic must be limited to

what really needs to be programmable for design efficient

the integration of programmable hardware in SOC introduces changes in the design flow. Different implementations can also be repeated to

produce different configurations for the same chip.


Embedded programmable logic in ASICs (cont.) the signoff of the system must be done for

each configuration, since for every configuration the logic implemented in the e-FPGA must operate correctly and possible timing violations need to be avoided an automated task to solve

the logic synthesis and optimization must be performed separately twice, for the hardwired logic and for the configuration logic, respectively.


Embedded programmable logic in ASICs (cont.)


System architecture

32 bit Extensible Microprocessor Five-stage pipeline 8 KB direct-mapped data/instruction caches 16/24 bit instruction format 64 bit processor interface (PIF)

48 KB SRAM Embedded FPGA

Extension of the processor datapath supporting a set of additional special-purpose instructions

Bus-mapped coprocessor Flexible I/O


System architecture (cont.)


Microprocessor to FPGA interface

The design uses a single context embedded FPGA to extend the instruction set of a commercial microprocessor architecture which allows adding user-defined instructions the number of user-defined instructions available at

a given time is limited by the e-FPGA logic capacity and instruction logic complexity

the size of the set of additional instructions exceeds the logic capacity of the e-FPGA, it must be split

The flexibility advantage of this architecture implies a speed penalty for the part of logic mapped inside the e-FPGA


Microprocessor to FPGA interface (cont.)


Microprocessor to FPGA interface (cont.)

The synchronization mechanism for two different opcode types


Block Description of the e-FPGA


Application example

A face recognition system


Application example (cont.)


System to RTL design flow

soft hardware (reconfigurable logic) to be mapped on the e-FPGA HDL RTL code of instruction extensions bus-mapped coprocessors special-purpose I/O peripherals

conventional fixed hardware (hardwired logic) Microprocessor RTL code AHB/APB bus peripherals;

embedded software (C code) application software low-level drivers for the hardware platform


System to RTL design flow (cont.)


RTL to Layout design flow


System implementation

Technology: 0.18μm CMOS 6-ML SRAM: Main 48KB (64-bit wide) Memory: I$:8KB D$:8KB (64-bit wid

e) Buffers: 4x256B (8-bit wide) Chip size: 5.5x5.5 mm2 (pad limited) Core size: 20 mm2

E-FPGA size: 8.2 mm2 (15K useable equivalent ASIC gates)

Customizable I/O: 24 general-purpose input/output and 8 general-purpose bidirs

Power supply: 2.7-3.6V (external), 1.8V (core, internally generated/regulated)


Conclusion

a novel system architecture based on a reconfigurable microprocessor has been presented and its implementation using embedded FPGA technology

The future work is investigated the impact of dynamic hardware configuration on energy efficiency of the computing system

a reconfigurable system featuring dynamically extensible embedded microprocessor, fpga, and...

Documents

system design

reconfigurable system

logic design

embedded programmable

system area

embedded fpga accounts

configuration logic

e fpga