A PlayA Play

Core Timer Core Timer InterruptsInterrupts

Acted by the Acted by the Human MicrocontrollerHuman Microcontroller

Ensemble from ENCM415 Ensemble from ENCM415

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Unanswered questionsUnanswered questions1. What does “volatile” mean?2. Why will “optimized code”

probably not work if volatile is not used?

3. How do you tell C++ that this function is an ISR and not a standard function?

4. Why do you need to tell C++ that this function is an ISR and not a standard function?

5. What is the difference (in coding) between an ISR and a standard function?

6. How does an interupt get latched, why and where?

7. Why do I have to tell the timer that the interrupt has been serviced, and how do I do it?

8. Remind me to ask Googan to help me with the “human microprocessor example” on Thursday.

Task 2 – file 2 (C++ or ASM)

extern volatile int foo_flag;

Tell “C++” that I am not a function but I am an ISR – interrupt service routine

void ISR_count( ) {foo_flag--;

Tell the timer that the interrupt has been serviced

}

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Timers available on BlackfinTimers available on Blackfin• Watchdog timer – Hardware Reference 15-49• Core timer – Hardware Reference 15-45• General purpose timers 15-1

– Pulse Width Modulation– Pulse Width Count and Capture– External Event

• Application of timers to provide code safety and improved version of UseFixedTimeASM( )

• Introduction to timer interrupts

04/18/23 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

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Act 1 – The MAIN taskAct 1 – The MAIN task

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Main.cpp as Main.cpp as assembly assembly

codecodeDebug optionDebug option

Number ofinterruptscheckedIn loop

04/18/23 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

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Main.cpp as Main.cpp as assembly codeassembly codeRelease optionRelease option

Number ofinterrupts

NOTcheckedIn loop

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Main.cpp as Main.cpp as assembly codeassembly codeRelease optionRelease option“Volatile” used“Volatile” used

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How NOT to add a C++ How NOT to add a C++ interrupt service routineinterrupt service routine

Standard return

From subroutine

04/18/23 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

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How NOT to add a C++ How NOT to add a C++ interrupt service routineinterrupt service routine

Since ISR’s can be caused to happen at “ANY” time by external signals you can’t code parameter passing or parameter returning

04/18/23 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

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A proper A proper C++ ISRC++ ISR

Save and recover ofall registers (volatile and nonvolatile)

After recovering allregisters we need toRTI -- return from interruptNOTreturn from subroutine FP? ASTAT?

Is saving all registers needed

R7 and P1 enough?

04/18/23 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

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The Core Timer RegistersThe Core Timer Registers• Core Timer Scale Register TSCALE

– Requires ability to communicate with TCOUNT register

• Core Timer Count Register TCOUNT– Requires ability to count backwards in steps of TSCALE

+ 1

• Core Timer Period Register TPERIOD– Requires ability to communicate with TCOUNT register

• Core Time Control Register TCNTL– Leadership role – has ability to put timer into low power

mode, disable timer, enable auto reload feature which place TPERIOD into TCOUNT whenever TCOUNT reaches zero (causing an interrupts). Has a “sticky bit”

04/18/23 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

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Core Timer ActionCore Timer Action

You set Core timer register TSCALE to 0 (decrement by 0 + 1)You set register TPERIOD to 0x2000You set register TCOUNT to 0x4000You enable timer using control register TCNTL

TCOUNT is decreased by 1 until it reaches 0 (0x4000 system clock ticks)When TCOUNT reaches 1, interrupt is caused andTCOUNT is reloaded with TPERIOD (0x2000) – counts down again

04/18/23 CORE Timer Interrupts -- a play, Copyright M. Smith, ECE, University of Calgary, Canada

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• The play is about to start

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Now we need Now we need to add the actorsto add the actors

Main( ) -- 2 actors• Doing something• Number_Interrupts

ISR routine – 1 actor

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The play startsThe play starts• The main program and ISR operation

will now be demonstrated

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Now we need Now we need to add the actorsto add the actors

Timer – 4 parts• Core Timer Scale

Register TSCALE• Core Timer Count

Register TCOUNT• Core Timer Period

Register TPERIOD• Core Time Control

Register TCNTL

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Starting the playStarting the playAttempt 2Attempt 2

Main( ) -- 2 actors• Doing something• Number_Interrupts

ISR routine – 1 actor

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Important system registersImportant system registers• Core interrupt mask register IMASK

– Must be super person with ability to stop / start all interrupts in the world

– Controls IVTMR interrupt bit• Core Interrupt Latch register ILAT

– Has ability to remember if interrupt has occurred (been latched) but is being ignored – bits set to zero when interrupt has been accepted

• Core Interrupt Pending Register IPEND– Read but not written – indicates that interrupt

is active or nested

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Now we need Now we need to add the actorsto add the actors

Timer – 4 parts• Core Timer Scale

Register TSCALE• Core Timer Count

Register TCOUNT• Core Timer Period

Register TPERIOD• Core Time Control

Register TCNTL

CORE SYSTEM REGISTERS – 1 person with many hands

• Core interrupt mask register IMASK

• Core Interrupt Latch register ILAT

• Core Interrupt Pending Register IPEND

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Real demonstrationReal demonstrationMain( ) -- 2 actors• Doing something• Number_Interrupts

• ISR routine – 1 actor• Timer registers – 4

actors• Core registers – 1

actor

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Real demonstrationReal demonstrationMain( ) -- 2 actors• Doing something• Number_Interrupts

• ISR routine – 1 actor• Timer registers – 4

actors• Core registers – 1

actor