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Nuclear Instruments and Methods in Physics Research A 604 (2009) 397–399

Contents lists available at ScienceDirect

Nuclear Instruments and Methods inPhysics Research A

0168-90

doi:10.1

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journal homepage: www.elsevier.com/locate/nima

A new ATLAS pixel front-end IC for upgraded LHC luminosity

M. Barbero a,�, D. Arutinov a, R. Beccherle b, G. Darbo b, R. Ely c, D. Fougeron d,M. Garcia-Sciveres c, D. Gnani c, T. Hemperek a, M. Karagounis a, R. Kluit e, V. Kostioukhine b,A. Mekkaoui c, M. Menouni d, J.-D. Schipper e

a Physikaliches Institut, Universitat Bonn, Nussallee 12, 53115 Bonn, Germanyb INFN Genova, via Dodecaneso 33, IT-16146 Genova, Italyc Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA 94720, USAd CPPM, Aix-Marseille Universite, CNRS/IN2P3, Marseille, Francee NIKHEF, National Institute for Subatomic Physics, Kruislaan 409, 1098 SJ Amsterdam, The Netherlands

a r t i c l e i n f o

Available online 5 February 2009

Keywords:

Pixel

Super-LHC

FE-14

Digital architecture

02/$ - see front matter & 2009 Elsevier B.V. A

016/j.nima.2009.01.160

esponding author.

ail address: barbero@physik.uni-bonn.de (M.

a b s t r a c t

A new pixel Front-End (FE) IC is being developed in a 130 nm technology for use in the upgraded ATLAS

pixel detector. The new pixel FE will be made of smaller pixels (50�250mm vs. 50� 400mm for the

present FE, FE-I3), a much improved active area over inactive area ratio, and a new analog pixel chain

tuned for low power and new detector input capacitance. The higher luminosity for which this IC is

tuned implies a complete redefinition of the digital architecture logic, which will not be based on

End-of-Column data buffering but on local pixel logic and local pixel data storage. An overview

of the new FE is given with particular emphasis on the new digital logic architecture and possible

architecture variations.

& 2009 Elsevier B.V. All rights reserved.

1. Introduction

In 2008, the ATLAS detector (A Toroidal LHC Apparatus [1]) willstart operation at the CERN Large Hadron Collider (LHC) ring.Located in a 2 T solenoidal field, the ATLAS Inner Tracker [2]combines continuous tracking elements, namely semiconductortracker and transition radiation tracker with high-resolution pixeldetectors [3] at the innermost radii. Plans to upgrade the trackerfor higher than nominal full LHC luminosity are already pursued,in particular the central pixel detector. The focus of the pixelupgrade is on two phases as will be explained in Section 2, a firstphase called ‘‘b-layer upgrade’’ and a second phase referred to as‘‘super-LHC upgrade’’. In Section 3, general specifications for theFE-I4 IC will be given together with an introduction to the chipanalog part. Section 4 will then focus on the new digitalarchitecture needed to accommodate the higher hit rates, whichwill be encountered both at super-LHC and, also potentially, at thetime of a b-layer upgrade.

2. Upgrades to the ATLAS pixel detector

The ATLAS pixel detector is made of �80 million channels,organized in 3 barrel layers and 3 end-caps. The inner pixel layer

ll rights reserved.

Barbero).

sits at r�5 cm and is designed to reconstruct vertices from long-lived particles containing c or b quarks; it is called the ‘‘b-layer’’.

For the ATLAS pixel detector, a ‘‘b-layer upgrade’’ is firstplanned before a ‘‘Super-LHC upgrade’’. As ATLAS and the LHC aredue to start at the end of 2008, there is, at present, no fixed dateon when these upgrades will precisely take place, and it must beunderstood that the dates given in this section are mainlyindicative, as a more precise timing will only be known after acouple of years of operational experience.

On a time scale of 2013, the present pixel detector performancecould be degraded due to both radiation damage and/orcomponent failures. Failures could be related to issues withcooling or opto-boards. Performance degradation will be mainlyrelated to the worsening of the charge collection efficiency due tothe integrated radiation dose recorded by the sensor. Performancedegradation could also come from limitations in the hit rate thatthe current pixel IC FE-I3 [4] can handle at high peak luminosity,as with new triplets and a first injector upgrade, a potential of2–3�1034 cm�2 s�1 peak luminosity could already be reached bythis time (more on this topic in Section 4). At present, thepreferred replacement scenario would be the insertion of asmaller-radius beam pipe and b-layer, developed in a newtechnology.

Plans are then already made for the LHC ring to see a majorupgrade around 2016–2018 with a new full injector chain, and therequired upgrade of the full inner detector, which will then bereplaced by a pure semiconductor-based tracker. Definition of the

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M. Barbero et al. / Nuclear Instruments and Methods in Physics Research A 604 (2009) 397–399398

upgraded ATLAS pixel detector specifications is on-going, but afew general points can be drawn:

1.

The pixel detector barrel might consist of 4 layers, covering theradii from approximately 4 cm (which requires a smaller radiusbeam pipe) to about 20 cm.

2.

The upgraded pixel detector b-layer will be submitted toextreme radiation doses and hit rates. A new sensor technologywill hence be needed. It is also believed that the challenges forthe design of the new FE for the smallest radii at super-LHC aretoo great to be overcome in a single technology step.

3.

It is finally interesting to note that the hit rate at radii above12 cm for sLHC luminosities will be rather similar to the ratesin the b-layer at the time of the b-layer upgrade.

Thus the pixel community devised a plan for an intermediateoccupancy FE in 130 nm technology, called ‘‘FE-I4’’, which wouldhave two main goals: it would target the b-layer replacement inthe years 2012–2013 and also be compatible with the needsrequired by pixel outer layers in the years 2016–2018. Theinnermost layer(s) at sLHC would then require appropriatedevelopment in a higher density process.

3. Development of the FE-I4 IC

Although all have been done to target the two goals introducedin the last paragraph, the b-layer upgrade and outermost layers ofsLHC present constraints of their own. For the FE, the main b-layerrequirements are as follows: a chip that handles 4–5 times higherhit rate (thus coping with higher luminosity and smaller radius), iscompatible with the present detector readout and control and iscompatible with 3D diamond or planar sensors. In contrast, the FErequirements for sLHC outer layers are as follows: a chip that islarge and compatible with automated flip chip assembly(to reduce module flip chip costs), is compatible with sLHCreadout and control, works at lower operating current per unitarea than the current detector and is compatible with new powerdistribution schemes considered [5]. FE-I4 should also start toaddress issues related to the sLHC upgrade of the innermost pixellayers, or at least the FE-I4 digital architecture and data outputshould scale to even higher hit rates.

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Geometry: The next pixel FE will be built from smaller pixels50�250mm – which will improve single point resolution –and a much improved active area over inactive area ratio wrtcurrent FE—which will reduce material and enhance thedetector’s vertexing capabilities. With bigger chip size andreduced periphery (possible in the new smaller feature size),the FE live fraction could increase from less than 75% in FE-I3to close to 90% for FE-I4. The pixel array size is, to date, in theprocess of being defined [6], with values ranging from 320�64to 336� 80 (row�column). Choice of the array size comesfrom the need to optimize various parameters: reduce bumpbonding costs, optimize the use of sensor wafers, optimizelayer geometry and stave services, take into account chip yieldmodels, and accommodate b-layer and sLHC outer layer dataoutput bandwidth (despite the hit rate at the time of upgradesbeing currently rather poorly known). Note that for the highestchip sizes, we are running close to the vendors maximumallowed chip sizes.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

� Hit prob. / DC

Fig. 1. Inefficiencies in FE-I3 at r ¼ 5 cm as a function of hit rate. Relation between

hit rate in the DC and luminosity is underlined. Sources of inefficiency related to

data shipment in the DC are labeled ‘‘busy/waiting’’ and ‘‘late copying’’.

Sensor compatibility: While it is clear that the analog chainneeds to accommodate electron signals, the sensor type fortwo upgrade goals will very likely differ. Thus the FE isdesigned to handle sensor capacitances in the range 0–0.5 pF,and leakage current up to 100 nA after irradiation.

�

Input/output and bandwidth: All I/O will be pseudo-LVDSsignals. The target output speed for FE-I4 is 160 Mb/s. � Analog and digital power: FE-I4 is designed for low-power

consumption. It is foreseen to keep about the same analogvoltage as in FE-I3, but reduce the digital voltage to maybe1.2 V (to be compared to �2 V presently), and to reduce analogand digital current consumptions to �10mA/pixel each. Hence,the power goal for FE-I4 is around 240 mW cm�2 (less than2/3rd of the power of FE-I3).

� Radiation hardness: Based on technology explorations [7], FE-I4

is expected to perform properly at least up to 200 Mrad, 4times b-layer specifications for FE-I3. Enclosed Layout Tran-sistors (ELT) are in general not needed for digital circuits.Guard rings only surround sensitive NMOS. Widths larger thanminimal are used. Due to the relative novelty of the 130 nmtechnology in our community, radiation tests will be a focus ofour testing efforts, both for device parameter evolution and forsensitivity of the smaller feature size to single event upset(dedicated test structures have been submitted).

� Analog Pixel Chain: The analog pixel chain is based on a pre-

amp, 2nd stage and comparator. The DC-coupled pre-ampinput device is a triple-well NMOS, and the pre-amp uses astraight regulated cascode configuration. The AC-coupledsecond stage is a folded cascode with a PMOS input transistor.The pre-amp has an active leakage current compensationcircuit for DC leakage current tolerance up to 100 nA. Pre-ampfeedback current and comparator threshold level can beconfigured (4 bits resp. 5 bits). More details concerning theanalog pixel are given in [8].

4. New digital architecture for higher hit rates

Before introducing the new digital architecture, it must first beunderstood why FE-I3 will perform properly only until hit ratescorresponding to a few times the foreseen LHC high luminosity.FE-I3 is based on a Double-Column (DC) structure. When acomparator falls in a pixel of a specific DC, the pixel sends timing,recorded charge and address information down the DC bus toEnd-of-Column (EoC) buffers. This pixel will stay inactive until thedata shipment to the next available EoC cell is finished. At higherhit rates, data congestion on the bus starts leading to reducedlifetime for the pixels, and it appears that at 2–3 times LHC highluminosity, the DC data flow reaches saturation (Fig. 1).

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9-10 cells

Fig. 2. Local buffer overflow inefficiency in FE-I4 at r ¼ 3.7 cm at 10� LHC high

luminosity as a function of buffer depth (in the RLU 2/LB 4 case).

M. Barbero et al. / Nuclear Instruments and Methods in Physics Research A 604 (2009) 397–399 399

An obvious solution is to prevent hits from moving to the EoCunless they are requested by a Level 1 Trigger (L1T). The newdigital concept is thus based on local storage of hits until L1Tlatency, now possible in the new ELT-free smaller feature sizetechnology.

The FE-I4 architecture is based on a structural hierarchydescribed here, following the logic flow. We encounter first aRegional Logic Unit (RLU), which in most scenarios would be a2-adjacent pixel unit. The RLU ties together the digital logic ofadjacent pixels, taking into account the inherently clusterednature of real hits. Then an even number of RLU (2 to say 16)shares the same Local Buffer (LB). The LB is of a depth that isdetermined by a trade-off between area available and LB overflowinefficiency. In LB cells, the data storage format could be asfollows: leading edge (time-stamping), 8 bits per RLU; trailingedge (encodes charge information/possibly other codes), 4 bits perpixel of the RLU; some RLU address bit(s) and possible extraneighbor logic bits (information from adjacent RLUs).

A high-level C+ + simulation of the FE has been developedusing physics data, and 2 main sources of inefficiency in thenew FE have been identified. The first one is the standardpile-up inefficiency, related to the return to baseline behaviorof the pixel analog chain and proportional to the hitprobability and the cell area. For a given return to baseline speed,reduction of the pile-up inefficiency at a given hit probabilitycan only come from the reduction of the cell area. In case of a2-pixel RLU, a factor 2 gain can be achieved with a truncationmechanism, where the comparator of a pixel in an RLU would

be able to stop the digitalization process of other pixels of thesame RLU (and trading a bit of single hit point resolution againstinefficiency). With truncation, FE-I4 pile-up inefficiency at 3 timesLHC high luminosity and 3.7 cm is 0.42%, which should bemanageable.

The second source of data loss identified is the overflow of theLB. It can be shown that this source of inefficiency decreases whenmoving to larger RLU or when tying more RLUs to a single LB(averaging-out effect); both these solutions come at the cost ofextra complexity in the logic implementation at the pixel level.Increasing the depth of the LB is also one of the main solutions wehave, as shown in Fig. 2.

In parallel to this high-level simulation effort, Verilogdescription at RTL and gate level (both post-synthesis andafter Place&Route) of the proposed logic has started, and theintegration of the two simulation frameworks is a presently on-going task.

5. Conclusion

Development of a full-scale FE-I4 chip in 130 nm technologytargeting ATLAS pixel b-layer replacement as well as super-LHCouter layer needs is taking place. Prototypes of the pixel analogarray are available, and other peripheral structures are already inan advanced designing phase (regulators, command decoder,DACs, LVDS drivers/receivers, SEU-tolerant latches,etc). The FEdigital architecture is being developed with parallel high-levelmodeling and transistor-level simulation. Design of a full-scaleFE-I4 IC is foreseen for the year 2009.

References

[1] ATLAS collaboration, The ATLAS experiment at the CERN large hadron collider,2008 JINST 3, S08003.

[2] ATLAS collaboration, Inner Tracker: Technical Design Report, 1, CERN-LHCC-97-016.ATLAS collaboration, Inner Tracker: Technical Design Report, 2, CERN-LHCC-97-017.

[3] ATLAS collaboration, ATLAS Pixel Detector: Technical Design Report, CERN-LHCC-98-013.

[4] G. Aad, et al., ATLAS pixel detector electronics and sensors, 2008 JINST 3,P07007.

[5] M. Garcia-Sciveres, Power distribution for silicon detectors, in: Proceedings ofScience, Proceedings of the 16th Workshop on vertex detectors, Lake Placid,NY, USA, September 2007.

[6] M. Garcia-Sciveres, et al., FE-I4 Chip Size , ATLAS pixel upgrade for SLHC-electronics, Internal Document, 2008.

[7] F. Faccio, et al., IEEE Trans. Nucl. Sci. NS-52 (2005) 2413.[8] A. Mekkaoui, FE-I4_PROTO1, ATLAS pixel upgrade for SLHC-electronics,

Internal Document, 2008.