A NEW 16A NEW 16--BITS RISC PROCESSOR ARCHITECTURE: BITS RISC PROCESSOR ARCHITECTURE:

CONTROLLER STATE MACHINES AND CONTROLLER STATE MACHINES AND FUNCTIONAL VERIFICATION USING VERILOG™ HDLFUNCTIONAL VERIFICATION USING VERILOG™ HDL

A NEW 16A NEW 16--BITS RISC PROCESSOR ARCHITECTURE: BITS RISC PROCESSOR ARCHITECTURE:

CONTROLLER STATE MACHINES AND CONTROLLER STATE MACHINES AND FUNCTIONAL VERIFICATION USING VERILOG™ HDLFUNCTIONAL VERIFICATION USING VERILOG™ HDL

Ismail Saad, Pukhraj Vaya, Abu Bakar ARMicroelectronics & Photonics Group

School of Engineering & ITUniversiti Malaysia Sabah (UMS)

OutlinesOutlines

•Introduction

•Processor Architecture

•Processor Verilog Modules

•Simulation

•Functional Verification

•Results

•Conclusion

IntroductionIntroduction

• Objective : To design and simulate 16-bit RISC microprocessor emphasized on Controller State Machine & functional verification using HDL based namely Verilog HDL.

• HDLHDL (Hardware Description Language) :

CAD tools used to design circuits by describing the circuit’s operation and can be tested to verify the functionalities by means of simulation.

VerilogVerilog--HDLHDL

• Verilog language is a text-based hardware programminglanguage that describes a relationship between signals in a circuit.

• Verilog supports design abstraction at three major levels:Behavioral-level, Register Transfer-level, Structural-level

• Verilog™ Hardware Description Language adopted as:IEEE Standard 1364IEEE Standard 1364 in 1995

Why HDLWhy HDL--Based??Based??

1.Traditional way (schematic-entry) is not practical to design complex circuits.

2. The fastest way to design the digital IC (time-to-market).

3. Cost saving.

4. Re-usable of Intellectual properties.

5. Easy.

Behavioral level

RT level

gate level

transistor level

Complexity

Flexibility of design decision

HDLHDL--Based Design AbstractionBased Design Abstraction

HDLHDL--Based Design flowBased Design flow

DesignSpecification

DesignSpecification

VerilogModelingVerilog

Modeling

SimulationSimulation

FunctionalVerification

met?

FunctionalVerification

met?

DoneDone

YES

NO

Processor ArchitectureProcessor Architecture

CPU

CPU_CORE AddressLatch

Address Decoder

ROM16 x 256

Address : 0 ~ 255

Datapath

Control

Alu

Clk

Data

SDO

SDI

Test

RAM16 x 256

Address : 256 ~ 512

I/OAddress : 513

514

AddrData DataData

Addr

16-bit

16-bit

R/W

OE

ME

ALERst

CE OE R/W

7-bit 7-bit 1-bit

16-bit 16-bit 16-bit

DATA_BUS

ADDRESS_BUS

AddrCE OE R/WCE OE

Output 16 LEDsInput

16 SWITCHES

zero_flag_reg

Zero

Zero Flag

Sysbus(16-bit)

CONTROL UNIT

15 14 13 12 11 10 8 7 6 59 4 3 02 1

ModeBit ALUFunc

OpCode

Rd Rs1 Rs2

InstructionRegister :

State : 0:Fetch13:Fetch21:Execute

Sub_state : 0:address_setup 1:address_hold 3:data_setup2:data_hold

FunctionZero

TrisPCTrisALUTrisRs2

TrisRdnTrisRd

PC incRs2 sel

WriteR1WriteR2WriteR3WritePC

ReadPC 1ReadR0 1ReadR1 1ReadR2 1ReadR3 1ReadPC 2ReadR1 2ReadR2 2ReadR3 2

LoadDRLoadPC

nOE RnWnME nALE

nENB

TrisMem

Operand

controller_state_machinecontroller_state_machine control_zero_flag_registercontrol_zero_flag_register

Instruction_set_architectureInstruction_set_architecture

Memory & I/O

Control Unit ArchitectureControl Unit Architecture

Databus(16-bit)

Controlller_State_Machine (CSM)Controlller_State_Machine (CSM)Controlller_State_Machine (CSM)Controlller_State_Machine (CSM)

Processor States :

Fetch1Fetch1(Register + Register)

Fetch2 & ExecuteFetch2 & Execute(Load & Store)

ExecuteExecute(Register + Immediate)

CSM Verilog CodingCSM Verilog Coding

always @(posedge Clock)begin

if (nReset = 0) state => high impedance;else begin

case (state)0: if (data_hold & ModeBit =00) state => Fetch1;else if (data_hold & ModeBit =01) state => Execute;else if (data_hold & (ModeBit =10 || 11) state => Fetch2;else if ( ModeBit =01|| 00) state => Fetch1;

3: if (data_hold & (ModeBit =10||11) state => Execute;else if ( ModeBit =10||11) state => Fetch2;

1: if (data_hold) states =>Fetch1;endend

always @(posedge Clock)begin

if (nReset = 0) state => high impedance;else begin

case (state)0: if (data_hold & ModeBit =00) state => Fetch1;else if (data_hold & ModeBit =01) state => Execute;else if (data_hold & (ModeBit =10 || 11) state => Fetch2;else if ( ModeBit =01|| 00) state => Fetch1;

3: if (data_hold & (ModeBit =10||11) state => Execute;else if ( ModeBit =10||11) state => Fetch2;

1: if (data_hold) states =>Fetch1;endend

`Fetch1

`Fetch2 `Execute

CSM State Diagram

CSM VerificationCSM Verification

Fig. 4.0: Fetch1 (0) to Execute (1) state transition

Fig. 4.1: Execute (1) to Fetch1 (0) state transition

Fig. 4.2: Fetch1 (0) to Fetch2 (3) state transition

Functional VerificationFunctional Verification

Processor OperationProcessor Operation

36 36 InstructionsInstructions

36 36 InstructionsInstructions

Register and Register

Register and ImmediateRegister and Immediate

ConditionalRegister and Register

Register and ImmediateConditional

Register and Immediate

Test Cond.Register and Register

Register and ImmediateTest Cond.

Register and Immediate

Register and Immediate operation

ADDi R1,R0,259 R1 0 + 259

assembly operation

Register and Register operation

ADDr R3,R1,R2 R3 R1 + R2

assembly operation

Store operation

ST R0,R1,259 Mem[259] R1

assembly operation

Interactive memory content display

Load operation

LD R2,R0,259 R2 Mem[259]

assembly operation

ConclusionConclusion

A new16-bit RISC microprocessor have been designed and simulated successfully using HDL-based approach.

Functional of controller state machine is verified and tested by run the 36 types of instruction.

Cost-effective by providing implementation the alternate solutions at the simulation level.

No need long time design-cycle to implement the various design solutions.