a low-power single chip li-ion battery protection...

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.4, AUGUST, 2015 ISSN(Print) 1598-1657 http://dx.doi.org/10.5573/JSTS.2015.15.4.445 ISSN(Online) 2233-4866

Manuscript received Mar. 3, 2015; accepted May. 14, 2015 Hongik University E-mail : HYPERLINK “mailto:[email protected]” [email protected]

A Low-Power Single Chip Li-Ion Battery Protection IC

Seunghyeong Lee, Yongjae Jeong, Yungwi Song, and Jongsun Kim

Abstract—A fully integrated cost-effective and low-power single chip Lithium-Ion (Li-Ion) battery protection IC (BPIC) for portable devices is presented. The control unit of the battery protection system and the MOSFET switches are integrated in a single package to protect the battery from over-charge, over-discharge, and over-current. The proposed BPIC enters into low-power standby mode when the battery becomes over-discharged. A new auto release function (ARF) is adopted to release the BPIC from standby mode and safely return it to normal operation mode. A new delay shorten mode (DSM) is also proposed to reduce the test time without increasing pin counts. The BPIC implemented in a 0.18-mm CMOS process occupies an area of 750 mm×610 mm. With DSM enabled, the measured test time is dramatically reduced from 56.82 s to 0.15 s. The BPIC chip consumes 3 mA under normal operating conditions and 0.45 mA under standby mode. Index Terms—Battery protection IC, BPIC, lithium-ion battery, battery protection

I. INTRODUCTION

As the market for portable electronic devices such as smartphones, MP3 players, digital cameras, and tablets grows exponentially, the demand for batteries that are portable, light, and capable of supplying steady power has grown accordingly.

Li-Ion batteries have emerged as the de facto standard

in portable devices because they are lighter, have higher energy density, high operating voltage, and have a long lifespan when compared to alternatives such as nickel cadmium or nickel hydrogen batteries. Li-ion batteries, however, have safety problems such as characteristic degradation, short life cycle, overheating or exploding when they are in the state of over-charge, over-discharge, or over-current. To safeguard against these risks, a Li-Ion battery usually contains a battery protection integrated circuit (BPIC) that protects it from overcharging and over depleting by managing the charging/discharging path [1-9].

The main flaw in the conventional BPIC design is that it can enter into an unstable operational mode when the battery is in an over-discharged state. While a load is attached across the battery, the BPIC should be able to return to normal mode from standby mode when the battery voltage rises above the discharge release voltage. In conventional BPIC, this return to normal mode does not occur unless a charger is attached to the battery. Also, a separate external capacitor has to be added to shorten the long return delay time to normal mode, otherwise a separate test mode control terminal is required. The other problem of conventional BPIC is that it takes a long test time. These problem become cost factors when the BPIC chip goes into mass production [1, 10].

To overcome the drawbacks mentioned above, this paper proposes a low-power fully integrated single chip BPIC that incorporates two new features for cost reduction: an auto release function (ARF) and a delay shorten mode (DSM). The ARF guarantees a stable exit from standby mode when the battery is in an over-discharged state. The DSM results in reduced test time without increasing pin counts. Implemented in a 0.18-mm CMOS process, the proposed BPIC consumes 3mA under

446 SEUNGHYEONG LEE et al : A LOW-POWER SINGLE CHIP LI-ION BATTERY PROTECTION IC

normal mode and 0.45 mA under standby mode. The measured test time is dramatically reduced from 56.82 s to 0.15 s with DSM enabled.

The rest of the paper is organized as follows. The overview of the battery protection system and the state diagram of the proposed BPIC are presented in Section II. The proposed BPIC architecture is presented and analyzed in Section III. Experimental results are showen in Section IV.

II. BATTERY PROTECTION SYSTEM

The configuration of conventional battery protection system for portable devices is shown in Fig. 1. It consists of a BPIC, two power MOSFETs, an RC filter (R1, C1) to protect the circuit from external disturbances, and a sensing resistance R2 to detect over-current condition. The Li-Ion battery is connected to the BPIC through an RC filter, and a load or charger is connected to the +VO/-VO terminals when charging or discharging. The BPIC monitors the battery voltages to provide overcharge protection and over-discharge protection by controlling the power MOSFETs. Also, the BPIC provides over-current protection.

Two switching power MOSFETs are connected back to back where one acts as ‘Discharging FET’ for cutting off the discharging path and the other ‘Charging FET’ is used to cut off the charging path. Power MOSFET has a parasitic BJT and an intrinsic body diode that is formed in the body-drain p-n junction connected between the

drain and source terminal. Therefore, two MOSFETs are connected in series to control current flow in both directions. Both MOSFETs are ON in the normal mode. In the event of over-charging or over-current, the BPIC cuts off the charging path by turning off the Charging FET via the CO terminal to protect the battery from over-charging or over-current. In this case, a discharge path is formed through the internal parasitic diode and the over-charged battery is allowed to become discharged. In the event of over-discharge or discharging over-current, the BPIC cuts off the discharging path by turning off the Discharging FET via the DO terminal to protect the battery. In this case a charging path is formed through the internal parasitic diode and the battery is allowed to become charged.

1. Over-Charge and Over-Discharge State

Fig. 2 depicts how CO and DO output signals, which

act as the control signals for the power MOSFETs, are generated as battery voltage (VDD) and current detection voltage (VM) undergo changes. When the battery voltage (VDD) rises above the overcharge detection voltage level (VDET1) and remains there for a period of time longer than the overcharge detection delay time (tVDET1), the

Fig. 1. Block diagram of battery protection system for portable devices.

Fig. 2. Operation of over-charge/over-discharge detection and charging over-current/discharging over-current detection.

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.15, NO.4, AUGUST, 2015 447

battery is deemed overcharged and the BPIC turns off the Charging FET to cut off the charging path by putting CO terminal to ‘Low’. By contrast, when the battery voltage (VDD) falls below the over-discharge detection voltage level (VDET2) and remains there for a period of time longer than the over-discharge detection delay time (tVDET2), the BPIC turns off the Discharging FET to cut off the discharging path by putting DO terminal to ‘Low’. When the battery is in the over-discharged state, the BPIC usually operates in the standby mode to minimize current consumption. In the standby mode, all circuits, including the reference voltage generator, are turned off. In conventional BPIC, the critical problem is that the charger has to be connected to turn on the reference voltage generator to exit from the standby mode.

Fig. 3 shows the state diagram of the proposed BPIC and the state of the battery in relation to the battery voltage applied. Depending on the battery voltage, the battery can stay in three different states: over-charge state, normal state, and over-discharge state. The state of the battery determines the level of output terminals, CO and DO, controlling the power MOSFETs. The proposed ARF was adopted to resolve the problem of the conventional BPIC not returning to normal mode from over-discharge state unless the charger is connected.

2. Charging Over-Current State and Discharging Over-Current State

The BPIC detects over-current produced during

charging and discharging states. The current produces a

voltage drop across the on resistance (Rds-on) of the two switching power MOSFETS connected in series. This voltage is sensed by the VM terminal and thus over-current is detected.

Portable devices in the past did not require large charging or discharge currents and therefore the power loss attributed to Rds-on was not significant. But the battery capacity in portable devices today has grown much larger and currents of over 1 A have to be used to shorten the charging time of the large battery capacities. With such high operating current, switching MOSFETs with their low Rds-on have to be used to reduce power consumption in the BPIC. The BPIC design proposed in this paper uses a switching MOSFET with Rds-on of 20 mΩ.

Therefore, when discharge over-current of 3.125 A flows through the MOSFETs, the VM terminal has a voltage of 125 mV. As shown in Fig. 2, when the VM terminal voltage rises above 125 mV, the discharging over-current state (VDET3) is detected. After the discharge over-current delay time (tVDET3) has passed, a ‘Low’ is output in the DO terminal to block the discharge path. This sequence is shown in Fig. 4, which shows the relationship between charging/discharging over-current detection and the state diagram of the proposed BPIC. In the case of charging over-current, the direction of current flow is opposite to that of discharging over-current. When the voltage at VM terminal falls below －100mV (VDET4), the BPIC senses charging over-current and after the charging over-current delay time (tVDET4) has transpired, CO terminal is changed to ‘Low’ to cut off the charging path.

Fig. 3. Battery condition and the proposed BPIC state.

Fig. 4. Charging/discharging over-current detection state diagram.


III. PROPOSED BPIC ARCHITECTURE

Fig. 5 shows the block diagram of the BPIC design proposed in this paper. The BPIC consists of an over-charging detector (VD1), an over-discharging detector (VD2), a charging over-current detector (VD4), a discharging over-current detector (VD3), a delay time generator, and logic blocks. The proposed new design adopts a reference voltage generator, a charger detector and a dual-mode delay time generator to implement the ARF and DSM functions.

1. Proposed Auto Release Function (ARF)

As already depicted in Fig. 3, the ARF was added to

resolve the problem of the conventional BPIC at the over-discharge state in standby mode. Fig. 6(a) shows the standby mode control block in a conventional BPIC. In the standby mode, the VM terminal is left in the OPEN (no charger). Therefore, when the BPIC tries to return to the normal mode from the standby mode, all blocks, including the reference voltage generator are turned off. The BPIC cannot be returned properly to the normal operational mode from the state of over-discharge.

This paper proposes the Auto Release Function as a solution to this problem. Fig. 6(b) shows the proposed standby mode control block with ARF implemented. As shown in Fig. 6(b), the proposed ARF consists of a voltage reference generator and a charger detector that

CHAR

GER

or L

OAD

Fig. 5. Block diagram of the proposed BPIC.

(a)

(b)

Fig. 6. Standby mode control block (a) conventional BPIC, (b) proposed BPIC with ARF.


can determine the presence of a charger through the VM terminal voltage. Because the reference voltage generator is always activated, the circuit stably returns to normal mode from over-discharge state. By taking advantage of the fact that VM terminal voltage is different depending on a load or a charger connection, the charger detector operates in the standby mode only when a load is connected.

The charger detector is made to operate as a hysteresis comparator. In the case of over-discharge state, the charger detector can distinguish between load or charger connection and determine the over-discharge release voltage (VREL2). When the charger is connected to the battery, the BPIC cuts off the over-discharging path to protect the battery and returns to normal mode when the battery voltage rises above the VREL2. When a load is connected to the battery, the BPIC cuts off the discharging path and enters into standby mode to minimize current consumption. When the battery voltage

rises above the standby mode release voltage (VREL2P), the battery exits from the standby mode and can return to normal mode, resulting in a more stable operation in comparison to conventional BPICs.

Fig. 7 shows the operation of ARF in standby mode. Fig. 7(a) shows the case for conventional BPIC. When the VM terminal is in an OPEN (no charger) state, the standby mode will not be exited even if the Li-Ion battery voltage rises above the over-discharge release voltage (VREL2) and DO terminal output will maintain a ‘Low’ level. The DO terminal goes ‘High’ and the BPIC returns to normal mode of operation only after the charger is attached. But in the BPIC with ARF implemented, as shown in Fig. 7(b), the BPIC is able to return to normal mode because the VREL2 level is different for load and charger connections. When a load is connected while the battery is in the over-discharge state, the BPIC can return to normal mode when VDD rises above the VREL2P. When a charger is connected while the battery is in the over-discharge state, the BPIC can return to normal mode when VDD rises above the over-discharge detection voltage (VDET2).

2. Delay Time Generator for Test Mode

The BPIC detects the voltage level with some delay

time to determine the state of the battery correctly. Delay Shorten Mode (DSM) is proposed in this paper to shorten the test time by minimizing this delay time for measuring voltage levels. In conventional BPIC without DSM, a maximum overcharge detection delay time of 1.2 s is required for each overcharge detection voltage level measurement. The overcharge detection voltage ranges from a minimum of 4.23 V to a maximum of 4.27 V in 1 mV increments. Therefore, to measure all the voltages requires taking 40 measurements with each measurement taking 1.2 s for a total test time of 48 s. To test all the categories using the same method requires a long test time of 56.825 s. With DSM, however, the detection delay time is reduced to 1ms which results in a total test time of only 0.15 s. Testing is a cost component and any reduction in testing time will enhance chip cost competitiveness.

Fig. 8 shows the structure of the delay time generator with the proposed DSM implemented. It consists of the DSM detection circuit for detecting test mode, a clock

(a)

VREL2P

VDD

t

VDET2

VDDVM

VDD

VM

DO

VSS

t

t

CO

ON

ON

OFF ON OFF ON

Connect Load

Connect Charger

VREL2

(b)

Fig. 7. Standby mode release operation (a) conventional BPIC, (b) proposed BPIC with ARF.


divider circuit implemented with a series of flip-flops with input signals SD and CD. Upon detection of over-charging, over-discharging, or over-current, the oscillator block in the BPIC sends a frequency signal to the CLK terminal. At the same time, Ctrl[0] signal is enabled, which sets the flip-flops. The divided delay times from each flip-flop output terminal are shown. When VDD rises to above 6 V, Ctrl[1] signal is enabled ‘High’ and the FF1 flip-flop is enabled to set position. When the CLK signal passes one cycle, input to the latch changes.

The change in the state of the latch brings the SD signal to ‘High’ which keeps all the flip-flops in the RESET state. When the flip-flops are RESET, frequency dividing activity ceases, so all the delay times become equal. When VDD terminal voltage becomes 0V, DSM is disabled.

IV. EXPERIMENTAL RESULTS

The proposed BPIC was implemented in a 0.18-mm CMOS process. Fig. 9(a) shows the layout of the proposed circuit with chip size measuring 750 mm × 610 mm. To achieve cost competitiveness, the BPIC and power switching MOSFETs are manufactured in a stack

QNQCN

CP

SDCD

QNQCN

CP

SDCD

QNQCN

CP

SDCD

D

QNQCN

CP

CD

D

CLK

Ctrl[0]

Test Mode Detection Block

Ctrl[1]

Ctrl[2]

QNQCN

CP

SDCD

Delay 1 Delay 2 Delay 3

Delay N

FF1

Fig. 8. Proposed delay time generator.

VD3 & VD4

MAINLOGIC

VD1 & VD2

OSC

Reference

ESD

ESD

ESD ESDChargerDetector

Delay timeGenerator

(a)

Charging FET

Discharging FET

BPIC

(b)

Fig. 9. Proposed BPIC (a) Layout, (b) single chip BPIC packaging photograph.

(a)

(b)

(c)

Fig. 10. Proposed BPIC (a) BPIC in a battery pack module, (b) BPIC test board, (c) Measurement setup.


structure and assembled together in multi-chip packaging. The single chip packaging of BPIC is shown in Fig. 9(b).

Fig. 10(a) shows an actual photo of the single chip BPIC attached to a battery pack. The test PCB for testing the characteristics of the BPIC is shown in Fig. 10(b). Fig. 10(c) shows the measurement setup.

Fig. 11(a) displays the measured over-charge detection voltage (VDET1) and over-charge detection delay time (tVDET1). VDD increases from 4.15 V to 4.25 V and after 1 s of delay time CO signal goes “Low” to turn off the charging MOSFET. Fig. 11(b) displays the measured over-discharge detection and delay time. After the over-discharge delay time, DO signal goes ‘Low’ to turn off the discharging MOSFET.

Fig. 12 shows the measurement results of over-current detection voltage VDET3 and VDET4. The discharging over-current delay (defined as discharging over-current delay time, tVDET3) is detected 12 ms after VM voltage reaches 123 mV. The charging over-current is detected 8 ms (defined as charging over-current delay time, tVDET4) after VM voltage reaches －100 mV (=VDET4).

Fig. 13 displays the ARF waveform. When VM terminal voltage is at 0 V (Fig. 13(a)), then the charger is

(a)

(b)

Fig. 11. Measured waveform (a) Over-charge detection voltage and delay time, (b) Over-discharge detection voltage and delay time and delay time.

VM = VDET3 = 0.123V

DOUT = LOWtVDET3 : 12ms

VM = 0.110V

(a)

VM = VDET4 = -0.100V

COUT = LOWtVDET4 : 8ms

VM = -0.80V

(b)

Fig. 12. (a) Measured waveform Discharging over-current detection voltage and delay time, (b) Charging over-current detection voltage and delay time.

VM = 0V

VDET2 = 2.300V VREL2 = 2.320V

DOUT = LOW

(a)

VDET2 = 2.300VVREL2' = 2.900V

VM = OPENDOUT = LOW

(b)

Fig. 13. Measured waveform of ARF (a) VM=0V(Connect charger), (b) VM=Open(Connect load).


connected to the battery. When VDD falls below the over-discharging detection voltage (VDET2), BPIC activates over-discharging detection. If VDD rises above over-discharge release voltage (VREL2), the over-discharging state will be exited. Fig. 13(b) shows the case when VM is OPEN. With load attached to the battery, VDD lower than the over-discharging detection voltage (VDET2) will activate over-discharging detection and BPIC will enter into standby mode. With the load attached, VDD level rising above standby mode release voltage (VREL2P) will result in standby mode exit and deactivation of over-discharge detection. Fig. 13(b) confirms DO signal rising to ‘High’ as standby mode is exited. In standby mode, the current consumption in BPIC is measured to be 400 nA.

Fig. 14 shows the shortened delay time in DSM mode. The over-charging detection delay time (tVDET1) under normal mode was measured to be 1s. With DSM enabled, Fig. 14 shows a shortened delay time of only 1ms. A performance summary is given in Table 1.

IV. CONCLUSION

This paper describes a single chip Li-Ion battery protection circuit (BPIC) with ARF and DSM features fabricated using a 0.18-mm CMOS process. The BPIC and switching power MOSFETs are assembled in a single package. The proposed Li-Ion BPIC consumes 3 mA in normal active mode and upon detecting over-discharging of battery into the load, the BPIC enters into standby mode where only 400 nA of current is consumed. A new ARF is adopted to release the BPIC from standby mode and safely return it to normal mode. A new DSM is also proposed to reduce the test time without increasing pin counts. With DSM enabled, the measured test time is dramatically reduced from 56.82 s to 0.15 s. These improvements have the potential to contribute significantly to production improvement and cost competiveness of commercial BPICs.

REFERENCES

[1] Datasheet of MM3280, “One-cell lithium-ion/ lithium-polymer battery protection IC,” http://www. mitsumi.co.jp/latest/Catalog/pdf/battery_mm_3280_e.pdf.

[2] Sang-Min Kim, et al, “Design of Charging and Discharging Switch Structure for Rechargeable Battery Protection IC,” 2001 Conference on Electronics and Information Communications, Vol.2, pp. 85-88. Jun,. 2001.

[3] Jang-Hyuck Lee and Joon-youp Sung, “Design of Battery Protection Circuit,” Proceedings of 2004 International Symposium on Intelligent Signal Processing and Communication Systems, pp. 784-786, Nov., 2004.

[4] S. Matsunaga, M. Sawada, M. Sugimot, and N. Fujishima, “Low Parasitic Current Half On Operation of Battery Protection IC,” 19th International Symposium on Power Semiconductor Devices and IC’s, pp. 49-52. May., 2007.

[5] D. Salerno and R. Korsunsky, “Practical considerations in the Design of Lithium-Ion Battery Protection Systems,” Applied Power Electronics Conference and Exposition, Vol. 2, pp. 700-707, Feb., 1998.

[6] Yen-Shyung Shyu and Jiin-Chuan Wu, “A 0.99 mA

VDD = 4.5V

COUT = LOW

tVDET1 : 1ms

VDD = 3.7V

TEST MODE

Fig. 14. Measured shortened delay time with DSM enabled.

Table 1. Performance summary and comparison

This work [1] [3] [10]

BPIC Process 0.18-mm CMOS - 0.5-mm

BCD -

MOSFET Switches

Packing on Chip

External Component

External Component

External Component

Current Consumption 3 mA 6 mA - 6 mA

Standby Mode Current

Consumption 400 nA 500 nA - 600 nA

Auto Release Function O X X X

Shortened Test Mode O O X O

Test Mode Control VDD pin External Pin X External

Cap


Operating Current Li-Ion Battery Protection IC,” IEICE Transactions on Electronics, vol. E85-C, No. 5, pp.1211-1215, May. 2002.

[7] G. Smith, “Micro power protection chip for rechargeable lithium-ion batteries,” Proceedings of the IEEE 1996 Custom Integrated Circuits Conference, pp. 131-134, May, 1996.

[8] Troy Stockstad, Tom Petty, and Renwin Yee, “A micropower safety IC for rechargeable lithium batteries,” Proceedings of the IEEE 1996 Custom Integrated Circuits Conference, pp. 127-130, May, 1996.

[9] C. Lampe-Onnerud, J. Shi, S.K. Singh, and B. Barnett, “Safety studies on lithium-ion batteries by accelerating rate calorimetry,” 14th Battery Conference on Applications and Advances, pp. 215-220, Jan., 1999.

[10] Dathsheet of R5421N Series, “Li-Ion Battery Pro- tector,” http://datasheet.eeworld.com.cn/pdf/RICOH/ 96509_R5421N152F-TR.pdf.

Seunghyeong Lee received his B.S. degree in electrical engineering from Pukyong National University, Korea, in 2010 and M.S. degree in the Department of Electronic and Elec- trical Engineering from Hongik University, Korea, in 2015 in the

field of Integrated Circuits and Systems, respectively. His current research areas include Triple-Output integrated DC-DC converters for AMOLED displays and Battery Protection ICs.

Yongjae Jeong received his B.S., M.S., and Ph.D. degrees in electrical engineering from Pukyong National University, Pusan, Korea, in 1999, 2002, and 2009, respectively. He is currently with Sanbud Co. Ltd., as a Chief research engineer. His research

interests include DC-DC switching converter, battery management, fuel gauge IC and systems.

Yungwi Song received his B.S. degrees in Physics from Dongeui University, Korea, in 2000, M.S. and Ph.D. degrees in electronics engineering from Pukyong National Uni- versity in 2002 and 2009, respect- tively. He is currently with Sanbud

Co. Ltd., as a chief research engineer. His research interests include battery protection, management, power management IC and systems.

Jongsun Kim received his Ph.D. degree in electrical engineering from the University of California, Los Angeles (UCLA) in 2006 in the field of Integrated Circuits and Systems. He was a postdoctoral fellow at UCLA from 2006 to 2007. From

1994 to 2001 and from 2007 to 2008, he was with Samsung Electronics as a senior research engineer in the DRAM Design Team, where he worked on the design and development of Synchronous DRAMs, SGDRAMs, Rambus DRAMs, DDR3 and DDR4 DRAMs. Dr. Kim joined the School of Electronic & Electrical Engineering, Hongik University in March 2008. Professor Kim’s research interests are in the areas of high-performance mixed-signal circuits and systems design. His current research areas include high-speed and low-power transceiver circuits for chip-to-chip communications, clock recovery circuits (PLLs/DLLs/CDRs), frequency synthesizers, signal integrity and power integrity, ultra low-power memories, power-management ICs (PMICs), RF-interconnect circuits, and low-power memory interface circuits and systems.

a low-power single chip li-ion battery protection...

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