IEEE Transactions on Nuclear Science, Vol. NS-27, No. 1, February 1980

A FAST DC COUPLED LINEAR PULSE AMPLIFIER

Helmuth Spieler

GSI - Gesellschaft fUr Schwerionenforschung6100 Darmstadt, West Germany

in an actual experiment.

A fast DC coupled pulse amplifier with the followingcharacteristics is described: rise time < 700 ps over

an output range of +1 ... -3V with negligible ringing,voltage gain = 10, noise < 50 pV. Measured gain andphase response of a model amplifier are compared withcalculations based on measured S-Parameters. Extendedbandwidth and insensivity to stray reactances are

achieved with a phase dependent feedback transferfunction. Practical design guidelines are presented.

Introduction

The amplifier described in this paper was designed as

a widely applicable modular unit for fast timingmeasurements. Two principal classes of applicationsdefine the required properties of such an amplifier:

1. Low level detector signals. A typical examplefor this case is a AE-E-time of flight telescope usingsilicon surface barrier detectors. With thin(5 ... 25 lm) large area (100 ... 300 mm2) AE detec-tors the voltage pulses on the detector may be as lowas a few hundred microvolts. The rise times are typi-cally less than 1 ns, even for medium weight heavyions (A < 50). At the current state of the art theobtainable time resolution is determined primarilyby signal to noise ratio.1 In this situation itis best to subdivide the amplifying chain into a pre-amplifier, which defines signal to noise ratio andperforms impedance transformation, and an insertionamplifier which provides enough gain (AV = 10 ... 100)and output drive capability (-2 ... -3 V into 50 Q) toexploit the dynamic range of the trigger unit (e.g.constant fraction trigger). The advantages of thisscheme are twofold: distributing the high gain re-quired (Av = 100 ... 1000) among two units greatlyreduces the risk of spurious oscillations and, sincevarious preamps specifically tailored to the applica-tion are often required, it avoids unnecessary redun-dancy in design.

2. Intermediate level signals. This case is exem-

pl7ified by a scintillation detector for low energyphotons, a parallel plate avalanche detector or a

secondary electron/channel plate detector operatedat low gain to improve count rate capability. Thesituation here is similar to that for the insertionamplifier in the low level case: signal to noise ratiois not of prime importance, the rise times may be fast(< 1 ns) and sufficient gain (Av X 10) and drive capa-bility are required.

A major consideration in both cases is count rate capa-bility, making DC coupling highly desirable. If ACcoupling is used the clipping time constant should bechosen as short as possible, i.e. much smaller thanthe time between successive pulses. Since the appro-priate clipping time constant depends on the type ofdetector in use and on the experimental conditions itfollows that DC coupling is a necessity if a widelyapplicable "off the shelf" amplifier is desired. How-ever, it should be stressed that DC coupling withoutadequate baseline stability is of little value (if any)

The amplifier to be described exhibits the followingcharacteristics:

Rise time: tr < 700 psVoltage gain: Av = 10, DC coupled

Output range: +1 ... -3 V into a 50 Q load

Input impedance: Z. = 50 Q

Noise (referred to input): Vn < 50 pV rms measuredover total bandwidth

DC baseline stability < 100 pV long term

Construction of the amplifier utilizes conventionalprinted circuit board techniques. One rather surprisingfeature is that the quoted performance can be achievedin production without "tweaking" and that the circuitis remarkably insensitive to changes in constructiontechniques, the PC board versions exhibiting essentiallythe same characteristics as several handwired bread-board versions.

Choice of Circuit

There are numerous circuit configurations suitable forhigh speed pulse amplifiers.2-8 However, some rathersimple considerations narrow the choice of circuitsconsiderably:

a) The simplest method to obtain a small input reflec-tion coefficient over a wide frequency range is tocreate an input impedance much larger than the desiredvalue and then to define the desired input impedancewith a shunt resistor. This indicates series feedbackin the input stage. Resistive impedance matching doesinvolve a noise penalty, which, however, can be toler-ated here since low input noise is not a major objec-tive in this design.

b) A major cause of ringing in wideband pulse ampli-fiers is the existence of parasitic resonances in thesignal or feedback path. Common culprits in this res-

pect are capacitors (the lead inductance resonatingwith the capacitance) or diodes not specificallydesigned for UHF applications. Resonances in the feed-back path are especially critical since their responsewill be impressed on the overall response of the ampli-fier. This rules out connecting the "cold" end of a

feedback resistor to an auxiliary DC voltage sourcesince this invariably involves bypass capacitors.

c) DC coupling implies that the quiescent DC voltagelevel at the input and at the output port of the ampli-fier is zero volts. This points to a cascade of PNP and

NPN transistors.

d) The stabilizing effect of negative feedback on the

properties of an amplifier with respect to variationsof component parameters improves if the open loop gainis increased. It is therefore desirable to apply feed-

back around the complete cascade. The validity of this

reasoning is certainly questionable at very high fre-

0018-9499/80/0200-0302$00.75© 1980 IEEE302

Abstract

quencies, because the increased phase shift as com-pared to an individual stage may lead to instability.However, as will be shown subsequently, a two stagefeedback amplifier with 500 MHz bandwidth can operatein a well controlled and stable manner, albeit forrather unorthodox reasons. Furthermore, good defini-tion of the DC operating points of the individualtransistors can be ensured in this configuration, anasset in production and repairs which should not beunderrated.

The Basic Circuit

The adopted circuit is a second collector to firstemitter (series-shunt) feedback pair as shown inFig. 1. The output of the feedback pair feeds anemitter follower to increase the load impedance ofthe second stage, thereby providing higher open loopgain and added drive capability. Resistors RF and REcomprise the feedback network.

DC STABILIZATIONLOOP

R2 1R+R2 Av

Fig. 1 Basic circuit configuration of the amplifier.

One of the greatest problems in the design of fast DCcoupled amplifiers is achieving good DC baseline sta-bility. This design makes use of an external DC feed-back loop. The important thing to keep in mind is thatan external stabilization loop may by no means intro-duce low frequency time constants, thereby creatingthe equivalent of AC coupling. DC coupling, if it isto be a meaningful concept in terms of count ratestability, means that DC gain is equal to midband gain,a simple criterion which is often overlooked.

In the circuit used here a high gain operational ampli-fier compares the output signal, attenuated by a factorequal to the forward gain of the fast amplifier, withthe input signal. The output of the operational ampli-fier, which is proportional to any deviation from thedefined relationship between input and output signal,be it DC or (low frequency) AC, is applied as a correc-tion signal to the emitter of the first stage of thefeedback pair (Fig. 1).

For low frequencies the stabilization amplifier is thedominant feedback path for the fast amplifier and, con-versely, the fast amplifier is the feedback path forthe stabilization amplifier. From both points of viewthe only pole in the feedback loop is determined by thefrequency response of the stabilization amplifier. The741 operational amplifier used here is fully frequency

compensated (maximum phase shift of 900) ensuring un-conditional stability. This scheme is by no means newbut does not seem to be very well known.

High Frequency Circuit Analysis

As pointed out above it is very questionable if a twostage feedback amplifier for subnanosecond risetimescan actually function properly, the reason being ex-cessive phase shift, which will lead to self oscilla-tion. Since the phase shifts in the feedback loop arequite sensitive to stray capacitances and inductances,it also seems evident that performance of a circuitwill vary considerably from one unit to another,necessitating individual phase compensation ("twea-king"). The lack of such traits is therefore quitesurprising.

In order to gain a quantitative insight into theworkings of the series shunt feedback pair the gainand phase response of a model amplifier were measuredin both closed and open loop configurations. Theemitter follower was omitted in the model amplifierto obtain a well defined load impedance. The basicconfiguration with the relevant circuit parameters isshown in Fig. 2. The circuit was operated with anexternal DC feedback loop (not shown in Fig. 2) toensure the same DC operating points in both the closedand open loop (RF removed) configurations. The BFT 95(PNP) and BFR 90 (NPN) transistors used are both strip-line packaged types with fT ; 2.5 GHz and fT % 4 GHzrespectively at the selected collector current (5 mAfor the BFT 95 and 10 mA for the BFR 90). The measure-ment technique followed standard procedures for thedetermination of S-parameters9, i.e. input and outputsignals were sensed via directional couplers. Themeasured data were then compared with the computedresponse of the stage.

V+

b3,3K

1o4r 4r <Fig. 2 Basic circuit of the model amplifier used for

measurement and calculation of gain and phaseresponse. The dashed connections indicate straycapacitances used in the calculation.

Input data for the computer calculations were S-para-meters measured at the appropriate collector currentfor one specimen, selected at random, of each of thetwo transistor types. These were in good agreement withthe less complete data in the manufacturer's data sheet.The S-parameters were transformed to (complex) h-para-meters which are better suited for the calculationswhile providing more physical insight (at least forme). Rigorously derived expressions for the currentgain, voltage gain, input impedance and source impe-dance of the individual stages of the feedback pair,including the effects of the feedback network wereused to calculate the total response. It should be noted

303

I I I F I I Iw

5A MEASURED 50 CALCULATEDOPEN LOOP RESPONSE RESPONSE

10 CLOSED LOOP 10 CLOSED LOOP

5 5

lAVOlIAVFI~

00 OPEN LOOP 0 OPEN LOOP

I-U_~~~~~~

CL -1800 -1800

0 ~ ~~~ ~ ~ ~ ~ ~ ~ ~~~~0

- 2700_ -270 _

10 100 1000 10 100 1000f[MhzI f[Mhzl

Fig. 3 Measured (left) and calculated (right) response of the model amplifier. The curvesshow voltage gain IAVIin both open and closed loop configurations (top), the ratioof open loop gain to closed loop gain IAvoI/IAvft (center), and the open loop phaseresponse (bottom). The measurements and the calculations were performed at the fre-quencies indicated by the data points. These were connected by smooth curves as aguide to the eye.

304

. I ... . . . , ,,,, ,, , , . r .ss-

as a word of caution that expressions for amplifiercharacteristics found in textbooks often make somesimplifying assumption, usually hiz = 0. This, how-ever, is not justified at high frequencies. Further-more, the effect of the feedback network is oftentreated in a too simplistic (idealized) manner, aswill be shown below.

The adopted procedure does not involve transistormodeling, where an equivalent circuit for the deviceis derived which is then used for the further cal-culations.2 Here the parasitic effects implicit in themeasured S-parameters are completely retained andenter unaltered into the calculations.

The main problem, however, is to correctly determinethe stray reactances. Since the main goal of thecalculations was more to gain qualitative under-standing than quantitative agreement, stray induc-tances were neglected and only the stray capacitancesindicated by dashed connections in Fig. 2 were in-cluded. CE and CCl were determined from mock-up measure-ments to 0.7 pF, whereas CC2 was adjusted to obtainagreement with the measured open loop phase response.The selected value for CC2 was 5 pF. Open loop ampli-tude response Avo is quite insensitive to stray para-meters, excellent agreement being obtained by neglec-ting stray reactances altogether.

The results of the measurements and the calculationsare shown in Fig. 3. The most striking feature is thatthe open loop phase shift increases to over 1800(corresponding to positive feedback) within the pass-band of the amplifier while still retaining uncondi-tional stability. Moreover, the ratio of open loop gainto closed loop gain lAvol/lAvfl attains its minimumvalue of about 0.8 at the same frequency where the openloop phase shift is equal to 180°, ruling out signi-ficant additional phase shift in the feedback network.The fact that the calculated response exhibits the samebehaviour as the measured data shows that these charac-teristics cannot be attributed to vagaries of compo-nents or layout. Of course, an increase in closed loopgain over open loop gain is easy to explain by posi-tive feedback, but in practice this is a very unstablesituation. In this specific case there is another ex-planation.

Fig. 4 illustrates the summing of the input and thefeedback signal in the first stage of the feedbackpair, redrawn to reflect the point of view of thefeedback signal.

RF

Ivi

Fig. 4 Input stage of the feedback pair redrawn to re-flect the point of view of the feedback signal.Vi signifies the input signal and VO the outputsignal.

If the output signal VO and the input signal Vj are inphase (¢ = 0) the emitter of the input transistor willpresent a high impedance load to the feedback network.This impedance will be infinite if the voltage acrossRE is equal to V.. This represents the situation atlow frequencies, where the feedback signal is sub-tracted from the input signal in accordance with thetransmission factor of the feedback networkAF = RE/(RF + RE). If, however, VO and Vi are out ofphase (¢ = 180°) the input stage appears to be workingin a mode similar to common base with respect to thefeedback signal (i.e. looking into the emitter). Itwill thus present a low impedance to the feedback net-work thereby decreasing the feedback transmissionfactor. If the emitter input impedance is much smallerthan R the feedback path can be represented by a trans-conductance gF = 1/RF. Assuming a common base currentgain of unity for the first stage the total loop gain isAL = gF ZLl A where Zl is the overall collector loadimpedance of the first s age and Av2 is the voltage gainof the second stage of the feedbac pair. The amplifierwill be stable if the magnitude of the total loop gainis less than unity, i.e. if 1Av*ZLl/RFl < 1. Theamplifier can therefore be stabilized in the positivefeedback mode (q = 1800) by increasing the resistancesin the feedback network.

If RF and RE are sufficiently large the feedback trans-mission factor will decrease as a function of phase shiftin just the correct manner to ensure stability. Closedloop gain then increases by the cumulative effects of thepositive feedback signal and the increase in transcond-uctance of the first stage, which approaches open loopoperation. Since the feedback factor is phase dependentit automatically adjusts to changes in stray reactances,eliminating the need for critical adjustments.With a low resistance feedback network the amplifierwill oscillate. Calculations for RE = 90 Q, RF = 10 Qand the same values of stray capacitance as in thepreceding example indicate very unstable behaviour.The input resistance becomes negative over a fre-quency range of 50 to 600 MHz assuming values as lowas -12 Q. The amplifier cannot be stabilized by in-creasing the shunt capacitance over RE. On the onehand high frequency roll-off of the feedback trans-mission factor is not sufficiently steep to ensurea loop gain IAF-Avol < 1, and on the other hand thephase shift in the first stage begins to roll off atlower frequencies because of diminished local feed-back.

Conversely, a high resistance feedback network leadsto a very well behaved amplifier, even in terms ofconventional feedback theory. This is gained at theexpense of bandwidth. RF = 1600 Q and RE = 180 Q yield-a calculated bandwidth of about 180 MHz, with an asso-ciated phase shift of -650. The increased local feed-back in the first stage also improves input matchingby virtue of the higher intrinsic input impedance.

Values of RF = 820 a and RE = 91 Q were adopted for thefinal design yielding both stable performance (calcu-ated oop gain AFAvol |w 0.3) and adequate bandwidth.Use of an emitter follower as an output driver provides

a higher load impedance. Open loop gain at high frequen-ces (f > 100 MHz) is only increased by about 60 ... 70 %in this configuration, since the reverse transfer coeffi-cient hl2 of the second stage causes a decrease in inputimpedance of this stage with increased load impedance,thereby decreasing the voltage gain of the first stage.However, incorporating the emitter follower does increasethe output drive capability from -1.5 to -3 volts. Herethe major factor in determining phase response is thecapacitance CC2 presented to the output of the feedbackpair, since CE and CC1 are both at low impedance pointsin the circuit.

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-0IC

Practical Realization of the Amplifier

A detailed circuit diagram of the amplifier is pre-sented in Fig. 5. Step response to an input pulsewith 400 ps rise time is shown in Fig. 6. Fig. 7 de-monstrates the lack of ringing exhibited by thisdesign. Non-linearity over the output range of+1 ... -3 V is smaller than 1 % with a 50 n load. Themagnitude of the input reflection coefficient typicallyremains under 5 % at frequencies up to 100 MHz and in-creases to values between 30 and 40 % at 500 MHz.This includes the effects of an input protection cir-cuit (antiparallel lN4151 diodes backbiased at 6 V)not shown in Fig. 5.

The photographs in Fig. 8 illustrate the adopted con-struction practices. Leadless chip capacitors must beused for bypassing at the emitter of the second stageand at the collector of the emitter follower to avoidringing due to parasitic resonances. These are mountedon the underside of the circuit board (Fig. 8 left).Effective ground connections for these capacitors areaccomplished via plated through slits, since smallcircular apertures exhibit inadequate transmissionproperties at high frequencies. The Zener diode at theemitter of the second stage provides effective by-passing up to about 100 MHz.

Type 2N4261, 2N4957, and BFR99 transistors have beenused in the input and output stages with equally goodsuccess. Stripline packages are by no means essentialin these stages. Since a low inductance emitter con-nection is crucial in the second stage the use of astripline packaged transistor is strongly recommended.BFR90 transistors are available from Philips, Motorola,and SGS-ATES with quite similar characteristics. Chan-ging from one manufacturer or from one batch to an-other may require modification of the compensation net-works at the input and output of the feedback network(Fig. 5). However, these are quite uncritical and as arule fine-tuning only serves cosmetic purposes.

Excessive output noise can usually be attributed tothe Zener diodes in the level adapter at the outputof the 741 stabilization amplifier and at the emitterof the second stage. The output noise spectrum thenpeaks in the 10-50 MHz range. The former may be re-placed by a resistor without noticeable degradation inperformance, whereas in the latter case trying anothermanufacturer or another batch of diodes is the onlysolution.

Fig. 6 Step response to an input pulse with 400 psrise time (vertical scale: 100 mV/div, hori-zontal scale: 200 ps div.)

ALL UNMARKED CAR: 2.2rF

o 12V477 k 47k i10

1k 1

OFFSET ADJ.

Fig. 5 Detailed circuit diagram of the amplifier

Fig. 7 Response to an input pulse (top) with 1 nsrise time exhibits negligible ringing. Ver-tical scale is 50 mV/div. for the input signal(top) and 500 mV/div. for the output signal(bottom). Horizontal scale is 2 ns/div.

306

DC baseline drift with the stabilization loop has twomajor causes, both of them at the input of the ampli-fier:

a) The base current of the input transistor flowingthrough the 50 Q input termination causes an in-put voltage in the order of millivolts which isindiscernible from a real input signal and willtherefore not be compensated by the stabilizationloop. Changes in the termination resistance withtemperature will therefore lead to baseline drift.

b) The base current itself changes with temperatureand time.

Both effects can be reduced by decreasing the collec-tor current of the input stage. Operation at 1 mAcollector current still provides adequate speed whilegreatly reducing DC baseline drift. To keep the firsteffect small a low temperature coefficient metal filmresistor should be used as an input termination.

Conclusion

The subnanosecond DC coupled amplifier presented hereachieves a high degree of DC baseline stability byuse of an external DC feedback loop without intro-ducing low frequency roll-off. The high frequencyportion of the amplifier may be used alone if DCstability is not important or if AC coupling at theoutput is feasible. A risetime of less than 700 pswith negligible ringing can be obtained without re-sorting to hybrid construction. Use of a feedbacknetwork with a phase dependent transmission factorprovides stable and reproducible performance withoutcritical adjustments.

References

1. H. Spieler, H.J. Kbrner, K.E. Rehm, M. Richter, andH.P. Rother, Z. Phys. A278 (1976) 241

2. H.G. Jackson, IEEE Trans. Nucl. Sci. NS-20 (1973) 3

3. I.S. Sherman, R.G. Roddick, and A.J. Metz,IEEE Trans. Nucl. Sci. NS-15 (1968) 500

4. M.A. Schapper, Nucl. Instr. and Meth. 27 (1964) 172

5. C.J. Rush, Rev. Sci. Instr. 35 (1964) 149

6. P.F. Manfredi and A. Rimini, Nucl. Instr. andMeth. 49 (1967) 71

7. J.B. Coughlin, R.J.H. Gelsing, P.J.W. Jochems,and H.J.M van der Laak, IEEE J. Solid-StateCircuits SC-8 (1973) 414

8. R.G. Meyer, R. Eschenbach, and R. Chin, IEEEJ. Solid-State Circuits SC-9 (1974) 167

9. Transistor Parameter Measurements,Hewlett Packard Appl. Note 77-1S-Parameter Design, Hewlett Packard Appl. Note 154

Fig. 8 Constructional details of the amplifier. Note the leadless chip bypass capacitors in the left photograph.

307