a buck & boost based grid connected pv inverter ... buck & boost based grid connected pv...

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2017.2774768, IEEETransactions on Industrial Electronics

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

A Buck & Boost based Grid Connected PVInverter Maximizing Power Yield from Two PV

Arrays in Mismatched Environmental ConditionsSubhendu Dutta, and Kishore Chatterjee, Member, IEEE

Abstract—A single phase grid connected transformer-less photo voltaic (PV) inverter which can operate either inbuck or in boost mode, and can extract maximum power si-multaneously from two serially connected subarrays whileeach of the subarray is facing different environmental con-ditions, is presented in this paper. As the inverter canoperate in buck as well as in boost mode depending onthe requirement, the constraint on the minimum numberof serially connected solar PV modules that is requiredto form a subarray is greatly reduced. As a result poweryield from each of the subarray increases when they are ex-posed to different environmental conditions. The topologi-cal configuration of the inverter and its control strategy aredesigned so that the high frequency components are notpresent in the common mode voltage thereby restrictingthe magnitude of the leakage current associated with thePV arrays within the specified limit. Further, high operatingefficiency is achieved throughout its operating range. Adetailed analysis of the system leading to the developmentof its mathematical model is carried out. The viability ofthe scheme is confirmed by performing detailed simulationstudies. A 1.5 kW laboratory prototype is developed, anddetailed experimental studies are carried out to corroboratethe validity of the scheme.

Index Terms—Grid connection, Single phase, Trans-formerless, Buck & Boost based PV inverter, Maximumpower point, Mismatched environmental condition, Seriesconnected module.

I. INTRODUCTION

THE major concern of a photo voltaic (PV) system is toensure optimum performance of individual PV modules

in a PV array while the modules are exposed to different en-vironmental conditions arising due to difference in insolationlevel and/or difference in operating temperature. The presenceof mismatch in operating condition of modules significantlyreduces the power output from the PV array [1]. The prob-lem with the mismatched environmental conditions (MEC)becomes significant if the number of modules connected inseries in a PV array is large. In order to achieve desiredmagnitude for the input dc link voltage of the inverter of agrid connected transformerless PV system, the requirementof series connected modules becomes high. Therefore, thepower output from a grid connected transformerless (GCT)

Manuscript received July 12, 2017; revised October 10, 2017; ac-cepted October 31, 2017.

S. Dutta and K. Chatterjee are with the Department of ElectricalEngineering, Indian Institute of Technology Bombay, Mumbai 400076,India (e-mail: [email protected]; [email protected]).

PV system such as single phase GCT (SPGCT) inverter basedsystems derived from H-bridge [2], [3] and neutral point clamp(NPC) inverter based systems [4], [5] get affected significantlyduring MEC.

In order to address the problem arising out of MEC in aPV system, various solutions are reported in the literature. Anexhaustive investigation of such techniques has been presentedin [6]. Power extraction during MEC can be increased bychoosing proper interconnection between PV modules [6], [7]or by tracking global maximum power point (MPP) of PVarray by employing complex MPP tracking (MPPT) algorithm[6], [8]. However, these techniques are not effective for lowpower SPGCT PV system. Similarly, reconfiguration of the PVmodules in a PV array by changing the electrical connectionof PV modules [9], [10] is not effective for SPGCT PVsystem due to the considerable increment in component countand escalation in operating complexity. In order to extractmaximum power from each PV module during MEC, attemptshave been made to control each PV module in a PV arrayeither by having a power electronic equalizer [11] or byinterfacing a dc to dc converter [1], [12]- [14]. Schemesutilizing power electronic equalizer require large componentcount thereby increasing the cost and operation complexityof the system. The scheme presented in [1] uses generationcontrol circuit (GCC) to operate each PV module at theirrespective MPP wherein the difference in power between eachmodule is only processed through the GCC. Scheme presentedin [12] uses shunt current compensation of each module aswell as series voltage compensation of each PV string in aPV array to enhance power yield during MEC. The schemesbased on module integrated converter [13], [14] use dedicateddc to dc converter integrated with each PV module. However,the efficiency of the aforesaid schemes are low due to theinvolvement of large number of converter stages, and furtherin these schemes the component count is high and hence theyface similar limitations as that of power electronic equalizerbased scheme. Instead of ensuring MPP operation of each andevery module, certain number of modules are connected inseries to form a string and the so formed strings are thenmade to operate under MPP in [15], [16]. Even then there isnot much reduction in overall component count and controlcomplexity [6].

In order to simplify the control configuration and to reducethe component count, schemes reported in [17], [18] combineall the PV modules into two subarrays, and then each of thesubarray is made to operate at their respective MPP. However,




the reported overall efficiency of both the schemes are poor.By introducing a buck and boost stage in SPGCT PV inverter,power extraction during MEC is improved in [19]- [21].Further, as a consequence of the presence of the intermediateboost stage, the requirement of series connected PV modulesin a PV array has become less. In the schemes presented in[19]- [21], the switches of either the dc to dc converter stageor inverter stage operate at high frequency, as a result there is aconsiderable reduction in the size of the passive element count,thereby improving the operating efficiency of these schemes.Further, the reported efficiency of [20] and [21] is 1-2 % higherthan that of [19].

An effort has been made in this paper to divide the PVmodules into two serially connected subarrays and controllingeach of the subarray by means of a buck and boost basedinverter so that optimum power evacuation from the subarraysis ascertained during MEC. This process of segregation ofinput PV array into two subarrays reduces the number of seriesconnected modules in a subarray almost by half compared tothat of the schemes proposed in [20], [21]. The topologicalstructure and control strategy of the proposed inverter ensurethat the magnitude of leakage current associated with thePV arrays remains within the permissible limit. Further, thevoltage stress across the active devices is reduced almost byhalf compared to that of the schemes presented in [20], [21],hence very high frequency operation without increasing theswitching loss is ensured. High frequency operation also leadsto the reduction in the size of the passive elements. As a resultthe operating efficiency of the proposed scheme is high. Themeasured peak efficiency and the European efficiency (ηeuro)of the proposed scheme is found to be 97.65% and 97.02%respectively.

The detailed operation of the proposed inverter with math-ematical validation is explained in Section II. Afterwards themathematical model of the proposed inverter has been derivedin Section III followed by the philosophy of control strategyin Section IV. The criteria to select the values of the outputfilter components are presented in Section V. The proposedscheme is verified by performing extensive simulation studiesand the simulated performance is presented in Section VI.A 1.5 kW laboratory prototype of the proposed inverter hasbeen fabricated to carry out thorough experimental studies.The measured performances of the scheme which confirm itsviability are presented in Section VII.

II. PROPOSED INVERTER AND ITS OPERATION

The schematic of the proposed Dual Buck & Boost basedInverter (DBBI) which is depicted in Fig. 1 is comprising ofa dc to dc converter stage followed by an inverting stage. Thedc to dc converter stage has two dc to dc converter segments,CONV1 and CONV2 to service the two subarrays, PV1 andPV2 of the solar PV array. The segment, CONV1 is consistingof the self-commutated switches, S1 along with its anti-parallelbody diode, D1, S3 along with its anti-parallel body diode, D3,the free wheeling diodes, Df1, Df3 and the filter inductors andcapacitors, L1, Cf1, and Co1. Similarly, the segment, CONV2is consisting of the self-commutated switches, S2 along with

Cf1

Cpv2

Vg

Cpv1

L2

S5 D5

S7

D7

Cf2

Co1

Co2

PV1

PV2

O1

S1

S3

S2S4

D3

D2

D1

D4 S6 D6

L1

S8

D8

Lg

Df1

Df2

Df3

Df4

DC to DC Converter stage Inverting stageCONV1

CONV2

Fig. 1. Dual Buck & Boost based Inverter (DBBI)

its anti-parallel body diode, D2, S4 along with its anti-parallelbody diode, D4, the free wheeling diodes, Df2, Df4 and thefilter inductors and capacitors, L2, Cf2, and Co2. The invertingstage is consisting of the self-commutated switches, S5, S6,S7, S8, and their corresponding body diodes, D5, D6,D7 andD8 respectively. The inverter stage is interfaced with the gridthrough the filter inductor, Lg . The PV array to the groundparasitic capacitance is modeled by the two capacitors, Cpv1and Cpv2.

0 2π

VpvN

π

vcoN

Buck

Boost

Buck

Buck

Boost

N=1,2

Fig. 2. Buck stage and Boost stage of the proposed inverter

Considering Fig. 2, CONV1 operates in buck mode whenVpv1 ≥ vco1, while CONV2 operates in buck mode whenVpv2 ≥ vco2. Vpv1, Vpv2 are the MPP voltages of PV1 and PV2and vco1, vco2 are the output voltages of CONV1 and CONV2respectively. During buck mode duty ratios of the switches,S1 and S2 are varied sinusoidally to ensure sinusoidal gridcurrent (ig) while S3 and S4 are kept off. When Vpv1 < vco1,CONV1 operates in boost mode while CONV2 operates inboost mode when Vpv2 < vco2. During boost mode dutyratios of the switches, S3 and S4 are varied sinusoidally toensure sinusoidal ig while S1 and S2 are kept on throughoutthis mode. The sinusoidal switching pulses of the switches ofCONV1 and CONV2 are synchronized with the grid voltage,vg to accomplish unity power factor operation. The switches,S5 and S8 are kept on and switches S6 and S7 are keptoff permanently during the entire positive half cycle (PHC)while during entire negative half cycle (NHC), the switches,S6 and S7 are kept on and switches, S5 and S8 are kept offpermanently. All the operating states of the proposed inverterare depicted in Fig. 3.

When the insolation level and ambient temperature of sub-array PV1 are different from that of PV2, the MPP parameters




Cf1

Vg

L2

S5 D5

S7 D7

Cf2

Co1

Co2

P

V1

P

V2

O1

S1

S3

S2 S4

D3

D2

D1

D4 S6 D6

L1

S8

D8

Lg

Df1

Df2

Df3

Df4

(a)

Cf1

Vg

L2

S5 D5

S7 D7

Cf2

Co1

Co2

P

V1

P

V2

O1

S1

S3

S2 S4

D3

D2

D1

D4 S6 D6

L1

S8

D8

Lg

Df1

Df2

Df3

Df4

(b)

Cf1

Vg

L2

S5 D5

S7 D7

Cf2

Co1

Co2

P

V1

P

V2

O1

S1

S3

S2 S4

D3

D2

D1

D4 S6 D6

L1

S8

D8

Lg

Df1

Df2

Df3

Df4

(c)

Cf1

Vg

L2

S5 D5

S7 D7

Cf2

Co1

Co2

P

V1

P

V2

O1

S1

S3

S2 S4

D3

D2

D1

D4 S6 D6

L1

S8

D8

Lg

Df1

Df2

Df3

Df4

(d)

Cf1

Vg

L2

S5 D5

S7 D7

Cf2

Co1

Co2

P

V1

P

V2

O1

S1

S3

S2 S4

D3

D2

D1

D4 S6 D6

L1

S8

D8

Lg

Df1

Df2

Df3

Df4

(e)

Cf1

Vg

L2

S5 D5

S7 D7

Cf2

Co1

Co2

P

V1

P

V2

O1

S1

S3

S2 S4

D3

D2

D1

D4 S6 D6

L1

S8

D8

Lg

Df1

Df2

Df3

Df4

(f)

Cf1

Vg

L2

S5 D5

S7 D7

Cf2

Co1

Co2

P

V1

P

V2

O1

S1

S3

S2 S4

D3

D2

D1

D4 S6 D6

L1

S8

D8

Lg

Df1

Df2

Df3

Df4

(g)

Cf1

Vg

L2

S5 D5

S7 D7

Cf2

Co1

Co2

P

V1

P

V2

O1

S1

S3

S2 S4

D3

D2

D1

D4 S6 D6

L1

S8

D8

Lg

Df1

Df2

Df3

Df4

(h)

Fig. 3. Operating states of DBBI: (a) Active and (b) Freewheeling statesin buck mode of PHC, (c) Active and (d) Freewheeling states in buckmode of NHC, (e) Active and (f) Freewheeling states in boost mode ofPHC, (g) Active and (h) Freewheeling states in boost mode of NHC

of the two subarrays, Vpv1 and Vpv2, MPP current, Ipv1 andIpv2 correspond to PV1 and PV2 respectively and power atMPP, Ppv1 and Ppv2 correspond to PV1 and PV2 respectivelydiffer from each other. By considering that both the subarraysare operating at their respective MPP and neglecting thelosses incurred in power processing stages, the average powerinvolved with Co1 and Co2, Pco1 and Pco2 over a half cyclecan be assumed equal to the power extracted from PV1 andPV2. Therefore,

Pco1 = Ppv1 & Pco2 = Ppv2 (1)

The power injected to the grid averaged over a half cycle, Pgcan be written as

Pg = Ppv1 + Ppv2 (2)

Further, at any half cycle

vg = vco1 + vco2 (3)

Hence, the instantaneous injected power to the grid, pg can bewritten as

pg = vgig = (vco1 + vco2)ig (4)

wherein vco1 and vco2 denote the instantaneous quantities ofVco1 and Vco2 respectively. As ig is in-phase with vg ,

Ig =PgVg

(5)

wherein Vg and Ig denote rms values of vg and ig respectively.The power injected to the grid can be expressed as

Pg =1

π

∫ π

0

pg d(ωt)

=1

π

∫ π

0

vco1ig d(ωt) +1

π

∫ π

0

vco2ig d(ωt) (6)

= Pco1 + Pco2 (7)

As vco1 and vco2 are synchronized with vg . Hence

Pco1 =1

π

∫ π

0

Vco1m sin(ωt) Igm sin(ωt) d(ωt)

=Vco1mIgm

2(8)

Similarly,

Pco2 =Vco2mIgm

2(9)

wherein the amplitudes of vco1, vco2 and ig are denoted asVco1m, Vco2m and Igm respectively. Combining (1), (8) and(9)

Vco1m =2Ppv1Igm

=

√2Ppv1Ig

=

√2Ppv1Pg/Vg

(10)

Vco2m =2Ppv2Igm

=

√2Ppv2Ig

=

√2Ppv2Pg/Vg

(11)

Similarly by combining (2), (10) and (11),

Vco1m =VmPpv1

Ppv1 + Ppv2& Vco2m =

VmPpv2Ppv1 + Ppv2

(12)

The voltage templates of vco1 and vco2 appear as full waverectified sinusoidal waveform with amplitudes, Vco1m andVco2m respectively. Vm is the amplitude of vg . It can bededuced from (12) that the magnitudes of Vco1m and Vco2mare decided by the power extracted from each of the subarray.If the power extracted from PV1 is less than PV2, thenVco1m < Vco2m, whereas Vco2m < Vco1m if power extractedfrom PV2 is less than PV1. During buck mode, the duty ratios,d1 of S1 and d2 of S2 vary sinusoidally with an amplitude d1mand d2m, wherein

d1m =Vco1mVpv1

& d2m =Vco2mVpv2

(13)

while during boost mode the duty ratios, d3 of S3 and d4 ofS4 vary sinusoidally with amplitude d3m and d4m, wherein

d3m = 1− Vpv1Vco1m

& d4m = 1− Vpv2Vco2m

(14)




The CONV1 and CONV2 are having the same output currentig . Hence, the input side currents before getting filtered byinput filter capacitors of CONV1, isw1 and CONV2, isw2

can be related with ig in the buck mode by considering theswitching cycle average of corresponding quantities as follows

〈isw1〉Ts= 〈d1〉Ts

〈ig〉Ts(15)

〈isw2〉Ts= 〈d2〉Ts

〈ig〉Ts(16)

Similarly by considering switching cycle average of corre-sponding quantities the relation between isw1, isw2 and ig canbe deduced during boost mode as

〈isw1〉Ts= 〈 1

1− d3〉Ts

〈ig〉Ts(17)

〈isw2〉Ts= 〈 1

1− d4〉Ts

〈ig〉Ts(18)

Therefore, it can be inferred from (12) and (13) that if theinsolation level of PV1 is lower than that of PV2, duringbuck mode, d1m < d2m, thereby 〈d1〉Ts

< 〈d2〉Tswhereas

during boost mode as per (12) and (14), d3m < d4m, thereby〈d3〉Ts

< 〈d4〉Ts. Hence, it can be concluded from (15), (16),

(17) and (18) that in any operating mode, 〈isw1〉Ts< 〈isw2〉Ts

,therefore Ipv1 < Ipv2. Following the same argument, Ipv1 >Ipv2 if the insolation level of PV1 is higher than that of PV2.

Considering Fig. 1 it can be noted that during operationin PHC, vcpv1 = vco2 + Vpv1, vcpv2 = vco2 − Vpv2 while

during NHC vcpv1 = −vco1 + Vpv1, vcpv2 = −vco1 − Vpv2,wherein vcpv1 and vcpv2 are the voltages impressed acrossCpv1 and Cpv2 respectively. Hence, the voltages across Cpv1and Cpv2 contain significant amount of dc and low frequencycomponents which also ensures that the magnitude of theleakage current is maintained within the limit specified in thestandard, VDE 0126-1-1, and also cited in [23].

III. MATHEMATICAL MODEL OF THE PROPOSED SCHEME

A small signal modeling of the proposed inverter has beencarried out for buck mode and boost mode of operation. Fig.4(a) and (b) represent the equivalent circuit of the proposedinverter while it operates in buck mode whereas Fig. 4(c)and (d) represent the equivalent circuit of the converter whileit operates in boost mode. RL1, RL2, Rg , Rco1 and Rco2are the parasitic resistances of L1, L2, Lg , Co1 and Co2respectively. As indirect grid current control method [21] isadopted to control ig , the quantities iL1, iL2, vco1, vco2 andig are considered to be the state variables. The state equationsrepresenting the buck mode of operation of the inverter arederived to be (19), (20) by considering the equivalent circuitsof Fig. 4(a), (b) while the state equations for boost mode arederived to be (21), (19) by considering the equivalent circuitsof Fig. 4(c), (d).

iL1(t)

iL2(t)

vco1(t)

vco2(t)

ig(t)

=

−RL1+Rco1

L10 − 1

L10 Rco1

L1

0 −RL2+Rco2

L20 − 1

L2

Rco2

L21Co1

0 0 0 − 1Co1

0 1Co2

0 0 − 1Co2

Rco1

Lg

Rco2

Lg

1Lg

1Lg−Rco1+Rco2+Rg

Lg

iL1(t)

iL2(t)

vco1(t)

vco2(t)

ig(t)

+

1L1

0 0

0 1L2

0

0 0 0

0 0 0

0 0 − 1Lg

vpv1(t)

vpv2(t)

vg(t)

(19)

iL1(t)

iL2(t)

vco1(t)

vco2(t)

ig(t)

=

−RL1+Rco1

L10 − 1

L10 Rco1

L1

0 −RL2+Rco2

L20 − 1

L2

Rco2

L21Co1

0 0 0 − 1Co1

0 1Co2

0 0 − 1Co2

Rco1

Lg

Rco2

Lg

1Lg

1Lg−Rco1+Rco2+Rg

Lg

iL1(t)

iL2(t)

vco1(t)

vco2(t)

ig(t)

+

0 0 0

0 0 0

0 0 0

0 0 0

0 0− 1Lg

vpv1(t)

vpv2(t)

vg(t)

(20)

iL1(t)

iL2(t)

vco1(t)

vco2(t)

ig(t)

=

−RL1

L10 0 0 0

0 −RL2

L20 0 0

0 0 0 0 − 1Co1

0 0 0 0 − 1Co2

0 0 1Lg

1Lg−Rco1+Rco2+Rg

Lg

iL1(t)

iL2(t)

vco1(t)

vco2(t)

ig(t)

+

1L1

0 0

0 1L2

0

0 0 0

0 0 0

0 0 − 1Lg

vpv1(t)

vpv2(t)

vg(t)

(21)

The state space averaging based technique is adopted as thegrid frequency, fg is adequately lower than the switching fre-quency, fs. In order to simplify the analysis, Vpv1, Vpv2 and vgare considered as stiff voltage sources, and the effect of inputfilter capacitors is neglected. The values of the system param-eters are considered to be as follows: RL1 = RL2 = 0.12 Ω,Rg = 0.04 Ω, Rco1 = Rco2 = 0.26 Ω, Vpv1 = Vpv2 = 130 V .Considering symmetry in operation of CONV1 and CONV2,

and by applying state space averaging technique to (19),(20) and (21), the simplified transfer functions of ig(s)/d(s),iL1(s)/d(s) and vco1(s)/d(s) in s-domain during buck mode




L1

VPV2

Vg

L2

VPV1 Co1

Co2

RL1

RL2

iL1

iL2

vco1

vco2

(a) (b)

Lg

Rco1

Rg

Rco2

ig

L1

Vg

L2

Co1

Co2

RL1

RL2

iL1

iL2

vco1

vco2

Lg

Rco1

Rg

Rco2

ig

L1

VPV2

Vg

L2

VPV1Co1

Co2

RL1

RL2

iL1

iL2

vco1

vco2

(c) (d)

Lg

Rco1

Rg

Rco2

ig

L1

VPV2

Vg

L2

VPV1 Co1

Co2

RL1

RL2

iL1

iL2

vco1

vco2

Lg

Rco1

Rg

Rco2

ig

Fig. 4. Equivalent circuit in Buck mode (a) S1, S2 are ON (b) S1, S2 areOFF, in Boost mode (c) S3, S4 are ON (d) S3, S4 are OFF

are obtained as

ig(s)

d(s)=

2.87× 108s+ 2.2× 1014

s3 + 2267× s2 + 1.33× 109s+ 3× 1011(22)

iL1(s)

d(s)=

2.17× 105s2 + 3.52× 108s+ 2.2× 1014

s3 + 2267× s2 + 1.33× 109s+ 3× 1011(23)

vco1(s)

d(s)=

4.33× 1010s+ 1.3× 1013

s3 + 2267× s2 + 1.33× 109s+ 3× 1011(24)

wherein, d is the duty ratio of component converters. Similarly,the simplified transfer functions of ig(s)/d(s), iL1(s)/d(s)and vco1(s)/d(s) in s-domain during boost mode are obtainedas

ig(s)

d(s)=

−9487s2 − 9.7× 109s+ 2.1× 1014

s3 + 2018× s2 + 1.26× 109s+ 2.7× 1011(25)

iL1(s)

d(s)=

2.4× 105s2 + 3.3× 109s+ 2.4× 1014

s3 + 2018× s2 + 1.26× 109s+ 2.7× 1011(26)

vco1(s)

d(s)=

−2× 106s2 + 4.1× 1010s+ 4× 1012

s3 + 2018× s2 + 1.26× 109s+ 2.7× 1011(27)

Due to the existence of symmetry, transfer functions foriL2(s)/d(s) and vco2(s)/d(s) remain the same as that of (23),(24) in buck mode and (26), (27) in boost mode respectively.Based on the derived transfer functions of the system, com-pensators are designed to achieve the phase margin of 90 forboth the plants, and at the same time to maintain the desiredtotal harmonic distortion (THD) for the grid current.

IV. CONTROL STRATEGY OF THE PROPOSED SCHEME

The control strategy of the proposed scheme is depictedin Fig. 5. The controller is designed to fulfill the followingobjectives: i) both subarrays operate at their correspondingMPP simultaneously, ii) sensing of output voltages, vco1 andvco2 are not required, iii) ig is sinusoidal and is in-phase withvg throughout the operating range. Two separate MPP trackersand two proportional integral (PI) controllers are employedto determine the value of Ppv1 and Ppv2 which are required

PIN

MPPT

Algo

VpvN

VpvN

VmppN

IpvN PpvN

N = 1, 2

P = 1, 2

Q = 3, 4

iLNref = vcoN/RpcoN

Buck Mode (VpvN ≥ vcoN)

iLNref = v2coN/(RpcoN*VpvN)

Boost Mode (VpvN < vcoN)

1/√2

VcoNm

PpvN

RpcoN

Ppv1

Ppv2

/

/

Vm R

Vco1m

Vco2m

vco1

vco2

0 p 2p

dQ

dP

0 p 2p

PI

PLLX

Vg ZCD

Y Z

0 2p 4pZ

Y

X

FBR0

R

NOT

p 2p

1

1

/

iLNPI

B

AIf VpvN ≥ vcoN

dP=A, dQ=0

Else dP=1, dQ=B

iLNref

iLNref

Fig. 5. Control configuration of the proposed inverter

to estimate Vco1m and Vco2m. Using (12), Vco1m and Vco2mare determined where the information of Vm is obtained fromthe phase locked loop (PLL). A rectified version of a unitysinusoidal function, R is generated from a unity sinusoidalfunction, X, synchronized with vg , and is obtained from thesame PLL. R is multiplied with Vco1m and Vco2m to estimatevco1 and vco2. Hence, two voltage sensors which otherwisewould have been required to determine vco1 and vco2 geteliminated. Vpv1 and vco1 are compared to decide about themode of operation (buck mode or boost mode) of CONV1,while Vpv2 and vco2 are compared to determine the modeof operation of CONV2. RMS values of vco1 and vco2 areestimated which are then subsequently squared and are thendivided by Ppv1 and Ppv2 to obtain the emulated effectiveresistances, Rpco1 and Rpco2 of the two component converters.Subsequently the reference current, iL1ref of L1 and thereference current, iL2ref of L2, are synthesized by utilizing(28) in the buck mode [21],

iL1ref =vco1Rpco1

and iL2ref =vco2Rpco2

(28)

while for boost mode (29) is used to generate iL1ref andiL2ref [21].

iL1ref =v2co1

Rpco1Vpv1and iL2ref =

v2co2Rpco2Vpv2

(29)

The sensed inductor currents, iL1 and iL2 are compared withtheir corresponding references iL1ref and iL2ref . The errorsso obtained are processed through two separate PI controllersto generate the required sinusoidal duty ratios for the switches,S1 and S2 during buck mode. Similarly, two separate PIcontrollers are engaged to process the generated errors tosynthesize required sinusoidal duty ratios for switches S3 andS4 during boost mode. Signal Y is used to generate gatingsignals for S5, S8 while signal Z is used to generate gatingsignals for S6, S7 of the grid frequency unfolding inverter.

V. SELECTION OF L1, L2, Lg & Co1, Co2In order to select the value of the filter elements, L1, L2,

Lg & Co1, Co2 the design principle given in [24] is followed




TABLE IEMPLOYED PARAMETERS/ELEMENTS FOR SIMULATION AND

EXPERIMENTAL PURPOSE

Parameter/elements ValueVg and fg 220 V and 50 HzL1, L2, Lg & Co1, Co2 0.6 mH, 0.6 mH, 0.4 mH & 5 µF, 5 µFCpv1 and Cpv2 0.1 µFMPPT Algorithm Incremental ConductanceMosfets (S1-S8) IPW60R041C6Diodes (Df1-Df4) MBR40250fs of S1-S4 & fs of S5-S8 50 kHz & 50 HzDigital Signal Controller TMS320F28335

TABLE IIESTIMATED VARIATIONS OF DIFFERENT QUANTITIES DURING APPLIEDVARIATIONS ON INSOLATION AND TEMPERATURE OF TWO SUBARRAYS

Time in Second 0-1 1-2 2-3 3-4 4-5 5-6 6-7 7-8Insol. in PV1 (kW/m2) 0.5 0.6 0.7 0.8 0.9 1.0 1.0 1.0Insol. in PV2 (kW/m2) 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8Temp. in PV1 (C) 25 25 25 25 25 25 30 35Temp. in PV2 (C) 25 25 25 25 25 25 25 25Ppv1 (W) 331 397 463 529 595 661 638 621Ppv2 (W) 529 529 529 529 529 529 529 529Igm (A) 5.5 6.0 6.4 6.8 7.2 7.7 7.5 7.4Vco1m (V) 120 133 147 155 165 173 170 168Vco2m (V) 191 178 164 156 146 138 141 143IL1m (A) 5.7 7 8.1 9 10.3 11.4 11 10.7IL2m (A) 9 9 9 9 9 9 9 9

and the buck mode of operation for the inverter is considered.Values of L1 and L2 are obtained from the expression givenin [24]

L1 =Vpv1

4∆IL1fs& L2 =

Vpv24∆IL2fs

(30)

wherein, Vpv1 = Vpv2 = 200 V, percentage peak to peak rippleof iL1 and iL2, ∆IL1 and ∆IL2 are considered as 15% ofrated peak current.

The values of Co1 and Co2 are obtained from the expressiongiven in [24]

Co1 =xPco1

2πfgV 2co1

& Co2 =xPco2

2πfgV 2co2

(31)

wherein, Vco1 = Vco2 = 110 V, Pco1 = Pco2 = 750 W and factorx = 2.5%.

In order to achieve wide stability margin and large controlbandwidth a value which is less than L1 or L2 is selected forLg [24].

VI. SIMULATION STUDY

To demonstrate the efficacy of the proposed inverter aPV array consisting of two PV subarrays while each ofthe subarray having four series connected Canadian solarpolycrystalline modules ‘CS6P-165PE’ [25] is considered. TheMPP parameters of each subarray at standard test condition(STC) are as follows: Vpv1 = Vpv2 = 116 V, Ipv1 = Ipv2 = 5.7A and Ppv1 = Ppv2 = 661 W. The parameters which are used tosimulate the proposed inverter are indicated in Table I. Matlab-Simulink platform is utilized to simulate the performance ofthe proposed inverter.

The variation in insolation level and temperature withrespect to time which is considered for the two subarraysto demonstrate the effectiveness of the proposed inverter aretabulated in Table II. Estimated variation of Ppv1, Ppv2 alongwith the other parameters Igm, Vco1m, Vco2m, peak of iL1(IL1m) and peak of iL2 (IL2m) are also indicated in the sametable. Fig. 6(a)-(c) represents the variation of Ppv1, Ppv2, Vpv1,Vpv2, Ipv1, Ipv2 of the two subarrays and also demonstrate theability of the proposed inverter to operate the two subarrayssimultaneously at their respective MPP. Variation in ig , iL1,iL2, vco1 and vco2 along with their magnified versions for twodifferent insolation levels are depicted in Figs. 7 to 9. Theestimated values of the aforementioned quantities as tabulatedin Table II conform to that of obtained through simulationstudies thereby ensuring the viability of the proposed scheme.

p pv1

, ppv

2 (W

)

ppv1 ppv2

0 1 2 3time (s)

4 5 6 7 8

700

300

600

500

400

(a)v p

v1, v

pv2

(V

)

vpv2 vpv1

0 1 2 3time (s)4 5 6 7 8

130

120

110

100

(b)

i pv1

, i p

v2 (

A)

ipv1ipv2

0 1 2 3time (s)

4 5 6 7 82

3

4

5

6

(c)

Fig. 6. Simulated waveform: Variation in (a) ppv1 and ppv2, (b) vpv1 andvpv2, (c) ipv1 and ipv2 during entire range of operation

v g (

V)

& i

g (

A)

vg/30 ig time (s)0 1 2 3 4 5 6 7 8

-10

-5

0

5

10

-10

-5

0

510

-10

-5

0

510

1.50 1.51 1.52 1.53 1.54 1.55 5.515.50 5.52 5.53 5.54 5.55

vg/30 igvg/30 ig

Fig. 7. Simulated waveform: vg and ig and their magnified views




i L1, i

L2 (

A)

iL2

time (s)

1.50 1.51 1.52 1.53 1.54 1.55 5.515.50 5.52 5.53 5.54 5.55

0

5

0 1 2 3 4

iL1

5 6 7 8

10

0

5

10 iL1iL2

0

5

10iL2 iL1

Fig. 8. Simulated waveform: iL1 and iL2 and their magnified views

v co1,

v co

2(V

)

vco1 time (s)

0

50

100

150

200

0 1 2 3 4

vco2

5 6 7 8

1.50 1.51 1.52 1.53 1.54 1.55 5.515.50 5.52 5.53 5.54 5.550

50

100

150

200

0

50

100

150

200

vco1

vco2 vco2 vco1

Fig. 9. Simulated waveform: vco1 and vco2 and their magnified views

VII. EXPERIMENTAL VERIFICATION

A 1.5 kW laboratory prototype of the proposed inverter isfabricated and detailed experimental studies have been carriedout to demonstrate the effectiveness of the proposed scheme.The parameters as mentioned in Table I are used to realize thelaboratory prototype of the inverter. In order to realize PV1and PV2 two programmable EPS PSI9360-15 power supplieshaving solar PV emulation feature are utilized. The photographof the experimental prototype is shown in Fig. 10.

Buck stageBoost stage

Inverting

stage

Sensing board

Buffer circuit

Driver

Fig. 10. Experimental prototype of the proposed inverter

The EPS PSI9306-15 power supply has the provision tochange only the effect of insolation level while the optionto change the effect of temperature is unavailable. In orderto emulate simultaneous variation in temperature and level of

TABLE IIIESTIMATED VARIATION IN Ipv1 , Ipv2 , Ppv1 , Ppv2 , Vco1m , Vco2m , Igm ,

IL1m , IL2m DURING PV1 INSOLATION VARIATION

% Insol. of PV1 40 50 60 70 80 90 100% Insol. of PV2 80 80 80 80 80 80 80Ipv1 (A) 2 2.5 3 3.5 4 4.5 5Ipv2 (A) 4 4 4 4 4 4 4Ppv1 (W) 260 325 390 455 520 585 650Ppv2 (W) 480 480 480 480 480 480 480Vco1m (V) 109 126 140 151 162 171 179Vco2m (V) 202 185 171 160 149 140 132Igm (A) 4.6 5 5.4 5.8 6.2 6.6 7IL1m (A) 4.6 5 5.8 6.8 7.8 8.7 10IL2m (A) 7.7 7.7 7.7 7.7 7.7 7.7 7.7

insolation, the MPP parameters of the two solar emulators(solar emulator 1 as PV1 and solar emulator 2 as PV2) areset as follows at STC: Vpv1 = 130 V, Ipv1 = 5 A and Vpv2 =120 V, Ipv2 = 5 A. The variation in insolation level of PV1is indicated in Table III while the insolation level of PV2 ismaintained at 80%. The expected values of Ipv1, Ipv2, Ppv1,Ppv2, Vco1m, Vco2m, Igm, IL1m, IL2m for the entire operatingrange are tabulated in the Table III. Fig. 11 depicts the changein ig , Ipv1, Ipv2, Ppv1, Ppv2 throughout the range of variationin the level of insolation as specified in Table III. Magnifiedversion of the responses of vco1, vco2, iL1 and iL2 along withvg , ig are also shown in Fig. 12(a) to (f) for two differentinsolation levels of PV1. The figures Fig. 12(a) and (b) ensurethat ig remains to be sinusoidal and in-phase with vg in spiteof having difference in the magnitude of power being extractedfrom the two subarrays. From Fig. 12(c) it can be inferred thatthe converter associated with PV1 operates completely in buckmode, whereas the converter associated with PV2 operates inboth buck and boost mode depending on the requirement. Thusit can be inferred that the two converter segments are able tooperate in a decoupled fashion. The measured variables, Ipv1,Ipv2, Ppv1, Ppv2, Vco1m, Vco2m, Igm, IL1m, IL2m as depictedin Figs. 11, 12 are more or less same as that of the estimatedones presented in Table III, and this validates the ability ofthe proposed inverter to extract maximum power from twosubarrays operating under MEC.

Fig.13 depicts the Fast Fourier Transform (FFT) of ig . TheTHD of ig is found to be 4.61% which is below the limit of5% as specified in the standards, IEEE 1574/IEC 61727 [22].It may be noted that the measured THD of vg is found to be2.12% and hence the contribution to THD from the inverter ismuch less than 4.61%.

The measured and estimated efficiency curves of the pro-posed inverter are shown Fig.14. In order to measure theefficiency of the proposed inverter the Yokogawa make poweranalyzer, WT1800 is used and further, the losses incurredin the active and passive elements of the power circuit isconsidered while the losses involved with the control circuitare neglected. The efficiency is determined while both Vpv1and Vpv2 are set at 130 V. Measured peak efficiency is foundto be 97.65% and the measured European efficiency (ηeuro)is obtained as 97.02%.




ipv1,2:2 A/div, ig:5 A/div, ppv1,2:200 W/divvg:200 V/div, vpv1,2:100 V/div,

ipv2ipv1

ppv2 ppv1

vg ig

vpv1vpv2

Fig. 11. Experimental waveforms: vpv1, vpv2, ig , vg , ipv1, ipv2, ppv1,ppv2 throughout the entire operating range

vg:200 V/div, vpv1,2 & vco1,2:100 V/div, ig:10 A/div, iL1,2:5 A/div

iL2

iL1

vg

ig

vco2 vco1

vpv2vpv1

iL2

iL1

vg

ig

vco2vco1

vpv2vpv1

(a) (b)

(c) (d)

(e) (f)

Fig. 12. Experimental waveforms: Magnified version of ig , vg when(a) insolation of PV1=40% & insolation of PV2=80%, (b) insolation ofPV1=100% & insolation of PV2=80%, magnified version of vpv1, vpv2,vco1, vco2 when (c) insolation of PV1=40% & insolation of PV2=80%, (d)insolation of PV1=100% & insolation of PV2=80%, magnified version ofiL1, iL2 when (e) insolation of PV1=40% & insolation of PV2=80%, (f)insolation of PV1=100% & insolation of PV2=80%

In order to measure the leakage current involved with theproposed inverter, 0.1 µF polypropylene film capacitors areused to emulate Cpv1 and Cpv2. Fig. 15 depicts the voltagesthat appear across Cpv1 and Cpv2, and the leakage currents,icpv1 and icpv2 flowing through Cpv1 and Cpv2. The measuredwaveforms of vcpv1 and vcpv2 show that they contain signif-

0

ig (A): 5 cycles. FFT window (in cyan): 2 cycles

5 10 15Harmonic order

20 25

2

0

0 0.01 0.02

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

-10

0

10

Selected signal: 5.005 cycles. FFT window (in red): 2 cycles

Time (s)

0 5 10 15 20 25 300

2

4

6

8

10

Harmonic order

Fundamental (50Hz) = 9.031 , THD= 7.96%

Mag (

% o

f F

undam

enta

l)

0.03 0.04 0.05 0.06time (s)

0.07 0.08 0.09 0.1

15

-15

0

i g (

A)

Fundamental (50 Hz) = 9.03 A, THD = 4.61%

4

Mag

(%

of

Fundam

enta

l)

30

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1

-10

0

10

Selected signal: 5.005 cycles. FFT window (in red): 2 cycles

Time (s)

0 5 10 15 20 25 30 35 400

2

4

6

8

10

Harmonic order

Fundamental (50Hz) = 9.031 , THD= 7.96%

Mag (%

of F

undam

ental)

Fig. 13. Experimental waveform: FFT of ig

Efficiency curve of the Proposed Inverter

Eff

icie

ncy

(%

)

Output power (W)250 500 750 1000 1250

Estimated efficiency curve Measured efficiency curve

96.5

97.23

96.71

0 1500

97.0

97.5

98.0

98.5

96.0

98.01

98.12 98.0697.92

97.7497.57 97.4697.60 97.50

97.2597.00

96.8096.50

96.40

Fig. 14. Efficiency curves of the Proposed inverter

icant amount of dc and low frequency components whereaspresence of high frequency components are negligible. Themeasured RMS value of total leakage current is found to be80.7 mA which is much lower than the limit 300 mA asspecified in the standard, VDE 0126-1-1, and also cited in[23].

vcpv1

vg

icpv2

vg & vcpv1,2 :200V/div, icpv1,2:500 mA/div

vcpv2

icpv1

Fig. 15. Experimental waveform: vg , vcpv1, vcpv2, icpv1, icpv2

In order to demonstrate the stability of the proposed schemein the event of a disturbance in vg , a step change of 70 V (150V to 220 V) is introduced in vg while Vpv1 and Vpv2 are keptat 130 V and the references for the current controllers are




vg:200V/div, ig:10A/div, vco1,2:100V/div, vpv1,2:100V/div

vgig

vg

igvg

ig vpv1,2

vco1,2

vpv1,2

vco1,2 vco1,2

vpv1,2

Fig. 16. Experimental waveform: vg , ig , vco1, vco2, vpv1, vpv2 when vgis changed from 150 V to 220 V

purposely set at a fixed value in each mode. The response ofthe system during the aforesaid test condition where mode ofoperation of the proposed inverter is shifted from buck modeto buck and boost mode is shown in Fig. 16. It can be inferredfrom the Fig. 16 that the system can effectively ride throughsituations arising due to the disturbances in vg .

A comparison of various features of the proposed schemewith existing transformerless schemes such as NPC basedscheme [5], H-Bridge based scheme [2], schemes presentedin [18] and [21] has been performed and presented in TableIV. Following issues are considered for carrying out thiscomparison: i) solar modules, Canadian solar ‘CS6P-165PE’[25] are utilized for the purpose, ii) Minimum input voltagerequirement for NPC based scheme [5] and H-Bridge basedscheme [2] is taken to be 800 V and 400 V respectively whileminimum input voltage requirement of the schemes presentedin [18], [21] and that of the proposed scheme is taken tobe 230 V, iii) for simplicity total area required for a systemis determined by multiplying the total number of modulesrequired with the area of a single module. The nomenclaturesused in the Table IV are defined as follows: NPV R = requirednumber of PV arrays/subarrays, NPV C = number of PV arrayscontrolled simultaneously, VIN = input voltage requirement,NMS = number of modules connected in series in a PVstring of a PV array/subarray which is made with a singlestring, NMT = minimum number of modules required todesign the PV system, PSY S = minimum power rating of thePV system, APV = minimum area required to install all PVmodules, EMEC = possibility to get affected by MEC which isdetermined from Table V. Based on the objective comparisonpresented in the Table IV it can be inferred that the proposedinverter deals with MEC in the most effective way.

In order to compare the power extraction from PV arrayby various transformerless schemes as mentioned in TableIV while the schemes are operating under MEC, a 5.3 kWPV system at STC, built with 32 ‘CS6P-165PE’ Canadiansolar modules [25] is considered. Depending on the minimumDC voltage requirement, type of input connection required

TABLE IVCOMPARISON TABLE OF VARIOUS TRANSFORMERLESS SCHEMES

SchemesNPV R

&NPV C

VIN(V)

NMS

&NMT

PSY S

(kW)APV

(m2) EMEC

NPC based [5] 1 & 1 > 2Vm 28 & 28 4.6 44.8 HighestH-Bridge based [2] 1 & 1 > Vm 14 & 14 2.3 22.4 HighReported in [18] 2 & 2 < Vm 8 & 16 2.6 25.6 LowReported in [21] 1 & 1 < Vm 8 & 8 1.3 12.8 LowProposed DBBI 2 & 2 < Vm 4 & 8 1.3 12.8 Lowest

TABLE VEFFECT OF MEC IN DIFFERENT TRANSFORMERLESS SCHEMES

Mod1in (%) 100 90 80 70 60 50Schemes Pavl (kW) 5.3 5.27 5.25 5.24 5.22 5.2

Pext (kW) 5.3 5.2 4.9 4.53 4.1 3.6NPC based [5] Pdiff (kW) 0 0.07 0.35 0.71 1.12 1.6

Plost (%) 0 1.3 6.7 13.5 21.7 31.5Pext (kW) 5.3 5.23 5.04 4.8 4.54 4.25

H-Bridge based [2] Pdiff (kW) 0 0.04 0.21 0.44 0.68 0.95Plost (%) 0 0.8 4 8.2 13.1 18.3Pext (kW) 5.3 5.25 5.15 5.03 4.90 4.75

Reported in [18] Pdiff (kW) 0 0.02 0.1 0.21 0.32 0.45Plost (%) 0 0.4 2 4 6.1 8.6Pext (kW) 5.3 5.25 5.15 5.03 4.90 4.75

Reported in [21] Pdiff (kW) 0 0.02 0.1 0.21 0.32 0.45Plost (%) 0 0.4 2 4 6.1 8.6Pext (kW) 5.3 5.26 5.21 5.14 5.08 5.01

Proposed DBBI Pdiff (kW) 0 0.01 0.04 0.1 0.14 0.19Plost (%) 0 0.2 0.8 2 2.7 3.6

and power rating of the schemes, required number of PVmodules are connected in series-parallel combination to formPV array/subarrays. The PV arrays/subarrays of the schemesare configured as follows: i) NMS = 32 in [5], ii) NMS =16 and NMP = 2 in [2], wherein NMP = number of stringsconnected in parallel in an array/subarray, iii) NMS = 8 andNMP = 2 in [18], iv) NMS = 8 and NMP = 4 in [21], v) NMS

= 4 and NMP = 4 in DBBI. Further, it is also assumed that noparallel diode is connected across PV modules. The insolationlevel of one module, Mod1in is varied from 100% to 50% witha step of 10% while the insolation of rest of the 31 modulesare kept at 100%, i.e. at STC. The total estimated extractedpower from the PV subarrays during MEC by any scheme,Pext = power of affected string + power of rest of the string,the actual available maximum power in the PV array of anyscheme, Pavl = 31xpower of each module + power of affectedmodule, their difference, Pdiff and the percentage loss ofpower due to MEC in any scheme, Plost are tabulated in TableV. As the effect of MEC is less severe in parallel connectedPV strings, the aforementioned effect is neglected to avoidcomplexity in calculation. From Table V it can be concludedthat the proposed inverter is the most effective solution inextracting power during MEC.

VIII. CONCLUSION

A single phase grid connected transformerless buck andboost based PV inverter which can operate two subarraysat their respective MPP was proposed in this paper. Theattractive features of this inverter were i) effect of mismatchedenvironmental conditions on the PV array could be dealt with




in an effective way, ii) operating efficiency achieved, ηeuro =97.02% was high, iii) decoupled control of component convert-ers was possible, iv) simple MPPT algorithm was employedto ensure MPP operation for the component converters, v)leakage current associated with the PV arrays was within thelimit mentioned in VDE 0126-1-1. Mathematical analysis ofthe proposed inverter leading to the development of its smallsignal model was carried out. The criterion to select the valuesof the output filter components was presented. The schemewas validated by carrying out detailed simulation studiesand subsequently the viability of the scheme was ascertainedby carrying out thorough experimental studies on a 1.5 kWprototype of the inverter fabricated for the purpose.

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[25] Information on Canadian solar module CS6P-165PE. [Online]. Avail-able: www.solarhub.com/product-catalog/pv-modules/124

Subhendu Dutta was born in West Bengal,India. He received the B.Tech. degree in elec-trical engineering from West Bengal Universityof Technology, Kolkata, India, in 2009, the M.E.degree in electrical engineering from JadavpurUniversity, Kolkata, India, in 2012. He is currentlyworking toward the Ph.D. degree in the area ofpower electronics in the Department of Electri-cal Engineering, Indian Institute of TechnologyBombay, Mumbai, India.

He worked as an Assistant Professor in theCollege of Engineering & Management, Kolaghat, India from 2012 to2013. His current research interests include shading effect on solarphoto voltaic system, design and efficiency improvement of powerelectronic converter for solar photovoltaic applications and design ofmagnetic elements for power electronic system.

Kishore Chatterjee (M’10) was born in Cal-cutta, India, in 1967. He received the B.E. de-gree in electrical engineering from the MaulanaAzad National Institute of Technology (MANIT),Bhopal, India, in 1990, the M.E. degree in electri-cal engineering from Indian Institute of Engineer-ing Science and Technology (IIEST), Howrah,India in 1992, both in electrical engineering, andthe Ph.D. degree from the Indian Institute ofTechnology Kanpur, Kanpur, India, in 1998.

From 1997 to 1998, he was a Senior ResearchAssociate with the Indian Institute of Technology Kanpur. Since 1998,he has been with the Department of Electrical Engineering, IndianInstitute of Technology Bombay, Mumbai, India, where he is currentlya Professor. He was a Visiting Fellow for a year at ETS, Universityof Quebec, Montreal, QC, Canada, in 2004. He has been leading thepower electronic group of the National Centre for Photovoltaic Researchand Education (NCPRE) being hosted at IIT Bombay since 2009. Hiscurrent research interests are power evacuation strategies from solarphotovoltaic systems, modern VAr compensators, active power filters,utility-friendly converter topologies, and induction motor drives.

a buck & boost based grid connected pv inverter ... buck & boost based grid connected pv...

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