Symposia on VLSI Technology and Circuits

Zhijie Chen, Masaya Miyahara, Akira Matsuzawa

Tokyo Institute of Technology

A 9.35-ENOB, 14.8 fJ/conv.-step Fully-

Passive Noise-Shaping SAR ADC

Outline

• Background and motivation

• Conventional Noise shaping technique

• Proposed fully passive noise shaping SAR ADC

• Experimental results

• Conclusion

Slide 1

Background and Motivation

Slide 2

Vin

VREFPVCM

VREFN

CC2C4C

CLK

D Q

Clk

Q

SAR logicSample Conversion

Switch and Capacitor

DigitalComparator

• SAR ADC mainly consists of digital circuits

• It can benefit from the technology scaling (like speed)

• Analog components affect the performance

SAR ADC architecture:

Vin

VREFPVCM

VREFN

CC2C4C

CLK

D Q

Clk

Q

SAR logicSample Conversion

Switch and Capacitor in SAR ADC

Slide 3

Switch and Capacitor

• Higher resolution Larger cap Larger settling time

• Larger cap Larger chip size Slower speed

Capacitor array affects SAR ADC performance

Vin

VREFPVCM

VREFN

CC2.1C3.9C

CLK

D Q

Clk

Q

SAR logicJitter

VN

VREFP

VREFN

error

Non-ideal effects

Slide 4

• Non-ideal effects further degrade performance

• How to improve the resolution?

noise

jitter

Mismatch

Settling error

Noise shaping technique

Slide 5

• Sacrifice speed for resolution

• Noise shaping is based on integrator, usually opamp

Move noise out of band of interest

-150

-100

-50

0

104 105 106 107 108

PSD of Sigma-Delta Modulator

Frequency [Hz]P

SD

[d

B] Noise Shaping

Order

Bandwidth

OSR

X

-

Integrator

Y

Quantizer

DAC

Simulation results of non-ideal effects

Slide 6

• Noise shaping reduces non-ideal effects

Fin = 6.24 MHz

Settling error (LSB)Comparator noise: Vn (σ(LSB))

0.05 0.1 0.15 0.2 0.25

10.5

0.01

SAR NS SAR

EN

OB

(B

its

)

7.5

8

8.5

9

9.5

10

10.5

SAR NS SAR

EN

OB

(B

its

)

7.5

8

8.5

9

9.5

10

0.1 0.5 1 1.5 2

Jitter (ps)DAC mismatch (LSB)

10.5

SAR NS SAR

EN

OB

(B

its

)

7.5

8

8.5

9

9.5

10

10.5

SAR NS SAR

EN

OB

(B

its

)

7.5

8

8.5

9

9.5

10

0.1 0.5 1 1.5 2 10 40 70 100

Noise shaping effect on capacitance

Slide 7

• Noise shaping SAR ADC

• Traditional SAR ADC

Thermal noise = kT/C

Thermal noise = (1-Z-1) kT/C/OSR

Same SNR, smaller capacitor for noise shaping SAR ADC

Outline

• Conventional Noise shaping technique

Slide 8

Conventional noise shaping technique

Slide 9

FIR filter introduces extra noise and extra area;

Opamp : extra power and flicker noise

[1] J. Fredenburg, et al., JSSC 2012

Tech. scaling, difficult to design high performance Opamp

Dout(z)

Dout(z)

VIN(z)

FIR Filter

VIN(z) a1z-1

a2z-1

z-1

kA

Q(z)

FIR Filter IIR Filter

OpampCap Array

Outline

• Proposed fully passive noise shaping SAR ADC

Slide 10

Traditional architecture

Slide 11

Traditional 1st-order noise shaping architecture

E

X

-

Z-1

1-Z-1

Y

DAC

OTA based integrator

SAR ADC

E: quantization noise

Y=X+(1-Z-1)E

XSAR,in

Y=(X-Z-1E)+E Y(N)=X(N)+XSAR,in(N-1)-Y(N-1)+E(N)

Previous residue

Proposed FPNS-SAR ADC architecture

Slide 12

Proposed noise shaping architecture (FPNS-SAR)

Step 1: Get previous residue on top-plate of C-DAC;

Step 2: Feed it back to input.

E

Xin Y

DACZ-1

-E

XSAR,in=Xin - Z-1

E

SAR

: Realized by Charge redistribution

Residue in SAR ADC

Slide 13

Residue on the top-plate of SAR ADC

Vin

VREFPVCM

VREFN

CC2C4C

CLK

D Q

Clk

Q

SAR logic

CLK

N-1 N

Vtop

After conversion @ N-1, residue Vtop(N-1)=XSAR,in(N-1)-Y(N-1)

FPNS-SAR ADC implementation

Slide 14

1. Conversion @ N-1

After conversion, Vtop=-E(n-1)/2;

2. Clear Charge@ ΦNS2

Clear Charge of C3, QC3=0;

ФS

Vin

C1 C2

C3

+

-

ФC

ФNS1

ФNS2

ФNS3

ФS

ФC

N-1 N

ФNS1

ФNS2

ФNS3

Vtop

+ ФS

Vin

C1 C2

C3

+

-

ФC

ФNS1

ФNS2

ФNS3

ФS

ФC

N-1 N

ФNS1

ФNS2

ФNS3

Vtop

+

FPNS-SAR ADC implementation

Slide 15

3. Charge share @ ΦNS3

Get half top voltage, VC3= Vtop (n-1)/2;

4. Sample @ N

Sampling input, Vin(n);

ФS

Vin

C1 C2

C3

+

-

ФC

ФNS1

ФNS2

ФNS3

ФS

ФC

N-1 N

ФNS1

ФNS2

ФNS3

Vtop

+ ФS

Vin

C1 C2

C3

+

-

ФC

ФNS1

ФNS2

ФNS3

ФS

ФC

N-1 N

ФNS1

ФNS2

ФNS3

Vtop

+

FPNS-SAR ADC implementation

Slide 16

5. Conversion@ N

VDAC(n) = Vin(n)-E(n-1)+E(n)

With the help of C2 and C3:

VDAC(Z) = Vin(Z)+(1-Z-1)E(Z)

Realize 1st-order NS

ФS

ФC

N-1 N

ФNS1

ФNS2

ФNS3

ФS

Vin

C1 C2

C3

+

-

ФC

ФNS1

ФNS2

ФNS3

Vtop

+

Capacitance comparison

Slide 17

Traditional 10b SAR-ADC

Proposed 10b noise shaping architecture (FPNS-SAR)

ФSC

ФC

+

-

Vin

C 2C

C: 8b C-DAC

Total: 4 X C

Total: 3 X C1

C1<C, hence, proposal saves area

ФSC1

C2

ФC

ФNS1

ФNS3

C3

+

-

ФNS2C1=C2=C3

+

ФS

Vin

C1

C2

C3

+

-

ФC

ФNS1

ФNS2

ФNS3

Vtop

+

SAR Logic

ФNS2

ФNS3

:NMOS SwitchФS :Bootstrap switch

ФNS1 :CMOS Switch :NMOS Switch

Circuit details

Slide 18

Total Circuit of FPNS-SAR ADC:

Asynchronous logic; 8-bit C-DAC

8-bit

Different switches; four inputs comparator

Circuit details

Slide 19

Dynamic comparator [4]

[4] H. Wei, et al., JSSC 2012

Dynamic comparator, save power

AVDD

Vinp Vinn

CLK

CLK

cn

cp

cn

cp

Vp

VnVinp,p Vinn,n

SR LATCH:

Outline

• Experimental results

Slide 20

Chip photograph

Slide 21

C-DAC

230.1 µm

53.4

µm

CMOS 65 nm

COMP

CLK LOGIC

Experimental results

Slide 22

• Realized 1st-order Noise Shaping

Power supply: 0.8-V

Power : 120.7-µW

-60 -50 -40 -30 -20 -10 00

102030405060

input signal [dBFS]

SN

DR

[d

B]

104 105 106 107-140

-120

-100

-80

-60

-40

-20

0Power Spectral Density

Frequency [Hz]

PS

D [

dB

]

SNDR = 58.03 dB ENOB = 9.35 bits Fin = 999.5 kHzOSR = 4Fs = 50 MHz

BW = 6.25 MHz

20dB/Oct

Experimental results-Comparison

Slide 23

[1] J. A. Fredenburg , et al., JSSC 2012

[2] M. V. Elzakker, et al., JSSC 2010

[3] A. Jain, et al., JSSC 2012

JSSC’10 [2]

JSSC’12[3]

JSSC’12 [1]

This work

Architecture SAR CT-SDM NS-SAR FPNS-SAR

OTA No Yes

Technology (nm) 65 130 65 65

Bandwidth (MHz) 0.5 15.6 11 6.25

Core Area (mm2) 0.0259 0.27 0.0323 0.0123

Supply (V) 1 1.3 1.2 0.8

Power (μW) 1.9 4000 806 120.7

ENOB (bits) 8.75 9.6 10 9.35

FoMW

(fJ/conv.) 4.42 160 35.8 14.8

Noise Shaping No Yes Yes Yes Yes No

Outline

• Conclusion

Slide 24

Conclusion

• First work that realizes Passive noise shaping SAR, save power;

• Maintain basic architecture and operation of SAR-ADC, inherits advantage of SAR-ADC;

• No Opamp, most are digital circuits, robust to future technology and power supply downscaling;

• Relax the requirement of circuit blocks, save area and save power.

Slide 25

Acknowledgements

This work was partially supported by HUAWEI, Mentor

Graphics for the use of the Analog Fast SPICE (AFS)

Platform, and VDEC in collaboration with Cadence

Design Systems, Inc.

Slide 26